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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Linaro Ltd
4 * Author: Sumit Semwal <sumit.semwal@linaro.org>
5 *
6 * This driver is for the DSI interface to panels using the NT36672A display driver IC
7 * from Novatek.
8 * Currently supported are the Tianma FHD+ panels found in some Xiaomi phones, including
9 * some variants of the Poco F1 phone.
10 *
11 * Panels using the Novatek NT37762A IC should add appropriate configuration per-panel and
12 * use this driver.
13 */
14
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20
21#include <linux/gpio/consumer.h>
22#include <linux/pinctrl/consumer.h>
23#include <linux/regulator/consumer.h>
24
25#include <drm/drm_device.h>
26#include <drm/drm_mipi_dsi.h>
27#include <drm/drm_modes.h>
28#include <drm/drm_panel.h>
29
30#include <video/mipi_display.h>
31
32struct nt36672a_panel_cmd {
33 const char data[2];
34};
35
36static const char * const nt36672a_regulator_names[] = {
37 "vddio",
38 "vddpos",
39 "vddneg",
40};
41
42static unsigned long const nt36672a_regulator_enable_loads[] = {
43 62000,
44 100000,
45 100000
46};
47
48struct nt36672a_panel_desc {
49 const struct drm_display_mode *display_mode;
50 const char *panel_name;
51
52 unsigned int width_mm;
53 unsigned int height_mm;
54
55 unsigned long mode_flags;
56 enum mipi_dsi_pixel_format format;
57 unsigned int lanes;
58
59 unsigned int num_on_cmds_1;
60 const struct nt36672a_panel_cmd *on_cmds_1;
61 unsigned int num_on_cmds_2;
62 const struct nt36672a_panel_cmd *on_cmds_2;
63
64 unsigned int num_off_cmds;
65 const struct nt36672a_panel_cmd *off_cmds;
66};
67
68struct nt36672a_panel {
69 struct drm_panel base;
70 struct mipi_dsi_device *link;
71 const struct nt36672a_panel_desc *desc;
72
73 struct regulator_bulk_data supplies[ARRAY_SIZE(nt36672a_regulator_names)];
74
75 struct gpio_desc *reset_gpio;
76
77 bool prepared;
78};
79
80static inline struct nt36672a_panel *to_nt36672a_panel(struct drm_panel *panel)
81{
82 return container_of(panel, struct nt36672a_panel, base);
83}
84
85static int nt36672a_send_cmds(struct drm_panel *panel, const struct nt36672a_panel_cmd *cmds,
86 int num)
87{
88 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
89 unsigned int i;
90 int err;
91
92 for (i = 0; i < num; i++) {
93 const struct nt36672a_panel_cmd *cmd = &cmds[i];
94
95 err = mipi_dsi_dcs_write(pinfo->link, cmd->data[0], cmd->data + 1, 1);
96
97 if (err < 0)
98 return err;
99 }
100
101 return 0;
102}
103
104static int nt36672a_panel_power_off(struct drm_panel *panel)
105{
106 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
107 int ret = 0;
108
109 gpiod_set_value(pinfo->reset_gpio, 1);
110
111 ret = regulator_bulk_disable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies);
112 if (ret)
113 dev_err(panel->dev, "regulator_bulk_disable failed %d\n", ret);
114
115 return ret;
116}
117
118static int nt36672a_panel_unprepare(struct drm_panel *panel)
119{
120 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
121 int ret;
122
123 if (!pinfo->prepared)
124 return 0;
125
126 /* send off cmds */
127 ret = nt36672a_send_cmds(panel, pinfo->desc->off_cmds,
128 pinfo->desc->num_off_cmds);
129
130 if (ret < 0)
131 dev_err(panel->dev, "failed to send DCS off cmds: %d\n", ret);
132
133 ret = mipi_dsi_dcs_set_display_off(pinfo->link);
134 if (ret < 0)
135 dev_err(panel->dev, "set_display_off cmd failed ret = %d\n", ret);
136
137 /* 120ms delay required here as per DCS spec */
138 msleep(120);
139
140 ret = mipi_dsi_dcs_enter_sleep_mode(pinfo->link);
141 if (ret < 0)
142 dev_err(panel->dev, "enter_sleep cmd failed ret = %d\n", ret);
143
144 /* 0x3C = 60ms delay */
145 msleep(60);
146
147 ret = nt36672a_panel_power_off(panel);
148 if (ret < 0)
149 dev_err(panel->dev, "power_off failed ret = %d\n", ret);
150
151 pinfo->prepared = false;
152
153 return ret;
154}
155
156static int nt36672a_panel_power_on(struct nt36672a_panel *pinfo)
157{
158 int ret;
159
160 ret = regulator_bulk_enable(ARRAY_SIZE(pinfo->supplies), pinfo->supplies);
161 if (ret < 0)
162 return ret;
163
164 /*
165 * As per downstream kernel, Reset sequence of Tianma FHD panel requires the panel to
166 * be out of reset for 10ms, followed by being held in reset for 10ms. But for Android
167 * AOSP, we needed to bump it upto 200ms otherwise we get white screen sometimes.
168 * FIXME: Try to reduce this 200ms to a lesser value.
169 */
170 gpiod_set_value(pinfo->reset_gpio, 1);
171 msleep(200);
172 gpiod_set_value(pinfo->reset_gpio, 0);
173 msleep(200);
174
175 return 0;
176}
177
178static int nt36672a_panel_prepare(struct drm_panel *panel)
179{
180 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
181 int err;
182
183 if (pinfo->prepared)
184 return 0;
185
186 err = nt36672a_panel_power_on(pinfo);
187 if (err < 0)
188 goto poweroff;
189
190 /* send first part of init cmds */
191 err = nt36672a_send_cmds(panel, pinfo->desc->on_cmds_1,
192 pinfo->desc->num_on_cmds_1);
193
194 if (err < 0) {
195 dev_err(panel->dev, "failed to send DCS Init 1st Code: %d\n", err);
196 goto poweroff;
197 }
198
199 err = mipi_dsi_dcs_exit_sleep_mode(pinfo->link);
200 if (err < 0) {
201 dev_err(panel->dev, "failed to exit sleep mode: %d\n", err);
202 goto poweroff;
203 }
204
205 /* 0x46 = 70 ms delay */
206 msleep(70);
207
208 err = mipi_dsi_dcs_set_display_on(pinfo->link);
209 if (err < 0) {
210 dev_err(panel->dev, "failed to Set Display ON: %d\n", err);
211 goto poweroff;
212 }
213
214 /* Send rest of the init cmds */
215 err = nt36672a_send_cmds(panel, pinfo->desc->on_cmds_2,
216 pinfo->desc->num_on_cmds_2);
217
218 if (err < 0) {
219 dev_err(panel->dev, "failed to send DCS Init 2nd Code: %d\n", err);
220 goto poweroff;
221 }
222
223 msleep(120);
224
225 pinfo->prepared = true;
226
227 return 0;
228
229poweroff:
230 gpiod_set_value(pinfo->reset_gpio, 0);
231 return err;
232}
233
234static int nt36672a_panel_get_modes(struct drm_panel *panel,
235 struct drm_connector *connector)
236{
237 struct nt36672a_panel *pinfo = to_nt36672a_panel(panel);
238 const struct drm_display_mode *m = pinfo->desc->display_mode;
239 struct drm_display_mode *mode;
240
241 mode = drm_mode_duplicate(connector->dev, m);
242 if (!mode) {
243 dev_err(panel->dev, "failed to add mode %ux%u@%u\n", m->hdisplay,
244 m->vdisplay, drm_mode_vrefresh(m));
245 return -ENOMEM;
246 }
247
248 connector->display_info.width_mm = pinfo->desc->width_mm;
249 connector->display_info.height_mm = pinfo->desc->height_mm;
250
251 drm_mode_set_name(mode);
252 drm_mode_probed_add(connector, mode);
253
254 return 1;
255}
256
257static const struct drm_panel_funcs panel_funcs = {
258 .unprepare = nt36672a_panel_unprepare,
259 .prepare = nt36672a_panel_prepare,
260 .get_modes = nt36672a_panel_get_modes,
261};
262
263static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_1[] = {
264 /* skin enhancement mode */
265 { .data = {0xFF, 0x22} },
266 { .data = {0x00, 0x40} },
267 { .data = {0x01, 0xC0} },
268 { .data = {0x02, 0x40} },
269 { .data = {0x03, 0x40} },
270 { .data = {0x04, 0x40} },
271 { .data = {0x05, 0x40} },
272 { .data = {0x06, 0x40} },
273 { .data = {0x07, 0x40} },
274 { .data = {0x08, 0x40} },
275 { .data = {0x09, 0x40} },
276 { .data = {0x0A, 0x40} },
277 { .data = {0x0B, 0x40} },
278 { .data = {0x0C, 0x40} },
279 { .data = {0x0D, 0x40} },
280 { .data = {0x0E, 0x40} },
281 { .data = {0x0F, 0x40} },
282 { .data = {0x10, 0x40} },
283 { .data = {0x11, 0x50} },
284 { .data = {0x12, 0x60} },
285 { .data = {0x13, 0x70} },
286 { .data = {0x14, 0x58} },
287 { .data = {0x15, 0x68} },
288 { .data = {0x16, 0x78} },
289 { .data = {0x17, 0x77} },
290 { .data = {0x18, 0x39} },
291 { .data = {0x19, 0x2D} },
292 { .data = {0x1A, 0x2E} },
293 { .data = {0x1B, 0x32} },
294 { .data = {0x1C, 0x37} },
295 { .data = {0x1D, 0x3A} },
296 { .data = {0x1E, 0x40} },
297 { .data = {0x1F, 0x40} },
298 { .data = {0x20, 0x40} },
299 { .data = {0x21, 0x40} },
300 { .data = {0x22, 0x40} },
301 { .data = {0x23, 0x40} },
302 { .data = {0x24, 0x40} },
303 { .data = {0x25, 0x40} },
304 { .data = {0x26, 0x40} },
305 { .data = {0x27, 0x40} },
306 { .data = {0x28, 0x40} },
307 { .data = {0x2D, 0x00} },
308 { .data = {0x2F, 0x40} },
309 { .data = {0x30, 0x40} },
310 { .data = {0x31, 0x40} },
311 { .data = {0x32, 0x40} },
312 { .data = {0x33, 0x40} },
313 { .data = {0x34, 0x40} },
314 { .data = {0x35, 0x40} },
315 { .data = {0x36, 0x40} },
316 { .data = {0x37, 0x40} },
317 { .data = {0x38, 0x40} },
318 { .data = {0x39, 0x40} },
319 { .data = {0x3A, 0x40} },
320 { .data = {0x3B, 0x40} },
321 { .data = {0x3D, 0x40} },
322 { .data = {0x3F, 0x40} },
323 { .data = {0x40, 0x40} },
324 { .data = {0x41, 0x40} },
325 { .data = {0x42, 0x40} },
326 { .data = {0x43, 0x40} },
327 { .data = {0x44, 0x40} },
328 { .data = {0x45, 0x40} },
329 { .data = {0x46, 0x40} },
330 { .data = {0x47, 0x40} },
331 { .data = {0x48, 0x40} },
332 { .data = {0x49, 0x40} },
333 { .data = {0x4A, 0x40} },
334 { .data = {0x4B, 0x40} },
335 { .data = {0x4C, 0x40} },
336 { .data = {0x4D, 0x40} },
337 { .data = {0x4E, 0x40} },
338 { .data = {0x4F, 0x40} },
339 { .data = {0x50, 0x40} },
340 { .data = {0x51, 0x40} },
341 { .data = {0x52, 0x40} },
342 { .data = {0x53, 0x01} },
343 { .data = {0x54, 0x01} },
344 { .data = {0x55, 0xFE} },
345 { .data = {0x56, 0x77} },
346 { .data = {0x58, 0xCD} },
347 { .data = {0x59, 0xD0} },
348 { .data = {0x5A, 0xD0} },
349 { .data = {0x5B, 0x50} },
350 { .data = {0x5C, 0x50} },
351 { .data = {0x5D, 0x50} },
352 { .data = {0x5E, 0x50} },
353 { .data = {0x5F, 0x50} },
354 { .data = {0x60, 0x50} },
355 { .data = {0x61, 0x50} },
356 { .data = {0x62, 0x50} },
357 { .data = {0x63, 0x50} },
358 { .data = {0x64, 0x50} },
359 { .data = {0x65, 0x50} },
360 { .data = {0x66, 0x50} },
361 { .data = {0x67, 0x50} },
362 { .data = {0x68, 0x50} },
363 { .data = {0x69, 0x50} },
364 { .data = {0x6A, 0x50} },
365 { .data = {0x6B, 0x50} },
366 { .data = {0x6C, 0x50} },
367 { .data = {0x6D, 0x50} },
368 { .data = {0x6E, 0x50} },
369 { .data = {0x6F, 0x50} },
370 { .data = {0x70, 0x07} },
371 { .data = {0x71, 0x00} },
372 { .data = {0x72, 0x00} },
373 { .data = {0x73, 0x00} },
374 { .data = {0x74, 0x06} },
375 { .data = {0x75, 0x0C} },
376 { .data = {0x76, 0x03} },
377 { .data = {0x77, 0x09} },
378 { .data = {0x78, 0x0F} },
379 { .data = {0x79, 0x68} },
380 { .data = {0x7A, 0x88} },
381 { .data = {0x7C, 0x80} },
382 { .data = {0x7D, 0x80} },
383 { .data = {0x7E, 0x80} },
384 { .data = {0x7F, 0x00} },
385 { .data = {0x80, 0x00} },
386 { .data = {0x81, 0x00} },
387 { .data = {0x83, 0x01} },
388 { .data = {0x84, 0x00} },
389 { .data = {0x85, 0x80} },
390 { .data = {0x86, 0x80} },
391 { .data = {0x87, 0x80} },
392 { .data = {0x88, 0x40} },
393 { .data = {0x89, 0x91} },
394 { .data = {0x8A, 0x98} },
395 { .data = {0x8B, 0x80} },
396 { .data = {0x8C, 0x80} },
397 { .data = {0x8D, 0x80} },
398 { .data = {0x8E, 0x80} },
399 { .data = {0x8F, 0x80} },
400 { .data = {0x90, 0x80} },
401 { .data = {0x91, 0x80} },
402 { .data = {0x92, 0x80} },
403 { .data = {0x93, 0x80} },
404 { .data = {0x94, 0x80} },
405 { .data = {0x95, 0x80} },
406 { .data = {0x96, 0x80} },
407 { .data = {0x97, 0x80} },
408 { .data = {0x98, 0x80} },
409 { .data = {0x99, 0x80} },
410 { .data = {0x9A, 0x80} },
411 { .data = {0x9B, 0x80} },
412 { .data = {0x9C, 0x80} },
413 { .data = {0x9D, 0x80} },
414 { .data = {0x9E, 0x80} },
415 { .data = {0x9F, 0x80} },
416 { .data = {0xA0, 0x8A} },
417 { .data = {0xA2, 0x80} },
418 { .data = {0xA6, 0x80} },
419 { .data = {0xA7, 0x80} },
420 { .data = {0xA9, 0x80} },
421 { .data = {0xAA, 0x80} },
422 { .data = {0xAB, 0x80} },
423 { .data = {0xAC, 0x80} },
424 { .data = {0xAD, 0x80} },
425 { .data = {0xAE, 0x80} },
426 { .data = {0xAF, 0x80} },
427 { .data = {0xB7, 0x76} },
428 { .data = {0xB8, 0x76} },
429 { .data = {0xB9, 0x05} },
430 { .data = {0xBA, 0x0D} },
431 { .data = {0xBB, 0x14} },
432 { .data = {0xBC, 0x0F} },
433 { .data = {0xBD, 0x18} },
434 { .data = {0xBE, 0x1F} },
435 { .data = {0xBF, 0x05} },
436 { .data = {0xC0, 0x0D} },
437 { .data = {0xC1, 0x14} },
438 { .data = {0xC2, 0x03} },
439 { .data = {0xC3, 0x07} },
440 { .data = {0xC4, 0x0A} },
441 { .data = {0xC5, 0xA0} },
442 { .data = {0xC6, 0x55} },
443 { .data = {0xC7, 0xFF} },
444 { .data = {0xC8, 0x39} },
445 { .data = {0xC9, 0x44} },
446 { .data = {0xCA, 0x12} },
447 { .data = {0xCD, 0x80} },
448 { .data = {0xDB, 0x80} },
449 { .data = {0xDC, 0x80} },
450 { .data = {0xDD, 0x80} },
451 { .data = {0xE0, 0x80} },
452 { .data = {0xE1, 0x80} },
453 { .data = {0xE2, 0x80} },
454 { .data = {0xE3, 0x80} },
455 { .data = {0xE4, 0x80} },
456 { .data = {0xE5, 0x40} },
457 { .data = {0xE6, 0x40} },
458 { .data = {0xE7, 0x40} },
459 { .data = {0xE8, 0x40} },
460 { .data = {0xE9, 0x40} },
461 { .data = {0xEA, 0x40} },
462 { .data = {0xEB, 0x40} },
463 { .data = {0xEC, 0x40} },
464 { .data = {0xED, 0x40} },
465 { .data = {0xEE, 0x40} },
466 { .data = {0xEF, 0x40} },
467 { .data = {0xF0, 0x40} },
468 { .data = {0xF1, 0x40} },
469 { .data = {0xF2, 0x40} },
470 { .data = {0xF3, 0x40} },
471 { .data = {0xF4, 0x40} },
472 { .data = {0xF5, 0x40} },
473 { .data = {0xF6, 0x40} },
474 { .data = {0xFB, 0x1} },
475 { .data = {0xFF, 0x23} },
476 { .data = {0xFB, 0x01} },
477 /* dimming enable */
478 { .data = {0x01, 0x84} },
479 { .data = {0x05, 0x2D} },
480 { .data = {0x06, 0x00} },
481 /* resolution 1080*2246 */
482 { .data = {0x11, 0x01} },
483 { .data = {0x12, 0x7B} },
484 { .data = {0x15, 0x6F} },
485 { .data = {0x16, 0x0B} },
486 /* UI mode */
487 { .data = {0x29, 0x0A} },
488 { .data = {0x30, 0xFF} },
489 { .data = {0x31, 0xFF} },
490 { .data = {0x32, 0xFF} },
491 { .data = {0x33, 0xFF} },
492 { .data = {0x34, 0xFF} },
493 { .data = {0x35, 0xFF} },
494 { .data = {0x36, 0xFF} },
495 { .data = {0x37, 0xFF} },
496 { .data = {0x38, 0xFC} },
497 { .data = {0x39, 0xF8} },
498 { .data = {0x3A, 0xF4} },
499 { .data = {0x3B, 0xF1} },
500 { .data = {0x3D, 0xEE} },
501 { .data = {0x3F, 0xEB} },
502 { .data = {0x40, 0xE8} },
503 { .data = {0x41, 0xE5} },
504 /* STILL mode */
505 { .data = {0x2A, 0x13} },
506 { .data = {0x45, 0xFF} },
507 { .data = {0x46, 0xFF} },
508 { .data = {0x47, 0xFF} },
509 { .data = {0x48, 0xFF} },
510 { .data = {0x49, 0xFF} },
511 { .data = {0x4A, 0xFF} },
512 { .data = {0x4B, 0xFF} },
513 { .data = {0x4C, 0xFF} },
514 { .data = {0x4D, 0xED} },
515 { .data = {0x4E, 0xD5} },
516 { .data = {0x4F, 0xBF} },
517 { .data = {0x50, 0xA6} },
518 { .data = {0x51, 0x96} },
519 { .data = {0x52, 0x86} },
520 { .data = {0x53, 0x76} },
521 { .data = {0x54, 0x66} },
522 /* MOVING mode */
523 { .data = {0x2B, 0x0E} },
524 { .data = {0x58, 0xFF} },
525 { .data = {0x59, 0xFF} },
526 { .data = {0x5A, 0xFF} },
527 { .data = {0x5B, 0xFF} },
528 { .data = {0x5C, 0xFF} },
529 { .data = {0x5D, 0xFF} },
530 { .data = {0x5E, 0xFF} },
531 { .data = {0x5F, 0xFF} },
532 { .data = {0x60, 0xF6} },
533 { .data = {0x61, 0xEA} },
534 { .data = {0x62, 0xE1} },
535 { .data = {0x63, 0xD8} },
536 { .data = {0x64, 0xCE} },
537 { .data = {0x65, 0xC3} },
538 { .data = {0x66, 0xBA} },
539 { .data = {0x67, 0xB3} },
540 { .data = {0xFF, 0x25} },
541 { .data = {0xFB, 0x01} },
542 { .data = {0x05, 0x04} },
543 { .data = {0xFF, 0x26} },
544 { .data = {0xFB, 0x01} },
545 { .data = {0x1C, 0xAF} },
546 { .data = {0xFF, 0x10} },
547 { .data = {0xFB, 0x01} },
548 { .data = {0x51, 0xFF} },
549 { .data = {0x53, 0x24} },
550 { .data = {0x55, 0x00} },
551};
552
553static const struct nt36672a_panel_cmd tianma_fhd_video_on_cmds_2[] = {
554 { .data = {0xFF, 0x24} },
555 { .data = {0xFB, 0x01} },
556 { .data = {0xC3, 0x01} },
557 { .data = {0xC4, 0x54} },
558 { .data = {0xFF, 0x10} },
559};
560
561static const struct nt36672a_panel_cmd tianma_fhd_video_off_cmds[] = {
562 { .data = {0xFF, 0x24} },
563 { .data = {0xFB, 0x01} },
564 { .data = {0xC3, 0x01} },
565 { .data = {0xFF, 0x10} },
566};
567
568static const struct drm_display_mode tianma_fhd_video_panel_default_mode = {
569 .clock = 161331,
570
571 .hdisplay = 1080,
572 .hsync_start = 1080 + 40,
573 .hsync_end = 1080 + 40 + 20,
574 .htotal = 1080 + 40 + 20 + 44,
575
576 .vdisplay = 2246,
577 .vsync_start = 2246 + 15,
578 .vsync_end = 2246 + 15 + 2,
579 .vtotal = 2246 + 15 + 2 + 8,
580
581 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
582};
583
584static const struct nt36672a_panel_desc tianma_fhd_video_panel_desc = {
585 .display_mode = &tianma_fhd_video_panel_default_mode,
586
587 .width_mm = 68,
588 .height_mm = 136,
589
590 .mode_flags = MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO
591 | MIPI_DSI_MODE_VIDEO_HSE
592 | MIPI_DSI_CLOCK_NON_CONTINUOUS
593 | MIPI_DSI_MODE_VIDEO_BURST,
594 .format = MIPI_DSI_FMT_RGB888,
595 .lanes = 4,
596 .on_cmds_1 = tianma_fhd_video_on_cmds_1,
597 .num_on_cmds_1 = ARRAY_SIZE(tianma_fhd_video_on_cmds_1),
598 .on_cmds_2 = tianma_fhd_video_on_cmds_2,
599 .num_on_cmds_2 = ARRAY_SIZE(tianma_fhd_video_on_cmds_2),
600 .off_cmds = tianma_fhd_video_off_cmds,
601 .num_off_cmds = ARRAY_SIZE(tianma_fhd_video_off_cmds),
602};
603
604static int nt36672a_panel_add(struct nt36672a_panel *pinfo)
605{
606 struct device *dev = &pinfo->link->dev;
607 int i, ret;
608
609 for (i = 0; i < ARRAY_SIZE(pinfo->supplies); i++)
610 pinfo->supplies[i].supply = nt36672a_regulator_names[i];
611
612 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pinfo->supplies),
613 pinfo->supplies);
614 if (ret < 0)
615 return dev_err_probe(dev, ret, "failed to get regulators\n");
616
617 for (i = 0; i < ARRAY_SIZE(pinfo->supplies); i++) {
618 ret = regulator_set_load(pinfo->supplies[i].consumer,
619 nt36672a_regulator_enable_loads[i]);
620 if (ret)
621 return dev_err_probe(dev, ret, "failed to set regulator enable loads\n");
622 }
623
624 pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
625 if (IS_ERR(pinfo->reset_gpio))
626 return dev_err_probe(dev, PTR_ERR(pinfo->reset_gpio),
627 "failed to get reset gpio from DT\n");
628
629 drm_panel_init(&pinfo->base, dev, &panel_funcs, DRM_MODE_CONNECTOR_DSI);
630
631 ret = drm_panel_of_backlight(&pinfo->base);
632 if (ret)
633 return dev_err_probe(dev, ret, "Failed to get backlight\n");
634
635 drm_panel_add(&pinfo->base);
636
637 return 0;
638}
639
640static int nt36672a_panel_probe(struct mipi_dsi_device *dsi)
641{
642 struct nt36672a_panel *pinfo;
643 const struct nt36672a_panel_desc *desc;
644 int err;
645
646 pinfo = devm_kzalloc(&dsi->dev, sizeof(*pinfo), GFP_KERNEL);
647 if (!pinfo)
648 return -ENOMEM;
649
650 desc = of_device_get_match_data(&dsi->dev);
651 dsi->mode_flags = desc->mode_flags;
652 dsi->format = desc->format;
653 dsi->lanes = desc->lanes;
654 pinfo->desc = desc;
655 pinfo->link = dsi;
656
657 mipi_dsi_set_drvdata(dsi, pinfo);
658
659 err = nt36672a_panel_add(pinfo);
660 if (err < 0)
661 return err;
662
663 err = mipi_dsi_attach(dsi);
664 if (err < 0) {
665 drm_panel_remove(&pinfo->base);
666 return err;
667 }
668
669 return 0;
670}
671
672static void nt36672a_panel_remove(struct mipi_dsi_device *dsi)
673{
674 struct nt36672a_panel *pinfo = mipi_dsi_get_drvdata(dsi);
675 int err;
676
677 err = drm_panel_unprepare(&pinfo->base);
678 if (err < 0)
679 dev_err(&dsi->dev, "failed to unprepare panel: %d\n", err);
680
681 err = drm_panel_disable(&pinfo->base);
682 if (err < 0)
683 dev_err(&dsi->dev, "failed to disable panel: %d\n", err);
684
685 err = mipi_dsi_detach(dsi);
686 if (err < 0)
687 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
688
689 drm_panel_remove(&pinfo->base);
690}
691
692static void nt36672a_panel_shutdown(struct mipi_dsi_device *dsi)
693{
694 struct nt36672a_panel *pinfo = mipi_dsi_get_drvdata(dsi);
695
696 drm_panel_disable(&pinfo->base);
697 drm_panel_unprepare(&pinfo->base);
698}
699
700static const struct of_device_id tianma_fhd_video_of_match[] = {
701 { .compatible = "tianma,fhd-video", .data = &tianma_fhd_video_panel_desc },
702 { },
703};
704MODULE_DEVICE_TABLE(of, tianma_fhd_video_of_match);
705
706static struct mipi_dsi_driver nt36672a_panel_driver = {
707 .driver = {
708 .name = "panel-tianma-nt36672a",
709 .of_match_table = tianma_fhd_video_of_match,
710 },
711 .probe = nt36672a_panel_probe,
712 .remove = nt36672a_panel_remove,
713 .shutdown = nt36672a_panel_shutdown,
714};
715module_mipi_dsi_driver(nt36672a_panel_driver);
716
717MODULE_AUTHOR("Sumit Semwal <sumit.semwal@linaro.org>");
718MODULE_DESCRIPTION("NOVATEK NT36672A based MIPI-DSI LCD panel driver");
719MODULE_LICENSE("GPL");