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1/*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/interconnect.h>
9#include <linux/irq.h>
10#include <linux/irqchip.h>
11#include <linux/irqdesc.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/pm_runtime.h>
14#include <linux/reset.h>
15
16#include "msm_drv.h"
17#include "msm_kms.h"
18
19/* for DPU_HW_* defines */
20#include "disp/dpu1/dpu_hw_catalog.h"
21
22#define HW_REV 0x0
23#define HW_INTR_STATUS 0x0010
24
25#define UBWC_DEC_HW_VERSION 0x58
26#define UBWC_STATIC 0x144
27#define UBWC_CTRL_2 0x150
28#define UBWC_PREDICTION_MODE 0x154
29
30#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
31
32struct msm_mdss {
33 struct device *dev;
34
35 void __iomem *mmio;
36 struct clk_bulk_data *clocks;
37 size_t num_clocks;
38 bool is_mdp5;
39 struct {
40 unsigned long enabled_mask;
41 struct irq_domain *domain;
42 } irq_controller;
43 struct icc_path *path[2];
44 u32 num_paths;
45};
46
47static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
48 struct msm_mdss *msm_mdss)
49{
50 struct icc_path *path0;
51 struct icc_path *path1;
52
53 path0 = of_icc_get(dev, "mdp0-mem");
54 if (IS_ERR_OR_NULL(path0))
55 return PTR_ERR_OR_ZERO(path0);
56
57 msm_mdss->path[0] = path0;
58 msm_mdss->num_paths = 1;
59
60 path1 = of_icc_get(dev, "mdp1-mem");
61 if (!IS_ERR_OR_NULL(path1)) {
62 msm_mdss->path[1] = path1;
63 msm_mdss->num_paths++;
64 }
65
66 return 0;
67}
68
69static void msm_mdss_put_icc_path(void *data)
70{
71 struct msm_mdss *msm_mdss = data;
72 int i;
73
74 for (i = 0; i < msm_mdss->num_paths; i++)
75 icc_put(msm_mdss->path[i]);
76}
77
78static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw)
79{
80 int i;
81
82 for (i = 0; i < msm_mdss->num_paths; i++)
83 icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw));
84}
85
86static void msm_mdss_irq(struct irq_desc *desc)
87{
88 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
89 struct irq_chip *chip = irq_desc_get_chip(desc);
90 u32 interrupts;
91
92 chained_irq_enter(chip, desc);
93
94 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);
95
96 while (interrupts) {
97 irq_hw_number_t hwirq = fls(interrupts) - 1;
98 int rc;
99
100 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
101 hwirq);
102 if (rc < 0) {
103 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
104 hwirq, rc);
105 break;
106 }
107
108 interrupts &= ~(1 << hwirq);
109 }
110
111 chained_irq_exit(chip, desc);
112}
113
114static void msm_mdss_irq_mask(struct irq_data *irqd)
115{
116 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
117
118 /* memory barrier */
119 smp_mb__before_atomic();
120 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
121 /* memory barrier */
122 smp_mb__after_atomic();
123}
124
125static void msm_mdss_irq_unmask(struct irq_data *irqd)
126{
127 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
128
129 /* memory barrier */
130 smp_mb__before_atomic();
131 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
132 /* memory barrier */
133 smp_mb__after_atomic();
134}
135
136static struct irq_chip msm_mdss_irq_chip = {
137 .name = "msm_mdss",
138 .irq_mask = msm_mdss_irq_mask,
139 .irq_unmask = msm_mdss_irq_unmask,
140};
141
142static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key;
143
144static int msm_mdss_irqdomain_map(struct irq_domain *domain,
145 unsigned int irq, irq_hw_number_t hwirq)
146{
147 struct msm_mdss *msm_mdss = domain->host_data;
148
149 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key);
150 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq);
151
152 return irq_set_chip_data(irq, msm_mdss);
153}
154
155static const struct irq_domain_ops msm_mdss_irqdomain_ops = {
156 .map = msm_mdss_irqdomain_map,
157 .xlate = irq_domain_xlate_onecell,
158};
159
160static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
161{
162 struct device *dev;
163 struct irq_domain *domain;
164
165 dev = msm_mdss->dev;
166
167 domain = irq_domain_add_linear(dev->of_node, 32,
168 &msm_mdss_irqdomain_ops, msm_mdss);
169 if (!domain) {
170 dev_err(dev, "failed to add irq_domain\n");
171 return -EINVAL;
172 }
173
174 msm_mdss->irq_controller.enabled_mask = 0;
175 msm_mdss->irq_controller.domain = domain;
176
177 return 0;
178}
179
180#define UBWC_1_0 0x10000000
181#define UBWC_2_0 0x20000000
182#define UBWC_3_0 0x30000000
183#define UBWC_4_0 0x40000000
184
185static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss,
186 u32 ubwc_static)
187{
188 writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC);
189}
190
191static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss,
192 unsigned int ubwc_version,
193 u32 ubwc_swizzle,
194 u32 highest_bank_bit,
195 u32 macrotile_mode)
196{
197 u32 value = (ubwc_swizzle & 0x1) |
198 (highest_bank_bit & 0x3) << 4 |
199 (macrotile_mode & 0x1) << 12;
200
201 if (ubwc_version == UBWC_3_0)
202 value |= BIT(10);
203
204 if (ubwc_version == UBWC_1_0)
205 value |= BIT(8);
206
207 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
208}
209
210static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss,
211 unsigned int ubwc_version,
212 u32 ubwc_swizzle,
213 u32 ubwc_static,
214 u32 highest_bank_bit,
215 u32 macrotile_mode)
216{
217 u32 value = (ubwc_swizzle & 0x7) |
218 (ubwc_static & 0x1) << 3 |
219 (highest_bank_bit & 0x7) << 4 |
220 (macrotile_mode & 0x1) << 12;
221
222 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
223
224 if (ubwc_version == UBWC_3_0) {
225 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
226 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
227 } else {
228 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
229 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
230 }
231}
232
233static int msm_mdss_enable(struct msm_mdss *msm_mdss)
234{
235 int ret;
236 u32 hw_rev;
237
238 /*
239 * Several components have AXI clocks that can only be turned on if
240 * the interconnect is enabled (non-zero bandwidth). Let's make sure
241 * that the interconnects are at least at a minimum amount.
242 */
243 msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW);
244
245 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
246 if (ret) {
247 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
248 return ret;
249 }
250
251 /*
252 * HW_REV requires MDSS_MDP_CLK, which is not enabled by the mdss on
253 * mdp5 hardware. Skip reading it for now.
254 */
255 if (msm_mdss->is_mdp5)
256 return 0;
257
258 hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV);
259 dev_dbg(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev);
260 dev_dbg(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
261 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
262
263 /*
264 * ubwc config is part of the "mdss" region which is not accessible
265 * from the rest of the driver. hardcode known configurations here
266 *
267 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
268 * UBWC_n and the rest of params comes from hw_catalog.
269 * Unforunately this driver can not access hw catalog, so we have to
270 * hardcode them here.
271 */
272 switch (hw_rev) {
273 case DPU_HW_VER_500:
274 case DPU_HW_VER_501:
275 msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0);
276 break;
277 case DPU_HW_VER_600:
278 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
279 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
280 break;
281 case DPU_HW_VER_620:
282 /* UBWC_2_0 */
283 msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
284 break;
285 case DPU_HW_VER_630:
286 /* UBWC_2_0 */
287 msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f);
288 break;
289 case DPU_HW_VER_720:
290 msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
291 break;
292 }
293
294 return ret;
295}
296
297static int msm_mdss_disable(struct msm_mdss *msm_mdss)
298{
299 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
300 msm_mdss_icc_request_bw(msm_mdss, 0);
301
302 return 0;
303}
304
305static void msm_mdss_destroy(struct msm_mdss *msm_mdss)
306{
307 struct platform_device *pdev = to_platform_device(msm_mdss->dev);
308 int irq;
309
310 pm_runtime_suspend(msm_mdss->dev);
311 pm_runtime_disable(msm_mdss->dev);
312 irq_domain_remove(msm_mdss->irq_controller.domain);
313 msm_mdss->irq_controller.domain = NULL;
314 irq = platform_get_irq(pdev, 0);
315 irq_set_chained_handler_and_data(irq, NULL, NULL);
316}
317
318static int msm_mdss_reset(struct device *dev)
319{
320 struct reset_control *reset;
321
322 reset = reset_control_get_optional_exclusive(dev, NULL);
323 if (!reset) {
324 /* Optional reset not specified */
325 return 0;
326 } else if (IS_ERR(reset)) {
327 return dev_err_probe(dev, PTR_ERR(reset),
328 "failed to acquire mdss reset\n");
329 }
330
331 reset_control_assert(reset);
332 /*
333 * Tests indicate that reset has to be held for some period of time,
334 * make it one frame in a typical system
335 */
336 msleep(20);
337 reset_control_deassert(reset);
338
339 reset_control_put(reset);
340
341 return 0;
342}
343
344/*
345 * MDP5 MDSS uses at most three specified clocks.
346 */
347#define MDP5_MDSS_NUM_CLOCKS 3
348static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks)
349{
350 struct clk_bulk_data *bulk;
351 int num_clocks = 0;
352 int ret;
353
354 if (!pdev)
355 return -EINVAL;
356
357 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
358 if (!bulk)
359 return -ENOMEM;
360
361 bulk[num_clocks++].id = "iface";
362 bulk[num_clocks++].id = "bus";
363 bulk[num_clocks++].id = "vsync";
364
365 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
366 if (ret)
367 return ret;
368
369 *clocks = bulk;
370
371 return num_clocks;
372}
373
374static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
375{
376 struct msm_mdss *msm_mdss;
377 int ret;
378 int irq;
379
380 ret = msm_mdss_reset(&pdev->dev);
381 if (ret)
382 return ERR_PTR(ret);
383
384 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
385 if (!msm_mdss)
386 return ERR_PTR(-ENOMEM);
387
388 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
389 if (IS_ERR(msm_mdss->mmio))
390 return ERR_CAST(msm_mdss->mmio);
391
392 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
393
394 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
395 if (ret)
396 return ERR_PTR(ret);
397 ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss);
398 if (ret)
399 return ERR_PTR(ret);
400
401 if (is_mdp5)
402 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
403 else
404 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
405 if (ret < 0) {
406 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
407 return ERR_PTR(ret);
408 }
409 msm_mdss->num_clocks = ret;
410 msm_mdss->is_mdp5 = is_mdp5;
411
412 msm_mdss->dev = &pdev->dev;
413
414 irq = platform_get_irq(pdev, 0);
415 if (irq < 0)
416 return ERR_PTR(irq);
417
418 ret = _msm_mdss_irq_domain_add(msm_mdss);
419 if (ret)
420 return ERR_PTR(ret);
421
422 irq_set_chained_handler_and_data(irq, msm_mdss_irq,
423 msm_mdss);
424
425 pm_runtime_enable(&pdev->dev);
426
427 return msm_mdss;
428}
429
430static int __maybe_unused mdss_runtime_suspend(struct device *dev)
431{
432 struct msm_mdss *mdss = dev_get_drvdata(dev);
433
434 DBG("");
435
436 return msm_mdss_disable(mdss);
437}
438
439static int __maybe_unused mdss_runtime_resume(struct device *dev)
440{
441 struct msm_mdss *mdss = dev_get_drvdata(dev);
442
443 DBG("");
444
445 return msm_mdss_enable(mdss);
446}
447
448static int __maybe_unused mdss_pm_suspend(struct device *dev)
449{
450
451 if (pm_runtime_suspended(dev))
452 return 0;
453
454 return mdss_runtime_suspend(dev);
455}
456
457static int __maybe_unused mdss_pm_resume(struct device *dev)
458{
459 if (pm_runtime_suspended(dev))
460 return 0;
461
462 return mdss_runtime_resume(dev);
463}
464
465static const struct dev_pm_ops mdss_pm_ops = {
466 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume)
467 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL)
468};
469
470static int mdss_probe(struct platform_device *pdev)
471{
472 struct msm_mdss *mdss;
473 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
474 struct device *dev = &pdev->dev;
475 int ret;
476
477 mdss = msm_mdss_init(pdev, is_mdp5);
478 if (IS_ERR(mdss))
479 return PTR_ERR(mdss);
480
481 platform_set_drvdata(pdev, mdss);
482
483 /*
484 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
485 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
486 * Populate the children devices, find the MDP5/DPU node, and then add
487 * the interfaces to our components list.
488 */
489 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
490 if (ret) {
491 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
492 msm_mdss_destroy(mdss);
493 return ret;
494 }
495
496 return 0;
497}
498
499static int mdss_remove(struct platform_device *pdev)
500{
501 struct msm_mdss *mdss = platform_get_drvdata(pdev);
502
503 of_platform_depopulate(&pdev->dev);
504
505 msm_mdss_destroy(mdss);
506
507 return 0;
508}
509
510static const struct of_device_id mdss_dt_match[] = {
511 { .compatible = "qcom,mdss" },
512 { .compatible = "qcom,msm8998-mdss" },
513 { .compatible = "qcom,qcm2290-mdss" },
514 { .compatible = "qcom,sdm845-mdss" },
515 { .compatible = "qcom,sc7180-mdss" },
516 { .compatible = "qcom,sc7280-mdss" },
517 { .compatible = "qcom,sc8180x-mdss" },
518 { .compatible = "qcom,sm6115-mdss" },
519 { .compatible = "qcom,sm8150-mdss" },
520 { .compatible = "qcom,sm8250-mdss" },
521 {}
522};
523MODULE_DEVICE_TABLE(of, mdss_dt_match);
524
525static struct platform_driver mdss_platform_driver = {
526 .probe = mdss_probe,
527 .remove = mdss_remove,
528 .driver = {
529 .name = "msm-mdss",
530 .of_match_table = mdss_dt_match,
531 .pm = &mdss_pm_ops,
532 },
533};
534
535void __init msm_mdss_register(void)
536{
537 platform_driver_register(&mdss_platform_driver);
538}
539
540void __exit msm_mdss_unregister(void)
541{
542 platform_driver_unregister(&mdss_platform_driver);
543}