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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/module.h>
15#include <linux/component.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/list.h>
21#include <linux/iommu.h>
22#include <linux/types.h>
23#include <linux/of_graph.h>
24#include <linux/of_device.h>
25#include <linux/sizes.h>
26#include <linux/kthread.h>
27
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_probe_helper.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/display/drm_dsc.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36#ifdef CONFIG_FAULT_INJECTION
37extern struct fault_attr fail_gem_alloc;
38extern struct fault_attr fail_gem_iova;
39#else
40# define should_fail(attr, size) 0
41#endif
42
43struct msm_kms;
44struct msm_gpu;
45struct msm_mmu;
46struct msm_mdss;
47struct msm_rd_state;
48struct msm_perf_state;
49struct msm_gem_submit;
50struct msm_fence_context;
51struct msm_gem_address_space;
52struct msm_gem_vma;
53struct msm_disp_state;
54
55#define MAX_CRTCS 8
56#define MAX_BRIDGES 8
57
58#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
59
60enum msm_dp_controller {
61 MSM_DP_CONTROLLER_0,
62 MSM_DP_CONTROLLER_1,
63 MSM_DP_CONTROLLER_2,
64 MSM_DP_CONTROLLER_COUNT,
65};
66
67#define MSM_GPU_MAX_RINGS 4
68#define MAX_H_TILES_PER_DISPLAY 2
69
70/**
71 * enum msm_event_wait - type of HW events to wait for
72 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
73 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
74 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
75 */
76enum msm_event_wait {
77 MSM_ENC_COMMIT_DONE = 0,
78 MSM_ENC_TX_COMPLETE,
79 MSM_ENC_VBLANK,
80};
81
82/**
83 * struct msm_display_topology - defines a display topology pipeline
84 * @num_lm: number of layer mixers used
85 * @num_enc: number of compression encoder blocks used
86 * @num_intf: number of interfaces the panel is mounted on
87 * @num_dspp: number of dspp blocks used
88 * @num_dsc: number of Display Stream Compression (DSC) blocks used
89 */
90struct msm_display_topology {
91 u32 num_lm;
92 u32 num_enc;
93 u32 num_intf;
94 u32 num_dspp;
95 u32 num_dsc;
96};
97
98/* Commit/Event thread specific structure */
99struct msm_drm_thread {
100 struct drm_device *dev;
101 unsigned int crtc_id;
102 struct kthread_worker *worker;
103};
104
105struct msm_drm_private {
106
107 struct drm_device *dev;
108
109 struct msm_kms *kms;
110 int (*kms_init)(struct drm_device *dev);
111
112 /* subordinate devices, if present: */
113 struct platform_device *gpu_pdev;
114
115 /* possibly this should be in the kms component, but it is
116 * shared by both mdp4 and mdp5..
117 */
118 struct hdmi *hdmi;
119
120 /* DSI is shared by mdp4 and mdp5 */
121 struct msm_dsi *dsi[2];
122
123 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT];
124
125 /* when we have more than one 'msm_gpu' these need to be an array: */
126 struct msm_gpu *gpu;
127
128 /* gpu is only set on open(), but we need this info earlier */
129 bool is_a2xx;
130 bool has_cached_coherent;
131
132 struct drm_fb_helper *fbdev;
133
134 struct msm_rd_state *rd; /* debugfs to dump all submits */
135 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
136 struct msm_perf_state *perf;
137
138 /**
139 * List of all GEM objects (mainly for debugfs, protected by obj_lock
140 * (acquire before per GEM object lock)
141 */
142 struct list_head objects;
143 struct mutex obj_lock;
144
145 /**
146 * lru:
147 *
148 * The various LRU's that a GEM object is in at various stages of
149 * it's lifetime. Objects start out in the unbacked LRU. When
150 * pinned (for scannout or permanently mapped GPU buffers, like
151 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When
152 * unpinned, it moves into willneed or dontneed LRU depending on
153 * madvise state. When backing pages are evicted (willneed) or
154 * purged (dontneed) it moves back into the unbacked LRU.
155 *
156 * The dontneed LRU is considered by the shrinker for objects
157 * that are candidate for purging, and the willneed LRU is
158 * considered for objects that could be evicted.
159 */
160 struct {
161 /**
162 * unbacked:
163 *
164 * The LRU for GEM objects without backing pages allocated.
165 * This mostly exists so that objects are always is one
166 * LRU.
167 */
168 struct drm_gem_lru unbacked;
169
170 /**
171 * pinned:
172 *
173 * The LRU for pinned GEM objects
174 */
175 struct drm_gem_lru pinned;
176
177 /**
178 * willneed:
179 *
180 * The LRU for unpinned GEM objects which are in madvise
181 * WILLNEED state (ie. can be evicted)
182 */
183 struct drm_gem_lru willneed;
184
185 /**
186 * dontneed:
187 *
188 * The LRU for unpinned GEM objects which are in madvise
189 * DONTNEED state (ie. can be purged)
190 */
191 struct drm_gem_lru dontneed;
192
193 /**
194 * lock:
195 *
196 * Protects manipulation of all of the LRUs.
197 */
198 struct mutex lock;
199 } lru;
200
201 struct workqueue_struct *wq;
202
203 unsigned int num_crtcs;
204 struct drm_crtc *crtcs[MAX_CRTCS];
205
206 struct msm_drm_thread event_thread[MAX_CRTCS];
207
208 unsigned int num_bridges;
209 struct drm_bridge *bridges[MAX_BRIDGES];
210
211 /* VRAM carveout, used when no IOMMU: */
212 struct {
213 unsigned long size;
214 dma_addr_t paddr;
215 /* NOTE: mm managed at the page level, size is in # of pages
216 * and position mm_node->start is in # of pages:
217 */
218 struct drm_mm mm;
219 spinlock_t lock; /* Protects drm_mm node allocation/removal */
220 } vram;
221
222 struct notifier_block vmap_notifier;
223 struct shrinker shrinker;
224
225 struct drm_atomic_state *pm_state;
226
227 /**
228 * hangcheck_period: For hang detection, in ms
229 *
230 * Note that in practice, a submit/job will get at least two hangcheck
231 * periods, due to checking for progress being implemented as simply
232 * "have the CP position registers changed since last time?"
233 */
234 unsigned int hangcheck_period;
235
236 /**
237 * disable_err_irq:
238 *
239 * Disable handling of GPU hw error interrupts, to force fallback to
240 * sw hangcheck timer. Written (via debugfs) by igt tests to test
241 * the sw hangcheck mechanism.
242 */
243 bool disable_err_irq;
244};
245
246struct msm_format {
247 uint32_t pixel_format;
248};
249
250struct msm_pending_timer;
251
252int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
253 struct msm_kms *kms, int crtc_idx);
254void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer);
255void msm_atomic_commit_tail(struct drm_atomic_state *state);
256struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
257void msm_atomic_state_clear(struct drm_atomic_state *state);
258void msm_atomic_state_free(struct drm_atomic_state *state);
259
260int msm_crtc_enable_vblank(struct drm_crtc *crtc);
261void msm_crtc_disable_vblank(struct drm_crtc *crtc);
262
263int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
264void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
265
266struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev);
267bool msm_use_mmu(struct drm_device *dev);
268
269int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
270 struct drm_file *file);
271
272#ifdef CONFIG_DEBUG_FS
273unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan);
274#endif
275
276void msm_gem_shrinker_init(struct drm_device *dev);
277void msm_gem_shrinker_cleanup(struct drm_device *dev);
278
279int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
280struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
281int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
282void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
283struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
284 struct dma_buf_attachment *attach, struct sg_table *sg);
285int msm_gem_prime_pin(struct drm_gem_object *obj);
286void msm_gem_prime_unpin(struct drm_gem_object *obj);
287
288int msm_framebuffer_prepare(struct drm_framebuffer *fb,
289 struct msm_gem_address_space *aspace, bool needs_dirtyfb);
290void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
291 struct msm_gem_address_space *aspace, bool needed_dirtyfb);
292uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
293 struct msm_gem_address_space *aspace, int plane);
294struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
295const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
296struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
297 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
298struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
299 int w, int h, int p, uint32_t format);
300
301struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
302void msm_fbdev_free(struct drm_device *dev);
303
304struct hdmi;
305#ifdef CONFIG_DRM_MSM_HDMI
306int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
307 struct drm_encoder *encoder);
308void __init msm_hdmi_register(void);
309void __exit msm_hdmi_unregister(void);
310#else
311static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
312 struct drm_encoder *encoder)
313{
314 return -EINVAL;
315}
316static inline void __init msm_hdmi_register(void) {}
317static inline void __exit msm_hdmi_unregister(void) {}
318#endif
319
320struct msm_dsi;
321#ifdef CONFIG_DRM_MSM_DSI
322int dsi_dev_attach(struct platform_device *pdev);
323void dsi_dev_detach(struct platform_device *pdev);
324void __init msm_dsi_register(void);
325void __exit msm_dsi_unregister(void);
326int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
327 struct drm_encoder *encoder);
328void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi);
329bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
330bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
331bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
332struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
333#else
334static inline void __init msm_dsi_register(void)
335{
336}
337static inline void __exit msm_dsi_unregister(void)
338{
339}
340static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
341 struct drm_device *dev,
342 struct drm_encoder *encoder)
343{
344 return -EINVAL;
345}
346static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi)
347{
348}
349static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
350{
351 return false;
352}
353static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi)
354{
355 return false;
356}
357static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
358{
359 return false;
360}
361
362static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
363{
364 return NULL;
365}
366#endif
367
368#ifdef CONFIG_DRM_MSM_DP
369int __init msm_dp_register(void);
370void __exit msm_dp_unregister(void);
371int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
372 struct drm_encoder *encoder);
373void msm_dp_irq_postinstall(struct msm_dp *dp_display);
374void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);
375
376void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
377bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);
378
379#else
380static inline int __init msm_dp_register(void)
381{
382 return -EINVAL;
383}
384static inline void __exit msm_dp_unregister(void)
385{
386}
387static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
388 struct drm_device *dev,
389 struct drm_encoder *encoder)
390{
391 return -EINVAL;
392}
393
394static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
395{
396}
397
398static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display)
399{
400}
401
402static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
403 struct drm_minor *minor)
404{
405}
406
407static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)
408{
409 return false;
410}
411
412#endif
413
414#ifdef CONFIG_DRM_MSM_MDP4
415void msm_mdp4_register(void);
416void msm_mdp4_unregister(void);
417#else
418static inline void msm_mdp4_register(void) {}
419static inline void msm_mdp4_unregister(void) {}
420#endif
421
422#ifdef CONFIG_DRM_MSM_MDP5
423void msm_mdp_register(void);
424void msm_mdp_unregister(void);
425#else
426static inline void msm_mdp_register(void) {}
427static inline void msm_mdp_unregister(void) {}
428#endif
429
430#ifdef CONFIG_DRM_MSM_DPU
431void msm_dpu_register(void);
432void msm_dpu_unregister(void);
433#else
434static inline void msm_dpu_register(void) {}
435static inline void msm_dpu_unregister(void) {}
436#endif
437
438#ifdef CONFIG_DRM_MSM_MDSS
439void msm_mdss_register(void);
440void msm_mdss_unregister(void);
441#else
442static inline void msm_mdss_register(void) {}
443static inline void msm_mdss_unregister(void) {}
444#endif
445
446#ifdef CONFIG_DEBUG_FS
447void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
448int msm_debugfs_late_init(struct drm_device *dev);
449int msm_rd_debugfs_init(struct drm_minor *minor);
450void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
451__printf(3, 4)
452void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
453 const char *fmt, ...);
454int msm_perf_debugfs_init(struct drm_minor *minor);
455void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
456#else
457static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
458__printf(3, 4)
459static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
460 struct msm_gem_submit *submit,
461 const char *fmt, ...) {}
462static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
463static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
464#endif
465
466struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
467
468struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
469 const char *name);
470void __iomem *msm_ioremap(struct platform_device *pdev, const char *name);
471void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
472 phys_addr_t *size);
473void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name);
474
475struct icc_path *msm_icc_get(struct device *dev, const char *name);
476
477#define msm_writel(data, addr) writel((data), (addr))
478#define msm_readl(addr) readl((addr))
479
480static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
481{
482 u32 val = msm_readl(addr);
483
484 val &= ~mask;
485 msm_writel(val | or, addr);
486}
487
488/**
489 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work
490 *
491 * @timer: hrtimer to control when the kthread work is triggered
492 * @work: the kthread work
493 * @worker: the kthread worker the work will be scheduled on
494 */
495struct msm_hrtimer_work {
496 struct hrtimer timer;
497 struct kthread_work work;
498 struct kthread_worker *worker;
499};
500
501void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
502 ktime_t wakeup_time,
503 enum hrtimer_mode mode);
504void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
505 struct kthread_worker *worker,
506 kthread_work_func_t fn,
507 clockid_t clock_id,
508 enum hrtimer_mode mode);
509
510#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
511#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
512
513static inline int align_pitch(int width, int bpp)
514{
515 int bytespp = (bpp + 7) / 8;
516 /* adreno needs pitch aligned to 32 pixels: */
517 return bytespp * ALIGN(width, 32);
518}
519
520/* for the generated headers: */
521#define INVALID_IDX(idx) ({BUG(); 0;})
522#define fui(x) ({BUG(); 0;})
523#define _mesa_float_to_half(x) ({BUG(); 0;})
524
525
526#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
527
528/* for conditionally setting boolean flag(s): */
529#define COND(bool, val) ((bool) ? (val) : 0)
530
531static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
532{
533 ktime_t now = ktime_get();
534 s64 remaining_jiffies;
535
536 if (ktime_compare(*timeout, now) < 0) {
537 remaining_jiffies = 0;
538 } else {
539 ktime_t rem = ktime_sub(*timeout, now);
540 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
541 }
542
543 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX);
544}
545
546/* Driver helpers */
547
548extern const struct component_master_ops msm_drm_ops;
549
550int msm_pm_prepare(struct device *dev);
551void msm_pm_complete(struct device *dev);
552
553int msm_drv_probe(struct device *dev,
554 int (*kms_init)(struct drm_device *dev));
555void msm_drv_shutdown(struct platform_device *pdev);
556
557
558#endif /* __MSM_DRV_H__ */