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1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3 */
4
5#if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
6#define _DPU_TRACE_H_
7
8#include <linux/stringify.h>
9#include <linux/types.h>
10#include <linux/tracepoint.h>
11
12#include <drm/drm_rect.h>
13#include "dpu_crtc.h"
14#include "dpu_encoder_phys.h"
15#include "dpu_hw_mdss.h"
16#include "dpu_hw_vbif.h"
17#include "dpu_plane.h"
18
19#undef TRACE_SYSTEM
20#define TRACE_SYSTEM dpu
21#undef TRACE_INCLUDE_FILE
22#define TRACE_INCLUDE_FILE dpu_trace
23
24TRACE_EVENT(dpu_perf_set_qos_luts,
25 TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl,
26 u32 lut, u32 lut_usage),
27 TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage),
28 TP_STRUCT__entry(
29 __field(u32, pnum)
30 __field(u32, fmt)
31 __field(bool, rt)
32 __field(u32, fl)
33 __field(u64, lut)
34 __field(u32, lut_usage)
35 ),
36 TP_fast_assign(
37 __entry->pnum = pnum;
38 __entry->fmt = fmt;
39 __entry->rt = rt;
40 __entry->fl = fl;
41 __entry->lut = lut;
42 __entry->lut_usage = lut_usage;
43 ),
44 TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d",
45 __entry->pnum, __entry->fmt,
46 __entry->rt, __entry->fl,
47 __entry->lut, __entry->lut_usage)
48);
49
50TRACE_EVENT(dpu_perf_set_danger_luts,
51 TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut,
52 u32 safe_lut),
53 TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut),
54 TP_STRUCT__entry(
55 __field(u32, pnum)
56 __field(u32, fmt)
57 __field(u32, mode)
58 __field(u32, danger_lut)
59 __field(u32, safe_lut)
60 ),
61 TP_fast_assign(
62 __entry->pnum = pnum;
63 __entry->fmt = fmt;
64 __entry->mode = mode;
65 __entry->danger_lut = danger_lut;
66 __entry->safe_lut = safe_lut;
67 ),
68 TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]",
69 __entry->pnum, __entry->fmt,
70 __entry->mode, __entry->danger_lut,
71 __entry->safe_lut)
72);
73
74TRACE_EVENT(dpu_perf_set_ot,
75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx),
76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx),
77 TP_STRUCT__entry(
78 __field(u32, pnum)
79 __field(u32, xin_id)
80 __field(u32, rd_lim)
81 __field(u32, vbif_idx)
82 ),
83 TP_fast_assign(
84 __entry->pnum = pnum;
85 __entry->xin_id = xin_id;
86 __entry->rd_lim = rd_lim;
87 __entry->vbif_idx = vbif_idx;
88 ),
89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d",
90 __entry->pnum, __entry->xin_id, __entry->rd_lim,
91 __entry->vbif_idx)
92)
93
94TRACE_EVENT(dpu_cmd_release_bw,
95 TP_PROTO(u32 crtc_id),
96 TP_ARGS(crtc_id),
97 TP_STRUCT__entry(
98 __field(u32, crtc_id)
99 ),
100 TP_fast_assign(
101 __entry->crtc_id = crtc_id;
102 ),
103 TP_printk("crtc:%d", __entry->crtc_id)
104);
105
106TRACE_EVENT(tracing_mark_write,
107 TP_PROTO(int pid, const char *name, bool trace_begin),
108 TP_ARGS(pid, name, trace_begin),
109 TP_STRUCT__entry(
110 __field(int, pid)
111 __string(trace_name, name)
112 __field(bool, trace_begin)
113 ),
114 TP_fast_assign(
115 __entry->pid = pid;
116 __assign_str(trace_name, name);
117 __entry->trace_begin = trace_begin;
118 ),
119 TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E",
120 __entry->pid, __get_str(trace_name))
121)
122
123TRACE_EVENT(dpu_trace_counter,
124 TP_PROTO(int pid, char *name, int value),
125 TP_ARGS(pid, name, value),
126 TP_STRUCT__entry(
127 __field(int, pid)
128 __string(counter_name, name)
129 __field(int, value)
130 ),
131 TP_fast_assign(
132 __entry->pid = current->tgid;
133 __assign_str(counter_name, name);
134 __entry->value = value;
135 ),
136 TP_printk("%d|%s|%d", __entry->pid,
137 __get_str(counter_name), __entry->value)
138)
139
140TRACE_EVENT(dpu_perf_crtc_update,
141 TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate,
142 bool stop_req, bool update_bus, bool update_clk),
143 TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk),
144 TP_STRUCT__entry(
145 __field(u32, crtc)
146 __field(u64, bw_ctl)
147 __field(u32, core_clk_rate)
148 __field(bool, stop_req)
149 __field(u32, update_bus)
150 __field(u32, update_clk)
151 ),
152 TP_fast_assign(
153 __entry->crtc = crtc;
154 __entry->bw_ctl = bw_ctl;
155 __entry->core_clk_rate = core_clk_rate;
156 __entry->stop_req = stop_req;
157 __entry->update_bus = update_bus;
158 __entry->update_clk = update_clk;
159 ),
160 TP_printk(
161 "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d",
162 __entry->crtc,
163 __entry->bw_ctl,
164 __entry->core_clk_rate,
165 __entry->stop_req,
166 __entry->update_bus,
167 __entry->update_clk)
168);
169
170DECLARE_EVENT_CLASS(dpu_irq_template,
171 TP_PROTO(int irq_idx),
172 TP_ARGS(irq_idx),
173 TP_STRUCT__entry(
174 __field( int, irq_idx )
175 ),
176 TP_fast_assign(
177 __entry->irq_idx = irq_idx;
178 ),
179 TP_printk("irq=%d", __entry->irq_idx)
180);
181DEFINE_EVENT(dpu_irq_template, dpu_irq_register_success,
182 TP_PROTO(int irq_idx),
183 TP_ARGS(irq_idx)
184);
185DEFINE_EVENT(dpu_irq_template, dpu_irq_unregister_success,
186 TP_PROTO(int irq_idx),
187 TP_ARGS(irq_idx)
188);
189
190TRACE_EVENT(dpu_enc_irq_wait_success,
191 TP_PROTO(uint32_t drm_id, void *func,
192 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
193 TP_ARGS(drm_id, func, irq_idx, pp_idx, atomic_cnt),
194 TP_STRUCT__entry(
195 __field( uint32_t, drm_id )
196 __field( void *, func )
197 __field( int, irq_idx )
198 __field( enum dpu_pingpong, pp_idx )
199 __field( int, atomic_cnt )
200 ),
201 TP_fast_assign(
202 __entry->drm_id = drm_id;
203 __entry->func = func;
204 __entry->irq_idx = irq_idx;
205 __entry->pp_idx = pp_idx;
206 __entry->atomic_cnt = atomic_cnt;
207 ),
208 TP_printk("id=%u, callback=%ps, irq=%d, pp=%d, atomic_cnt=%d",
209 __entry->drm_id, __entry->func,
210 __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
211);
212
213DECLARE_EVENT_CLASS(dpu_drm_obj_template,
214 TP_PROTO(uint32_t drm_id),
215 TP_ARGS(drm_id),
216 TP_STRUCT__entry(
217 __field( uint32_t, drm_id )
218 ),
219 TP_fast_assign(
220 __entry->drm_id = drm_id;
221 ),
222 TP_printk("id=%u", __entry->drm_id)
223);
224DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check,
225 TP_PROTO(uint32_t drm_id),
226 TP_ARGS(drm_id)
227);
228DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set,
229 TP_PROTO(uint32_t drm_id),
230 TP_ARGS(drm_id)
231);
232DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable,
233 TP_PROTO(uint32_t drm_id),
234 TP_ARGS(drm_id)
235);
236DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff,
237 TP_PROTO(uint32_t drm_id),
238 TP_ARGS(drm_id)
239);
240DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff,
241 TP_PROTO(uint32_t drm_id),
242 TP_ARGS(drm_id)
243);
244DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
245 TP_PROTO(uint32_t drm_id),
246 TP_ARGS(drm_id)
247);
248DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip,
249 TP_PROTO(uint32_t drm_id),
250 TP_ARGS(drm_id)
251);
252DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb,
253 TP_PROTO(uint32_t drm_id),
254 TP_ARGS(drm_id)
255);
256DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
257 TP_PROTO(uint32_t drm_id),
258 TP_ARGS(drm_id)
259);
260DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
261 TP_PROTO(uint32_t drm_id),
262 TP_ARGS(drm_id)
263);
264DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
265 TP_PROTO(uint32_t drm_id),
266 TP_ARGS(drm_id)
267);
268DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume,
269 TP_PROTO(uint32_t drm_id),
270 TP_ARGS(drm_id)
271);
272
273TRACE_EVENT(dpu_enc_enable,
274 TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
275 TP_ARGS(drm_id, hdisplay, vdisplay),
276 TP_STRUCT__entry(
277 __field( uint32_t, drm_id )
278 __field( int, hdisplay )
279 __field( int, vdisplay )
280 ),
281 TP_fast_assign(
282 __entry->drm_id = drm_id;
283 __entry->hdisplay = hdisplay;
284 __entry->vdisplay = vdisplay;
285 ),
286 TP_printk("id=%u, mode=%dx%d",
287 __entry->drm_id, __entry->hdisplay, __entry->vdisplay)
288);
289
290DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
291 TP_PROTO(uint32_t drm_id, int val),
292 TP_ARGS(drm_id, val),
293 TP_STRUCT__entry(
294 __field( uint32_t, drm_id )
295 __field( int, val )
296 ),
297 TP_fast_assign(
298 __entry->drm_id = drm_id;
299 __entry->val = val;
300 ),
301 TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val)
302);
303DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb,
304 TP_PROTO(uint32_t drm_id, int count),
305 TP_ARGS(drm_id, count)
306);
307DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start,
308 TP_PROTO(uint32_t drm_id, int ctl_idx),
309 TP_ARGS(drm_id, ctl_idx)
310);
311
312TRACE_EVENT(dpu_enc_atomic_check_flags,
313 TP_PROTO(uint32_t drm_id, unsigned int flags),
314 TP_ARGS(drm_id, flags),
315 TP_STRUCT__entry(
316 __field( uint32_t, drm_id )
317 __field( unsigned int, flags )
318 ),
319 TP_fast_assign(
320 __entry->drm_id = drm_id;
321 __entry->flags = flags;
322 ),
323 TP_printk("id=%u, flags=%u",
324 __entry->drm_id, __entry->flags)
325);
326
327DECLARE_EVENT_CLASS(dpu_enc_id_enable_template,
328 TP_PROTO(uint32_t drm_id, bool enable),
329 TP_ARGS(drm_id, enable),
330 TP_STRUCT__entry(
331 __field( uint32_t, drm_id )
332 __field( bool, enable )
333 ),
334 TP_fast_assign(
335 __entry->drm_id = drm_id;
336 __entry->enable = enable;
337 ),
338 TP_printk("id=%u, enable=%s",
339 __entry->drm_id, __entry->enable ? "true" : "false")
340);
341DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper,
342 TP_PROTO(uint32_t drm_id, bool enable),
343 TP_ARGS(drm_id, enable)
344);
345DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
346 TP_PROTO(uint32_t drm_id, bool enable),
347 TP_ARGS(drm_id, enable)
348);
349DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb,
350 TP_PROTO(uint32_t drm_id, bool enable),
351 TP_ARGS(drm_id, enable)
352);
353DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te,
354 TP_PROTO(uint32_t drm_id, bool enable),
355 TP_ARGS(drm_id, enable)
356);
357
358TRACE_EVENT(dpu_enc_rc,
359 TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
360 int rc_state, const char *stage),
361 TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage),
362 TP_STRUCT__entry(
363 __field( uint32_t, drm_id )
364 __field( u32, sw_event )
365 __field( bool, idle_pc_supported )
366 __field( int, rc_state )
367 __string( stage_str, stage )
368 ),
369 TP_fast_assign(
370 __entry->drm_id = drm_id;
371 __entry->sw_event = sw_event;
372 __entry->idle_pc_supported = idle_pc_supported;
373 __entry->rc_state = rc_state;
374 __assign_str(stage_str, stage);
375 ),
376 TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d",
377 __get_str(stage_str), __entry->drm_id, __entry->sw_event,
378 __entry->idle_pc_supported ? "true" : "false",
379 __entry->rc_state)
380);
381
382TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
383 TP_PROTO(uint32_t drm_id, u32 event, char *intf_mode, enum dpu_intf intf_idx,
384 enum dpu_wb wb_idx),
385 TP_ARGS(drm_id, event, intf_mode, intf_idx, wb_idx),
386 TP_STRUCT__entry(
387 __field( uint32_t, drm_id )
388 __field( u32, event )
389 __string( intf_mode_str, intf_mode )
390 __field( enum dpu_intf, intf_idx )
391 __field( enum dpu_wb, wb_idx )
392 ),
393 TP_fast_assign(
394 __entry->drm_id = drm_id;
395 __entry->event = event;
396 __assign_str(intf_mode_str, intf_mode);
397 __entry->intf_idx = intf_idx;
398 __entry->wb_idx = wb_idx;
399 ),
400 TP_printk("id=%u, event=%u, intf_mode=%s intf=%d wb=%d", __entry->drm_id,
401 __entry->event, __get_str(intf_mode_str),
402 __entry->intf_idx, __entry->wb_idx)
403);
404
405TRACE_EVENT(dpu_enc_frame_done_cb,
406 TP_PROTO(uint32_t drm_id, unsigned int idx,
407 unsigned long frame_busy_mask),
408 TP_ARGS(drm_id, idx, frame_busy_mask),
409 TP_STRUCT__entry(
410 __field( uint32_t, drm_id )
411 __field( unsigned int, idx )
412 __field( unsigned long, frame_busy_mask )
413 ),
414 TP_fast_assign(
415 __entry->drm_id = drm_id;
416 __entry->idx = idx;
417 __entry->frame_busy_mask = frame_busy_mask;
418 ),
419 TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id,
420 __entry->idx, __entry->frame_busy_mask)
421);
422
423TRACE_EVENT(dpu_enc_trigger_flush,
424 TP_PROTO(uint32_t drm_id, char *intf_mode, enum dpu_intf intf_idx, enum dpu_wb wb_idx,
425 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
426 u32 pending_flush_ret),
427 TP_ARGS(drm_id, intf_mode, intf_idx, wb_idx, pending_kickoff_cnt, ctl_idx,
428 extra_flush_bits, pending_flush_ret),
429 TP_STRUCT__entry(
430 __field( uint32_t, drm_id )
431 __string( intf_mode_str, intf_mode )
432 __field( enum dpu_intf, intf_idx )
433 __field( enum dpu_wb, wb_idx )
434 __field( int, pending_kickoff_cnt )
435 __field( int, ctl_idx )
436 __field( u32, extra_flush_bits )
437 __field( u32, pending_flush_ret )
438 ),
439 TP_fast_assign(
440 __entry->drm_id = drm_id;
441 __assign_str(intf_mode_str, intf_mode);
442 __entry->intf_idx = intf_idx;
443 __entry->wb_idx = wb_idx;
444 __entry->pending_kickoff_cnt = pending_kickoff_cnt;
445 __entry->ctl_idx = ctl_idx;
446 __entry->extra_flush_bits = extra_flush_bits;
447 __entry->pending_flush_ret = pending_flush_ret;
448 ),
449 TP_printk("id=%u, intf_mode=%s, intf_idx=%d, wb_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d "
450 "extra_flush_bits=0x%x pending_flush_ret=0x%x",
451 __entry->drm_id, __get_str(intf_mode_str), __entry->intf_idx, __entry->wb_idx,
452 __entry->pending_kickoff_cnt, __entry->ctl_idx,
453 __entry->extra_flush_bits, __entry->pending_flush_ret)
454);
455
456DECLARE_EVENT_CLASS(dpu_enc_ktime_template,
457 TP_PROTO(uint32_t drm_id, ktime_t time),
458 TP_ARGS(drm_id, time),
459 TP_STRUCT__entry(
460 __field( uint32_t, drm_id )
461 __field( ktime_t, time )
462 ),
463 TP_fast_assign(
464 __entry->drm_id = drm_id;
465 __entry->time = time;
466 ),
467 TP_printk("id=%u, time=%lld", __entry->drm_id,
468 ktime_to_ms(__entry->time))
469);
470DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work,
471 TP_PROTO(uint32_t drm_id, ktime_t time),
472 TP_ARGS(drm_id, time)
473);
474DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff,
475 TP_PROTO(uint32_t drm_id, ktime_t time),
476 TP_ARGS(drm_id, time)
477);
478
479DECLARE_EVENT_CLASS(dpu_id_event_template,
480 TP_PROTO(uint32_t drm_id, u32 event),
481 TP_ARGS(drm_id, event),
482 TP_STRUCT__entry(
483 __field( uint32_t, drm_id )
484 __field( u32, event )
485 ),
486 TP_fast_assign(
487 __entry->drm_id = drm_id;
488 __entry->event = event;
489 ),
490 TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event)
491);
492DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
493 TP_PROTO(uint32_t drm_id, u32 event),
494 TP_ARGS(drm_id, event)
495);
496DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb,
497 TP_PROTO(uint32_t drm_id, u32 event),
498 TP_ARGS(drm_id, event)
499);
500DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done,
501 TP_PROTO(uint32_t drm_id, u32 event),
502 TP_ARGS(drm_id, event)
503);
504DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
505 TP_PROTO(uint32_t drm_id, u32 event),
506 TP_ARGS(drm_id, event)
507);
508
509TRACE_EVENT(dpu_enc_wait_event_timeout,
510 TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
511 s64 expected_time, int atomic_cnt),
512 TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
513 TP_STRUCT__entry(
514 __field( uint32_t, drm_id )
515 __field( int, irq_idx )
516 __field( int, rc )
517 __field( s64, time )
518 __field( s64, expected_time )
519 __field( int, atomic_cnt )
520 ),
521 TP_fast_assign(
522 __entry->drm_id = drm_id;
523 __entry->irq_idx = irq_idx;
524 __entry->rc = rc;
525 __entry->time = time;
526 __entry->expected_time = expected_time;
527 __entry->atomic_cnt = atomic_cnt;
528 ),
529 TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
530 __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
531 __entry->expected_time, __entry->atomic_cnt)
532);
533
534TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl,
535 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable,
536 int refcnt),
537 TP_ARGS(drm_id, pp, enable, refcnt),
538 TP_STRUCT__entry(
539 __field( uint32_t, drm_id )
540 __field( enum dpu_pingpong, pp )
541 __field( bool, enable )
542 __field( int, refcnt )
543 ),
544 TP_fast_assign(
545 __entry->drm_id = drm_id;
546 __entry->pp = pp;
547 __entry->enable = enable;
548 __entry->refcnt = refcnt;
549 ),
550 TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id,
551 __entry->pp, __entry->enable ? "true" : "false",
552 __entry->refcnt)
553);
554
555TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done,
556 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count,
557 u32 event),
558 TP_ARGS(drm_id, pp, new_count, event),
559 TP_STRUCT__entry(
560 __field( uint32_t, drm_id )
561 __field( enum dpu_pingpong, pp )
562 __field( int, new_count )
563 __field( u32, event )
564 ),
565 TP_fast_assign(
566 __entry->drm_id = drm_id;
567 __entry->pp = pp;
568 __entry->new_count = new_count;
569 __entry->event = event;
570 ),
571 TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id,
572 __entry->pp, __entry->new_count, __entry->event)
573);
574
575TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
576 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count,
577 int kickoff_count, u32 event),
578 TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event),
579 TP_STRUCT__entry(
580 __field( uint32_t, drm_id )
581 __field( enum dpu_pingpong, pp )
582 __field( int, timeout_count )
583 __field( int, kickoff_count )
584 __field( u32, event )
585 ),
586 TP_fast_assign(
587 __entry->drm_id = drm_id;
588 __entry->pp = pp;
589 __entry->timeout_count = timeout_count;
590 __entry->kickoff_count = kickoff_count;
591 __entry->event = event;
592 ),
593 TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u",
594 __entry->drm_id, __entry->pp, __entry->timeout_count,
595 __entry->kickoff_count, __entry->event)
596);
597
598TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
599 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
600 TP_ARGS(drm_id, intf_idx),
601 TP_STRUCT__entry(
602 __field( uint32_t, drm_id )
603 __field( enum dpu_intf, intf_idx )
604 ),
605 TP_fast_assign(
606 __entry->drm_id = drm_id;
607 __entry->intf_idx = intf_idx;
608 ),
609 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
610);
611
612TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
613 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable,
614 int refcnt),
615 TP_ARGS(drm_id, intf_idx, enable, refcnt),
616 TP_STRUCT__entry(
617 __field( uint32_t, drm_id )
618 __field( enum dpu_intf, intf_idx )
619 __field( bool, enable )
620 __field( int, refcnt )
621 ),
622 TP_fast_assign(
623 __entry->drm_id = drm_id;
624 __entry->intf_idx = intf_idx;
625 __entry->enable = enable;
626 __entry->refcnt = refcnt;
627 ),
628 TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id,
629 __entry->intf_idx, __entry->enable ? "true" : "false",
630 __entry->drm_id)
631);
632
633TRACE_EVENT(dpu_crtc_setup_mixer,
634 TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
635 struct drm_plane_state *state, struct dpu_plane_state *pstate,
636 uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format,
637 uint64_t modifier),
638 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
639 pixel_format, modifier),
640 TP_STRUCT__entry(
641 __field( uint32_t, crtc_id )
642 __field( uint32_t, plane_id )
643 __field( uint32_t, fb_id )
644 __field_struct( struct drm_rect, src_rect )
645 __field_struct( struct drm_rect, dst_rect )
646 __field( uint32_t, stage_idx )
647 __field( enum dpu_stage, stage )
648 __field( enum dpu_sspp, sspp )
649 __field( uint32_t, multirect_idx )
650 __field( uint32_t, multirect_mode )
651 __field( uint32_t, pixel_format )
652 __field( uint64_t, modifier )
653 ),
654 TP_fast_assign(
655 __entry->crtc_id = crtc_id;
656 __entry->plane_id = plane_id;
657 __entry->fb_id = state ? state->fb->base.id : 0;
658 __entry->src_rect = drm_plane_state_src(state);
659 __entry->dst_rect = drm_plane_state_dest(state);
660 __entry->stage_idx = stage_idx;
661 __entry->stage = pstate->stage;
662 __entry->sspp = sspp;
663 __entry->multirect_idx = pstate->multirect_index;
664 __entry->multirect_mode = pstate->multirect_mode;
665 __entry->pixel_format = pixel_format;
666 __entry->modifier = modifier;
667 ),
668 TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
669 " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
670 "multirect_index:%d multirect_mode:%u pix_format:%u "
671 "modifier:%llu",
672 __entry->crtc_id, __entry->plane_id, __entry->fb_id,
673 DRM_RECT_FP_ARG(&__entry->src_rect),
674 DRM_RECT_ARG(&__entry->dst_rect),
675 __entry->stage_idx, __entry->stage, __entry->sspp,
676 __entry->multirect_idx, __entry->multirect_mode,
677 __entry->pixel_format, __entry->modifier)
678);
679
680TRACE_EVENT(dpu_crtc_setup_lm_bounds,
681 TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds),
682 TP_ARGS(drm_id, mixer, bounds),
683 TP_STRUCT__entry(
684 __field( uint32_t, drm_id )
685 __field( int, mixer )
686 __field_struct( struct drm_rect, bounds )
687 ),
688 TP_fast_assign(
689 __entry->drm_id = drm_id;
690 __entry->mixer = mixer;
691 __entry->bounds = *bounds;
692 ),
693 TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id,
694 __entry->mixer, DRM_RECT_ARG(&__entry->bounds))
695);
696
697TRACE_EVENT(dpu_crtc_vblank_enable,
698 TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable,
699 struct dpu_crtc *crtc),
700 TP_ARGS(drm_id, enc_id, enable, crtc),
701 TP_STRUCT__entry(
702 __field( uint32_t, drm_id )
703 __field( uint32_t, enc_id )
704 __field( bool, enable )
705 __field( bool, enabled )
706 ),
707 TP_fast_assign(
708 __entry->drm_id = drm_id;
709 __entry->enc_id = enc_id;
710 __entry->enable = enable;
711 __entry->enabled = crtc->enabled;
712 ),
713 TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}",
714 __entry->drm_id, __entry->enc_id,
715 __entry->enable ? "true" : "false",
716 __entry->enabled ? "true" : "false")
717);
718
719DECLARE_EVENT_CLASS(dpu_crtc_enable_template,
720 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
721 TP_ARGS(drm_id, enable, crtc),
722 TP_STRUCT__entry(
723 __field( uint32_t, drm_id )
724 __field( bool, enable )
725 __field( bool, enabled )
726 ),
727 TP_fast_assign(
728 __entry->drm_id = drm_id;
729 __entry->enable = enable;
730 __entry->enabled = crtc->enabled;
731 ),
732 TP_printk("id:%u enable:%s state{enabled:%s}",
733 __entry->drm_id, __entry->enable ? "true" : "false",
734 __entry->enabled ? "true" : "false")
735);
736DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable,
737 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
738 TP_ARGS(drm_id, enable, crtc)
739);
740DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable,
741 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
742 TP_ARGS(drm_id, enable, crtc)
743);
744DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank,
745 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
746 TP_ARGS(drm_id, enable, crtc)
747);
748
749TRACE_EVENT(dpu_crtc_disable_frame_pending,
750 TP_PROTO(uint32_t drm_id, int frame_pending),
751 TP_ARGS(drm_id, frame_pending),
752 TP_STRUCT__entry(
753 __field( uint32_t, drm_id )
754 __field( int, frame_pending )
755 ),
756 TP_fast_assign(
757 __entry->drm_id = drm_id;
758 __entry->frame_pending = frame_pending;
759 ),
760 TP_printk("id:%u frame_pending:%d", __entry->drm_id,
761 __entry->frame_pending)
762);
763
764TRACE_EVENT(dpu_plane_set_scanout,
765 TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
766 enum dpu_sspp_multirect_index multirect_index),
767 TP_ARGS(index, layout, multirect_index),
768 TP_STRUCT__entry(
769 __field( enum dpu_sspp, index )
770 __field_struct( struct dpu_hw_fmt_layout, layout )
771 __field( enum dpu_sspp_multirect_index, multirect_index)
772 ),
773 TP_fast_assign(
774 __entry->index = index;
775 __entry->layout = *layout;
776 __entry->multirect_index = multirect_index;
777 ),
778 TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
779 "multirect_index:%d", __entry->index, __entry->layout.width,
780 __entry->layout.height, __entry->layout.plane_addr[0],
781 __entry->layout.plane_size[0],
782 __entry->layout.plane_addr[1],
783 __entry->layout.plane_size[1],
784 __entry->layout.plane_addr[2],
785 __entry->layout.plane_size[2],
786 __entry->layout.plane_addr[3],
787 __entry->layout.plane_size[3], __entry->multirect_index)
788);
789
790TRACE_EVENT(dpu_plane_disable,
791 TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
792 TP_ARGS(drm_id, is_virtual, multirect_mode),
793 TP_STRUCT__entry(
794 __field( uint32_t, drm_id )
795 __field( bool, is_virtual )
796 __field( uint32_t, multirect_mode )
797 ),
798 TP_fast_assign(
799 __entry->drm_id = drm_id;
800 __entry->is_virtual = is_virtual;
801 __entry->multirect_mode = multirect_mode;
802 ),
803 TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
804 __entry->is_virtual ? "true" : "false",
805 __entry->multirect_mode)
806);
807
808DECLARE_EVENT_CLASS(dpu_rm_iter_template,
809 TP_PROTO(uint32_t id, uint32_t enc_id),
810 TP_ARGS(id, enc_id),
811 TP_STRUCT__entry(
812 __field( uint32_t, id )
813 __field( uint32_t, enc_id )
814 ),
815 TP_fast_assign(
816 __entry->id = id;
817 __entry->enc_id = enc_id;
818 ),
819 TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id)
820);
821DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
822 TP_PROTO(uint32_t id, uint32_t enc_id),
823 TP_ARGS(id, enc_id)
824);
825DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
826 TP_PROTO(uint32_t id, uint32_t enc_id),
827 TP_ARGS(id, enc_id)
828);
829
830TRACE_EVENT(dpu_rm_reserve_lms,
831 TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id),
832 TP_ARGS(id, enc_id, pp_id),
833 TP_STRUCT__entry(
834 __field( uint32_t, id )
835 __field( uint32_t, enc_id )
836 __field( uint32_t, pp_id )
837 ),
838 TP_fast_assign(
839 __entry->id = id;
840 __entry->enc_id = enc_id;
841 __entry->pp_id = pp_id;
842 ),
843 TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id,
844 __entry->enc_id, __entry->pp_id)
845);
846
847TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
848 TP_PROTO(enum dpu_vbif index, u32 xin_id),
849 TP_ARGS(index, xin_id),
850 TP_STRUCT__entry(
851 __field( enum dpu_vbif, index )
852 __field( u32, xin_id )
853 ),
854 TP_fast_assign(
855 __entry->index = index;
856 __entry->xin_id = xin_id;
857 ),
858 TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
859);
860
861TRACE_EVENT(dpu_pp_connect_ext_te,
862 TP_PROTO(enum dpu_pingpong pp, u32 cfg),
863 TP_ARGS(pp, cfg),
864 TP_STRUCT__entry(
865 __field( enum dpu_pingpong, pp )
866 __field( u32, cfg )
867 ),
868 TP_fast_assign(
869 __entry->pp = pp;
870 __entry->cfg = cfg;
871 ),
872 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
873);
874
875TRACE_EVENT(dpu_core_irq_register_callback,
876 TP_PROTO(int irq_idx, void *callback),
877 TP_ARGS(irq_idx, callback),
878 TP_STRUCT__entry(
879 __field( int, irq_idx )
880 __field( void *, callback)
881 ),
882 TP_fast_assign(
883 __entry->irq_idx = irq_idx;
884 __entry->callback = callback;
885 ),
886 TP_printk("irq_idx:%d callback:%ps", __entry->irq_idx,
887 __entry->callback)
888);
889
890TRACE_EVENT(dpu_core_irq_unregister_callback,
891 TP_PROTO(int irq_idx),
892 TP_ARGS(irq_idx),
893 TP_STRUCT__entry(
894 __field( int, irq_idx )
895 ),
896 TP_fast_assign(
897 __entry->irq_idx = irq_idx;
898 ),
899 TP_printk("irq_idx:%d", __entry->irq_idx)
900);
901
902TRACE_EVENT(dpu_core_perf_update_clk,
903 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
904 TP_ARGS(dev, stop_req, clk_rate),
905 TP_STRUCT__entry(
906 __string( dev_name, dev->unique )
907 __field( bool, stop_req )
908 __field( u64, clk_rate )
909 ),
910 TP_fast_assign(
911 __assign_str(dev_name, dev->unique);
912 __entry->stop_req = stop_req;
913 __entry->clk_rate = clk_rate;
914 ),
915 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name),
916 __entry->stop_req ? "true" : "false", __entry->clk_rate)
917);
918
919TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
920 TP_PROTO(u32 new_bits, u32 pending_mask),
921 TP_ARGS(new_bits, pending_mask),
922 TP_STRUCT__entry(
923 __field( u32, new_bits )
924 __field( u32, pending_mask )
925 ),
926 TP_fast_assign(
927 __entry->new_bits = new_bits;
928 __entry->pending_mask = pending_mask;
929 ),
930 TP_printk("new=%x existing=%x", __entry->new_bits,
931 __entry->pending_mask)
932);
933
934DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
935 TP_PROTO(u32 pending_mask, u32 ctl_flush),
936 TP_ARGS(pending_mask, ctl_flush),
937 TP_STRUCT__entry(
938 __field( u32, pending_mask )
939 __field( u32, ctl_flush )
940 ),
941 TP_fast_assign(
942 __entry->pending_mask = pending_mask;
943 __entry->ctl_flush = ctl_flush;
944 ),
945 TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
946 __entry->ctl_flush)
947);
948DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
949 TP_PROTO(u32 pending_mask, u32 ctl_flush),
950 TP_ARGS(pending_mask, ctl_flush)
951);
952DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
953 dpu_hw_ctl_trigger_pending_flush,
954 TP_PROTO(u32 pending_mask, u32 ctl_flush),
955 TP_ARGS(pending_mask, ctl_flush)
956);
957DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
958 TP_PROTO(u32 pending_mask, u32 ctl_flush),
959 TP_ARGS(pending_mask, ctl_flush)
960);
961DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
962 TP_PROTO(u32 pending_mask, u32 ctl_flush),
963 TP_ARGS(pending_mask, ctl_flush)
964);
965
966#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
967#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
968#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
969
970#define DPU_ATRACE_INT(name, value) \
971 trace_dpu_trace_counter(current->tgid, name, value)
972
973#endif /* _DPU_TRACE_H_ */
974
975/* This part must be outside protection */
976#undef TRACE_INCLUDE_PATH
977#define TRACE_INCLUDE_PATH .
978#include <trace/define_trace.h>