1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef __DPU_RM_H__
  7#define __DPU_RM_H__
  8
  9#include <linux/list.h>
 10
 11#include "msm_kms.h"
 12#include "dpu_hw_top.h"
 13
 14struct dpu_global_state;
 15
 16/**
 17 * struct dpu_rm - DPU dynamic hardware resource manager
 18 * @pingpong_blks: array of pingpong hardware resources
 19 * @mixer_blks: array of layer mixer hardware resources
 20 * @ctl_blks: array of ctl hardware resources
 21 * @hw_intf: array of intf hardware resources
 22 * @hw_wb: array of wb hardware resources
 23 * @dspp_blks: array of dspp hardware resources
 24 */
 25struct dpu_rm {
 26	struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
 27	struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
 28	struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
 29	struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
 30	struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
 31	struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
 32	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
 33	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
 34};
 35
 36/**
 37 * dpu_rm_init - Read hardware catalog and create reservation tracking objects
 38 *	for all HW blocks.
 39 * @rm: DPU Resource Manager handle
 40 * @cat: Pointer to hardware catalog
 41 * @mmio: mapped register io address of MDP
 42 * @Return: 0 on Success otherwise -ERROR
 43 */
 44int dpu_rm_init(struct dpu_rm *rm,
 45		const struct dpu_mdss_cfg *cat,
 46		void __iomem *mmio);
 47
 48/**
 49 * dpu_rm_destroy - Free all memory allocated by dpu_rm_init
 50 * @rm: DPU Resource Manager handle
 51 * @Return: 0 on Success otherwise -ERROR
 52 */
 53int dpu_rm_destroy(struct dpu_rm *rm);
 54
 55/**
 56 * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze
 57 *	the use connections and user requirements, specified through related
 58 *	topology control properties, and reserve hardware blocks to that
 59 *	display chain.
 60 *	HW blocks can then be accessed through dpu_rm_get_* functions.
 61 *	HW Reservations should be released via dpu_rm_release_hw.
 62 * @rm: DPU Resource Manager handle
 63 * @drm_enc: DRM Encoder handle
 64 * @crtc_state: Proposed Atomic DRM CRTC State handle
 65 * @topology: Pointer to topology info for the display
 66 * @Return: 0 on Success otherwise -ERROR
 67 */
 68int dpu_rm_reserve(struct dpu_rm *rm,
 69		struct dpu_global_state *global_state,
 70		struct drm_encoder *drm_enc,
 71		struct drm_crtc_state *crtc_state,
 72		struct msm_display_topology topology);
 73
 74/**
 75 * dpu_rm_reserve - Given the encoder for the display chain, release any
 76 *	HW blocks previously reserved for that use case.
 77 * @rm: DPU Resource Manager handle
 78 * @enc: DRM Encoder handle
 79 * @Return: 0 on Success otherwise -ERROR
 80 */
 81void dpu_rm_release(struct dpu_global_state *global_state,
 82		struct drm_encoder *enc);
 83
 84/**
 85 * Get hw resources of the given type that are assigned to this encoder.
 86 */
 87int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
 88	struct dpu_global_state *global_state, uint32_t enc_id,
 89	enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
 90
 91/**
 92 * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
 93 * @rm: DPU Resource Manager handle
 94 * @intf_idx: INTF's index
 95 */
 96static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
 97{
 98	return rm->hw_intf[intf_idx - INTF_0];
 99}
100
101/**
102 * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
103 * @rm: DPU Resource Manager handle
104 * @wb_idx: WB index
105 */
106static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx)
107{
108	return rm->hw_wb[wb_idx - WB_0];
109}
110
111#endif /* __DPU_RM_H__ */
112