1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  5 */
  6
  7#include "dpu_kms.h"
  8#include "dpu_hw_catalog.h"
  9#include "dpu_hwio.h"
 10#include "dpu_hw_lm.h"
 11#include "dpu_hw_mdss.h"
 12
 13#define LM_OP_MODE                        0x00
 14#define LM_OUT_SIZE                       0x04
 15#define LM_BORDER_COLOR_0                 0x08
 16#define LM_BORDER_COLOR_1                 0x010
 17
 18/* These register are offset to mixer base + stage base */
 19#define LM_BLEND0_OP                     0x00
 20#define LM_BLEND0_CONST_ALPHA            0x04
 21#define LM_FG_COLOR_FILL_COLOR_0         0x08
 22#define LM_FG_COLOR_FILL_COLOR_1         0x0C
 23#define LM_FG_COLOR_FILL_SIZE            0x10
 24#define LM_FG_COLOR_FILL_XY              0x14
 25
 26#define LM_BLEND0_FG_ALPHA               0x04
 27#define LM_BLEND0_BG_ALPHA               0x08
 28
 29#define LM_MISR_CTRL                     0x310
 30#define LM_MISR_SIGNATURE                0x314
 31
 32
 33static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
 34		const struct dpu_mdss_cfg *m,
 35		void __iomem *addr,
 36		struct dpu_hw_blk_reg_map *b)
 37{
 38	int i;
 39
 40	for (i = 0; i < m->mixer_count; i++) {
 41		if (mixer == m->mixer[i].id) {
 42			b->blk_addr = addr + m->mixer[i].base;
 43			b->log_mask = DPU_DBG_MASK_LM;
 44			return &m->mixer[i];
 45		}
 46	}
 47
 48	return ERR_PTR(-ENOMEM);
 49}
 50
 51/**
 52 * _stage_offset(): returns the relative offset of the blend registers
 53 * for the stage to be setup
 54 * @ctx:     mixer ctx contains the mixer to be programmed
 55 * @stage: stage index to setup
 56 */
 57static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage)
 58{
 59	const struct dpu_lm_sub_blks *sblk = ctx->cap->sblk;
 60	if (stage != DPU_STAGE_BASE && stage <= sblk->maxblendstages)
 61		return sblk->blendstage_base[stage - DPU_STAGE_0];
 62
 63	return -EINVAL;
 64}
 65
 66static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx,
 67		struct dpu_hw_mixer_cfg *mixer)
 68{
 69	struct dpu_hw_blk_reg_map *c = &ctx->hw;
 70	u32 outsize;
 71	u32 op_mode;
 72
 73	op_mode = DPU_REG_READ(c, LM_OP_MODE);
 74
 75	outsize = mixer->out_height << 16 | mixer->out_width;
 76	DPU_REG_WRITE(c, LM_OUT_SIZE, outsize);
 77
 78	/* SPLIT_LEFT_RIGHT */
 79	if (mixer->right_mixer)
 80		op_mode |= BIT(31);
 81	else
 82		op_mode &= ~BIT(31);
 83	DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
 84}
 85
 86static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
 87		struct dpu_mdss_color *color,
 88		u8 border_en)
 89{
 90	struct dpu_hw_blk_reg_map *c = &ctx->hw;
 91
 92	if (border_en) {
 93		DPU_REG_WRITE(c, LM_BORDER_COLOR_0,
 94			(color->color_0 & 0xFFF) |
 95			((color->color_1 & 0xFFF) << 0x10));
 96		DPU_REG_WRITE(c, LM_BORDER_COLOR_1,
 97			(color->color_2 & 0xFFF) |
 98			((color->color_3 & 0xFFF) << 0x10));
 99	}
100}
101
102static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)
103{
104	dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count);
105}
106
107static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
108{
109	return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value);
110}
111
112static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
113	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
114{
115	struct dpu_hw_blk_reg_map *c = &ctx->hw;
116	int stage_off;
117	u32 const_alpha;
118
119	if (stage == DPU_STAGE_BASE)
120		return;
121
122	stage_off = _stage_offset(ctx, stage);
123	if (WARN_ON(stage_off < 0))
124		return;
125
126	const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
127	DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
128	DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
129}
130
131static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
132	u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
133{
134	struct dpu_hw_blk_reg_map *c = &ctx->hw;
135	int stage_off;
136
137	if (stage == DPU_STAGE_BASE)
138		return;
139
140	stage_off = _stage_offset(ctx, stage);
141	if (WARN_ON(stage_off < 0))
142		return;
143
144	DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
145	DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
146	DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
147}
148
149static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
150	uint32_t mixer_op_mode)
151{
152	struct dpu_hw_blk_reg_map *c = &ctx->hw;
153	int op_mode;
154
155	/* read the existing op_mode configuration */
156	op_mode = DPU_REG_READ(c, LM_OP_MODE);
157
158	op_mode = (op_mode & (BIT(31) | BIT(30))) | mixer_op_mode;
159
160	DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
161}
162
163static void _setup_mixer_ops(const struct dpu_mdss_cfg *m,
164		struct dpu_hw_lm_ops *ops,
165		unsigned long features)
166{
167	ops->setup_mixer_out = dpu_hw_lm_setup_out;
168	if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features))
169		ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
170	else
171		ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
172	ops->setup_alpha_out = dpu_hw_lm_setup_color3;
173	ops->setup_border_color = dpu_hw_lm_setup_border_color;
174	ops->setup_misr = dpu_hw_lm_setup_misr;
175	ops->collect_misr = dpu_hw_lm_collect_misr;
176}
177
178struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
179		void __iomem *addr,
180		const struct dpu_mdss_cfg *m)
181{
182	struct dpu_hw_mixer *c;
183	const struct dpu_lm_cfg *cfg;
184
185	c = kzalloc(sizeof(*c), GFP_KERNEL);
186	if (!c)
187		return ERR_PTR(-ENOMEM);
188
189	cfg = _lm_offset(idx, m, addr, &c->hw);
190	if (IS_ERR_OR_NULL(cfg)) {
191		kfree(c);
192		return ERR_PTR(-EINVAL);
193	}
194
195	/* Assign ops */
196	c->idx = idx;
197	c->cap = cfg;
198	_setup_mixer_ops(m, &c->ops, c->cap->features);
199
200	return c;
201}
202
203void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm)
204{
205	kfree(lm);
206}