Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
7 */
8
9#include <linux/ascii85.h>
10#include <linux/interconnect.h>
11#include <linux/qcom_scm.h>
12#include <linux/kernel.h>
13#include <linux/of_address.h>
14#include <linux/pm_opp.h>
15#include <linux/slab.h>
16#include <linux/soc/qcom/mdt_loader.h>
17#include <linux/nvmem-consumer.h>
18#include <soc/qcom/ocmem.h>
19#include "adreno_gpu.h"
20#include "a6xx_gpu.h"
21#include "msm_gem.h"
22#include "msm_mmu.h"
23
24static u64 address_space_size = 0;
25MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
26module_param(address_space_size, ullong, 0600);
27
28static bool zap_available = true;
29
30static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
31 u32 pasid)
32{
33 struct device *dev = &gpu->pdev->dev;
34 const struct firmware *fw;
35 const char *signed_fwname = NULL;
36 struct device_node *np, *mem_np;
37 struct resource r;
38 phys_addr_t mem_phys;
39 ssize_t mem_size;
40 void *mem_region = NULL;
41 int ret;
42
43 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
44 zap_available = false;
45 return -EINVAL;
46 }
47
48 np = of_get_child_by_name(dev->of_node, "zap-shader");
49 if (!np) {
50 zap_available = false;
51 return -ENODEV;
52 }
53
54 mem_np = of_parse_phandle(np, "memory-region", 0);
55 of_node_put(np);
56 if (!mem_np) {
57 zap_available = false;
58 return -EINVAL;
59 }
60
61 ret = of_address_to_resource(mem_np, 0, &r);
62 of_node_put(mem_np);
63 if (ret)
64 return ret;
65
66 mem_phys = r.start;
67
68 /*
69 * Check for a firmware-name property. This is the new scheme
70 * to handle firmware that may be signed with device specific
71 * keys, allowing us to have a different zap fw path for different
72 * devices.
73 *
74 * If the firmware-name property is found, we bypass the
75 * adreno_request_fw() mechanism, because we don't need to handle
76 * the /lib/firmware/qcom/... vs /lib/firmware/... case.
77 *
78 * If the firmware-name property is not found, for backwards
79 * compatibility we fall back to the fwname from the gpulist
80 * table.
81 */
82 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
83 if (signed_fwname) {
84 fwname = signed_fwname;
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
86 if (ret)
87 fw = ERR_PTR(ret);
88 } else if (fwname) {
89 /* Request the MDT file from the default location: */
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
91 } else {
92 /*
93 * For new targets, we require the firmware-name property,
94 * if a zap-shader is required, rather than falling back
95 * to a firmware name specified in gpulist.
96 *
97 * Because the firmware is signed with a (potentially)
98 * device specific key, having the name come from gpulist
99 * was a bad idea, and is only provided for backwards
100 * compatibility for older targets.
101 */
102 return -ENODEV;
103 }
104
105 if (IS_ERR(fw)) {
106 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
107 return PTR_ERR(fw);
108 }
109
110 /* Figure out how much memory we need */
111 mem_size = qcom_mdt_get_size(fw);
112 if (mem_size < 0) {
113 ret = mem_size;
114 goto out;
115 }
116
117 if (mem_size > resource_size(&r)) {
118 DRM_DEV_ERROR(dev,
119 "memory region is too small to load the MDT\n");
120 ret = -E2BIG;
121 goto out;
122 }
123
124 /* Allocate memory for the firmware image */
125 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC);
126 if (!mem_region) {
127 ret = -ENOMEM;
128 goto out;
129 }
130
131 /*
132 * Load the rest of the MDT
133 *
134 * Note that we could be dealing with two different paths, since
135 * with upstream linux-firmware it would be in a qcom/ subdir..
136 * adreno_request_fw() handles this, but qcom_mdt_load() does
137 * not. But since we've already gotten through adreno_request_fw()
138 * we know which of the two cases it is:
139 */
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
141 ret = qcom_mdt_load(dev, fw, fwname, pasid,
142 mem_region, mem_phys, mem_size, NULL);
143 } else {
144 char *newname;
145
146 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
147
148 ret = qcom_mdt_load(dev, fw, newname, pasid,
149 mem_region, mem_phys, mem_size, NULL);
150 kfree(newname);
151 }
152 if (ret)
153 goto out;
154
155 /* Send the image to the secure world */
156 ret = qcom_scm_pas_auth_and_reset(pasid);
157
158 /*
159 * If the scm call returns -EOPNOTSUPP we assume that this target
160 * doesn't need/support the zap shader so quietly fail
161 */
162 if (ret == -EOPNOTSUPP)
163 zap_available = false;
164 else if (ret)
165 DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
166
167out:
168 if (mem_region)
169 memunmap(mem_region);
170
171 release_firmware(fw);
172
173 return ret;
174}
175
176int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
177{
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
179 struct platform_device *pdev = gpu->pdev;
180
181 /* Short cut if we determine the zap shader isn't available/needed */
182 if (!zap_available)
183 return -ENODEV;
184
185 /* We need SCM to be able to load the firmware */
186 if (!qcom_scm_is_available()) {
187 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
188 return -EPROBE_DEFER;
189 }
190
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
192}
193
194struct msm_gem_address_space *
195adreno_create_address_space(struct msm_gpu *gpu,
196 struct platform_device *pdev)
197{
198 return adreno_iommu_create_address_space(gpu, pdev, 0);
199}
200
201struct msm_gem_address_space *
202adreno_iommu_create_address_space(struct msm_gpu *gpu,
203 struct platform_device *pdev,
204 unsigned long quirks)
205{
206 struct iommu_domain_geometry *geometry;
207 struct msm_mmu *mmu;
208 struct msm_gem_address_space *aspace;
209 u64 start, size;
210
211 mmu = msm_iommu_new(&pdev->dev, quirks);
212 if (IS_ERR_OR_NULL(mmu))
213 return ERR_CAST(mmu);
214
215 geometry = msm_iommu_get_geometry(mmu);
216 if (IS_ERR(geometry))
217 return ERR_CAST(geometry);
218
219 /*
220 * Use the aperture start or SZ_16M, whichever is greater. This will
221 * ensure that we align with the allocated pagetable range while still
222 * allowing room in the lower 32 bits for GMEM and whatnot
223 */
224 start = max_t(u64, SZ_16M, geometry->aperture_start);
225 size = geometry->aperture_end - start + 1;
226
227 aspace = msm_gem_address_space_create(mmu, "gpu",
228 start & GENMASK_ULL(48, 0), size);
229
230 if (IS_ERR(aspace) && !IS_ERR(mmu))
231 mmu->funcs->destroy(mmu);
232
233 return aspace;
234}
235
236u64 adreno_private_address_space_size(struct msm_gpu *gpu)
237{
238 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
239
240 if (address_space_size)
241 return address_space_size;
242
243 if (adreno_gpu->info->address_space_size)
244 return adreno_gpu->info->address_space_size;
245
246 return SZ_4G;
247}
248
249int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
250 uint32_t param, uint64_t *value, uint32_t *len)
251{
252 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
253
254 /* No pointer params yet */
255 if (*len != 0)
256 return -EINVAL;
257
258 switch (param) {
259 case MSM_PARAM_GPU_ID:
260 *value = adreno_gpu->info->revn;
261 return 0;
262 case MSM_PARAM_GMEM_SIZE:
263 *value = adreno_gpu->gmem;
264 return 0;
265 case MSM_PARAM_GMEM_BASE:
266 *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
267 return 0;
268 case MSM_PARAM_CHIP_ID:
269 *value = (uint64_t)adreno_gpu->rev.patchid |
270 ((uint64_t)adreno_gpu->rev.minor << 8) |
271 ((uint64_t)adreno_gpu->rev.major << 16) |
272 ((uint64_t)adreno_gpu->rev.core << 24);
273 if (!adreno_gpu->info->revn)
274 *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
275 return 0;
276 case MSM_PARAM_MAX_FREQ:
277 *value = adreno_gpu->base.fast_rate;
278 return 0;
279 case MSM_PARAM_TIMESTAMP:
280 if (adreno_gpu->funcs->get_timestamp) {
281 int ret;
282
283 pm_runtime_get_sync(&gpu->pdev->dev);
284 ret = adreno_gpu->funcs->get_timestamp(gpu, value);
285 pm_runtime_put_autosuspend(&gpu->pdev->dev);
286
287 return ret;
288 }
289 return -EINVAL;
290 case MSM_PARAM_PRIORITIES:
291 *value = gpu->nr_rings * NR_SCHED_PRIORITIES;
292 return 0;
293 case MSM_PARAM_PP_PGTABLE:
294 *value = 0;
295 return 0;
296 case MSM_PARAM_FAULTS:
297 if (ctx->aspace)
298 *value = gpu->global_faults + ctx->aspace->faults;
299 else
300 *value = gpu->global_faults;
301 return 0;
302 case MSM_PARAM_SUSPENDS:
303 *value = gpu->suspend_count;
304 return 0;
305 case MSM_PARAM_VA_START:
306 if (ctx->aspace == gpu->aspace)
307 return -EINVAL;
308 *value = ctx->aspace->va_start;
309 return 0;
310 case MSM_PARAM_VA_SIZE:
311 if (ctx->aspace == gpu->aspace)
312 return -EINVAL;
313 *value = ctx->aspace->va_size;
314 return 0;
315 default:
316 DBG("%s: invalid param: %u", gpu->name, param);
317 return -EINVAL;
318 }
319}
320
321int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
322 uint32_t param, uint64_t value, uint32_t len)
323{
324 switch (param) {
325 case MSM_PARAM_COMM:
326 case MSM_PARAM_CMDLINE:
327 /* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so
328 * that should be a reasonable upper bound
329 */
330 if (len > PAGE_SIZE)
331 return -EINVAL;
332 break;
333 default:
334 if (len != 0)
335 return -EINVAL;
336 }
337
338 switch (param) {
339 case MSM_PARAM_COMM:
340 case MSM_PARAM_CMDLINE: {
341 char *str, **paramp;
342
343 str = kmalloc(len + 1, GFP_KERNEL);
344 if (!str)
345 return -ENOMEM;
346
347 if (copy_from_user(str, u64_to_user_ptr(value), len)) {
348 kfree(str);
349 return -EFAULT;
350 }
351
352 /* Ensure string is null terminated: */
353 str[len] = '\0';
354
355 mutex_lock(&gpu->lock);
356
357 if (param == MSM_PARAM_COMM) {
358 paramp = &ctx->comm;
359 } else {
360 paramp = &ctx->cmdline;
361 }
362
363 kfree(*paramp);
364 *paramp = str;
365
366 mutex_unlock(&gpu->lock);
367
368 return 0;
369 }
370 case MSM_PARAM_SYSPROF:
371 if (!capable(CAP_SYS_ADMIN))
372 return -EPERM;
373 return msm_file_private_set_sysprof(ctx, gpu, value);
374 default:
375 DBG("%s: invalid param: %u", gpu->name, param);
376 return -EINVAL;
377 }
378}
379
380const struct firmware *
381adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
382{
383 struct drm_device *drm = adreno_gpu->base.dev;
384 const struct firmware *fw = NULL;
385 char *newname;
386 int ret;
387
388 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
389 if (!newname)
390 return ERR_PTR(-ENOMEM);
391
392 /*
393 * Try first to load from qcom/$fwfile using a direct load (to avoid
394 * a potential timeout waiting for usermode helper)
395 */
396 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
397 (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
398
399 ret = request_firmware_direct(&fw, newname, drm->dev);
400 if (!ret) {
401 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
402 newname);
403 adreno_gpu->fwloc = FW_LOCATION_NEW;
404 goto out;
405 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
406 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
407 newname, ret);
408 fw = ERR_PTR(ret);
409 goto out;
410 }
411 }
412
413 /*
414 * Then try the legacy location without qcom/ prefix
415 */
416 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
417 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
418
419 ret = request_firmware_direct(&fw, fwname, drm->dev);
420 if (!ret) {
421 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
422 newname);
423 adreno_gpu->fwloc = FW_LOCATION_LEGACY;
424 goto out;
425 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
426 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
427 fwname, ret);
428 fw = ERR_PTR(ret);
429 goto out;
430 }
431 }
432
433 /*
434 * Finally fall back to request_firmware() for cases where the
435 * usermode helper is needed (I think mainly android)
436 */
437 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
438 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
439
440 ret = request_firmware(&fw, newname, drm->dev);
441 if (!ret) {
442 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
443 newname);
444 adreno_gpu->fwloc = FW_LOCATION_HELPER;
445 goto out;
446 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
447 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
448 newname, ret);
449 fw = ERR_PTR(ret);
450 goto out;
451 }
452 }
453
454 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
455 fw = ERR_PTR(-ENOENT);
456out:
457 kfree(newname);
458 return fw;
459}
460
461int adreno_load_fw(struct adreno_gpu *adreno_gpu)
462{
463 int i;
464
465 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
466 const struct firmware *fw;
467
468 if (!adreno_gpu->info->fw[i])
469 continue;
470
471 /* Skip if the firmware has already been loaded */
472 if (adreno_gpu->fw[i])
473 continue;
474
475 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
476 if (IS_ERR(fw))
477 return PTR_ERR(fw);
478
479 adreno_gpu->fw[i] = fw;
480 }
481
482 return 0;
483}
484
485struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
486 const struct firmware *fw, u64 *iova)
487{
488 struct drm_gem_object *bo;
489 void *ptr;
490
491 ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
492 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
493
494 if (IS_ERR(ptr))
495 return ERR_CAST(ptr);
496
497 memcpy(ptr, &fw->data[4], fw->size - 4);
498
499 msm_gem_put_vaddr(bo);
500
501 return bo;
502}
503
504int adreno_hw_init(struct msm_gpu *gpu)
505{
506 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
507 int ret, i;
508
509 VERB("%s", gpu->name);
510
511 ret = adreno_load_fw(adreno_gpu);
512 if (ret)
513 return ret;
514
515 for (i = 0; i < gpu->nr_rings; i++) {
516 struct msm_ringbuffer *ring = gpu->rb[i];
517
518 if (!ring)
519 continue;
520
521 ring->cur = ring->start;
522 ring->next = ring->start;
523 ring->memptrs->rptr = 0;
524
525 /* Detect and clean up an impossible fence, ie. if GPU managed
526 * to scribble something invalid, we don't want that to confuse
527 * us into mistakingly believing that submits have completed.
528 */
529 if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
530 ring->memptrs->fence = ring->fctx->last_fence;
531 }
532 }
533
534 return 0;
535}
536
537/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
538static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
539 struct msm_ringbuffer *ring)
540{
541 struct msm_gpu *gpu = &adreno_gpu->base;
542
543 return gpu->funcs->get_rptr(gpu, ring);
544}
545
546struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
547{
548 return gpu->rb[0];
549}
550
551void adreno_recover(struct msm_gpu *gpu)
552{
553 struct drm_device *dev = gpu->dev;
554 int ret;
555
556 // XXX pm-runtime?? we *need* the device to be off after this
557 // so maybe continuing to call ->pm_suspend/resume() is better?
558
559 gpu->funcs->pm_suspend(gpu);
560 gpu->funcs->pm_resume(gpu);
561
562 ret = msm_gpu_hw_init(gpu);
563 if (ret) {
564 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
565 /* hmm, oh well? */
566 }
567}
568
569void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)
570{
571 uint32_t wptr;
572
573 /* Copy the shadow to the actual register */
574 ring->cur = ring->next;
575
576 /*
577 * Mask wptr value that we calculate to fit in the HW range. This is
578 * to account for the possibility that the last command fit exactly into
579 * the ringbuffer and rb->next hasn't wrapped to zero yet
580 */
581 wptr = get_wptr(ring);
582
583 /* ensure writes to ringbuffer have hit system memory: */
584 mb();
585
586 gpu_write(gpu, reg, wptr);
587}
588
589bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
590{
591 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
592 uint32_t wptr = get_wptr(ring);
593
594 /* wait for CP to drain ringbuffer: */
595 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
596 return true;
597
598 /* TODO maybe we need to reset GPU here to recover from hang? */
599 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
600 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
601
602 return false;
603}
604
605int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
606{
607 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
608 int i, count = 0;
609
610 WARN_ON(!mutex_is_locked(&gpu->lock));
611
612 kref_init(&state->ref);
613
614 ktime_get_real_ts64(&state->time);
615
616 for (i = 0; i < gpu->nr_rings; i++) {
617 int size = 0, j;
618
619 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
620 state->ring[i].iova = gpu->rb[i]->iova;
621 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence;
622 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
623 state->ring[i].wptr = get_wptr(gpu->rb[i]);
624
625 /* Copy at least 'wptr' dwords of the data */
626 size = state->ring[i].wptr;
627
628 /* After wptr find the last non zero dword to save space */
629 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
630 if (gpu->rb[i]->start[j])
631 size = j + 1;
632
633 if (size) {
634 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
635 if (state->ring[i].data) {
636 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
637 state->ring[i].data_size = size << 2;
638 }
639 }
640 }
641
642 /* Some targets prefer to collect their own registers */
643 if (!adreno_gpu->registers)
644 return 0;
645
646 /* Count the number of registers */
647 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
648 count += adreno_gpu->registers[i + 1] -
649 adreno_gpu->registers[i] + 1;
650
651 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
652 if (state->registers) {
653 int pos = 0;
654
655 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
656 u32 start = adreno_gpu->registers[i];
657 u32 end = adreno_gpu->registers[i + 1];
658 u32 addr;
659
660 for (addr = start; addr <= end; addr++) {
661 state->registers[pos++] = addr;
662 state->registers[pos++] = gpu_read(gpu, addr);
663 }
664 }
665
666 state->nr_registers = count;
667 }
668
669 return 0;
670}
671
672void adreno_gpu_state_destroy(struct msm_gpu_state *state)
673{
674 int i;
675
676 for (i = 0; i < ARRAY_SIZE(state->ring); i++)
677 kvfree(state->ring[i].data);
678
679 for (i = 0; state->bos && i < state->nr_bos; i++)
680 kvfree(state->bos[i].data);
681
682 kfree(state->bos);
683 kfree(state->comm);
684 kfree(state->cmd);
685 kfree(state->registers);
686}
687
688static void adreno_gpu_state_kref_destroy(struct kref *kref)
689{
690 struct msm_gpu_state *state = container_of(kref,
691 struct msm_gpu_state, ref);
692
693 adreno_gpu_state_destroy(state);
694 kfree(state);
695}
696
697int adreno_gpu_state_put(struct msm_gpu_state *state)
698{
699 if (IS_ERR_OR_NULL(state))
700 return 1;
701
702 return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
703}
704
705#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
706
707static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
708{
709 void *buf;
710 size_t buf_itr = 0, buffer_size;
711 char out[ASCII85_BUFSZ];
712 long l;
713 int i;
714
715 if (!src || !len)
716 return NULL;
717
718 l = ascii85_encode_len(len);
719
720 /*
721 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
722 * account for the worst case of 5 bytes per dword plus the 1 for '\0'
723 */
724 buffer_size = (l * 5) + 1;
725
726 buf = kvmalloc(buffer_size, GFP_KERNEL);
727 if (!buf)
728 return NULL;
729
730 for (i = 0; i < l; i++)
731 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
732 ascii85_encode(src[i], out));
733
734 return buf;
735}
736
737/* len is expected to be in bytes
738 *
739 * WARNING: *ptr should be allocated with kvmalloc or friends. It can be free'd
740 * with kvfree() and replaced with a newly kvmalloc'd buffer on the first call
741 * when the unencoded raw data is encoded
742 */
743void adreno_show_object(struct drm_printer *p, void **ptr, int len,
744 bool *encoded)
745{
746 if (!*ptr || !len)
747 return;
748
749 if (!*encoded) {
750 long datalen, i;
751 u32 *buf = *ptr;
752
753 /*
754 * Only dump the non-zero part of the buffer - rarely will
755 * any data completely fill the entire allocated size of
756 * the buffer.
757 */
758 for (datalen = 0, i = 0; i < len >> 2; i++)
759 if (buf[i])
760 datalen = ((i + 1) << 2);
761
762 /*
763 * If we reach here, then the originally captured binary buffer
764 * will be replaced with the ascii85 encoded string
765 */
766 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
767
768 kvfree(buf);
769
770 *encoded = true;
771 }
772
773 if (!*ptr)
774 return;
775
776 drm_puts(p, " data: !!ascii85 |\n");
777 drm_puts(p, " ");
778
779 drm_puts(p, *ptr);
780
781 drm_puts(p, "\n");
782}
783
784void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
785 struct drm_printer *p)
786{
787 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
788 int i;
789
790 if (IS_ERR_OR_NULL(state))
791 return;
792
793 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
794 adreno_gpu->info->revn, adreno_gpu->rev.core,
795 adreno_gpu->rev.major, adreno_gpu->rev.minor,
796 adreno_gpu->rev.patchid);
797 /*
798 * If this is state collected due to iova fault, so fault related info
799 *
800 * TTBR0 would not be zero, so this is a good way to distinguish
801 */
802 if (state->fault_info.ttbr0) {
803 const struct msm_gpu_fault_info *info = &state->fault_info;
804
805 drm_puts(p, "fault-info:\n");
806 drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0);
807 drm_printf(p, " - iova=%.16lx\n", info->iova);
808 drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
809 drm_printf(p, " - type=%s\n", info->type);
810 drm_printf(p, " - source=%s\n", info->block);
811 }
812
813 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
814
815 drm_puts(p, "ringbuffer:\n");
816
817 for (i = 0; i < gpu->nr_rings; i++) {
818 drm_printf(p, " - id: %d\n", i);
819 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova);
820 drm_printf(p, " last-fence: %u\n", state->ring[i].seqno);
821 drm_printf(p, " retired-fence: %u\n", state->ring[i].fence);
822 drm_printf(p, " rptr: %u\n", state->ring[i].rptr);
823 drm_printf(p, " wptr: %u\n", state->ring[i].wptr);
824 drm_printf(p, " size: %u\n", MSM_GPU_RINGBUFFER_SZ);
825
826 adreno_show_object(p, &state->ring[i].data,
827 state->ring[i].data_size, &state->ring[i].encoded);
828 }
829
830 if (state->bos) {
831 drm_puts(p, "bos:\n");
832
833 for (i = 0; i < state->nr_bos; i++) {
834 drm_printf(p, " - iova: 0x%016llx\n",
835 state->bos[i].iova);
836 drm_printf(p, " size: %zd\n", state->bos[i].size);
837 drm_printf(p, " name: %-32s\n", state->bos[i].name);
838
839 adreno_show_object(p, &state->bos[i].data,
840 state->bos[i].size, &state->bos[i].encoded);
841 }
842 }
843
844 if (state->nr_registers) {
845 drm_puts(p, "registers:\n");
846
847 for (i = 0; i < state->nr_registers; i++) {
848 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n",
849 state->registers[i * 2] << 2,
850 state->registers[(i * 2) + 1]);
851 }
852 }
853}
854#endif
855
856/* Dump common gpu status and scratch registers on any hang, to make
857 * the hangcheck logs more useful. The scratch registers seem always
858 * safe to read when GPU has hung (unlike some other regs, depending
859 * on how the GPU hung), and they are useful to match up to cmdstream
860 * dumps when debugging hangs:
861 */
862void adreno_dump_info(struct msm_gpu *gpu)
863{
864 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
865 int i;
866
867 printk("revision: %d (%d.%d.%d.%d)\n",
868 adreno_gpu->info->revn, adreno_gpu->rev.core,
869 adreno_gpu->rev.major, adreno_gpu->rev.minor,
870 adreno_gpu->rev.patchid);
871
872 for (i = 0; i < gpu->nr_rings; i++) {
873 struct msm_ringbuffer *ring = gpu->rb[i];
874
875 printk("rb %d: fence: %d/%d\n", i,
876 ring->memptrs->fence,
877 ring->fctx->last_fence);
878
879 printk("rptr: %d\n", get_rptr(adreno_gpu, ring));
880 printk("rb wptr: %d\n", get_wptr(ring));
881 }
882}
883
884/* would be nice to not have to duplicate the _show() stuff with printk(): */
885void adreno_dump(struct msm_gpu *gpu)
886{
887 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
888 int i;
889
890 if (!adreno_gpu->registers)
891 return;
892
893 /* dump these out in a form that can be parsed by demsm: */
894 printk("IO:region %s 00000000 00020000\n", gpu->name);
895 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
896 uint32_t start = adreno_gpu->registers[i];
897 uint32_t end = adreno_gpu->registers[i+1];
898 uint32_t addr;
899
900 for (addr = start; addr <= end; addr++) {
901 uint32_t val = gpu_read(gpu, addr);
902 printk("IO:R %08x %08x\n", addr<<2, val);
903 }
904 }
905}
906
907static uint32_t ring_freewords(struct msm_ringbuffer *ring)
908{
909 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
910 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
911 /* Use ring->next to calculate free size */
912 uint32_t wptr = ring->next - ring->start;
913 uint32_t rptr = get_rptr(adreno_gpu, ring);
914 return (rptr + (size - 1) - wptr) % size;
915}
916
917void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
918{
919 if (spin_until(ring_freewords(ring) >= ndwords))
920 DRM_DEV_ERROR(ring->gpu->dev->dev,
921 "timeout waiting for space in ringbuffer %d\n",
922 ring->id);
923}
924
925/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
926static int adreno_get_legacy_pwrlevels(struct device *dev)
927{
928 struct device_node *child, *node;
929 int ret;
930
931 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
932 if (!node) {
933 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
934 return -ENXIO;
935 }
936
937 for_each_child_of_node(node, child) {
938 unsigned int val;
939
940 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
941 if (ret)
942 continue;
943
944 /*
945 * Skip the intentionally bogus clock value found at the bottom
946 * of most legacy frequency tables
947 */
948 if (val != 27000000)
949 dev_pm_opp_add(dev, val, 0);
950 }
951
952 of_node_put(node);
953
954 return 0;
955}
956
957static void adreno_get_pwrlevels(struct device *dev,
958 struct msm_gpu *gpu)
959{
960 unsigned long freq = ULONG_MAX;
961 struct dev_pm_opp *opp;
962 int ret;
963
964 gpu->fast_rate = 0;
965
966 /* You down with OPP? */
967 if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
968 ret = adreno_get_legacy_pwrlevels(dev);
969 else {
970 ret = devm_pm_opp_of_add_table(dev);
971 if (ret)
972 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
973 }
974
975 if (!ret) {
976 /* Find the fastest defined rate */
977 opp = dev_pm_opp_find_freq_floor(dev, &freq);
978 if (!IS_ERR(opp)) {
979 gpu->fast_rate = freq;
980 dev_pm_opp_put(opp);
981 }
982 }
983
984 if (!gpu->fast_rate) {
985 dev_warn(dev,
986 "Could not find a clock rate. Using a reasonable default\n");
987 /* Pick a suitably safe clock speed for any target */
988 gpu->fast_rate = 200000000;
989 }
990
991 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
992}
993
994int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
995 struct adreno_ocmem *adreno_ocmem)
996{
997 struct ocmem_buf *ocmem_hdl;
998 struct ocmem *ocmem;
999
1000 ocmem = of_get_ocmem(dev);
1001 if (IS_ERR(ocmem)) {
1002 if (PTR_ERR(ocmem) == -ENODEV) {
1003 /*
1004 * Return success since either the ocmem property was
1005 * not specified in device tree, or ocmem support is
1006 * not compiled into the kernel.
1007 */
1008 return 0;
1009 }
1010
1011 return PTR_ERR(ocmem);
1012 }
1013
1014 ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
1015 if (IS_ERR(ocmem_hdl))
1016 return PTR_ERR(ocmem_hdl);
1017
1018 adreno_ocmem->ocmem = ocmem;
1019 adreno_ocmem->base = ocmem_hdl->addr;
1020 adreno_ocmem->hdl = ocmem_hdl;
1021 adreno_gpu->gmem = ocmem_hdl->len;
1022
1023 return 0;
1024}
1025
1026void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
1027{
1028 if (adreno_ocmem && adreno_ocmem->base)
1029 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
1030 adreno_ocmem->hdl);
1031}
1032
1033int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1034{
1035 return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
1036}
1037
1038int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
1039 struct adreno_gpu *adreno_gpu,
1040 const struct adreno_gpu_funcs *funcs, int nr_rings)
1041{
1042 struct device *dev = &pdev->dev;
1043 struct adreno_platform_config *config = dev->platform_data;
1044 struct msm_gpu_config adreno_gpu_config = { 0 };
1045 struct msm_gpu *gpu = &adreno_gpu->base;
1046 struct adreno_rev *rev = &config->rev;
1047 const char *gpu_name;
1048 u32 speedbin;
1049
1050 adreno_gpu->funcs = funcs;
1051 adreno_gpu->info = adreno_info(config->rev);
1052 adreno_gpu->gmem = adreno_gpu->info->gmem;
1053 adreno_gpu->revn = adreno_gpu->info->revn;
1054 adreno_gpu->rev = *rev;
1055
1056 if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1057 speedbin = 0xffff;
1058 adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1059
1060 gpu_name = adreno_gpu->info->name;
1061 if (!gpu_name) {
1062 gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
1063 rev->core, rev->major, rev->minor,
1064 rev->patchid);
1065 if (!gpu_name)
1066 return -ENOMEM;
1067 }
1068
1069 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1070
1071 adreno_gpu_config.nr_rings = nr_rings;
1072
1073 adreno_get_pwrlevels(dev, gpu);
1074
1075 pm_runtime_set_autosuspend_delay(dev,
1076 adreno_gpu->info->inactive_period);
1077 pm_runtime_use_autosuspend(dev);
1078
1079 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1080 gpu_name, &adreno_gpu_config);
1081}
1082
1083void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1084{
1085 struct msm_gpu *gpu = &adreno_gpu->base;
1086 struct msm_drm_private *priv = gpu->dev->dev_private;
1087 unsigned int i;
1088
1089 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1090 release_firmware(adreno_gpu->fw[i]);
1091
1092 if (pm_runtime_enabled(&priv->gpu_pdev->dev))
1093 pm_runtime_disable(&priv->gpu_pdev->dev);
1094
1095 msm_gpu_cleanup(&adreno_gpu->base);
1096}