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1/*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef __INTEL_UNCORE_H__
26#define __INTEL_UNCORE_H__
27
28#include <linux/spinlock.h>
29#include <linux/notifier.h>
30#include <linux/hrtimer.h>
31#include <linux/io-64-nonatomic-lo-hi.h>
32#include <linux/types.h>
33
34#include "i915_reg_defs.h"
35
36struct drm_device;
37struct drm_i915_private;
38struct intel_runtime_pm;
39struct intel_uncore;
40struct intel_gt;
41
42struct intel_uncore_mmio_debug {
43 spinlock_t lock; /** lock is also taken in irq contexts. */
44 int unclaimed_mmio_check;
45 int saved_mmio_check;
46 u32 suspend_count;
47};
48
49enum forcewake_domain_id {
50 FW_DOMAIN_ID_RENDER = 0,
51 FW_DOMAIN_ID_GT, /* also includes blitter engine */
52 FW_DOMAIN_ID_MEDIA,
53 FW_DOMAIN_ID_MEDIA_VDBOX0,
54 FW_DOMAIN_ID_MEDIA_VDBOX1,
55 FW_DOMAIN_ID_MEDIA_VDBOX2,
56 FW_DOMAIN_ID_MEDIA_VDBOX3,
57 FW_DOMAIN_ID_MEDIA_VDBOX4,
58 FW_DOMAIN_ID_MEDIA_VDBOX5,
59 FW_DOMAIN_ID_MEDIA_VDBOX6,
60 FW_DOMAIN_ID_MEDIA_VDBOX7,
61 FW_DOMAIN_ID_MEDIA_VEBOX0,
62 FW_DOMAIN_ID_MEDIA_VEBOX1,
63 FW_DOMAIN_ID_MEDIA_VEBOX2,
64 FW_DOMAIN_ID_MEDIA_VEBOX3,
65 FW_DOMAIN_ID_GSC,
66
67 FW_DOMAIN_ID_COUNT
68};
69
70enum forcewake_domains {
71 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
72 FORCEWAKE_GT = BIT(FW_DOMAIN_ID_GT),
73 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
74 FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
75 FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
76 FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
77 FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
78 FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4),
79 FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5),
80 FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6),
81 FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7),
82 FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
83 FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
84 FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2),
85 FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3),
86 FORCEWAKE_GSC = BIT(FW_DOMAIN_ID_GSC),
87
88 FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
89};
90
91struct intel_uncore_fw_get {
92 void (*force_wake_get)(struct intel_uncore *uncore,
93 enum forcewake_domains domains);
94};
95
96struct intel_uncore_funcs {
97 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
98 i915_reg_t r);
99 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
100 i915_reg_t r);
101
102 u8 (*mmio_readb)(struct intel_uncore *uncore,
103 i915_reg_t r, bool trace);
104 u16 (*mmio_readw)(struct intel_uncore *uncore,
105 i915_reg_t r, bool trace);
106 u32 (*mmio_readl)(struct intel_uncore *uncore,
107 i915_reg_t r, bool trace);
108 u64 (*mmio_readq)(struct intel_uncore *uncore,
109 i915_reg_t r, bool trace);
110
111 void (*mmio_writeb)(struct intel_uncore *uncore,
112 i915_reg_t r, u8 val, bool trace);
113 void (*mmio_writew)(struct intel_uncore *uncore,
114 i915_reg_t r, u16 val, bool trace);
115 void (*mmio_writel)(struct intel_uncore *uncore,
116 i915_reg_t r, u32 val, bool trace);
117};
118
119struct intel_forcewake_range {
120 u32 start;
121 u32 end;
122
123 enum forcewake_domains domains;
124};
125
126/* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
127struct i915_range {
128 u32 start;
129 u32 end;
130};
131
132struct intel_uncore {
133 void __iomem *regs;
134
135 struct drm_i915_private *i915;
136 struct intel_gt *gt;
137 struct intel_runtime_pm *rpm;
138
139 spinlock_t lock; /** lock is also taken in irq contexts. */
140
141 /*
142 * Do we need to apply an additional offset to reach the beginning
143 * of the basic non-engine GT registers (referred to as "GSI" on
144 * newer platforms, or "GT block" on older platforms)? If so, we'll
145 * track that here and apply it transparently to registers in the
146 * appropriate range to maintain compatibility with our existing
147 * register definitions and GT code.
148 */
149 u32 gsi_offset;
150
151 unsigned int flags;
152#define UNCORE_HAS_FORCEWAKE BIT(0)
153#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
154#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
155#define UNCORE_HAS_FIFO BIT(3)
156
157 const struct intel_forcewake_range *fw_domains_table;
158 unsigned int fw_domains_table_entries;
159
160 /*
161 * Shadowed registers are special cases where we can safely write
162 * to the register *without* grabbing forcewake.
163 */
164 const struct i915_range *shadowed_reg_table;
165 unsigned int shadowed_reg_table_entries;
166
167 struct notifier_block pmic_bus_access_nb;
168 const struct intel_uncore_fw_get *fw_get_funcs;
169 struct intel_uncore_funcs funcs;
170
171 unsigned int fifo_count;
172
173 enum forcewake_domains fw_domains;
174 enum forcewake_domains fw_domains_active;
175 enum forcewake_domains fw_domains_timer;
176 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
177
178 struct intel_uncore_forcewake_domain {
179 struct intel_uncore *uncore;
180 enum forcewake_domain_id id;
181 enum forcewake_domains mask;
182 unsigned int wake_count;
183 bool active;
184 struct hrtimer timer;
185 u32 __iomem *reg_set;
186 u32 __iomem *reg_ack;
187 } *fw_domain[FW_DOMAIN_ID_COUNT];
188
189 unsigned int user_forcewake_count;
190
191 struct intel_uncore_mmio_debug *debug;
192};
193
194/* Iterate over initialised fw domains */
195#define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
196 for (tmp__ = (mask__); tmp__ ;) \
197 for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)])
198
199#define for_each_fw_domain(domain__, uncore__, tmp__) \
200 for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
201
202static inline bool
203intel_uncore_has_forcewake(const struct intel_uncore *uncore)
204{
205 return uncore->flags & UNCORE_HAS_FORCEWAKE;
206}
207
208static inline bool
209intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
210{
211 return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
212}
213
214static inline bool
215intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
216{
217 return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
218}
219
220static inline bool
221intel_uncore_has_fifo(const struct intel_uncore *uncore)
222{
223 return uncore->flags & UNCORE_HAS_FIFO;
224}
225
226void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
227void intel_uncore_init_early(struct intel_uncore *uncore,
228 struct intel_gt *gt);
229int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
230int intel_uncore_init_mmio(struct intel_uncore *uncore);
231void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
232 struct intel_gt *gt);
233bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
234bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
235void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
236void intel_uncore_fini_mmio(struct drm_device *dev, void *data);
237void intel_uncore_suspend(struct intel_uncore *uncore);
238void intel_uncore_resume_early(struct intel_uncore *uncore);
239void intel_uncore_runtime_resume(struct intel_uncore *uncore);
240
241void assert_forcewakes_inactive(struct intel_uncore *uncore);
242void assert_forcewakes_active(struct intel_uncore *uncore,
243 enum forcewake_domains fw_domains);
244const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
245
246enum forcewake_domains
247intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
248 i915_reg_t reg, unsigned int op);
249#define FW_REG_READ (1)
250#define FW_REG_WRITE (2)
251
252void intel_uncore_forcewake_get(struct intel_uncore *uncore,
253 enum forcewake_domains domains);
254void intel_uncore_forcewake_put(struct intel_uncore *uncore,
255 enum forcewake_domains domains);
256void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
257 enum forcewake_domains domains);
258void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
259 enum forcewake_domains fw_domains);
260
261/*
262 * Like above but the caller must manage the uncore.lock itself.
263 * Must be used with intel_uncore_read_fw() and friends.
264 */
265void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
266 enum forcewake_domains domains);
267void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
268 enum forcewake_domains domains);
269
270void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
271void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
272
273int __intel_wait_for_register(struct intel_uncore *uncore,
274 i915_reg_t reg,
275 u32 mask,
276 u32 value,
277 unsigned int fast_timeout_us,
278 unsigned int slow_timeout_ms,
279 u32 *out_value);
280static inline int
281intel_wait_for_register(struct intel_uncore *uncore,
282 i915_reg_t reg,
283 u32 mask,
284 u32 value,
285 unsigned int timeout_ms)
286{
287 return __intel_wait_for_register(uncore, reg, mask, value, 2,
288 timeout_ms, NULL);
289}
290
291int __intel_wait_for_register_fw(struct intel_uncore *uncore,
292 i915_reg_t reg,
293 u32 mask,
294 u32 value,
295 unsigned int fast_timeout_us,
296 unsigned int slow_timeout_ms,
297 u32 *out_value);
298static inline int
299intel_wait_for_register_fw(struct intel_uncore *uncore,
300 i915_reg_t reg,
301 u32 mask,
302 u32 value,
303 unsigned int timeout_ms)
304{
305 return __intel_wait_for_register_fw(uncore, reg, mask, value,
306 2, timeout_ms, NULL);
307}
308
309#define IS_GSI_REG(reg) ((reg) < 0x40000)
310
311/* register access functions */
312#define __raw_read(x__, s__) \
313static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
314 i915_reg_t reg) \
315{ \
316 u32 offset = i915_mmio_reg_offset(reg); \
317 if (IS_GSI_REG(offset)) \
318 offset += uncore->gsi_offset; \
319 return read##s__(uncore->regs + offset); \
320}
321
322#define __raw_write(x__, s__) \
323static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
324 i915_reg_t reg, u##x__ val) \
325{ \
326 u32 offset = i915_mmio_reg_offset(reg); \
327 if (IS_GSI_REG(offset)) \
328 offset += uncore->gsi_offset; \
329 write##s__(val, uncore->regs + offset); \
330}
331__raw_read(8, b)
332__raw_read(16, w)
333__raw_read(32, l)
334__raw_read(64, q)
335
336__raw_write(8, b)
337__raw_write(16, w)
338__raw_write(32, l)
339__raw_write(64, q)
340
341#undef __raw_read
342#undef __raw_write
343
344#define __uncore_read(name__, x__, s__, trace__) \
345static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
346 i915_reg_t reg) \
347{ \
348 return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
349}
350
351#define __uncore_write(name__, x__, s__, trace__) \
352static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
353 i915_reg_t reg, u##x__ val) \
354{ \
355 uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
356}
357
358__uncore_read(read8, 8, b, true)
359__uncore_read(read16, 16, w, true)
360__uncore_read(read, 32, l, true)
361__uncore_read(read16_notrace, 16, w, false)
362__uncore_read(read_notrace, 32, l, false)
363
364__uncore_write(write8, 8, b, true)
365__uncore_write(write16, 16, w, true)
366__uncore_write(write, 32, l, true)
367__uncore_write(write_notrace, 32, l, false)
368
369/* Be very careful with read/write 64-bit values. On 32-bit machines, they
370 * will be implemented using 2 32-bit writes in an arbitrary order with
371 * an arbitrary delay between them. This can cause the hardware to
372 * act upon the intermediate value, possibly leading to corruption and
373 * machine death. For this reason we do not support intel_uncore_write64,
374 * or uncore->funcs.mmio_writeq.
375 *
376 * When reading a 64-bit value as two 32-bit values, the delay may cause
377 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
378 * occasionally a 64-bit register does not actually support a full readq
379 * and must be read using two 32-bit reads.
380 *
381 * You have been warned.
382 */
383__uncore_read(read64, 64, q, true)
384
385#define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
386#define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
387
388#undef __uncore_read
389#undef __uncore_write
390
391/* These are untraced mmio-accessors that are only valid to be used inside
392 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
393 * controlled.
394 *
395 * Think twice, and think again, before using these.
396 *
397 * As an example, these accessors can possibly be used between:
398 *
399 * spin_lock_irq(&uncore->lock);
400 * intel_uncore_forcewake_get__locked();
401 *
402 * and
403 *
404 * intel_uncore_forcewake_put__locked();
405 * spin_unlock_irq(&uncore->lock);
406 *
407 *
408 * Note: some registers may not need forcewake held, so
409 * intel_uncore_forcewake_{get,put} can be omitted, see
410 * intel_uncore_forcewake_for_reg().
411 *
412 * Certain architectures will die if the same cacheline is concurrently accessed
413 * by different clients (e.g. on Ivybridge). Access to registers should
414 * therefore generally be serialised, by either the dev_priv->uncore.lock or
415 * a more localised lock guarding all access to that bank of registers.
416 */
417#define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
418#define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
419#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
420#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
421
422static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
423 i915_reg_t reg, u32 clear, u32 set)
424{
425 u32 old, val;
426
427 old = intel_uncore_read(uncore, reg);
428 val = (old & ~clear) | set;
429 intel_uncore_write(uncore, reg, val);
430 return old;
431}
432
433static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
434 i915_reg_t reg, u32 clear, u32 set)
435{
436 u32 old, val;
437
438 old = intel_uncore_read_fw(uncore, reg);
439 val = (old & ~clear) | set;
440 if (val != old)
441 intel_uncore_write_fw(uncore, reg, val);
442}
443
444static inline u64
445intel_uncore_read64_2x32(struct intel_uncore *uncore,
446 i915_reg_t lower_reg, i915_reg_t upper_reg)
447{
448 u32 upper, lower, old_upper, loop = 0;
449 enum forcewake_domains fw_domains;
450 unsigned long flags;
451
452 fw_domains = intel_uncore_forcewake_for_reg(uncore, lower_reg,
453 FW_REG_READ);
454
455 fw_domains |= intel_uncore_forcewake_for_reg(uncore, upper_reg,
456 FW_REG_READ);
457
458 spin_lock_irqsave(&uncore->lock, flags);
459 intel_uncore_forcewake_get__locked(uncore, fw_domains);
460
461 upper = intel_uncore_read_fw(uncore, upper_reg);
462 do {
463 old_upper = upper;
464 lower = intel_uncore_read_fw(uncore, lower_reg);
465 upper = intel_uncore_read_fw(uncore, upper_reg);
466 } while (upper != old_upper && loop++ < 2);
467
468 intel_uncore_forcewake_put__locked(uncore, fw_domains);
469 spin_unlock_irqrestore(&uncore->lock, flags);
470
471 return (u64)upper << 32 | lower;
472}
473
474static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
475 i915_reg_t reg, u32 val,
476 u32 mask, u32 expected_val)
477{
478 u32 reg_val;
479
480 intel_uncore_write(uncore, reg, val);
481 reg_val = intel_uncore_read(uncore, reg);
482
483 return (reg_val & mask) != expected_val ? -EINVAL : 0;
484}
485
486/*
487 * The raw_reg_{read,write} macros are intended as a micro-optimization for
488 * interrupt handlers so that the pointer indirection on uncore->regs can
489 * be computed once (and presumably cached in a register) instead of generating
490 * extra load instructions for each MMIO access.
491 *
492 * Given that these macros are only intended for non-GSI interrupt registers
493 * (and the goal is to avoid extra instructions generated by the compiler),
494 * these macros do not account for uncore->gsi_offset. Any caller that needs
495 * to use these macros on a GSI register is responsible for adding the
496 * appropriate GSI offset to the 'base' parameter.
497 */
498#define raw_reg_read(base, reg) \
499 readl(base + i915_mmio_reg_offset(reg))
500#define raw_reg_write(base, reg, value) \
501 writel(value, base + i915_mmio_reg_offset(reg))
502
503#endif /* !__INTEL_UNCORE_H__ */