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1/*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Robert Bragg <robert@sixbynine.org>
25 */
26
27
28/**
29 * DOC: i915 Perf Overview
30 *
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
33 * GPU.
34 *
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
38 *
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
41 *
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
46 * sysctl option.
47 *
48 */
49
50/**
51 * DOC: i915 Perf History and Comparison with Core Perf
52 *
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
55 *
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
67 *
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
71 *
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
80 *
81 *
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
84 *
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
89 *
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
93 *
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
100 *
101 *
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
104 * hit:
105 *
106 * - The perf based OA PMU driver broke some significant design assumptions:
107 *
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
113 *
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
116 *
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
120 *
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
126 *
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
141 *
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
147 *
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
150 *
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
154 *
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
165 * command streamer.
166 *
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
177 *
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
180 *
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
192 */
193
194#include <linux/anon_inodes.h>
195#include <linux/sizes.h>
196#include <linux/uuid.h>
197
198#include "gem/i915_gem_context.h"
199#include "gem/i915_gem_internal.h"
200#include "gt/intel_engine_pm.h"
201#include "gt/intel_engine_regs.h"
202#include "gt/intel_engine_user.h"
203#include "gt/intel_execlists_submission.h"
204#include "gt/intel_gpu_commands.h"
205#include "gt/intel_gt.h"
206#include "gt/intel_gt_clock_utils.h"
207#include "gt/intel_gt_mcr.h"
208#include "gt/intel_gt_regs.h"
209#include "gt/intel_lrc.h"
210#include "gt/intel_lrc_reg.h"
211#include "gt/intel_ring.h"
212#include "gt/uc/intel_guc_slpc.h"
213
214#include "i915_drv.h"
215#include "i915_file_private.h"
216#include "i915_perf.h"
217#include "i915_perf_oa_regs.h"
218#include "i915_reg.h"
219
220/* HW requires this to be a power of two, between 128k and 16M, though driver
221 * is currently generally designed assuming the largest 16M size is used such
222 * that the overflow cases are unlikely in normal operation.
223 */
224#define OA_BUFFER_SIZE SZ_16M
225
226#define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
227
228/**
229 * DOC: OA Tail Pointer Race
230 *
231 * There's a HW race condition between OA unit tail pointer register updates and
232 * writes to memory whereby the tail pointer can sometimes get ahead of what's
233 * been written out to the OA buffer so far (in terms of what's visible to the
234 * CPU).
235 *
236 * Although this can be observed explicitly while copying reports to userspace
237 * by checking for a zeroed report-id field in tail reports, we want to account
238 * for this earlier, as part of the oa_buffer_check_unlocked to avoid lots of
239 * redundant read() attempts.
240 *
241 * We workaround this issue in oa_buffer_check_unlocked() by reading the reports
242 * in the OA buffer, starting from the tail reported by the HW until we find a
243 * report with its first 2 dwords not 0 meaning its previous report is
244 * completely in memory and ready to be read. Those dwords are also set to 0
245 * once read and the whole buffer is cleared upon OA buffer initialization. The
246 * first dword is the reason for this report while the second is the timestamp,
247 * making the chances of having those 2 fields at 0 fairly unlikely. A more
248 * detailed explanation is available in oa_buffer_check_unlocked().
249 *
250 * Most of the implementation details for this workaround are in
251 * oa_buffer_check_unlocked() and _append_oa_reports()
252 *
253 * Note for posterity: previously the driver used to define an effective tail
254 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
255 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
256 * This was flawed considering that the OA unit may also automatically generate
257 * non-periodic reports (such as on context switch) or the OA unit may be
258 * enabled without any periodic sampling.
259 */
260#define OA_TAIL_MARGIN_NSEC 100000ULL
261#define INVALID_TAIL_PTR 0xffffffff
262
263/* The default frequency for checking whether the OA unit has written new
264 * reports to the circular OA buffer...
265 */
266#define DEFAULT_POLL_FREQUENCY_HZ 200
267#define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
268
269/* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
270static u32 i915_perf_stream_paranoid = true;
271
272/* The maximum exponent the hardware accepts is 63 (essentially it selects one
273 * of the 64bit timestamp bits to trigger reports from) but there's currently
274 * no known use case for sampling as infrequently as once per 47 thousand years.
275 *
276 * Since the timestamps included in OA reports are only 32bits it seems
277 * reasonable to limit the OA exponent where it's still possible to account for
278 * overflow in OA report timestamps.
279 */
280#define OA_EXPONENT_MAX 31
281
282#define INVALID_CTX_ID 0xffffffff
283
284/* On Gen8+ automatically triggered OA reports include a 'reason' field... */
285#define OAREPORT_REASON_MASK 0x3f
286#define OAREPORT_REASON_MASK_EXTENDED 0x7f
287#define OAREPORT_REASON_SHIFT 19
288#define OAREPORT_REASON_TIMER (1<<0)
289#define OAREPORT_REASON_CTX_SWITCH (1<<3)
290#define OAREPORT_REASON_CLK_RATIO (1<<5)
291
292#define HAS_MI_SET_PREDICATE(i915) (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
293
294/* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
295 *
296 * The highest sampling frequency we can theoretically program the OA unit
297 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
298 *
299 * Initialized just before we register the sysctl parameter.
300 */
301static int oa_sample_rate_hard_limit;
302
303/* Theoretically we can program the OA unit to sample every 160ns but don't
304 * allow that by default unless root...
305 *
306 * The default threshold of 100000Hz is based on perf's similar
307 * kernel.perf_event_max_sample_rate sysctl parameter.
308 */
309static u32 i915_oa_max_sample_rate = 100000;
310
311/* XXX: beware if future OA HW adds new report formats that the current
312 * code assumes all reports have a power-of-two size and ~(size - 1) can
313 * be used as a mask to align the OA tail pointer.
314 */
315static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
316 [I915_OA_FORMAT_A13] = { 0, 64 },
317 [I915_OA_FORMAT_A29] = { 1, 128 },
318 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
319 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
320 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
321 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
322 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
323 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
324 [I915_OA_FORMAT_A12] = { 0, 64 },
325 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
326 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
327 [I915_OAR_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
328 [I915_OA_FORMAT_A24u40_A14u32_B8_C8] = { 5, 256 },
329};
330
331#define SAMPLE_OA_REPORT (1<<0)
332
333/**
334 * struct perf_open_properties - for validated properties given to open a stream
335 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
336 * @single_context: Whether a single or all gpu contexts should be monitored
337 * @hold_preemption: Whether the preemption is disabled for the filtered
338 * context
339 * @ctx_handle: A gem ctx handle for use with @single_context
340 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
341 * @oa_format: An OA unit HW report format
342 * @oa_periodic: Whether to enable periodic OA unit sampling
343 * @oa_period_exponent: The OA unit sampling period is derived from this
344 * @engine: The engine (typically rcs0) being monitored by the OA unit
345 * @has_sseu: Whether @sseu was specified by userspace
346 * @sseu: internal SSEU configuration computed either from the userspace
347 * specified configuration in the opening parameters or a default value
348 * (see get_default_sseu_config())
349 * @poll_oa_period: The period in nanoseconds at which the CPU will check for OA
350 * data availability
351 *
352 * As read_properties_unlocked() enumerates and validates the properties given
353 * to open a stream of metrics the configuration is built up in the structure
354 * which starts out zero initialized.
355 */
356struct perf_open_properties {
357 u32 sample_flags;
358
359 u64 single_context:1;
360 u64 hold_preemption:1;
361 u64 ctx_handle;
362
363 /* OA sampling state */
364 int metrics_set;
365 int oa_format;
366 bool oa_periodic;
367 int oa_period_exponent;
368
369 struct intel_engine_cs *engine;
370
371 bool has_sseu;
372 struct intel_sseu sseu;
373
374 u64 poll_oa_period;
375};
376
377struct i915_oa_config_bo {
378 struct llist_node node;
379
380 struct i915_oa_config *oa_config;
381 struct i915_vma *vma;
382};
383
384static struct ctl_table_header *sysctl_header;
385
386static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
387
388void i915_oa_config_release(struct kref *ref)
389{
390 struct i915_oa_config *oa_config =
391 container_of(ref, typeof(*oa_config), ref);
392
393 kfree(oa_config->flex_regs);
394 kfree(oa_config->b_counter_regs);
395 kfree(oa_config->mux_regs);
396
397 kfree_rcu(oa_config, rcu);
398}
399
400struct i915_oa_config *
401i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
402{
403 struct i915_oa_config *oa_config;
404
405 rcu_read_lock();
406 oa_config = idr_find(&perf->metrics_idr, metrics_set);
407 if (oa_config)
408 oa_config = i915_oa_config_get(oa_config);
409 rcu_read_unlock();
410
411 return oa_config;
412}
413
414static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
415{
416 i915_oa_config_put(oa_bo->oa_config);
417 i915_vma_put(oa_bo->vma);
418 kfree(oa_bo);
419}
420
421static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
422{
423 struct intel_uncore *uncore = stream->uncore;
424
425 return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
426 GEN12_OAG_OATAILPTR_MASK;
427}
428
429static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
430{
431 struct intel_uncore *uncore = stream->uncore;
432
433 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
434}
435
436static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
437{
438 struct intel_uncore *uncore = stream->uncore;
439 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
440
441 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
442}
443
444/**
445 * oa_buffer_check_unlocked - check for data and update tail ptr state
446 * @stream: i915 stream instance
447 *
448 * This is either called via fops (for blocking reads in user ctx) or the poll
449 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
450 * if there is data available for userspace to read.
451 *
452 * This function is central to providing a workaround for the OA unit tail
453 * pointer having a race with respect to what data is visible to the CPU.
454 * It is responsible for reading tail pointers from the hardware and giving
455 * the pointers time to 'age' before they are made available for reading.
456 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
457 *
458 * Besides returning true when there is data available to read() this function
459 * also updates the tail, aging_tail and aging_timestamp in the oa_buffer
460 * object.
461 *
462 * Note: It's safe to read OA config state here unlocked, assuming that this is
463 * only called while the stream is enabled, while the global OA configuration
464 * can't be modified.
465 *
466 * Returns: %true if the OA buffer contains data, else %false
467 */
468static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
469{
470 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
471 int report_size = stream->oa_buffer.format->size;
472 unsigned long flags;
473 bool pollin;
474 u32 hw_tail;
475 u64 now;
476
477 /* We have to consider the (unlikely) possibility that read() errors
478 * could result in an OA buffer reset which might reset the head and
479 * tail state.
480 */
481 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
482
483 hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
484
485 /* The tail pointer increases in 64 byte increments,
486 * not in report_size steps...
487 */
488 hw_tail &= ~(report_size - 1);
489
490 now = ktime_get_mono_fast_ns();
491
492 if (hw_tail == stream->oa_buffer.aging_tail &&
493 (now - stream->oa_buffer.aging_timestamp) > OA_TAIL_MARGIN_NSEC) {
494 /* If the HW tail hasn't move since the last check and the HW
495 * tail has been aging for long enough, declare it the new
496 * tail.
497 */
498 stream->oa_buffer.tail = stream->oa_buffer.aging_tail;
499 } else {
500 u32 head, tail, aged_tail;
501
502 /* NB: The head we observe here might effectively be a little
503 * out of date. If a read() is in progress, the head could be
504 * anywhere between this head and stream->oa_buffer.tail.
505 */
506 head = stream->oa_buffer.head - gtt_offset;
507 aged_tail = stream->oa_buffer.tail - gtt_offset;
508
509 hw_tail -= gtt_offset;
510 tail = hw_tail;
511
512 /* Walk the stream backward until we find a report with dword 0
513 * & 1 not at 0. Since the circular buffer pointers progress by
514 * increments of 64 bytes and that reports can be up to 256
515 * bytes long, we can't tell whether a report has fully landed
516 * in memory before the first 2 dwords of the following report
517 * have effectively landed.
518 *
519 * This is assuming that the writes of the OA unit land in
520 * memory in the order they were written to.
521 * If not : (╯°□°）╯︵ ┻━┻
522 */
523 while (OA_TAKEN(tail, aged_tail) >= report_size) {
524 u32 *report32 = (void *)(stream->oa_buffer.vaddr + tail);
525
526 if (report32[0] != 0 || report32[1] != 0)
527 break;
528
529 tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
530 }
531
532 if (OA_TAKEN(hw_tail, tail) > report_size &&
533 __ratelimit(&stream->perf->tail_pointer_race))
534 drm_notice(&stream->uncore->i915->drm,
535 "unlanded report(s) head=0x%x tail=0x%x hw_tail=0x%x\n",
536 head, tail, hw_tail);
537
538 stream->oa_buffer.tail = gtt_offset + tail;
539 stream->oa_buffer.aging_tail = gtt_offset + hw_tail;
540 stream->oa_buffer.aging_timestamp = now;
541 }
542
543 pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
544 stream->oa_buffer.head - gtt_offset) >= report_size;
545
546 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
547
548 return pollin;
549}
550
551/**
552 * append_oa_status - Appends a status record to a userspace read() buffer.
553 * @stream: An i915-perf stream opened for OA metrics
554 * @buf: destination buffer given by userspace
555 * @count: the number of bytes userspace wants to read
556 * @offset: (inout): the current position for writing into @buf
557 * @type: The kind of status to report to userspace
558 *
559 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
560 * into the userspace read() buffer.
561 *
562 * The @buf @offset will only be updated on success.
563 *
564 * Returns: 0 on success, negative error code on failure.
565 */
566static int append_oa_status(struct i915_perf_stream *stream,
567 char __user *buf,
568 size_t count,
569 size_t *offset,
570 enum drm_i915_perf_record_type type)
571{
572 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
573
574 if ((count - *offset) < header.size)
575 return -ENOSPC;
576
577 if (copy_to_user(buf + *offset, &header, sizeof(header)))
578 return -EFAULT;
579
580 (*offset) += header.size;
581
582 return 0;
583}
584
585/**
586 * append_oa_sample - Copies single OA report into userspace read() buffer.
587 * @stream: An i915-perf stream opened for OA metrics
588 * @buf: destination buffer given by userspace
589 * @count: the number of bytes userspace wants to read
590 * @offset: (inout): the current position for writing into @buf
591 * @report: A single OA report to (optionally) include as part of the sample
592 *
593 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
594 * properties when opening a stream, tracked as `stream->sample_flags`. This
595 * function copies the requested components of a single sample to the given
596 * read() @buf.
597 *
598 * The @buf @offset will only be updated on success.
599 *
600 * Returns: 0 on success, negative error code on failure.
601 */
602static int append_oa_sample(struct i915_perf_stream *stream,
603 char __user *buf,
604 size_t count,
605 size_t *offset,
606 const u8 *report)
607{
608 int report_size = stream->oa_buffer.format->size;
609 struct drm_i915_perf_record_header header;
610
611 header.type = DRM_I915_PERF_RECORD_SAMPLE;
612 header.pad = 0;
613 header.size = stream->sample_size;
614
615 if ((count - *offset) < header.size)
616 return -ENOSPC;
617
618 buf += *offset;
619 if (copy_to_user(buf, &header, sizeof(header)))
620 return -EFAULT;
621 buf += sizeof(header);
622
623 if (copy_to_user(buf, report, report_size))
624 return -EFAULT;
625
626 (*offset) += header.size;
627
628 return 0;
629}
630
631/**
632 * gen8_append_oa_reports - Copies all buffered OA reports into
633 * userspace read() buffer.
634 * @stream: An i915-perf stream opened for OA metrics
635 * @buf: destination buffer given by userspace
636 * @count: the number of bytes userspace wants to read
637 * @offset: (inout): the current position for writing into @buf
638 *
639 * Notably any error condition resulting in a short read (-%ENOSPC or
640 * -%EFAULT) will be returned even though one or more records may
641 * have been successfully copied. In this case it's up to the caller
642 * to decide if the error should be squashed before returning to
643 * userspace.
644 *
645 * Note: reports are consumed from the head, and appended to the
646 * tail, so the tail chases the head?... If you think that's mad
647 * and back-to-front you're not alone, but this follows the
648 * Gen PRM naming convention.
649 *
650 * Returns: 0 on success, negative error code on failure.
651 */
652static int gen8_append_oa_reports(struct i915_perf_stream *stream,
653 char __user *buf,
654 size_t count,
655 size_t *offset)
656{
657 struct intel_uncore *uncore = stream->uncore;
658 int report_size = stream->oa_buffer.format->size;
659 u8 *oa_buf_base = stream->oa_buffer.vaddr;
660 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
661 u32 mask = (OA_BUFFER_SIZE - 1);
662 size_t start_offset = *offset;
663 unsigned long flags;
664 u32 head, tail;
665 int ret = 0;
666
667 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
668 return -EIO;
669
670 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
671
672 head = stream->oa_buffer.head;
673 tail = stream->oa_buffer.tail;
674
675 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
676
677 /*
678 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
679 * while indexing relative to oa_buf_base.
680 */
681 head -= gtt_offset;
682 tail -= gtt_offset;
683
684 /*
685 * An out of bounds or misaligned head or tail pointer implies a driver
686 * bug since we validate + align the tail pointers we read from the
687 * hardware and we are in full control of the head pointer which should
688 * only be incremented by multiples of the report size (notably also
689 * all a power of two).
690 */
691 if (drm_WARN_ONCE(&uncore->i915->drm,
692 head > OA_BUFFER_SIZE || head % report_size ||
693 tail > OA_BUFFER_SIZE || tail % report_size,
694 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
695 head, tail))
696 return -EIO;
697
698
699 for (/* none */;
700 OA_TAKEN(tail, head);
701 head = (head + report_size) & mask) {
702 u8 *report = oa_buf_base + head;
703 u32 *report32 = (void *)report;
704 u32 ctx_id;
705 u32 reason;
706
707 /*
708 * All the report sizes factor neatly into the buffer
709 * size so we never expect to see a report split
710 * between the beginning and end of the buffer.
711 *
712 * Given the initial alignment check a misalignment
713 * here would imply a driver bug that would result
714 * in an overrun.
715 */
716 if (drm_WARN_ON(&uncore->i915->drm,
717 (OA_BUFFER_SIZE - head) < report_size)) {
718 drm_err(&uncore->i915->drm,
719 "Spurious OA head ptr: non-integral report offset\n");
720 break;
721 }
722
723 /*
724 * The reason field includes flags identifying what
725 * triggered this specific report (mostly timer
726 * triggered or e.g. due to a context switch).
727 *
728 * This field is never expected to be zero so we can
729 * check that the report isn't invalid before copying
730 * it to userspace...
731 */
732 reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
733 (GRAPHICS_VER(stream->perf->i915) == 12 ?
734 OAREPORT_REASON_MASK_EXTENDED :
735 OAREPORT_REASON_MASK));
736
737 ctx_id = report32[2] & stream->specific_ctx_id_mask;
738
739 /*
740 * Squash whatever is in the CTX_ID field if it's marked as
741 * invalid to be sure we avoid false-positive, single-context
742 * filtering below...
743 *
744 * Note: that we don't clear the valid_ctx_bit so userspace can
745 * understand that the ID has been squashed by the kernel.
746 */
747 if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
748 GRAPHICS_VER(stream->perf->i915) <= 11)
749 ctx_id = report32[2] = INVALID_CTX_ID;
750
751 /*
752 * NB: For Gen 8 the OA unit no longer supports clock gating
753 * off for a specific context and the kernel can't securely
754 * stop the counters from updating as system-wide / global
755 * values.
756 *
757 * Automatic reports now include a context ID so reports can be
758 * filtered on the cpu but it's not worth trying to
759 * automatically subtract/hide counter progress for other
760 * contexts while filtering since we can't stop userspace
761 * issuing MI_REPORT_PERF_COUNT commands which would still
762 * provide a side-band view of the real values.
763 *
764 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
765 * to normalize counters for a single filtered context then it
766 * needs be forwarded bookend context-switch reports so that it
767 * can track switches in between MI_REPORT_PERF_COUNT commands
768 * and can itself subtract/ignore the progress of counters
769 * associated with other contexts. Note that the hardware
770 * automatically triggers reports when switching to a new
771 * context which are tagged with the ID of the newly active
772 * context. To avoid the complexity (and likely fragility) of
773 * reading ahead while parsing reports to try and minimize
774 * forwarding redundant context switch reports (i.e. between
775 * other, unrelated contexts) we simply elect to forward them
776 * all.
777 *
778 * We don't rely solely on the reason field to identify context
779 * switches since it's not-uncommon for periodic samples to
780 * identify a switch before any 'context switch' report.
781 */
782 if (!stream->ctx ||
783 stream->specific_ctx_id == ctx_id ||
784 stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
785 reason & OAREPORT_REASON_CTX_SWITCH) {
786
787 /*
788 * While filtering for a single context we avoid
789 * leaking the IDs of other contexts.
790 */
791 if (stream->ctx &&
792 stream->specific_ctx_id != ctx_id) {
793 report32[2] = INVALID_CTX_ID;
794 }
795
796 ret = append_oa_sample(stream, buf, count, offset,
797 report);
798 if (ret)
799 break;
800
801 stream->oa_buffer.last_ctx_id = ctx_id;
802 }
803
804 /*
805 * Clear out the first 2 dword as a mean to detect unlanded
806 * reports.
807 */
808 report32[0] = 0;
809 report32[1] = 0;
810 }
811
812 if (start_offset != *offset) {
813 i915_reg_t oaheadptr;
814
815 oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
816 GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR;
817
818 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
819
820 /*
821 * We removed the gtt_offset for the copy loop above, indexing
822 * relative to oa_buf_base so put back here...
823 */
824 head += gtt_offset;
825 intel_uncore_write(uncore, oaheadptr,
826 head & GEN12_OAG_OAHEADPTR_MASK);
827 stream->oa_buffer.head = head;
828
829 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
830 }
831
832 return ret;
833}
834
835/**
836 * gen8_oa_read - copy status records then buffered OA reports
837 * @stream: An i915-perf stream opened for OA metrics
838 * @buf: destination buffer given by userspace
839 * @count: the number of bytes userspace wants to read
840 * @offset: (inout): the current position for writing into @buf
841 *
842 * Checks OA unit status registers and if necessary appends corresponding
843 * status records for userspace (such as for a buffer full condition) and then
844 * initiate appending any buffered OA reports.
845 *
846 * Updates @offset according to the number of bytes successfully copied into
847 * the userspace buffer.
848 *
849 * NB: some data may be successfully copied to the userspace buffer
850 * even if an error is returned, and this is reflected in the
851 * updated @offset.
852 *
853 * Returns: zero on success or a negative error code
854 */
855static int gen8_oa_read(struct i915_perf_stream *stream,
856 char __user *buf,
857 size_t count,
858 size_t *offset)
859{
860 struct intel_uncore *uncore = stream->uncore;
861 u32 oastatus;
862 i915_reg_t oastatus_reg;
863 int ret;
864
865 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
866 return -EIO;
867
868 oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
869 GEN12_OAG_OASTATUS : GEN8_OASTATUS;
870
871 oastatus = intel_uncore_read(uncore, oastatus_reg);
872
873 /*
874 * We treat OABUFFER_OVERFLOW as a significant error:
875 *
876 * Although theoretically we could handle this more gracefully
877 * sometimes, some Gens don't correctly suppress certain
878 * automatically triggered reports in this condition and so we
879 * have to assume that old reports are now being trampled
880 * over.
881 *
882 * Considering how we don't currently give userspace control
883 * over the OA buffer size and always configure a large 16MB
884 * buffer, then a buffer overflow does anyway likely indicate
885 * that something has gone quite badly wrong.
886 */
887 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
888 ret = append_oa_status(stream, buf, count, offset,
889 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
890 if (ret)
891 return ret;
892
893 drm_dbg(&stream->perf->i915->drm,
894 "OA buffer overflow (exponent = %d): force restart\n",
895 stream->period_exponent);
896
897 stream->perf->ops.oa_disable(stream);
898 stream->perf->ops.oa_enable(stream);
899
900 /*
901 * Note: .oa_enable() is expected to re-init the oabuffer and
902 * reset GEN8_OASTATUS for us
903 */
904 oastatus = intel_uncore_read(uncore, oastatus_reg);
905 }
906
907 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
908 ret = append_oa_status(stream, buf, count, offset,
909 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
910 if (ret)
911 return ret;
912
913 intel_uncore_rmw(uncore, oastatus_reg,
914 GEN8_OASTATUS_COUNTER_OVERFLOW |
915 GEN8_OASTATUS_REPORT_LOST,
916 IS_GRAPHICS_VER(uncore->i915, 8, 11) ?
917 (GEN8_OASTATUS_HEAD_POINTER_WRAP |
918 GEN8_OASTATUS_TAIL_POINTER_WRAP) : 0);
919 }
920
921 return gen8_append_oa_reports(stream, buf, count, offset);
922}
923
924/**
925 * gen7_append_oa_reports - Copies all buffered OA reports into
926 * userspace read() buffer.
927 * @stream: An i915-perf stream opened for OA metrics
928 * @buf: destination buffer given by userspace
929 * @count: the number of bytes userspace wants to read
930 * @offset: (inout): the current position for writing into @buf
931 *
932 * Notably any error condition resulting in a short read (-%ENOSPC or
933 * -%EFAULT) will be returned even though one or more records may
934 * have been successfully copied. In this case it's up to the caller
935 * to decide if the error should be squashed before returning to
936 * userspace.
937 *
938 * Note: reports are consumed from the head, and appended to the
939 * tail, so the tail chases the head?... If you think that's mad
940 * and back-to-front you're not alone, but this follows the
941 * Gen PRM naming convention.
942 *
943 * Returns: 0 on success, negative error code on failure.
944 */
945static int gen7_append_oa_reports(struct i915_perf_stream *stream,
946 char __user *buf,
947 size_t count,
948 size_t *offset)
949{
950 struct intel_uncore *uncore = stream->uncore;
951 int report_size = stream->oa_buffer.format->size;
952 u8 *oa_buf_base = stream->oa_buffer.vaddr;
953 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
954 u32 mask = (OA_BUFFER_SIZE - 1);
955 size_t start_offset = *offset;
956 unsigned long flags;
957 u32 head, tail;
958 int ret = 0;
959
960 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
961 return -EIO;
962
963 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
964
965 head = stream->oa_buffer.head;
966 tail = stream->oa_buffer.tail;
967
968 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
969
970 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
971 * while indexing relative to oa_buf_base.
972 */
973 head -= gtt_offset;
974 tail -= gtt_offset;
975
976 /* An out of bounds or misaligned head or tail pointer implies a driver
977 * bug since we validate + align the tail pointers we read from the
978 * hardware and we are in full control of the head pointer which should
979 * only be incremented by multiples of the report size (notably also
980 * all a power of two).
981 */
982 if (drm_WARN_ONCE(&uncore->i915->drm,
983 head > OA_BUFFER_SIZE || head % report_size ||
984 tail > OA_BUFFER_SIZE || tail % report_size,
985 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
986 head, tail))
987 return -EIO;
988
989
990 for (/* none */;
991 OA_TAKEN(tail, head);
992 head = (head + report_size) & mask) {
993 u8 *report = oa_buf_base + head;
994 u32 *report32 = (void *)report;
995
996 /* All the report sizes factor neatly into the buffer
997 * size so we never expect to see a report split
998 * between the beginning and end of the buffer.
999 *
1000 * Given the initial alignment check a misalignment
1001 * here would imply a driver bug that would result
1002 * in an overrun.
1003 */
1004 if (drm_WARN_ON(&uncore->i915->drm,
1005 (OA_BUFFER_SIZE - head) < report_size)) {
1006 drm_err(&uncore->i915->drm,
1007 "Spurious OA head ptr: non-integral report offset\n");
1008 break;
1009 }
1010
1011 /* The report-ID field for periodic samples includes
1012 * some undocumented flags related to what triggered
1013 * the report and is never expected to be zero so we
1014 * can check that the report isn't invalid before
1015 * copying it to userspace...
1016 */
1017 if (report32[0] == 0) {
1018 if (__ratelimit(&stream->perf->spurious_report_rs))
1019 drm_notice(&uncore->i915->drm,
1020 "Skipping spurious, invalid OA report\n");
1021 continue;
1022 }
1023
1024 ret = append_oa_sample(stream, buf, count, offset, report);
1025 if (ret)
1026 break;
1027
1028 /* Clear out the first 2 dwords as a mean to detect unlanded
1029 * reports.
1030 */
1031 report32[0] = 0;
1032 report32[1] = 0;
1033 }
1034
1035 if (start_offset != *offset) {
1036 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1037
1038 /* We removed the gtt_offset for the copy loop above, indexing
1039 * relative to oa_buf_base so put back here...
1040 */
1041 head += gtt_offset;
1042
1043 intel_uncore_write(uncore, GEN7_OASTATUS2,
1044 (head & GEN7_OASTATUS2_HEAD_MASK) |
1045 GEN7_OASTATUS2_MEM_SELECT_GGTT);
1046 stream->oa_buffer.head = head;
1047
1048 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1049 }
1050
1051 return ret;
1052}
1053
1054/**
1055 * gen7_oa_read - copy status records then buffered OA reports
1056 * @stream: An i915-perf stream opened for OA metrics
1057 * @buf: destination buffer given by userspace
1058 * @count: the number of bytes userspace wants to read
1059 * @offset: (inout): the current position for writing into @buf
1060 *
1061 * Checks Gen 7 specific OA unit status registers and if necessary appends
1062 * corresponding status records for userspace (such as for a buffer full
1063 * condition) and then initiate appending any buffered OA reports.
1064 *
1065 * Updates @offset according to the number of bytes successfully copied into
1066 * the userspace buffer.
1067 *
1068 * Returns: zero on success or a negative error code
1069 */
1070static int gen7_oa_read(struct i915_perf_stream *stream,
1071 char __user *buf,
1072 size_t count,
1073 size_t *offset)
1074{
1075 struct intel_uncore *uncore = stream->uncore;
1076 u32 oastatus1;
1077 int ret;
1078
1079 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
1080 return -EIO;
1081
1082 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1083
1084 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1085 * bits while the OA unit is enabled (while the tail pointer
1086 * may be updated asynchronously) so we ignore status bits
1087 * that have already been reported to userspace.
1088 */
1089 oastatus1 &= ~stream->perf->gen7_latched_oastatus1;
1090
1091 /* We treat OABUFFER_OVERFLOW as a significant error:
1092 *
1093 * - The status can be interpreted to mean that the buffer is
1094 * currently full (with a higher precedence than OA_TAKEN()
1095 * which will start to report a near-empty buffer after an
1096 * overflow) but it's awkward that we can't clear the status
1097 * on Haswell, so without a reset we won't be able to catch
1098 * the state again.
1099 *
1100 * - Since it also implies the HW has started overwriting old
1101 * reports it may also affect our sanity checks for invalid
1102 * reports when copying to userspace that assume new reports
1103 * are being written to cleared memory.
1104 *
1105 * - In the future we may want to introduce a flight recorder
1106 * mode where the driver will automatically maintain a safe
1107 * guard band between head/tail, avoiding this overflow
1108 * condition, but we avoid the added driver complexity for
1109 * now.
1110 */
1111 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1112 ret = append_oa_status(stream, buf, count, offset,
1113 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1114 if (ret)
1115 return ret;
1116
1117 drm_dbg(&stream->perf->i915->drm,
1118 "OA buffer overflow (exponent = %d): force restart\n",
1119 stream->period_exponent);
1120
1121 stream->perf->ops.oa_disable(stream);
1122 stream->perf->ops.oa_enable(stream);
1123
1124 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1125 }
1126
1127 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1128 ret = append_oa_status(stream, buf, count, offset,
1129 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1130 if (ret)
1131 return ret;
1132 stream->perf->gen7_latched_oastatus1 |=
1133 GEN7_OASTATUS1_REPORT_LOST;
1134 }
1135
1136 return gen7_append_oa_reports(stream, buf, count, offset);
1137}
1138
1139/**
1140 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1141 * @stream: An i915-perf stream opened for OA metrics
1142 *
1143 * Called when userspace tries to read() from a blocking stream FD opened
1144 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1145 * OA buffer and wakes us.
1146 *
1147 * Note: it's acceptable to have this return with some false positives
1148 * since any subsequent read handling will return -EAGAIN if there isn't
1149 * really data ready for userspace yet.
1150 *
1151 * Returns: zero on success or a negative error code
1152 */
1153static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1154{
1155 /* We would wait indefinitely if periodic sampling is not enabled */
1156 if (!stream->periodic)
1157 return -EIO;
1158
1159 return wait_event_interruptible(stream->poll_wq,
1160 oa_buffer_check_unlocked(stream));
1161}
1162
1163/**
1164 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1165 * @stream: An i915-perf stream opened for OA metrics
1166 * @file: An i915 perf stream file
1167 * @wait: poll() state table
1168 *
1169 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1170 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1171 * when it sees data ready to read in the circular OA buffer.
1172 */
1173static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1174 struct file *file,
1175 poll_table *wait)
1176{
1177 poll_wait(file, &stream->poll_wq, wait);
1178}
1179
1180/**
1181 * i915_oa_read - just calls through to &i915_oa_ops->read
1182 * @stream: An i915-perf stream opened for OA metrics
1183 * @buf: destination buffer given by userspace
1184 * @count: the number of bytes userspace wants to read
1185 * @offset: (inout): the current position for writing into @buf
1186 *
1187 * Updates @offset according to the number of bytes successfully copied into
1188 * the userspace buffer.
1189 *
1190 * Returns: zero on success or a negative error code
1191 */
1192static int i915_oa_read(struct i915_perf_stream *stream,
1193 char __user *buf,
1194 size_t count,
1195 size_t *offset)
1196{
1197 return stream->perf->ops.read(stream, buf, count, offset);
1198}
1199
1200static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
1201{
1202 struct i915_gem_engines_iter it;
1203 struct i915_gem_context *ctx = stream->ctx;
1204 struct intel_context *ce;
1205 struct i915_gem_ww_ctx ww;
1206 int err = -ENODEV;
1207
1208 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1209 if (ce->engine != stream->engine) /* first match! */
1210 continue;
1211
1212 err = 0;
1213 break;
1214 }
1215 i915_gem_context_unlock_engines(ctx);
1216
1217 if (err)
1218 return ERR_PTR(err);
1219
1220 i915_gem_ww_ctx_init(&ww, true);
1221retry:
1222 /*
1223 * As the ID is the gtt offset of the context's vma we
1224 * pin the vma to ensure the ID remains fixed.
1225 */
1226 err = intel_context_pin_ww(ce, &ww);
1227 if (err == -EDEADLK) {
1228 err = i915_gem_ww_ctx_backoff(&ww);
1229 if (!err)
1230 goto retry;
1231 }
1232 i915_gem_ww_ctx_fini(&ww);
1233
1234 if (err)
1235 return ERR_PTR(err);
1236
1237 stream->pinned_ctx = ce;
1238 return stream->pinned_ctx;
1239}
1240
1241static int
1242__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
1243{
1244 u32 *cs, cmd;
1245
1246 cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1247 if (GRAPHICS_VER(rq->engine->i915) >= 8)
1248 cmd++;
1249
1250 cs = intel_ring_begin(rq, 4);
1251 if (IS_ERR(cs))
1252 return PTR_ERR(cs);
1253
1254 *cs++ = cmd;
1255 *cs++ = i915_mmio_reg_offset(reg);
1256 *cs++ = ggtt_offset;
1257 *cs++ = 0;
1258
1259 intel_ring_advance(rq, cs);
1260
1261 return 0;
1262}
1263
1264static int
1265__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
1266{
1267 struct i915_request *rq;
1268 int err;
1269
1270 rq = i915_request_create(ce);
1271 if (IS_ERR(rq))
1272 return PTR_ERR(rq);
1273
1274 i915_request_get(rq);
1275
1276 err = __store_reg_to_mem(rq, reg, ggtt_offset);
1277
1278 i915_request_add(rq);
1279 if (!err && i915_request_wait(rq, 0, HZ / 2) < 0)
1280 err = -ETIME;
1281
1282 i915_request_put(rq);
1283
1284 return err;
1285}
1286
1287static int
1288gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id)
1289{
1290 struct i915_vma *scratch;
1291 u32 *val;
1292 int err;
1293
1294 scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
1295 if (IS_ERR(scratch))
1296 return PTR_ERR(scratch);
1297
1298 err = i915_vma_sync(scratch);
1299 if (err)
1300 goto err_scratch;
1301
1302 err = __read_reg(ce, RING_EXECLIST_STATUS_HI(ce->engine->mmio_base),
1303 i915_ggtt_offset(scratch));
1304 if (err)
1305 goto err_scratch;
1306
1307 val = i915_gem_object_pin_map_unlocked(scratch->obj, I915_MAP_WB);
1308 if (IS_ERR(val)) {
1309 err = PTR_ERR(val);
1310 goto err_scratch;
1311 }
1312
1313 *ctx_id = *val;
1314 i915_gem_object_unpin_map(scratch->obj);
1315
1316err_scratch:
1317 i915_vma_unpin_and_release(&scratch, 0);
1318 return err;
1319}
1320
1321/*
1322 * For execlist mode of submission, pick an unused context id
1323 * 0 - (NUM_CONTEXT_TAG -1) are used by other contexts
1324 * XXX_MAX_CONTEXT_HW_ID is used by idle context
1325 *
1326 * For GuC mode of submission read context id from the upper dword of the
1327 * EXECLIST_STATUS register. Note that we read this value only once and expect
1328 * that the value stays fixed for the entire OA use case. There are cases where
1329 * GuC KMD implementation may deregister a context to reuse it's context id, but
1330 * we prevent that from happening to the OA context by pinning it.
1331 */
1332static int gen12_get_render_context_id(struct i915_perf_stream *stream)
1333{
1334 u32 ctx_id, mask;
1335 int ret;
1336
1337 if (intel_engine_uses_guc(stream->engine)) {
1338 ret = gen12_guc_sw_ctx_id(stream->pinned_ctx, &ctx_id);
1339 if (ret)
1340 return ret;
1341
1342 mask = ((1U << GEN12_GUC_SW_CTX_ID_WIDTH) - 1) <<
1343 (GEN12_GUC_SW_CTX_ID_SHIFT - 32);
1344 } else if (GRAPHICS_VER_FULL(stream->engine->i915) >= IP_VER(12, 50)) {
1345 ctx_id = (XEHP_MAX_CONTEXT_HW_ID - 1) <<
1346 (XEHP_SW_CTX_ID_SHIFT - 32);
1347
1348 mask = ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
1349 (XEHP_SW_CTX_ID_SHIFT - 32);
1350 } else {
1351 ctx_id = (GEN12_MAX_CONTEXT_HW_ID - 1) <<
1352 (GEN11_SW_CTX_ID_SHIFT - 32);
1353
1354 mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
1355 (GEN11_SW_CTX_ID_SHIFT - 32);
1356 }
1357 stream->specific_ctx_id = ctx_id & mask;
1358 stream->specific_ctx_id_mask = mask;
1359
1360 return 0;
1361}
1362
1363static bool oa_find_reg_in_lri(u32 *state, u32 reg, u32 *offset, u32 end)
1364{
1365 u32 idx = *offset;
1366 u32 len = min(MI_LRI_LEN(state[idx]) + idx, end);
1367 bool found = false;
1368
1369 idx++;
1370 for (; idx < len; idx += 2) {
1371 if (state[idx] == reg) {
1372 found = true;
1373 break;
1374 }
1375 }
1376
1377 *offset = idx;
1378 return found;
1379}
1380
1381static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
1382{
1383 u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
1384 u32 *state = ce->lrc_reg_state;
1385
1386 if (drm_WARN_ON(&ce->engine->i915->drm, !state))
1387 return U32_MAX;
1388
1389 for (offset = 0; offset < len; ) {
1390 if (IS_MI_LRI_CMD(state[offset])) {
1391 /*
1392 * We expect reg-value pairs in MI_LRI command, so
1393 * MI_LRI_LEN() should be even, if not, issue a warning.
1394 */
1395 drm_WARN_ON(&ce->engine->i915->drm,
1396 MI_LRI_LEN(state[offset]) & 0x1);
1397
1398 if (oa_find_reg_in_lri(state, reg, &offset, len))
1399 break;
1400 } else {
1401 offset++;
1402 }
1403 }
1404
1405 return offset < len ? offset : U32_MAX;
1406}
1407
1408static int set_oa_ctx_ctrl_offset(struct intel_context *ce)
1409{
1410 i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
1411 struct i915_perf *perf = &ce->engine->i915->perf;
1412 u32 offset = perf->ctx_oactxctrl_offset;
1413
1414 /* Do this only once. Failure is stored as offset of U32_MAX */
1415 if (offset)
1416 goto exit;
1417
1418 offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg));
1419 perf->ctx_oactxctrl_offset = offset;
1420
1421 drm_dbg(&ce->engine->i915->drm,
1422 "%s oa ctx control at 0x%08x dword offset\n",
1423 ce->engine->name, offset);
1424
1425exit:
1426 return offset && offset != U32_MAX ? 0 : -ENODEV;
1427}
1428
1429static bool engine_supports_mi_query(struct intel_engine_cs *engine)
1430{
1431 return engine->class == RENDER_CLASS;
1432}
1433
1434/**
1435 * oa_get_render_ctx_id - determine and hold ctx hw id
1436 * @stream: An i915-perf stream opened for OA metrics
1437 *
1438 * Determine the render context hw id, and ensure it remains fixed for the
1439 * lifetime of the stream. This ensures that we don't have to worry about
1440 * updating the context ID in OACONTROL on the fly.
1441 *
1442 * Returns: zero on success or a negative error code
1443 */
1444static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1445{
1446 struct intel_context *ce;
1447 int ret = 0;
1448
1449 ce = oa_pin_context(stream);
1450 if (IS_ERR(ce))
1451 return PTR_ERR(ce);
1452
1453 if (engine_supports_mi_query(stream->engine) &&
1454 HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
1455 /*
1456 * We are enabling perf query here. If we don't find the context
1457 * offset here, just return an error.
1458 */
1459 ret = set_oa_ctx_ctrl_offset(ce);
1460 if (ret) {
1461 intel_context_unpin(ce);
1462 drm_err(&stream->perf->i915->drm,
1463 "Enabling perf query failed for %s\n",
1464 stream->engine->name);
1465 return ret;
1466 }
1467 }
1468
1469 switch (GRAPHICS_VER(ce->engine->i915)) {
1470 case 7: {
1471 /*
1472 * On Haswell we don't do any post processing of the reports
1473 * and don't need to use the mask.
1474 */
1475 stream->specific_ctx_id = i915_ggtt_offset(ce->state);
1476 stream->specific_ctx_id_mask = 0;
1477 break;
1478 }
1479
1480 case 8:
1481 case 9:
1482 if (intel_engine_uses_guc(ce->engine)) {
1483 /*
1484 * When using GuC, the context descriptor we write in
1485 * i915 is read by GuC and rewritten before it's
1486 * actually written into the hardware. The LRCA is
1487 * what is put into the context id field of the
1488 * context descriptor by GuC. Because it's aligned to
1489 * a page, the lower 12bits are always at 0 and
1490 * dropped by GuC. They won't be part of the context
1491 * ID in the OA reports, so squash those lower bits.
1492 */
1493 stream->specific_ctx_id = ce->lrc.lrca >> 12;
1494
1495 /*
1496 * GuC uses the top bit to signal proxy submission, so
1497 * ignore that bit.
1498 */
1499 stream->specific_ctx_id_mask =
1500 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1501 } else {
1502 stream->specific_ctx_id_mask =
1503 (1U << GEN8_CTX_ID_WIDTH) - 1;
1504 stream->specific_ctx_id = stream->specific_ctx_id_mask;
1505 }
1506 break;
1507
1508 case 11:
1509 case 12:
1510 ret = gen12_get_render_context_id(stream);
1511 break;
1512
1513 default:
1514 MISSING_CASE(GRAPHICS_VER(ce->engine->i915));
1515 }
1516
1517 ce->tag = stream->specific_ctx_id;
1518
1519 drm_dbg(&stream->perf->i915->drm,
1520 "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1521 stream->specific_ctx_id,
1522 stream->specific_ctx_id_mask);
1523
1524 return ret;
1525}
1526
1527/**
1528 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1529 * @stream: An i915-perf stream opened for OA metrics
1530 *
1531 * In case anything needed doing to ensure the context HW ID would remain valid
1532 * for the lifetime of the stream, then that can be undone here.
1533 */
1534static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1535{
1536 struct intel_context *ce;
1537
1538 ce = fetch_and_zero(&stream->pinned_ctx);
1539 if (ce) {
1540 ce->tag = 0; /* recomputed on next submission after parking */
1541 intel_context_unpin(ce);
1542 }
1543
1544 stream->specific_ctx_id = INVALID_CTX_ID;
1545 stream->specific_ctx_id_mask = 0;
1546}
1547
1548static void
1549free_oa_buffer(struct i915_perf_stream *stream)
1550{
1551 i915_vma_unpin_and_release(&stream->oa_buffer.vma,
1552 I915_VMA_RELEASE_MAP);
1553
1554 stream->oa_buffer.vaddr = NULL;
1555}
1556
1557static void
1558free_oa_configs(struct i915_perf_stream *stream)
1559{
1560 struct i915_oa_config_bo *oa_bo, *tmp;
1561
1562 i915_oa_config_put(stream->oa_config);
1563 llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
1564 free_oa_config_bo(oa_bo);
1565}
1566
1567static void
1568free_noa_wait(struct i915_perf_stream *stream)
1569{
1570 i915_vma_unpin_and_release(&stream->noa_wait, 0);
1571}
1572
1573static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1574{
1575 struct i915_perf *perf = stream->perf;
1576 struct intel_gt *gt = stream->engine->gt;
1577
1578 if (WARN_ON(stream != gt->perf.exclusive_stream))
1579 return;
1580
1581 /*
1582 * Unset exclusive_stream first, it will be checked while disabling
1583 * the metric set on gen8+.
1584 *
1585 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
1586 */
1587 WRITE_ONCE(gt->perf.exclusive_stream, NULL);
1588 perf->ops.disable_metric_set(stream);
1589
1590 free_oa_buffer(stream);
1591
1592 /*
1593 * Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.
1594 */
1595 if (intel_uc_uses_guc_rc(>->uc) &&
1596 (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
1597 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)))
1598 drm_WARN_ON(>->i915->drm,
1599 intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc));
1600
1601 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
1602 intel_engine_pm_put(stream->engine);
1603
1604 if (stream->ctx)
1605 oa_put_render_ctx_id(stream);
1606
1607 free_oa_configs(stream);
1608 free_noa_wait(stream);
1609
1610 if (perf->spurious_report_rs.missed) {
1611 drm_notice(>->i915->drm,
1612 "%d spurious OA report notices suppressed due to ratelimiting\n",
1613 perf->spurious_report_rs.missed);
1614 }
1615}
1616
1617static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
1618{
1619 struct intel_uncore *uncore = stream->uncore;
1620 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1621 unsigned long flags;
1622
1623 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1624
1625 /* Pre-DevBDW: OABUFFER must be set with counters off,
1626 * before OASTATUS1, but after OASTATUS2
1627 */
1628 intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */
1629 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT);
1630 stream->oa_buffer.head = gtt_offset;
1631
1632 intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset);
1633
1634 intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */
1635 gtt_offset | OABUFFER_SIZE_16M);
1636
1637 /* Mark that we need updated tail pointers to read from... */
1638 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1639 stream->oa_buffer.tail = gtt_offset;
1640
1641 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1642
1643 /* On Haswell we have to track which OASTATUS1 flags we've
1644 * already seen since they can't be cleared while periodic
1645 * sampling is enabled.
1646 */
1647 stream->perf->gen7_latched_oastatus1 = 0;
1648
1649 /* NB: although the OA buffer will initially be allocated
1650 * zeroed via shmfs (and so this memset is redundant when
1651 * first allocating), we may re-init the OA buffer, either
1652 * when re-enabling a stream or in error/reset paths.
1653 *
1654 * The reason we clear the buffer for each re-init is for the
1655 * sanity check in gen7_append_oa_reports() that looks at the
1656 * report-id field to make sure it's non-zero which relies on
1657 * the assumption that new reports are being written to zeroed
1658 * memory...
1659 */
1660 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1661}
1662
1663static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
1664{
1665 struct intel_uncore *uncore = stream->uncore;
1666 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1667 unsigned long flags;
1668
1669 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1670
1671 intel_uncore_write(uncore, GEN8_OASTATUS, 0);
1672 intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset);
1673 stream->oa_buffer.head = gtt_offset;
1674
1675 intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0);
1676
1677 /*
1678 * PRM says:
1679 *
1680 * "This MMIO must be set before the OATAILPTR
1681 * register and after the OAHEADPTR register. This is
1682 * to enable proper functionality of the overflow
1683 * bit."
1684 */
1685 intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
1686 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1687 intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1688
1689 /* Mark that we need updated tail pointers to read from... */
1690 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1691 stream->oa_buffer.tail = gtt_offset;
1692
1693 /*
1694 * Reset state used to recognise context switches, affecting which
1695 * reports we will forward to userspace while filtering for a single
1696 * context.
1697 */
1698 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1699
1700 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1701
1702 /*
1703 * NB: although the OA buffer will initially be allocated
1704 * zeroed via shmfs (and so this memset is redundant when
1705 * first allocating), we may re-init the OA buffer, either
1706 * when re-enabling a stream or in error/reset paths.
1707 *
1708 * The reason we clear the buffer for each re-init is for the
1709 * sanity check in gen8_append_oa_reports() that looks at the
1710 * reason field to make sure it's non-zero which relies on
1711 * the assumption that new reports are being written to zeroed
1712 * memory...
1713 */
1714 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1715}
1716
1717static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
1718{
1719 struct intel_uncore *uncore = stream->uncore;
1720 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1721 unsigned long flags;
1722
1723 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1724
1725 intel_uncore_write(uncore, GEN12_OAG_OASTATUS, 0);
1726 intel_uncore_write(uncore, GEN12_OAG_OAHEADPTR,
1727 gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
1728 stream->oa_buffer.head = gtt_offset;
1729
1730 /*
1731 * PRM says:
1732 *
1733 * "This MMIO must be set before the OATAILPTR
1734 * register and after the OAHEADPTR register. This is
1735 * to enable proper functionality of the overflow
1736 * bit."
1737 */
1738 intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset |
1739 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1740 intel_uncore_write(uncore, GEN12_OAG_OATAILPTR,
1741 gtt_offset & GEN12_OAG_OATAILPTR_MASK);
1742
1743 /* Mark that we need updated tail pointers to read from... */
1744 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1745 stream->oa_buffer.tail = gtt_offset;
1746
1747 /*
1748 * Reset state used to recognise context switches, affecting which
1749 * reports we will forward to userspace while filtering for a single
1750 * context.
1751 */
1752 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1753
1754 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1755
1756 /*
1757 * NB: although the OA buffer will initially be allocated
1758 * zeroed via shmfs (and so this memset is redundant when
1759 * first allocating), we may re-init the OA buffer, either
1760 * when re-enabling a stream or in error/reset paths.
1761 *
1762 * The reason we clear the buffer for each re-init is for the
1763 * sanity check in gen8_append_oa_reports() that looks at the
1764 * reason field to make sure it's non-zero which relies on
1765 * the assumption that new reports are being written to zeroed
1766 * memory...
1767 */
1768 memset(stream->oa_buffer.vaddr, 0,
1769 stream->oa_buffer.vma->size);
1770}
1771
1772static int alloc_oa_buffer(struct i915_perf_stream *stream)
1773{
1774 struct drm_i915_private *i915 = stream->perf->i915;
1775 struct intel_gt *gt = stream->engine->gt;
1776 struct drm_i915_gem_object *bo;
1777 struct i915_vma *vma;
1778 int ret;
1779
1780 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.vma))
1781 return -ENODEV;
1782
1783 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1784 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1785
1786 bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE);
1787 if (IS_ERR(bo)) {
1788 drm_err(&i915->drm, "Failed to allocate OA buffer\n");
1789 return PTR_ERR(bo);
1790 }
1791
1792 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1793
1794 /* PreHSW required 512K alignment, HSW requires 16M */
1795 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1796 if (IS_ERR(vma)) {
1797 ret = PTR_ERR(vma);
1798 goto err_unref;
1799 }
1800
1801 /*
1802 * PreHSW required 512K alignment.
1803 * HSW and onwards, align to requested size of OA buffer.
1804 */
1805 ret = i915_vma_pin(vma, 0, SZ_16M, PIN_GLOBAL | PIN_HIGH);
1806 if (ret) {
1807 drm_err(>->i915->drm, "Failed to pin OA buffer %d\n", ret);
1808 goto err_unref;
1809 }
1810
1811 stream->oa_buffer.vma = vma;
1812
1813 stream->oa_buffer.vaddr =
1814 i915_gem_object_pin_map_unlocked(bo, I915_MAP_WB);
1815 if (IS_ERR(stream->oa_buffer.vaddr)) {
1816 ret = PTR_ERR(stream->oa_buffer.vaddr);
1817 goto err_unpin;
1818 }
1819
1820 return 0;
1821
1822err_unpin:
1823 __i915_vma_unpin(vma);
1824
1825err_unref:
1826 i915_gem_object_put(bo);
1827
1828 stream->oa_buffer.vaddr = NULL;
1829 stream->oa_buffer.vma = NULL;
1830
1831 return ret;
1832}
1833
1834static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
1835 bool save, i915_reg_t reg, u32 offset,
1836 u32 dword_count)
1837{
1838 u32 cmd;
1839 u32 d;
1840
1841 cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
1842 cmd |= MI_SRM_LRM_GLOBAL_GTT;
1843 if (GRAPHICS_VER(stream->perf->i915) >= 8)
1844 cmd++;
1845
1846 for (d = 0; d < dword_count; d++) {
1847 *cs++ = cmd;
1848 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1849 *cs++ = intel_gt_scratch_offset(stream->engine->gt,
1850 offset) + 4 * d;
1851 *cs++ = 0;
1852 }
1853
1854 return cs;
1855}
1856
1857static int alloc_noa_wait(struct i915_perf_stream *stream)
1858{
1859 struct drm_i915_private *i915 = stream->perf->i915;
1860 struct intel_gt *gt = stream->engine->gt;
1861 struct drm_i915_gem_object *bo;
1862 struct i915_vma *vma;
1863 const u64 delay_ticks = 0xffffffffffffffff -
1864 intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
1865 atomic64_read(&stream->perf->noa_programming_delay));
1866 const u32 base = stream->engine->mmio_base;
1867#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
1868 u32 *batch, *ts0, *cs, *jump;
1869 struct i915_gem_ww_ctx ww;
1870 int ret, i;
1871 enum {
1872 START_TS,
1873 NOW_TS,
1874 DELTA_TS,
1875 JUMP_PREDICATE,
1876 DELTA_TARGET,
1877 N_CS_GPR
1878 };
1879 i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
1880 MI_PREDICATE_RESULT_2_ENGINE(base) :
1881 MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
1882
1883 bo = i915_gem_object_create_internal(i915, 4096);
1884 if (IS_ERR(bo)) {
1885 drm_err(&i915->drm,
1886 "Failed to allocate NOA wait batchbuffer\n");
1887 return PTR_ERR(bo);
1888 }
1889
1890 i915_gem_ww_ctx_init(&ww, true);
1891retry:
1892 ret = i915_gem_object_lock(bo, &ww);
1893 if (ret)
1894 goto out_ww;
1895
1896 /*
1897 * We pin in GGTT because we jump into this buffer now because
1898 * multiple OA config BOs will have a jump to this address and it
1899 * needs to be fixed during the lifetime of the i915/perf stream.
1900 */
1901 vma = i915_vma_instance(bo, >->ggtt->vm, NULL);
1902 if (IS_ERR(vma)) {
1903 ret = PTR_ERR(vma);
1904 goto out_ww;
1905 }
1906
1907 ret = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
1908 if (ret)
1909 goto out_ww;
1910
1911 batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
1912 if (IS_ERR(batch)) {
1913 ret = PTR_ERR(batch);
1914 goto err_unpin;
1915 }
1916
1917 /* Save registers. */
1918 for (i = 0; i < N_CS_GPR; i++)
1919 cs = save_restore_register(
1920 stream, cs, true /* save */, CS_GPR(i),
1921 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
1922 cs = save_restore_register(
1923 stream, cs, true /* save */, mi_predicate_result,
1924 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
1925
1926 /* First timestamp snapshot location. */
1927 ts0 = cs;
1928
1929 /*
1930 * Initial snapshot of the timestamp register to implement the wait.
1931 * We work with 32b values, so clear out the top 32b bits of the
1932 * register because the ALU works 64bits.
1933 */
1934 *cs++ = MI_LOAD_REGISTER_IMM(1);
1935 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
1936 *cs++ = 0;
1937 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1938 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1939 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
1940
1941 /*
1942 * This is the location we're going to jump back into until the
1943 * required amount of time has passed.
1944 */
1945 jump = cs;
1946
1947 /*
1948 * Take another snapshot of the timestamp register. Take care to clear
1949 * up the top 32bits of CS_GPR(1) as we're using it for other
1950 * operations below.
1951 */
1952 *cs++ = MI_LOAD_REGISTER_IMM(1);
1953 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
1954 *cs++ = 0;
1955 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1956 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1957 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
1958
1959 /*
1960 * Do a diff between the 2 timestamps and store the result back into
1961 * CS_GPR(1).
1962 */
1963 *cs++ = MI_MATH(5);
1964 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
1965 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
1966 *cs++ = MI_MATH_SUB;
1967 *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);
1968 *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1969
1970 /*
1971 * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
1972 * timestamp have rolled over the 32bits) into the predicate register
1973 * to be used for the predicated jump.
1974 */
1975 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1976 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1977 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
1978
1979 if (HAS_MI_SET_PREDICATE(i915))
1980 *cs++ = MI_SET_PREDICATE | 1;
1981
1982 /* Restart from the beginning if we had timestamps roll over. */
1983 *cs++ = (GRAPHICS_VER(i915) < 8 ?
1984 MI_BATCH_BUFFER_START :
1985 MI_BATCH_BUFFER_START_GEN8) |
1986 MI_BATCH_PREDICATE;
1987 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
1988 *cs++ = 0;
1989
1990 if (HAS_MI_SET_PREDICATE(i915))
1991 *cs++ = MI_SET_PREDICATE;
1992
1993 /*
1994 * Now add the diff between to previous timestamps and add it to :
1995 * (((1 * << 64) - 1) - delay_ns)
1996 *
1997 * When the Carry Flag contains 1 this means the elapsed time is
1998 * longer than the expected delay, and we can exit the wait loop.
1999 */
2000 *cs++ = MI_LOAD_REGISTER_IMM(2);
2001 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));
2002 *cs++ = lower_32_bits(delay_ticks);
2003 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;
2004 *cs++ = upper_32_bits(delay_ticks);
2005
2006 *cs++ = MI_MATH(4);
2007 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));
2008 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));
2009 *cs++ = MI_MATH_ADD;
2010 *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
2011
2012 *cs++ = MI_ARB_CHECK;
2013
2014 /*
2015 * Transfer the result into the predicate register to be used for the
2016 * predicated jump.
2017 */
2018 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
2019 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
2020 *cs++ = i915_mmio_reg_offset(mi_predicate_result);
2021
2022 if (HAS_MI_SET_PREDICATE(i915))
2023 *cs++ = MI_SET_PREDICATE | 1;
2024
2025 /* Predicate the jump. */
2026 *cs++ = (GRAPHICS_VER(i915) < 8 ?
2027 MI_BATCH_BUFFER_START :
2028 MI_BATCH_BUFFER_START_GEN8) |
2029 MI_BATCH_PREDICATE;
2030 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
2031 *cs++ = 0;
2032
2033 if (HAS_MI_SET_PREDICATE(i915))
2034 *cs++ = MI_SET_PREDICATE;
2035
2036 /* Restore registers. */
2037 for (i = 0; i < N_CS_GPR; i++)
2038 cs = save_restore_register(
2039 stream, cs, false /* restore */, CS_GPR(i),
2040 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
2041 cs = save_restore_register(
2042 stream, cs, false /* restore */, mi_predicate_result,
2043 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
2044
2045 /* And return to the ring. */
2046 *cs++ = MI_BATCH_BUFFER_END;
2047
2048 GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));
2049
2050 i915_gem_object_flush_map(bo);
2051 __i915_gem_object_release_map(bo);
2052
2053 stream->noa_wait = vma;
2054 goto out_ww;
2055
2056err_unpin:
2057 i915_vma_unpin_and_release(&vma, 0);
2058out_ww:
2059 if (ret == -EDEADLK) {
2060 ret = i915_gem_ww_ctx_backoff(&ww);
2061 if (!ret)
2062 goto retry;
2063 }
2064 i915_gem_ww_ctx_fini(&ww);
2065 if (ret)
2066 i915_gem_object_put(bo);
2067 return ret;
2068}
2069
2070static u32 *write_cs_mi_lri(u32 *cs,
2071 const struct i915_oa_reg *reg_data,
2072 u32 n_regs)
2073{
2074 u32 i;
2075
2076 for (i = 0; i < n_regs; i++) {
2077 if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
2078 u32 n_lri = min_t(u32,
2079 n_regs - i,
2080 MI_LOAD_REGISTER_IMM_MAX_REGS);
2081
2082 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
2083 }
2084 *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
2085 *cs++ = reg_data[i].value;
2086 }
2087
2088 return cs;
2089}
2090
2091static int num_lri_dwords(int num_regs)
2092{
2093 int count = 0;
2094
2095 if (num_regs > 0) {
2096 count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
2097 count += num_regs * 2;
2098 }
2099
2100 return count;
2101}
2102
2103static struct i915_oa_config_bo *
2104alloc_oa_config_buffer(struct i915_perf_stream *stream,
2105 struct i915_oa_config *oa_config)
2106{
2107 struct drm_i915_gem_object *obj;
2108 struct i915_oa_config_bo *oa_bo;
2109 struct i915_gem_ww_ctx ww;
2110 size_t config_length = 0;
2111 u32 *cs;
2112 int err;
2113
2114 oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
2115 if (!oa_bo)
2116 return ERR_PTR(-ENOMEM);
2117
2118 config_length += num_lri_dwords(oa_config->mux_regs_len);
2119 config_length += num_lri_dwords(oa_config->b_counter_regs_len);
2120 config_length += num_lri_dwords(oa_config->flex_regs_len);
2121 config_length += 3; /* MI_BATCH_BUFFER_START */
2122 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
2123
2124 obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
2125 if (IS_ERR(obj)) {
2126 err = PTR_ERR(obj);
2127 goto err_free;
2128 }
2129
2130 i915_gem_ww_ctx_init(&ww, true);
2131retry:
2132 err = i915_gem_object_lock(obj, &ww);
2133 if (err)
2134 goto out_ww;
2135
2136 cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
2137 if (IS_ERR(cs)) {
2138 err = PTR_ERR(cs);
2139 goto out_ww;
2140 }
2141
2142 cs = write_cs_mi_lri(cs,
2143 oa_config->mux_regs,
2144 oa_config->mux_regs_len);
2145 cs = write_cs_mi_lri(cs,
2146 oa_config->b_counter_regs,
2147 oa_config->b_counter_regs_len);
2148 cs = write_cs_mi_lri(cs,
2149 oa_config->flex_regs,
2150 oa_config->flex_regs_len);
2151
2152 /* Jump into the active wait. */
2153 *cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?
2154 MI_BATCH_BUFFER_START :
2155 MI_BATCH_BUFFER_START_GEN8);
2156 *cs++ = i915_ggtt_offset(stream->noa_wait);
2157 *cs++ = 0;
2158
2159 i915_gem_object_flush_map(obj);
2160 __i915_gem_object_release_map(obj);
2161
2162 oa_bo->vma = i915_vma_instance(obj,
2163 &stream->engine->gt->ggtt->vm,
2164 NULL);
2165 if (IS_ERR(oa_bo->vma)) {
2166 err = PTR_ERR(oa_bo->vma);
2167 goto out_ww;
2168 }
2169
2170 oa_bo->oa_config = i915_oa_config_get(oa_config);
2171 llist_add(&oa_bo->node, &stream->oa_config_bos);
2172
2173out_ww:
2174 if (err == -EDEADLK) {
2175 err = i915_gem_ww_ctx_backoff(&ww);
2176 if (!err)
2177 goto retry;
2178 }
2179 i915_gem_ww_ctx_fini(&ww);
2180
2181 if (err)
2182 i915_gem_object_put(obj);
2183err_free:
2184 if (err) {
2185 kfree(oa_bo);
2186 return ERR_PTR(err);
2187 }
2188 return oa_bo;
2189}
2190
2191static struct i915_vma *
2192get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
2193{
2194 struct i915_oa_config_bo *oa_bo;
2195
2196 /*
2197 * Look for the buffer in the already allocated BOs attached
2198 * to the stream.
2199 */
2200 llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) {
2201 if (oa_bo->oa_config == oa_config &&
2202 memcmp(oa_bo->oa_config->uuid,
2203 oa_config->uuid,
2204 sizeof(oa_config->uuid)) == 0)
2205 goto out;
2206 }
2207
2208 oa_bo = alloc_oa_config_buffer(stream, oa_config);
2209 if (IS_ERR(oa_bo))
2210 return ERR_CAST(oa_bo);
2211
2212out:
2213 return i915_vma_get(oa_bo->vma);
2214}
2215
2216static int
2217emit_oa_config(struct i915_perf_stream *stream,
2218 struct i915_oa_config *oa_config,
2219 struct intel_context *ce,
2220 struct i915_active *active)
2221{
2222 struct i915_request *rq;
2223 struct i915_vma *vma;
2224 struct i915_gem_ww_ctx ww;
2225 int err;
2226
2227 vma = get_oa_vma(stream, oa_config);
2228 if (IS_ERR(vma))
2229 return PTR_ERR(vma);
2230
2231 i915_gem_ww_ctx_init(&ww, true);
2232retry:
2233 err = i915_gem_object_lock(vma->obj, &ww);
2234 if (err)
2235 goto err;
2236
2237 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
2238 if (err)
2239 goto err;
2240
2241 intel_engine_pm_get(ce->engine);
2242 rq = i915_request_create(ce);
2243 intel_engine_pm_put(ce->engine);
2244 if (IS_ERR(rq)) {
2245 err = PTR_ERR(rq);
2246 goto err_vma_unpin;
2247 }
2248
2249 if (!IS_ERR_OR_NULL(active)) {
2250 /* After all individual context modifications */
2251 err = i915_request_await_active(rq, active,
2252 I915_ACTIVE_AWAIT_ACTIVE);
2253 if (err)
2254 goto err_add_request;
2255
2256 err = i915_active_add_request(active, rq);
2257 if (err)
2258 goto err_add_request;
2259 }
2260
2261 err = i915_vma_move_to_active(vma, rq, 0);
2262 if (err)
2263 goto err_add_request;
2264
2265 err = rq->engine->emit_bb_start(rq,
2266 vma->node.start, 0,
2267 I915_DISPATCH_SECURE);
2268 if (err)
2269 goto err_add_request;
2270
2271err_add_request:
2272 i915_request_add(rq);
2273err_vma_unpin:
2274 i915_vma_unpin(vma);
2275err:
2276 if (err == -EDEADLK) {
2277 err = i915_gem_ww_ctx_backoff(&ww);
2278 if (!err)
2279 goto retry;
2280 }
2281
2282 i915_gem_ww_ctx_fini(&ww);
2283 i915_vma_put(vma);
2284 return err;
2285}
2286
2287static struct intel_context *oa_context(struct i915_perf_stream *stream)
2288{
2289 return stream->pinned_ctx ?: stream->engine->kernel_context;
2290}
2291
2292static int
2293hsw_enable_metric_set(struct i915_perf_stream *stream,
2294 struct i915_active *active)
2295{
2296 struct intel_uncore *uncore = stream->uncore;
2297
2298 /*
2299 * PRM:
2300 *
2301 * OA unit is using “crclk” for its functionality. When trunk
2302 * level clock gating takes place, OA clock would be gated,
2303 * unable to count the events from non-render clock domain.
2304 * Render clock gating must be disabled when OA is enabled to
2305 * count the events from non-render domain. Unit level clock
2306 * gating for RCS should also be disabled.
2307 */
2308 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2309 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
2310 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2311 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
2312
2313 return emit_oa_config(stream,
2314 stream->oa_config, oa_context(stream),
2315 active);
2316}
2317
2318static void hsw_disable_metric_set(struct i915_perf_stream *stream)
2319{
2320 struct intel_uncore *uncore = stream->uncore;
2321
2322 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2323 GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
2324 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2325 0, GEN7_DOP_CLOCK_GATE_ENABLE);
2326
2327 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2328}
2329
2330static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
2331 i915_reg_t reg)
2332{
2333 u32 mmio = i915_mmio_reg_offset(reg);
2334 int i;
2335
2336 /*
2337 * This arbitrary default will select the 'EU FPU0 Pipeline
2338 * Active' event. In the future it's anticipated that there
2339 * will be an explicit 'No Event' we can select, but not yet...
2340 */
2341 if (!oa_config)
2342 return 0;
2343
2344 for (i = 0; i < oa_config->flex_regs_len; i++) {
2345 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2346 return oa_config->flex_regs[i].value;
2347 }
2348
2349 return 0;
2350}
2351/*
2352 * NB: It must always remain pointer safe to run this even if the OA unit
2353 * has been disabled.
2354 *
2355 * It's fine to put out-of-date values into these per-context registers
2356 * in the case that the OA unit has been disabled.
2357 */
2358static void
2359gen8_update_reg_state_unlocked(const struct intel_context *ce,
2360 const struct i915_perf_stream *stream)
2361{
2362 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2363 u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2364 /* The MMIO offsets for Flex EU registers aren't contiguous */
2365 static const i915_reg_t flex_regs[] = {
2366 EU_PERF_CNTL0,
2367 EU_PERF_CNTL1,
2368 EU_PERF_CNTL2,
2369 EU_PERF_CNTL3,
2370 EU_PERF_CNTL4,
2371 EU_PERF_CNTL5,
2372 EU_PERF_CNTL6,
2373 };
2374 u32 *reg_state = ce->lrc_reg_state;
2375 int i;
2376
2377 reg_state[ctx_oactxctrl + 1] =
2378 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2379 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2380 GEN8_OA_COUNTER_RESUME;
2381
2382 for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
2383 reg_state[ctx_flexeu0 + i * 2 + 1] =
2384 oa_config_flex_reg(stream->oa_config, flex_regs[i]);
2385}
2386
2387struct flex {
2388 i915_reg_t reg;
2389 u32 offset;
2390 u32 value;
2391};
2392
2393static int
2394gen8_store_flex(struct i915_request *rq,
2395 struct intel_context *ce,
2396 const struct flex *flex, unsigned int count)
2397{
2398 u32 offset;
2399 u32 *cs;
2400
2401 cs = intel_ring_begin(rq, 4 * count);
2402 if (IS_ERR(cs))
2403 return PTR_ERR(cs);
2404
2405 offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;
2406 do {
2407 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
2408 *cs++ = offset + flex->offset * sizeof(u32);
2409 *cs++ = 0;
2410 *cs++ = flex->value;
2411 } while (flex++, --count);
2412
2413 intel_ring_advance(rq, cs);
2414
2415 return 0;
2416}
2417
2418static int
2419gen8_load_flex(struct i915_request *rq,
2420 struct intel_context *ce,
2421 const struct flex *flex, unsigned int count)
2422{
2423 u32 *cs;
2424
2425 GEM_BUG_ON(!count || count > 63);
2426
2427 cs = intel_ring_begin(rq, 2 * count + 2);
2428 if (IS_ERR(cs))
2429 return PTR_ERR(cs);
2430
2431 *cs++ = MI_LOAD_REGISTER_IMM(count);
2432 do {
2433 *cs++ = i915_mmio_reg_offset(flex->reg);
2434 *cs++ = flex->value;
2435 } while (flex++, --count);
2436 *cs++ = MI_NOOP;
2437
2438 intel_ring_advance(rq, cs);
2439
2440 return 0;
2441}
2442
2443static int gen8_modify_context(struct intel_context *ce,
2444 const struct flex *flex, unsigned int count)
2445{
2446 struct i915_request *rq;
2447 int err;
2448
2449 rq = intel_engine_create_kernel_request(ce->engine);
2450 if (IS_ERR(rq))
2451 return PTR_ERR(rq);
2452
2453 /* Serialise with the remote context */
2454 err = intel_context_prepare_remote_request(ce, rq);
2455 if (err == 0)
2456 err = gen8_store_flex(rq, ce, flex, count);
2457
2458 i915_request_add(rq);
2459 return err;
2460}
2461
2462static int
2463gen8_modify_self(struct intel_context *ce,
2464 const struct flex *flex, unsigned int count,
2465 struct i915_active *active)
2466{
2467 struct i915_request *rq;
2468 int err;
2469
2470 intel_engine_pm_get(ce->engine);
2471 rq = i915_request_create(ce);
2472 intel_engine_pm_put(ce->engine);
2473 if (IS_ERR(rq))
2474 return PTR_ERR(rq);
2475
2476 if (!IS_ERR_OR_NULL(active)) {
2477 err = i915_active_add_request(active, rq);
2478 if (err)
2479 goto err_add_request;
2480 }
2481
2482 err = gen8_load_flex(rq, ce, flex, count);
2483 if (err)
2484 goto err_add_request;
2485
2486err_add_request:
2487 i915_request_add(rq);
2488 return err;
2489}
2490
2491static int gen8_configure_context(struct i915_gem_context *ctx,
2492 struct flex *flex, unsigned int count)
2493{
2494 struct i915_gem_engines_iter it;
2495 struct intel_context *ce;
2496 int err = 0;
2497
2498 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2499 GEM_BUG_ON(ce == ce->engine->kernel_context);
2500
2501 if (ce->engine->class != RENDER_CLASS)
2502 continue;
2503
2504 /* Otherwise OA settings will be set upon first use */
2505 if (!intel_context_pin_if_active(ce))
2506 continue;
2507
2508 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
2509 err = gen8_modify_context(ce, flex, count);
2510
2511 intel_context_unpin(ce);
2512 if (err)
2513 break;
2514 }
2515 i915_gem_context_unlock_engines(ctx);
2516
2517 return err;
2518}
2519
2520static int gen12_configure_oar_context(struct i915_perf_stream *stream,
2521 struct i915_active *active)
2522{
2523 int err;
2524 struct intel_context *ce = stream->pinned_ctx;
2525 u32 format = stream->oa_buffer.format->format;
2526 u32 offset = stream->perf->ctx_oactxctrl_offset;
2527 struct flex regs_context[] = {
2528 {
2529 GEN8_OACTXCONTROL,
2530 offset + 1,
2531 active ? GEN8_OA_COUNTER_RESUME : 0,
2532 },
2533 };
2534 /* Offsets in regs_lri are not used since this configuration is only
2535 * applied using LRI. Initialize the correct offsets for posterity.
2536 */
2537#define GEN12_OAR_OACONTROL_OFFSET 0x5B0
2538 struct flex regs_lri[] = {
2539 {
2540 GEN12_OAR_OACONTROL,
2541 GEN12_OAR_OACONTROL_OFFSET + 1,
2542 (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
2543 (active ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0)
2544 },
2545 {
2546 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2547 CTX_CONTEXT_CONTROL,
2548 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2549 active ?
2550 GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2551 0)
2552 },
2553 };
2554
2555 /* Modify the context image of pinned context with regs_context */
2556 err = intel_context_lock_pinned(ce);
2557 if (err)
2558 return err;
2559
2560 err = gen8_modify_context(ce, regs_context,
2561 ARRAY_SIZE(regs_context));
2562 intel_context_unlock_pinned(ce);
2563 if (err)
2564 return err;
2565
2566 /* Apply regs_lri using LRI with pinned context */
2567 return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), active);
2568}
2569
2570/*
2571 * Manages updating the per-context aspects of the OA stream
2572 * configuration across all contexts.
2573 *
2574 * The awkward consideration here is that OACTXCONTROL controls the
2575 * exponent for periodic sampling which is primarily used for system
2576 * wide profiling where we'd like a consistent sampling period even in
2577 * the face of context switches.
2578 *
2579 * Our approach of updating the register state context (as opposed to
2580 * say using a workaround batch buffer) ensures that the hardware
2581 * won't automatically reload an out-of-date timer exponent even
2582 * transiently before a WA BB could be parsed.
2583 *
2584 * This function needs to:
2585 * - Ensure the currently running context's per-context OA state is
2586 * updated
2587 * - Ensure that all existing contexts will have the correct per-context
2588 * OA state if they are scheduled for use.
2589 * - Ensure any new contexts will be initialized with the correct
2590 * per-context OA state.
2591 *
2592 * Note: it's only the RCS/Render context that has any OA state.
2593 * Note: the first flex register passed must always be R_PWR_CLK_STATE
2594 */
2595static int
2596oa_configure_all_contexts(struct i915_perf_stream *stream,
2597 struct flex *regs,
2598 size_t num_regs,
2599 struct i915_active *active)
2600{
2601 struct drm_i915_private *i915 = stream->perf->i915;
2602 struct intel_engine_cs *engine;
2603 struct intel_gt *gt = stream->engine->gt;
2604 struct i915_gem_context *ctx, *cn;
2605 int err;
2606
2607 lockdep_assert_held(>->perf.lock);
2608
2609 /*
2610 * The OA register config is setup through the context image. This image
2611 * might be written to by the GPU on context switch (in particular on
2612 * lite-restore). This means we can't safely update a context's image,
2613 * if this context is scheduled/submitted to run on the GPU.
2614 *
2615 * We could emit the OA register config through the batch buffer but
2616 * this might leave small interval of time where the OA unit is
2617 * configured at an invalid sampling period.
2618 *
2619 * Note that since we emit all requests from a single ring, there
2620 * is still an implicit global barrier here that may cause a high
2621 * priority context to wait for an otherwise independent low priority
2622 * context. Contexts idle at the time of reconfiguration are not
2623 * trapped behind the barrier.
2624 */
2625 spin_lock(&i915->gem.contexts.lock);
2626 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
2627 if (!kref_get_unless_zero(&ctx->ref))
2628 continue;
2629
2630 spin_unlock(&i915->gem.contexts.lock);
2631
2632 err = gen8_configure_context(ctx, regs, num_regs);
2633 if (err) {
2634 i915_gem_context_put(ctx);
2635 return err;
2636 }
2637
2638 spin_lock(&i915->gem.contexts.lock);
2639 list_safe_reset_next(ctx, cn, link);
2640 i915_gem_context_put(ctx);
2641 }
2642 spin_unlock(&i915->gem.contexts.lock);
2643
2644 /*
2645 * After updating all other contexts, we need to modify ourselves.
2646 * If we don't modify the kernel_context, we do not get events while
2647 * idle.
2648 */
2649 for_each_uabi_engine(engine, i915) {
2650 struct intel_context *ce = engine->kernel_context;
2651
2652 if (engine->class != RENDER_CLASS)
2653 continue;
2654
2655 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
2656
2657 err = gen8_modify_self(ce, regs, num_regs, active);
2658 if (err)
2659 return err;
2660 }
2661
2662 return 0;
2663}
2664
2665static int
2666gen12_configure_all_contexts(struct i915_perf_stream *stream,
2667 const struct i915_oa_config *oa_config,
2668 struct i915_active *active)
2669{
2670 struct flex regs[] = {
2671 {
2672 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2673 CTX_R_PWR_CLK_STATE,
2674 },
2675 };
2676
2677 return oa_configure_all_contexts(stream,
2678 regs, ARRAY_SIZE(regs),
2679 active);
2680}
2681
2682static int
2683lrc_configure_all_contexts(struct i915_perf_stream *stream,
2684 const struct i915_oa_config *oa_config,
2685 struct i915_active *active)
2686{
2687 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2688 /* The MMIO offsets for Flex EU registers aren't contiguous */
2689 const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2690#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
2691 struct flex regs[] = {
2692 {
2693 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2694 CTX_R_PWR_CLK_STATE,
2695 },
2696 {
2697 GEN8_OACTXCONTROL,
2698 ctx_oactxctrl + 1,
2699 },
2700 { EU_PERF_CNTL0, ctx_flexeuN(0) },
2701 { EU_PERF_CNTL1, ctx_flexeuN(1) },
2702 { EU_PERF_CNTL2, ctx_flexeuN(2) },
2703 { EU_PERF_CNTL3, ctx_flexeuN(3) },
2704 { EU_PERF_CNTL4, ctx_flexeuN(4) },
2705 { EU_PERF_CNTL5, ctx_flexeuN(5) },
2706 { EU_PERF_CNTL6, ctx_flexeuN(6) },
2707 };
2708#undef ctx_flexeuN
2709 int i;
2710
2711 regs[1].value =
2712 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2713 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2714 GEN8_OA_COUNTER_RESUME;
2715
2716 for (i = 2; i < ARRAY_SIZE(regs); i++)
2717 regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
2718
2719 return oa_configure_all_contexts(stream,
2720 regs, ARRAY_SIZE(regs),
2721 active);
2722}
2723
2724static int
2725gen8_enable_metric_set(struct i915_perf_stream *stream,
2726 struct i915_active *active)
2727{
2728 struct intel_uncore *uncore = stream->uncore;
2729 struct i915_oa_config *oa_config = stream->oa_config;
2730 int ret;
2731
2732 /*
2733 * We disable slice/unslice clock ratio change reports on SKL since
2734 * they are too noisy. The HW generates a lot of redundant reports
2735 * where the ratio hasn't really changed causing a lot of redundant
2736 * work to processes and increasing the chances we'll hit buffer
2737 * overruns.
2738 *
2739 * Although we don't currently use the 'disable overrun' OABUFFER
2740 * feature it's worth noting that clock ratio reports have to be
2741 * disabled before considering to use that feature since the HW doesn't
2742 * correctly block these reports.
2743 *
2744 * Currently none of the high-level metrics we have depend on knowing
2745 * this ratio to normalize.
2746 *
2747 * Note: This register is not power context saved and restored, but
2748 * that's OK considering that we disable RC6 while the OA unit is
2749 * enabled.
2750 *
2751 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
2752 * be read back from automatically triggered reports, as part of the
2753 * RPT_ID field.
2754 */
2755 if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
2756 intel_uncore_write(uncore, GEN8_OA_DEBUG,
2757 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2758 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2759 }
2760
2761 /*
2762 * Update all contexts prior writing the mux configurations as we need
2763 * to make sure all slices/subslices are ON before writing to NOA
2764 * registers.
2765 */
2766 ret = lrc_configure_all_contexts(stream, oa_config, active);
2767 if (ret)
2768 return ret;
2769
2770 return emit_oa_config(stream,
2771 stream->oa_config, oa_context(stream),
2772 active);
2773}
2774
2775static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2776{
2777 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2778 (stream->sample_flags & SAMPLE_OA_REPORT) ?
2779 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2780}
2781
2782static int
2783gen12_enable_metric_set(struct i915_perf_stream *stream,
2784 struct i915_active *active)
2785{
2786 struct drm_i915_private *i915 = stream->perf->i915;
2787 struct intel_uncore *uncore = stream->uncore;
2788 struct i915_oa_config *oa_config = stream->oa_config;
2789 bool periodic = stream->periodic;
2790 u32 period_exponent = stream->period_exponent;
2791 u32 sqcnt1;
2792 int ret;
2793
2794 /*
2795 * Wa_1508761755:xehpsdv, dg2
2796 * EU NOA signals behave incorrectly if EU clock gating is enabled.
2797 * Disable thread stall DOP gating and EU DOP gating.
2798 */
2799 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2800 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2801 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
2802 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2803 _MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
2804 }
2805
2806 intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
2807 /* Disable clk ratio reports, like previous Gens. */
2808 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2809 GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2810 /*
2811 * If the user didn't require OA reports, instruct
2812 * the hardware not to emit ctx switch reports.
2813 */
2814 oag_report_ctx_switches(stream));
2815
2816 intel_uncore_write(uncore, GEN12_OAG_OAGLBCTXCTRL, periodic ?
2817 (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
2818 GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
2819 (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
2820 : 0);
2821
2822 /*
2823 * Initialize Super Queue Internal Cnt Register
2824 * Set PMON Enable in order to collect valid metrics.
2825 * Enable byets per clock reporting in OA for XEHPSDV onward.
2826 */
2827 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
2828 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
2829
2830 intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
2831
2832 /*
2833 * Update all contexts prior writing the mux configurations as we need
2834 * to make sure all slices/subslices are ON before writing to NOA
2835 * registers.
2836 */
2837 ret = gen12_configure_all_contexts(stream, oa_config, active);
2838 if (ret)
2839 return ret;
2840
2841 /*
2842 * For Gen12, performance counters are context
2843 * saved/restored. Only enable it for the context that
2844 * requested this.
2845 */
2846 if (stream->ctx) {
2847 ret = gen12_configure_oar_context(stream, active);
2848 if (ret)
2849 return ret;
2850 }
2851
2852 return emit_oa_config(stream,
2853 stream->oa_config, oa_context(stream),
2854 active);
2855}
2856
2857static void gen8_disable_metric_set(struct i915_perf_stream *stream)
2858{
2859 struct intel_uncore *uncore = stream->uncore;
2860
2861 /* Reset all contexts' slices/subslices configurations. */
2862 lrc_configure_all_contexts(stream, NULL, NULL);
2863
2864 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2865}
2866
2867static void gen11_disable_metric_set(struct i915_perf_stream *stream)
2868{
2869 struct intel_uncore *uncore = stream->uncore;
2870
2871 /* Reset all contexts' slices/subslices configurations. */
2872 lrc_configure_all_contexts(stream, NULL, NULL);
2873
2874 /* Make sure we disable noa to save power. */
2875 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2876}
2877
2878static void gen12_disable_metric_set(struct i915_perf_stream *stream)
2879{
2880 struct intel_uncore *uncore = stream->uncore;
2881 struct drm_i915_private *i915 = stream->perf->i915;
2882 u32 sqcnt1;
2883
2884 /*
2885 * Wa_1508761755:xehpsdv, dg2
2886 * Enable thread stall DOP gating and EU DOP gating.
2887 */
2888 if (IS_XEHPSDV(i915) || IS_DG2(i915)) {
2889 intel_gt_mcr_multicast_write(uncore->gt, GEN8_ROW_CHICKEN,
2890 _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
2891 intel_uncore_write(uncore, GEN7_ROW_CHICKEN2,
2892 _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
2893 }
2894
2895 /* Reset all contexts' slices/subslices configurations. */
2896 gen12_configure_all_contexts(stream, NULL, NULL);
2897
2898 /* disable the context save/restore or OAR counters */
2899 if (stream->ctx)
2900 gen12_configure_oar_context(stream, NULL);
2901
2902 /* Make sure we disable noa to save power. */
2903 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2904
2905 sqcnt1 = GEN12_SQCNT1_PMON_ENABLE |
2906 (HAS_OA_BPC_REPORTING(i915) ? GEN12_SQCNT1_OABPC : 0);
2907
2908 /* Reset PMON Enable to save power. */
2909 intel_uncore_rmw(uncore, GEN12_SQCNT1, sqcnt1, 0);
2910}
2911
2912static void gen7_oa_enable(struct i915_perf_stream *stream)
2913{
2914 struct intel_uncore *uncore = stream->uncore;
2915 struct i915_gem_context *ctx = stream->ctx;
2916 u32 ctx_id = stream->specific_ctx_id;
2917 bool periodic = stream->periodic;
2918 u32 period_exponent = stream->period_exponent;
2919 u32 report_format = stream->oa_buffer.format->format;
2920
2921 /*
2922 * Reset buf pointers so we don't forward reports from before now.
2923 *
2924 * Think carefully if considering trying to avoid this, since it
2925 * also ensures status flags and the buffer itself are cleared
2926 * in error paths, and we have checks for invalid reports based
2927 * on the assumption that certain fields are written to zeroed
2928 * memory which this helps maintains.
2929 */
2930 gen7_init_oa_buffer(stream);
2931
2932 intel_uncore_write(uncore, GEN7_OACONTROL,
2933 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
2934 (period_exponent <<
2935 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
2936 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
2937 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
2938 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
2939 GEN7_OACONTROL_ENABLE);
2940}
2941
2942static void gen8_oa_enable(struct i915_perf_stream *stream)
2943{
2944 struct intel_uncore *uncore = stream->uncore;
2945 u32 report_format = stream->oa_buffer.format->format;
2946
2947 /*
2948 * Reset buf pointers so we don't forward reports from before now.
2949 *
2950 * Think carefully if considering trying to avoid this, since it
2951 * also ensures status flags and the buffer itself are cleared
2952 * in error paths, and we have checks for invalid reports based
2953 * on the assumption that certain fields are written to zeroed
2954 * memory which this helps maintains.
2955 */
2956 gen8_init_oa_buffer(stream);
2957
2958 /*
2959 * Note: we don't rely on the hardware to perform single context
2960 * filtering and instead filter on the cpu based on the context-id
2961 * field of reports
2962 */
2963 intel_uncore_write(uncore, GEN8_OACONTROL,
2964 (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) |
2965 GEN8_OA_COUNTER_ENABLE);
2966}
2967
2968static void gen12_oa_enable(struct i915_perf_stream *stream)
2969{
2970 struct intel_uncore *uncore = stream->uncore;
2971 u32 report_format = stream->oa_buffer.format->format;
2972
2973 /*
2974 * If we don't want OA reports from the OA buffer, then we don't even
2975 * need to program the OAG unit.
2976 */
2977 if (!(stream->sample_flags & SAMPLE_OA_REPORT))
2978 return;
2979
2980 gen12_init_oa_buffer(stream);
2981
2982 intel_uncore_write(uncore, GEN12_OAG_OACONTROL,
2983 (report_format << GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) |
2984 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE);
2985}
2986
2987/**
2988 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
2989 * @stream: An i915 perf stream opened for OA metrics
2990 *
2991 * [Re]enables hardware periodic sampling according to the period configured
2992 * when opening the stream. This also starts a hrtimer that will periodically
2993 * check for data in the circular OA buffer for notifying userspace (e.g.
2994 * during a read() or poll()).
2995 */
2996static void i915_oa_stream_enable(struct i915_perf_stream *stream)
2997{
2998 stream->pollin = false;
2999
3000 stream->perf->ops.oa_enable(stream);
3001
3002 if (stream->sample_flags & SAMPLE_OA_REPORT)
3003 hrtimer_start(&stream->poll_check_timer,
3004 ns_to_ktime(stream->poll_oa_period),
3005 HRTIMER_MODE_REL_PINNED);
3006}
3007
3008static void gen7_oa_disable(struct i915_perf_stream *stream)
3009{
3010 struct intel_uncore *uncore = stream->uncore;
3011
3012 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
3013 if (intel_wait_for_register(uncore,
3014 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
3015 50))
3016 drm_err(&stream->perf->i915->drm,
3017 "wait for OA to be disabled timed out\n");
3018}
3019
3020static void gen8_oa_disable(struct i915_perf_stream *stream)
3021{
3022 struct intel_uncore *uncore = stream->uncore;
3023
3024 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
3025 if (intel_wait_for_register(uncore,
3026 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
3027 50))
3028 drm_err(&stream->perf->i915->drm,
3029 "wait for OA to be disabled timed out\n");
3030}
3031
3032static void gen12_oa_disable(struct i915_perf_stream *stream)
3033{
3034 struct intel_uncore *uncore = stream->uncore;
3035
3036 intel_uncore_write(uncore, GEN12_OAG_OACONTROL, 0);
3037 if (intel_wait_for_register(uncore,
3038 GEN12_OAG_OACONTROL,
3039 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
3040 50))
3041 drm_err(&stream->perf->i915->drm,
3042 "wait for OA to be disabled timed out\n");
3043
3044 intel_uncore_write(uncore, GEN12_OA_TLB_INV_CR, 1);
3045 if (intel_wait_for_register(uncore,
3046 GEN12_OA_TLB_INV_CR,
3047 1, 0,
3048 50))
3049 drm_err(&stream->perf->i915->drm,
3050 "wait for OA tlb invalidate timed out\n");
3051}
3052
3053/**
3054 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
3055 * @stream: An i915 perf stream opened for OA metrics
3056 *
3057 * Stops the OA unit from periodically writing counter reports into the
3058 * circular OA buffer. This also stops the hrtimer that periodically checks for
3059 * data in the circular OA buffer, for notifying userspace.
3060 */
3061static void i915_oa_stream_disable(struct i915_perf_stream *stream)
3062{
3063 stream->perf->ops.oa_disable(stream);
3064
3065 if (stream->sample_flags & SAMPLE_OA_REPORT)
3066 hrtimer_cancel(&stream->poll_check_timer);
3067}
3068
3069static const struct i915_perf_stream_ops i915_oa_stream_ops = {
3070 .destroy = i915_oa_stream_destroy,
3071 .enable = i915_oa_stream_enable,
3072 .disable = i915_oa_stream_disable,
3073 .wait_unlocked = i915_oa_wait_unlocked,
3074 .poll_wait = i915_oa_poll_wait,
3075 .read = i915_oa_read,
3076};
3077
3078static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
3079{
3080 struct i915_active *active;
3081 int err;
3082
3083 active = i915_active_create();
3084 if (!active)
3085 return -ENOMEM;
3086
3087 err = stream->perf->ops.enable_metric_set(stream, active);
3088 if (err == 0)
3089 __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
3090
3091 i915_active_put(active);
3092 return err;
3093}
3094
3095static void
3096get_default_sseu_config(struct intel_sseu *out_sseu,
3097 struct intel_engine_cs *engine)
3098{
3099 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
3100
3101 *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
3102
3103 if (GRAPHICS_VER(engine->i915) == 11) {
3104 /*
3105 * We only need subslice count so it doesn't matter which ones
3106 * we select - just turn off low bits in the amount of half of
3107 * all available subslices per slice.
3108 */
3109 out_sseu->subslice_mask =
3110 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
3111 out_sseu->slice_mask = 0x1;
3112 }
3113}
3114
3115static int
3116get_sseu_config(struct intel_sseu *out_sseu,
3117 struct intel_engine_cs *engine,
3118 const struct drm_i915_gem_context_param_sseu *drm_sseu)
3119{
3120 if (drm_sseu->engine.engine_class != engine->uabi_class ||
3121 drm_sseu->engine.engine_instance != engine->uabi_instance)
3122 return -EINVAL;
3123
3124 return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
3125}
3126
3127/*
3128 * OA timestamp frequency = CS timestamp frequency in most platforms. On some
3129 * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
3130 * cases, return the adjusted CS timestamp frequency to the user.
3131 */
3132u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
3133{
3134 /* Wa_18013179988:dg2 */
3135 if (IS_DG2(i915)) {
3136 intel_wakeref_t wakeref;
3137 u32 reg, shift;
3138
3139 with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref)
3140 reg = intel_uncore_read(to_gt(i915)->uncore, RPM_CONFIG0);
3141
3142 shift = REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK,
3143 reg);
3144
3145 return to_gt(i915)->clock_frequency << (3 - shift);
3146 }
3147
3148 return to_gt(i915)->clock_frequency;
3149}
3150
3151/**
3152 * i915_oa_stream_init - validate combined props for OA stream and init
3153 * @stream: An i915 perf stream
3154 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
3155 * @props: The property state that configures stream (individually validated)
3156 *
3157 * While read_properties_unlocked() validates properties in isolation it
3158 * doesn't ensure that the combination necessarily makes sense.
3159 *
3160 * At this point it has been determined that userspace wants a stream of
3161 * OA metrics, but still we need to further validate the combined
3162 * properties are OK.
3163 *
3164 * If the configuration makes sense then we can allocate memory for
3165 * a circular OA buffer and apply the requested metric set configuration.
3166 *
3167 * Returns: zero on success or a negative error code.
3168 */
3169static int i915_oa_stream_init(struct i915_perf_stream *stream,
3170 struct drm_i915_perf_open_param *param,
3171 struct perf_open_properties *props)
3172{
3173 struct drm_i915_private *i915 = stream->perf->i915;
3174 struct i915_perf *perf = stream->perf;
3175 struct intel_gt *gt;
3176 int ret;
3177
3178 if (!props->engine) {
3179 drm_dbg(&stream->perf->i915->drm,
3180 "OA engine not specified\n");
3181 return -EINVAL;
3182 }
3183 gt = props->engine->gt;
3184
3185 /*
3186 * If the sysfs metrics/ directory wasn't registered for some
3187 * reason then don't let userspace try their luck with config
3188 * IDs
3189 */
3190 if (!perf->metrics_kobj) {
3191 drm_dbg(&stream->perf->i915->drm,
3192 "OA metrics weren't advertised via sysfs\n");
3193 return -EINVAL;
3194 }
3195
3196 if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
3197 (GRAPHICS_VER(perf->i915) < 12 || !stream->ctx)) {
3198 drm_dbg(&stream->perf->i915->drm,
3199 "Only OA report sampling supported\n");
3200 return -EINVAL;
3201 }
3202
3203 if (!perf->ops.enable_metric_set) {
3204 drm_dbg(&stream->perf->i915->drm,
3205 "OA unit not supported\n");
3206 return -ENODEV;
3207 }
3208
3209 /*
3210 * To avoid the complexity of having to accurately filter
3211 * counter reports and marshal to the appropriate client
3212 * we currently only allow exclusive access
3213 */
3214 if (gt->perf.exclusive_stream) {
3215 drm_dbg(&stream->perf->i915->drm,
3216 "OA unit already in use\n");
3217 return -EBUSY;
3218 }
3219
3220 if (!props->oa_format) {
3221 drm_dbg(&stream->perf->i915->drm,
3222 "OA report format not specified\n");
3223 return -EINVAL;
3224 }
3225
3226 stream->engine = props->engine;
3227 stream->uncore = stream->engine->gt->uncore;
3228
3229 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
3230
3231 stream->oa_buffer.format = &perf->oa_formats[props->oa_format];
3232 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format->size == 0))
3233 return -EINVAL;
3234
3235 stream->sample_flags = props->sample_flags;
3236 stream->sample_size += stream->oa_buffer.format->size;
3237
3238 stream->hold_preemption = props->hold_preemption;
3239
3240 stream->periodic = props->oa_periodic;
3241 if (stream->periodic)
3242 stream->period_exponent = props->oa_period_exponent;
3243
3244 if (stream->ctx) {
3245 ret = oa_get_render_ctx_id(stream);
3246 if (ret) {
3247 drm_dbg(&stream->perf->i915->drm,
3248 "Invalid context id to filter with\n");
3249 return ret;
3250 }
3251 }
3252
3253 ret = alloc_noa_wait(stream);
3254 if (ret) {
3255 drm_dbg(&stream->perf->i915->drm,
3256 "Unable to allocate NOA wait batch buffer\n");
3257 goto err_noa_wait_alloc;
3258 }
3259
3260 stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set);
3261 if (!stream->oa_config) {
3262 drm_dbg(&stream->perf->i915->drm,
3263 "Invalid OA config id=%i\n", props->metrics_set);
3264 ret = -EINVAL;
3265 goto err_config;
3266 }
3267
3268 /* PRM - observability performance counters:
3269 *
3270 * OACONTROL, performance counter enable, note:
3271 *
3272 * "When this bit is set, in order to have coherent counts,
3273 * RC6 power state and trunk clock gating must be disabled.
3274 * This can be achieved by programming MMIO registers as
3275 * 0xA094=0 and 0xA090[31]=1"
3276 *
3277 * In our case we are expecting that taking pm + FORCEWAKE
3278 * references will effectively disable RC6.
3279 */
3280 intel_engine_pm_get(stream->engine);
3281 intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
3282
3283 /*
3284 * Wa_16011777198:dg2: GuC resets render as part of the Wa. This causes
3285 * OA to lose the configuration state. Prevent this by overriding GUCRC
3286 * mode.
3287 */
3288 if (intel_uc_uses_guc_rc(>->uc) &&
3289 (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
3290 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {
3291 ret = intel_guc_slpc_override_gucrc_mode(>->uc.guc.slpc,
3292 SLPC_GUCRC_MODE_GUCRC_NO_RC6);
3293 if (ret) {
3294 drm_dbg(&stream->perf->i915->drm,
3295 "Unable to override gucrc mode\n");
3296 goto err_config;
3297 }
3298 }
3299
3300 ret = alloc_oa_buffer(stream);
3301 if (ret)
3302 goto err_oa_buf_alloc;
3303
3304 stream->ops = &i915_oa_stream_ops;
3305
3306 stream->engine->gt->perf.sseu = props->sseu;
3307 WRITE_ONCE(gt->perf.exclusive_stream, stream);
3308
3309 ret = i915_perf_stream_enable_sync(stream);
3310 if (ret) {
3311 drm_dbg(&stream->perf->i915->drm,
3312 "Unable to enable metric set\n");
3313 goto err_enable;
3314 }
3315
3316 drm_dbg(&stream->perf->i915->drm,
3317 "opening stream oa config uuid=%s\n",
3318 stream->oa_config->uuid);
3319
3320 hrtimer_init(&stream->poll_check_timer,
3321 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3322 stream->poll_check_timer.function = oa_poll_check_timer_cb;
3323 init_waitqueue_head(&stream->poll_wq);
3324 spin_lock_init(&stream->oa_buffer.ptr_lock);
3325 mutex_init(&stream->lock);
3326
3327 return 0;
3328
3329err_enable:
3330 WRITE_ONCE(gt->perf.exclusive_stream, NULL);
3331 perf->ops.disable_metric_set(stream);
3332
3333 free_oa_buffer(stream);
3334
3335err_oa_buf_alloc:
3336 free_oa_configs(stream);
3337
3338 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
3339 intel_engine_pm_put(stream->engine);
3340
3341err_config:
3342 free_noa_wait(stream);
3343
3344err_noa_wait_alloc:
3345 if (stream->ctx)
3346 oa_put_render_ctx_id(stream);
3347
3348 return ret;
3349}
3350
3351void i915_oa_init_reg_state(const struct intel_context *ce,
3352 const struct intel_engine_cs *engine)
3353{
3354 struct i915_perf_stream *stream;
3355
3356 if (engine->class != RENDER_CLASS)
3357 return;
3358
3359 /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
3360 stream = READ_ONCE(engine->gt->perf.exclusive_stream);
3361 if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
3362 gen8_update_reg_state_unlocked(ce, stream);
3363}
3364
3365/**
3366 * i915_perf_read - handles read() FOP for i915 perf stream FDs
3367 * @file: An i915 perf stream file
3368 * @buf: destination buffer given by userspace
3369 * @count: the number of bytes userspace wants to read
3370 * @ppos: (inout) file seek position (unused)
3371 *
3372 * The entry point for handling a read() on a stream file descriptor from
3373 * userspace. Most of the work is left to the i915_perf_read_locked() and
3374 * &i915_perf_stream_ops->read but to save having stream implementations (of
3375 * which we might have multiple later) we handle blocking read here.
3376 *
3377 * We can also consistently treat trying to read from a disabled stream
3378 * as an IO error so implementations can assume the stream is enabled
3379 * while reading.
3380 *
3381 * Returns: The number of bytes copied or a negative error code on failure.
3382 */
3383static ssize_t i915_perf_read(struct file *file,
3384 char __user *buf,
3385 size_t count,
3386 loff_t *ppos)
3387{
3388 struct i915_perf_stream *stream = file->private_data;
3389 size_t offset = 0;
3390 int ret;
3391
3392 /* To ensure it's handled consistently we simply treat all reads of a
3393 * disabled stream as an error. In particular it might otherwise lead
3394 * to a deadlock for blocking file descriptors...
3395 */
3396 if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
3397 return -EIO;
3398
3399 if (!(file->f_flags & O_NONBLOCK)) {
3400 /* There's the small chance of false positives from
3401 * stream->ops->wait_unlocked.
3402 *
3403 * E.g. with single context filtering since we only wait until
3404 * oabuffer has >= 1 report we don't immediately know whether
3405 * any reports really belong to the current context
3406 */
3407 do {
3408 ret = stream->ops->wait_unlocked(stream);
3409 if (ret)
3410 return ret;
3411
3412 mutex_lock(&stream->lock);
3413 ret = stream->ops->read(stream, buf, count, &offset);
3414 mutex_unlock(&stream->lock);
3415 } while (!offset && !ret);
3416 } else {
3417 mutex_lock(&stream->lock);
3418 ret = stream->ops->read(stream, buf, count, &offset);
3419 mutex_unlock(&stream->lock);
3420 }
3421
3422 /* We allow the poll checking to sometimes report false positive EPOLLIN
3423 * events where we might actually report EAGAIN on read() if there's
3424 * not really any data available. In this situation though we don't
3425 * want to enter a busy loop between poll() reporting a EPOLLIN event
3426 * and read() returning -EAGAIN. Clearing the oa.pollin state here
3427 * effectively ensures we back off until the next hrtimer callback
3428 * before reporting another EPOLLIN event.
3429 * The exception to this is if ops->read() returned -ENOSPC which means
3430 * that more OA data is available than could fit in the user provided
3431 * buffer. In this case we want the next poll() call to not block.
3432 */
3433 if (ret != -ENOSPC)
3434 stream->pollin = false;
3435
3436 /* Possible values for ret are 0, -EFAULT, -ENOSPC, -EIO, ... */
3437 return offset ?: (ret ?: -EAGAIN);
3438}
3439
3440static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
3441{
3442 struct i915_perf_stream *stream =
3443 container_of(hrtimer, typeof(*stream), poll_check_timer);
3444
3445 if (oa_buffer_check_unlocked(stream)) {
3446 stream->pollin = true;
3447 wake_up(&stream->poll_wq);
3448 }
3449
3450 hrtimer_forward_now(hrtimer,
3451 ns_to_ktime(stream->poll_oa_period));
3452
3453 return HRTIMER_RESTART;
3454}
3455
3456/**
3457 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
3458 * @stream: An i915 perf stream
3459 * @file: An i915 perf stream file
3460 * @wait: poll() state table
3461 *
3462 * For handling userspace polling on an i915 perf stream, this calls through to
3463 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
3464 * will be woken for new stream data.
3465 *
3466 * Returns: any poll events that are ready without sleeping
3467 */
3468static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
3469 struct file *file,
3470 poll_table *wait)
3471{
3472 __poll_t events = 0;
3473
3474 stream->ops->poll_wait(stream, file, wait);
3475
3476 /* Note: we don't explicitly check whether there's something to read
3477 * here since this path may be very hot depending on what else
3478 * userspace is polling, or on the timeout in use. We rely solely on
3479 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
3480 * samples to read.
3481 */
3482 if (stream->pollin)
3483 events |= EPOLLIN;
3484
3485 return events;
3486}
3487
3488/**
3489 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
3490 * @file: An i915 perf stream file
3491 * @wait: poll() state table
3492 *
3493 * For handling userspace polling on an i915 perf stream, this ensures
3494 * poll_wait() gets called with a wait queue that will be woken for new stream
3495 * data.
3496 *
3497 * Note: Implementation deferred to i915_perf_poll_locked()
3498 *
3499 * Returns: any poll events that are ready without sleeping
3500 */
3501static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
3502{
3503 struct i915_perf_stream *stream = file->private_data;
3504 __poll_t ret;
3505
3506 mutex_lock(&stream->lock);
3507 ret = i915_perf_poll_locked(stream, file, wait);
3508 mutex_unlock(&stream->lock);
3509
3510 return ret;
3511}
3512
3513/**
3514 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
3515 * @stream: A disabled i915 perf stream
3516 *
3517 * [Re]enables the associated capture of data for this stream.
3518 *
3519 * If a stream was previously enabled then there's currently no intention
3520 * to provide userspace any guarantee about the preservation of previously
3521 * buffered data.
3522 */
3523static void i915_perf_enable_locked(struct i915_perf_stream *stream)
3524{
3525 if (stream->enabled)
3526 return;
3527
3528 /* Allow stream->ops->enable() to refer to this */
3529 stream->enabled = true;
3530
3531 if (stream->ops->enable)
3532 stream->ops->enable(stream);
3533
3534 if (stream->hold_preemption)
3535 intel_context_set_nopreempt(stream->pinned_ctx);
3536}
3537
3538/**
3539 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
3540 * @stream: An enabled i915 perf stream
3541 *
3542 * Disables the associated capture of data for this stream.
3543 *
3544 * The intention is that disabling an re-enabling a stream will ideally be
3545 * cheaper than destroying and re-opening a stream with the same configuration,
3546 * though there are no formal guarantees about what state or buffered data
3547 * must be retained between disabling and re-enabling a stream.
3548 *
3549 * Note: while a stream is disabled it's considered an error for userspace
3550 * to attempt to read from the stream (-EIO).
3551 */
3552static void i915_perf_disable_locked(struct i915_perf_stream *stream)
3553{
3554 if (!stream->enabled)
3555 return;
3556
3557 /* Allow stream->ops->disable() to refer to this */
3558 stream->enabled = false;
3559
3560 if (stream->hold_preemption)
3561 intel_context_clear_nopreempt(stream->pinned_ctx);
3562
3563 if (stream->ops->disable)
3564 stream->ops->disable(stream);
3565}
3566
3567static long i915_perf_config_locked(struct i915_perf_stream *stream,
3568 unsigned long metrics_set)
3569{
3570 struct i915_oa_config *config;
3571 long ret = stream->oa_config->id;
3572
3573 config = i915_perf_get_oa_config(stream->perf, metrics_set);
3574 if (!config)
3575 return -EINVAL;
3576
3577 if (config != stream->oa_config) {
3578 int err;
3579
3580 /*
3581 * If OA is bound to a specific context, emit the
3582 * reconfiguration inline from that context. The update
3583 * will then be ordered with respect to submission on that
3584 * context.
3585 *
3586 * When set globally, we use a low priority kernel context,
3587 * so it will effectively take effect when idle.
3588 */
3589 err = emit_oa_config(stream, config, oa_context(stream), NULL);
3590 if (!err)
3591 config = xchg(&stream->oa_config, config);
3592 else
3593 ret = err;
3594 }
3595
3596 i915_oa_config_put(config);
3597
3598 return ret;
3599}
3600
3601/**
3602 * i915_perf_ioctl_locked - support ioctl() usage with i915 perf stream FDs
3603 * @stream: An i915 perf stream
3604 * @cmd: the ioctl request
3605 * @arg: the ioctl data
3606 *
3607 * Returns: zero on success or a negative error code. Returns -EINVAL for
3608 * an unknown ioctl request.
3609 */
3610static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
3611 unsigned int cmd,
3612 unsigned long arg)
3613{
3614 switch (cmd) {
3615 case I915_PERF_IOCTL_ENABLE:
3616 i915_perf_enable_locked(stream);
3617 return 0;
3618 case I915_PERF_IOCTL_DISABLE:
3619 i915_perf_disable_locked(stream);
3620 return 0;
3621 case I915_PERF_IOCTL_CONFIG:
3622 return i915_perf_config_locked(stream, arg);
3623 }
3624
3625 return -EINVAL;
3626}
3627
3628/**
3629 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3630 * @file: An i915 perf stream file
3631 * @cmd: the ioctl request
3632 * @arg: the ioctl data
3633 *
3634 * Implementation deferred to i915_perf_ioctl_locked().
3635 *
3636 * Returns: zero on success or a negative error code. Returns -EINVAL for
3637 * an unknown ioctl request.
3638 */
3639static long i915_perf_ioctl(struct file *file,
3640 unsigned int cmd,
3641 unsigned long arg)
3642{
3643 struct i915_perf_stream *stream = file->private_data;
3644 long ret;
3645
3646 mutex_lock(&stream->lock);
3647 ret = i915_perf_ioctl_locked(stream, cmd, arg);
3648 mutex_unlock(&stream->lock);
3649
3650 return ret;
3651}
3652
3653/**
3654 * i915_perf_destroy_locked - destroy an i915 perf stream
3655 * @stream: An i915 perf stream
3656 *
3657 * Frees all resources associated with the given i915 perf @stream, disabling
3658 * any associated data capture in the process.
3659 *
3660 * Note: The >->perf.lock mutex has been taken to serialize
3661 * with any non-file-operation driver hooks.
3662 */
3663static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
3664{
3665 if (stream->enabled)
3666 i915_perf_disable_locked(stream);
3667
3668 if (stream->ops->destroy)
3669 stream->ops->destroy(stream);
3670
3671 if (stream->ctx)
3672 i915_gem_context_put(stream->ctx);
3673
3674 kfree(stream);
3675}
3676
3677/**
3678 * i915_perf_release - handles userspace close() of a stream file
3679 * @inode: anonymous inode associated with file
3680 * @file: An i915 perf stream file
3681 *
3682 * Cleans up any resources associated with an open i915 perf stream file.
3683 *
3684 * NB: close() can't really fail from the userspace point of view.
3685 *
3686 * Returns: zero on success or a negative error code.
3687 */
3688static int i915_perf_release(struct inode *inode, struct file *file)
3689{
3690 struct i915_perf_stream *stream = file->private_data;
3691 struct i915_perf *perf = stream->perf;
3692 struct intel_gt *gt = stream->engine->gt;
3693
3694 /*
3695 * Within this call, we know that the fd is being closed and we have no
3696 * other user of stream->lock. Use the perf lock to destroy the stream
3697 * here.
3698 */
3699 mutex_lock(>->perf.lock);
3700 i915_perf_destroy_locked(stream);
3701 mutex_unlock(>->perf.lock);
3702
3703 /* Release the reference the perf stream kept on the driver. */
3704 drm_dev_put(&perf->i915->drm);
3705
3706 return 0;
3707}
3708
3709
3710static const struct file_operations fops = {
3711 .owner = THIS_MODULE,
3712 .llseek = no_llseek,
3713 .release = i915_perf_release,
3714 .poll = i915_perf_poll,
3715 .read = i915_perf_read,
3716 .unlocked_ioctl = i915_perf_ioctl,
3717 /* Our ioctl have no arguments, so it's safe to use the same function
3718 * to handle 32bits compatibility.
3719 */
3720 .compat_ioctl = i915_perf_ioctl,
3721};
3722
3723
3724/**
3725 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
3726 * @perf: i915 perf instance
3727 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
3728 * @props: individually validated u64 property value pairs
3729 * @file: drm file
3730 *
3731 * See i915_perf_ioctl_open() for interface details.
3732 *
3733 * Implements further stream config validation and stream initialization on
3734 * behalf of i915_perf_open_ioctl() with the >->perf.lock mutex
3735 * taken to serialize with any non-file-operation driver hooks.
3736 *
3737 * Note: at this point the @props have only been validated in isolation and
3738 * it's still necessary to validate that the combination of properties makes
3739 * sense.
3740 *
3741 * In the case where userspace is interested in OA unit metrics then further
3742 * config validation and stream initialization details will be handled by
3743 * i915_oa_stream_init(). The code here should only validate config state that
3744 * will be relevant to all stream types / backends.
3745 *
3746 * Returns: zero on success or a negative error code.
3747 */
3748static int
3749i915_perf_open_ioctl_locked(struct i915_perf *perf,
3750 struct drm_i915_perf_open_param *param,
3751 struct perf_open_properties *props,
3752 struct drm_file *file)
3753{
3754 struct i915_gem_context *specific_ctx = NULL;
3755 struct i915_perf_stream *stream = NULL;
3756 unsigned long f_flags = 0;
3757 bool privileged_op = true;
3758 int stream_fd;
3759 int ret;
3760
3761 if (props->single_context) {
3762 u32 ctx_handle = props->ctx_handle;
3763 struct drm_i915_file_private *file_priv = file->driver_priv;
3764
3765 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
3766 if (IS_ERR(specific_ctx)) {
3767 drm_dbg(&perf->i915->drm,
3768 "Failed to look up context with ID %u for opening perf stream\n",
3769 ctx_handle);
3770 ret = PTR_ERR(specific_ctx);
3771 goto err;
3772 }
3773 }
3774
3775 /*
3776 * On Haswell the OA unit supports clock gating off for a specific
3777 * context and in this mode there's no visibility of metrics for the
3778 * rest of the system, which we consider acceptable for a
3779 * non-privileged client.
3780 *
3781 * For Gen8->11 the OA unit no longer supports clock gating off for a
3782 * specific context and the kernel can't securely stop the counters
3783 * from updating as system-wide / global values. Even though we can
3784 * filter reports based on the included context ID we can't block
3785 * clients from seeing the raw / global counter values via
3786 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
3787 * enable the OA unit by default.
3788 *
3789 * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
3790 * per context basis. So we can relax requirements there if the user
3791 * doesn't request global stream access (i.e. query based sampling
3792 * using MI_RECORD_PERF_COUNT.
3793 */
3794 if (IS_HASWELL(perf->i915) && specific_ctx)
3795 privileged_op = false;
3796 else if (GRAPHICS_VER(perf->i915) == 12 && specific_ctx &&
3797 (props->sample_flags & SAMPLE_OA_REPORT) == 0)
3798 privileged_op = false;
3799
3800 if (props->hold_preemption) {
3801 if (!props->single_context) {
3802 drm_dbg(&perf->i915->drm,
3803 "preemption disable with no context\n");
3804 ret = -EINVAL;
3805 goto err;
3806 }
3807 privileged_op = true;
3808 }
3809
3810 /*
3811 * Asking for SSEU configuration is a priviliged operation.
3812 */
3813 if (props->has_sseu)
3814 privileged_op = true;
3815 else
3816 get_default_sseu_config(&props->sseu, props->engine);
3817
3818 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
3819 * we check a dev.i915.perf_stream_paranoid sysctl option
3820 * to determine if it's ok to access system wide OA counters
3821 * without CAP_PERFMON or CAP_SYS_ADMIN privileges.
3822 */
3823 if (privileged_op &&
3824 i915_perf_stream_paranoid && !perfmon_capable()) {
3825 drm_dbg(&perf->i915->drm,
3826 "Insufficient privileges to open i915 perf stream\n");
3827 ret = -EACCES;
3828 goto err_ctx;
3829 }
3830
3831 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
3832 if (!stream) {
3833 ret = -ENOMEM;
3834 goto err_ctx;
3835 }
3836
3837 stream->perf = perf;
3838 stream->ctx = specific_ctx;
3839 stream->poll_oa_period = props->poll_oa_period;
3840
3841 ret = i915_oa_stream_init(stream, param, props);
3842 if (ret)
3843 goto err_alloc;
3844
3845 /* we avoid simply assigning stream->sample_flags = props->sample_flags
3846 * to have _stream_init check the combination of sample flags more
3847 * thoroughly, but still this is the expected result at this point.
3848 */
3849 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
3850 ret = -ENODEV;
3851 goto err_flags;
3852 }
3853
3854 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
3855 f_flags |= O_CLOEXEC;
3856 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
3857 f_flags |= O_NONBLOCK;
3858
3859 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
3860 if (stream_fd < 0) {
3861 ret = stream_fd;
3862 goto err_flags;
3863 }
3864
3865 if (!(param->flags & I915_PERF_FLAG_DISABLED))
3866 i915_perf_enable_locked(stream);
3867
3868 /* Take a reference on the driver that will be kept with stream_fd
3869 * until its release.
3870 */
3871 drm_dev_get(&perf->i915->drm);
3872
3873 return stream_fd;
3874
3875err_flags:
3876 if (stream->ops->destroy)
3877 stream->ops->destroy(stream);
3878err_alloc:
3879 kfree(stream);
3880err_ctx:
3881 if (specific_ctx)
3882 i915_gem_context_put(specific_ctx);
3883err:
3884 return ret;
3885}
3886
3887static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
3888{
3889 u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
3890 u32 den = i915_perf_oa_timestamp_frequency(perf->i915);
3891
3892 return div_u64(nom + den - 1, den);
3893}
3894
3895static __always_inline bool
3896oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
3897{
3898 return test_bit(format, perf->format_mask);
3899}
3900
3901static __always_inline void
3902oa_format_add(struct i915_perf *perf, enum drm_i915_oa_format format)
3903{
3904 __set_bit(format, perf->format_mask);
3905}
3906
3907/**
3908 * read_properties_unlocked - validate + copy userspace stream open properties
3909 * @perf: i915 perf instance
3910 * @uprops: The array of u64 key value pairs given by userspace
3911 * @n_props: The number of key value pairs expected in @uprops
3912 * @props: The stream configuration built up while validating properties
3913 *
3914 * Note this function only validates properties in isolation it doesn't
3915 * validate that the combination of properties makes sense or that all
3916 * properties necessary for a particular kind of stream have been set.
3917 *
3918 * Note that there currently aren't any ordering requirements for properties so
3919 * we shouldn't validate or assume anything about ordering here. This doesn't
3920 * rule out defining new properties with ordering requirements in the future.
3921 */
3922static int read_properties_unlocked(struct i915_perf *perf,
3923 u64 __user *uprops,
3924 u32 n_props,
3925 struct perf_open_properties *props)
3926{
3927 u64 __user *uprop = uprops;
3928 u32 i;
3929 int ret;
3930
3931 memset(props, 0, sizeof(struct perf_open_properties));
3932 props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
3933
3934 if (!n_props) {
3935 drm_dbg(&perf->i915->drm,
3936 "No i915 perf properties given\n");
3937 return -EINVAL;
3938 }
3939
3940 /* At the moment we only support using i915-perf on the RCS. */
3941 props->engine = intel_engine_lookup_user(perf->i915,
3942 I915_ENGINE_CLASS_RENDER,
3943 0);
3944 if (!props->engine) {
3945 drm_dbg(&perf->i915->drm,
3946 "No RENDER-capable engines\n");
3947 return -EINVAL;
3948 }
3949
3950 /* Considering that ID = 0 is reserved and assuming that we don't
3951 * (currently) expect any configurations to ever specify duplicate
3952 * values for a particular property ID then the last _PROP_MAX value is
3953 * one greater than the maximum number of properties we expect to get
3954 * from userspace.
3955 */
3956 if (n_props >= DRM_I915_PERF_PROP_MAX) {
3957 drm_dbg(&perf->i915->drm,
3958 "More i915 perf properties specified than exist\n");
3959 return -EINVAL;
3960 }
3961
3962 for (i = 0; i < n_props; i++) {
3963 u64 oa_period, oa_freq_hz;
3964 u64 id, value;
3965
3966 ret = get_user(id, uprop);
3967 if (ret)
3968 return ret;
3969
3970 ret = get_user(value, uprop + 1);
3971 if (ret)
3972 return ret;
3973
3974 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
3975 drm_dbg(&perf->i915->drm,
3976 "Unknown i915 perf property ID\n");
3977 return -EINVAL;
3978 }
3979
3980 switch ((enum drm_i915_perf_property_id)id) {
3981 case DRM_I915_PERF_PROP_CTX_HANDLE:
3982 props->single_context = 1;
3983 props->ctx_handle = value;
3984 break;
3985 case DRM_I915_PERF_PROP_SAMPLE_OA:
3986 if (value)
3987 props->sample_flags |= SAMPLE_OA_REPORT;
3988 break;
3989 case DRM_I915_PERF_PROP_OA_METRICS_SET:
3990 if (value == 0) {
3991 drm_dbg(&perf->i915->drm,
3992 "Unknown OA metric set ID\n");
3993 return -EINVAL;
3994 }
3995 props->metrics_set = value;
3996 break;
3997 case DRM_I915_PERF_PROP_OA_FORMAT:
3998 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
3999 drm_dbg(&perf->i915->drm,
4000 "Out-of-range OA report format %llu\n",
4001 value);
4002 return -EINVAL;
4003 }
4004 if (!oa_format_valid(perf, value)) {
4005 drm_dbg(&perf->i915->drm,
4006 "Unsupported OA report format %llu\n",
4007 value);
4008 return -EINVAL;
4009 }
4010 props->oa_format = value;
4011 break;
4012 case DRM_I915_PERF_PROP_OA_EXPONENT:
4013 if (value > OA_EXPONENT_MAX) {
4014 drm_dbg(&perf->i915->drm,
4015 "OA timer exponent too high (> %u)\n",
4016 OA_EXPONENT_MAX);
4017 return -EINVAL;
4018 }
4019
4020 /* Theoretically we can program the OA unit to sample
4021 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
4022 * for BXT. We don't allow such high sampling
4023 * frequencies by default unless root.
4024 */
4025
4026 BUILD_BUG_ON(sizeof(oa_period) != 8);
4027 oa_period = oa_exponent_to_ns(perf, value);
4028
4029 /* This check is primarily to ensure that oa_period <=
4030 * UINT32_MAX (before passing to do_div which only
4031 * accepts a u32 denominator), but we can also skip
4032 * checking anything < 1Hz which implicitly can't be
4033 * limited via an integer oa_max_sample_rate.
4034 */
4035 if (oa_period <= NSEC_PER_SEC) {
4036 u64 tmp = NSEC_PER_SEC;
4037 do_div(tmp, oa_period);
4038 oa_freq_hz = tmp;
4039 } else
4040 oa_freq_hz = 0;
4041
4042 if (oa_freq_hz > i915_oa_max_sample_rate && !perfmon_capable()) {
4043 drm_dbg(&perf->i915->drm,
4044 "OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
4045 i915_oa_max_sample_rate);
4046 return -EACCES;
4047 }
4048
4049 props->oa_periodic = true;
4050 props->oa_period_exponent = value;
4051 break;
4052 case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
4053 props->hold_preemption = !!value;
4054 break;
4055 case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
4056 struct drm_i915_gem_context_param_sseu user_sseu;
4057
4058 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
4059 drm_dbg(&perf->i915->drm,
4060 "SSEU config not supported on gfx %x\n",
4061 GRAPHICS_VER_FULL(perf->i915));
4062 return -ENODEV;
4063 }
4064
4065 if (copy_from_user(&user_sseu,
4066 u64_to_user_ptr(value),
4067 sizeof(user_sseu))) {
4068 drm_dbg(&perf->i915->drm,
4069 "Unable to copy global sseu parameter\n");
4070 return -EFAULT;
4071 }
4072
4073 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
4074 if (ret) {
4075 drm_dbg(&perf->i915->drm,
4076 "Invalid SSEU configuration\n");
4077 return ret;
4078 }
4079 props->has_sseu = true;
4080 break;
4081 }
4082 case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
4083 if (value < 100000 /* 100us */) {
4084 drm_dbg(&perf->i915->drm,
4085 "OA availability timer too small (%lluns < 100us)\n",
4086 value);
4087 return -EINVAL;
4088 }
4089 props->poll_oa_period = value;
4090 break;
4091 case DRM_I915_PERF_PROP_MAX:
4092 MISSING_CASE(id);
4093 return -EINVAL;
4094 }
4095
4096 uprop += 2;
4097 }
4098
4099 return 0;
4100}
4101
4102/**
4103 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
4104 * @dev: drm device
4105 * @data: ioctl data copied from userspace (unvalidated)
4106 * @file: drm file
4107 *
4108 * Validates the stream open parameters given by userspace including flags
4109 * and an array of u64 key, value pair properties.
4110 *
4111 * Very little is assumed up front about the nature of the stream being
4112 * opened (for instance we don't assume it's for periodic OA unit metrics). An
4113 * i915-perf stream is expected to be a suitable interface for other forms of
4114 * buffered data written by the GPU besides periodic OA metrics.
4115 *
4116 * Note we copy the properties from userspace outside of the i915 perf
4117 * mutex to avoid an awkward lockdep with mmap_lock.
4118 *
4119 * Most of the implementation details are handled by
4120 * i915_perf_open_ioctl_locked() after taking the >->perf.lock
4121 * mutex for serializing with any non-file-operation driver hooks.
4122 *
4123 * Return: A newly opened i915 Perf stream file descriptor or negative
4124 * error code on failure.
4125 */
4126int i915_perf_open_ioctl(struct drm_device *dev, void *data,
4127 struct drm_file *file)
4128{
4129 struct i915_perf *perf = &to_i915(dev)->perf;
4130 struct drm_i915_perf_open_param *param = data;
4131 struct intel_gt *gt;
4132 struct perf_open_properties props;
4133 u32 known_open_flags;
4134 int ret;
4135
4136 if (!perf->i915) {
4137 drm_dbg(&perf->i915->drm,
4138 "i915 perf interface not available for this system\n");
4139 return -ENOTSUPP;
4140 }
4141
4142 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
4143 I915_PERF_FLAG_FD_NONBLOCK |
4144 I915_PERF_FLAG_DISABLED;
4145 if (param->flags & ~known_open_flags) {
4146 drm_dbg(&perf->i915->drm,
4147 "Unknown drm_i915_perf_open_param flag\n");
4148 return -EINVAL;
4149 }
4150
4151 ret = read_properties_unlocked(perf,
4152 u64_to_user_ptr(param->properties_ptr),
4153 param->num_properties,
4154 &props);
4155 if (ret)
4156 return ret;
4157
4158 gt = props.engine->gt;
4159
4160 mutex_lock(>->perf.lock);
4161 ret = i915_perf_open_ioctl_locked(perf, param, &props, file);
4162 mutex_unlock(>->perf.lock);
4163
4164 return ret;
4165}
4166
4167/**
4168 * i915_perf_register - exposes i915-perf to userspace
4169 * @i915: i915 device instance
4170 *
4171 * In particular OA metric sets are advertised under a sysfs metrics/
4172 * directory allowing userspace to enumerate valid IDs that can be
4173 * used to open an i915-perf stream.
4174 */
4175void i915_perf_register(struct drm_i915_private *i915)
4176{
4177 struct i915_perf *perf = &i915->perf;
4178 struct intel_gt *gt = to_gt(i915);
4179
4180 if (!perf->i915)
4181 return;
4182
4183 /* To be sure we're synchronized with an attempted
4184 * i915_perf_open_ioctl(); considering that we register after
4185 * being exposed to userspace.
4186 */
4187 mutex_lock(>->perf.lock);
4188
4189 perf->metrics_kobj =
4190 kobject_create_and_add("metrics",
4191 &i915->drm.primary->kdev->kobj);
4192
4193 mutex_unlock(>->perf.lock);
4194}
4195
4196/**
4197 * i915_perf_unregister - hide i915-perf from userspace
4198 * @i915: i915 device instance
4199 *
4200 * i915-perf state cleanup is split up into an 'unregister' and
4201 * 'deinit' phase where the interface is first hidden from
4202 * userspace by i915_perf_unregister() before cleaning up
4203 * remaining state in i915_perf_fini().
4204 */
4205void i915_perf_unregister(struct drm_i915_private *i915)
4206{
4207 struct i915_perf *perf = &i915->perf;
4208
4209 if (!perf->metrics_kobj)
4210 return;
4211
4212 kobject_put(perf->metrics_kobj);
4213 perf->metrics_kobj = NULL;
4214}
4215
4216static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
4217{
4218 static const i915_reg_t flex_eu_regs[] = {
4219 EU_PERF_CNTL0,
4220 EU_PERF_CNTL1,
4221 EU_PERF_CNTL2,
4222 EU_PERF_CNTL3,
4223 EU_PERF_CNTL4,
4224 EU_PERF_CNTL5,
4225 EU_PERF_CNTL6,
4226 };
4227 int i;
4228
4229 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
4230 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
4231 return true;
4232 }
4233 return false;
4234}
4235
4236static bool reg_in_range_table(u32 addr, const struct i915_range *table)
4237{
4238 while (table->start || table->end) {
4239 if (addr >= table->start && addr <= table->end)
4240 return true;
4241
4242 table++;
4243 }
4244
4245 return false;
4246}
4247
4248#define REG_EQUAL(addr, mmio) \
4249 ((addr) == i915_mmio_reg_offset(mmio))
4250
4251static const struct i915_range gen7_oa_b_counters[] = {
4252 { .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
4253 { .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
4254 { .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
4255 {}
4256};
4257
4258static const struct i915_range gen12_oa_b_counters[] = {
4259 { .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
4260 { .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
4261 { .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8] */
4262 { .start = 0xd940, .end = 0xd97c }, /* GEN12_OAG_CEC[0-7][0-1] */
4263 { .start = 0xdc00, .end = 0xdc3c }, /* GEN12_OAG_SCEC[0-7][0-1] */
4264 { .start = 0xdc40, .end = 0xdc40 }, /* GEN12_OAG_SPCTR_CNF */
4265 { .start = 0xdc44, .end = 0xdc44 }, /* GEN12_OAA_DBG_REG */
4266 {}
4267};
4268
4269static const struct i915_range xehp_oa_b_counters[] = {
4270 { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
4271 { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */
4272};
4273
4274static const struct i915_range gen7_oa_mux_regs[] = {
4275 { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */
4276 { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
4277 { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
4278 {}
4279};
4280
4281static const struct i915_range hsw_oa_mux_regs[] = {
4282 { .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
4283 { .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
4284 { .start = 0x25100, .end = 0x2ff90 },
4285 {}
4286};
4287
4288static const struct i915_range chv_oa_mux_regs[] = {
4289 { .start = 0x182300, .end = 0x1823a4 },
4290 {}
4291};
4292
4293static const struct i915_range gen8_oa_mux_regs[] = {
4294 { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
4295 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4296 {}
4297};
4298
4299static const struct i915_range gen11_oa_mux_regs[] = {
4300 { .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
4301 {}
4302};
4303
4304static const struct i915_range gen12_oa_mux_regs[] = {
4305 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4306 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4307 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
4308 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
4309 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4310 {}
4311};
4312
4313static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4314{
4315 return reg_in_range_table(addr, gen7_oa_b_counters);
4316}
4317
4318static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4319{
4320 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4321 reg_in_range_table(addr, gen8_oa_mux_regs);
4322}
4323
4324static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4325{
4326 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4327 reg_in_range_table(addr, gen8_oa_mux_regs) ||
4328 reg_in_range_table(addr, gen11_oa_mux_regs);
4329}
4330
4331static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4332{
4333 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4334 reg_in_range_table(addr, hsw_oa_mux_regs);
4335}
4336
4337static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4338{
4339 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4340 reg_in_range_table(addr, chv_oa_mux_regs);
4341}
4342
4343static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4344{
4345 return reg_in_range_table(addr, gen12_oa_b_counters);
4346}
4347
4348static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4349{
4350 return reg_in_range_table(addr, xehp_oa_b_counters) ||
4351 reg_in_range_table(addr, gen12_oa_b_counters);
4352}
4353
4354static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4355{
4356 return reg_in_range_table(addr, gen12_oa_mux_regs);
4357}
4358
4359static u32 mask_reg_value(u32 reg, u32 val)
4360{
4361 /* HALF_SLICE_CHICKEN2 is programmed with a the
4362 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
4363 * programmed by userspace doesn't change this.
4364 */
4365 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
4366 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
4367
4368 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
4369 * indicated by its name and a bunch of selection fields used by OA
4370 * configs.
4371 */
4372 if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
4373 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
4374
4375 return val;
4376}
4377
4378static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf,
4379 bool (*is_valid)(struct i915_perf *perf, u32 addr),
4380 u32 __user *regs,
4381 u32 n_regs)
4382{
4383 struct i915_oa_reg *oa_regs;
4384 int err;
4385 u32 i;
4386
4387 if (!n_regs)
4388 return NULL;
4389
4390 /* No is_valid function means we're not allowing any register to be programmed. */
4391 GEM_BUG_ON(!is_valid);
4392 if (!is_valid)
4393 return ERR_PTR(-EINVAL);
4394
4395 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
4396 if (!oa_regs)
4397 return ERR_PTR(-ENOMEM);
4398
4399 for (i = 0; i < n_regs; i++) {
4400 u32 addr, value;
4401
4402 err = get_user(addr, regs);
4403 if (err)
4404 goto addr_err;
4405
4406 if (!is_valid(perf, addr)) {
4407 drm_dbg(&perf->i915->drm,
4408 "Invalid oa_reg address: %X\n", addr);
4409 err = -EINVAL;
4410 goto addr_err;
4411 }
4412
4413 err = get_user(value, regs + 1);
4414 if (err)
4415 goto addr_err;
4416
4417 oa_regs[i].addr = _MMIO(addr);
4418 oa_regs[i].value = mask_reg_value(addr, value);
4419
4420 regs += 2;
4421 }
4422
4423 return oa_regs;
4424
4425addr_err:
4426 kfree(oa_regs);
4427 return ERR_PTR(err);
4428}
4429
4430static ssize_t show_dynamic_id(struct kobject *kobj,
4431 struct kobj_attribute *attr,
4432 char *buf)
4433{
4434 struct i915_oa_config *oa_config =
4435 container_of(attr, typeof(*oa_config), sysfs_metric_id);
4436
4437 return sprintf(buf, "%d\n", oa_config->id);
4438}
4439
4440static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf,
4441 struct i915_oa_config *oa_config)
4442{
4443 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
4444 oa_config->sysfs_metric_id.attr.name = "id";
4445 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
4446 oa_config->sysfs_metric_id.show = show_dynamic_id;
4447 oa_config->sysfs_metric_id.store = NULL;
4448
4449 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
4450 oa_config->attrs[1] = NULL;
4451
4452 oa_config->sysfs_metric.name = oa_config->uuid;
4453 oa_config->sysfs_metric.attrs = oa_config->attrs;
4454
4455 return sysfs_create_group(perf->metrics_kobj,
4456 &oa_config->sysfs_metric);
4457}
4458
4459/**
4460 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
4461 * @dev: drm device
4462 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
4463 * userspace (unvalidated)
4464 * @file: drm file
4465 *
4466 * Validates the submitted OA register to be saved into a new OA config that
4467 * can then be used for programming the OA unit and its NOA network.
4468 *
4469 * Returns: A new allocated config number to be used with the perf open ioctl
4470 * or a negative error code on failure.
4471 */
4472int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
4473 struct drm_file *file)
4474{
4475 struct i915_perf *perf = &to_i915(dev)->perf;
4476 struct drm_i915_perf_oa_config *args = data;
4477 struct i915_oa_config *oa_config, *tmp;
4478 struct i915_oa_reg *regs;
4479 int err, id;
4480
4481 if (!perf->i915) {
4482 drm_dbg(&perf->i915->drm,
4483 "i915 perf interface not available for this system\n");
4484 return -ENOTSUPP;
4485 }
4486
4487 if (!perf->metrics_kobj) {
4488 drm_dbg(&perf->i915->drm,
4489 "OA metrics weren't advertised via sysfs\n");
4490 return -EINVAL;
4491 }
4492
4493 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4494 drm_dbg(&perf->i915->drm,
4495 "Insufficient privileges to add i915 OA config\n");
4496 return -EACCES;
4497 }
4498
4499 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
4500 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
4501 (!args->flex_regs_ptr || !args->n_flex_regs)) {
4502 drm_dbg(&perf->i915->drm,
4503 "No OA registers given\n");
4504 return -EINVAL;
4505 }
4506
4507 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
4508 if (!oa_config) {
4509 drm_dbg(&perf->i915->drm,
4510 "Failed to allocate memory for the OA config\n");
4511 return -ENOMEM;
4512 }
4513
4514 oa_config->perf = perf;
4515 kref_init(&oa_config->ref);
4516
4517 if (!uuid_is_valid(args->uuid)) {
4518 drm_dbg(&perf->i915->drm,
4519 "Invalid uuid format for OA config\n");
4520 err = -EINVAL;
4521 goto reg_err;
4522 }
4523
4524 /* Last character in oa_config->uuid will be 0 because oa_config is
4525 * kzalloc.
4526 */
4527 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
4528
4529 oa_config->mux_regs_len = args->n_mux_regs;
4530 regs = alloc_oa_regs(perf,
4531 perf->ops.is_valid_mux_reg,
4532 u64_to_user_ptr(args->mux_regs_ptr),
4533 args->n_mux_regs);
4534
4535 if (IS_ERR(regs)) {
4536 drm_dbg(&perf->i915->drm,
4537 "Failed to create OA config for mux_regs\n");
4538 err = PTR_ERR(regs);
4539 goto reg_err;
4540 }
4541 oa_config->mux_regs = regs;
4542
4543 oa_config->b_counter_regs_len = args->n_boolean_regs;
4544 regs = alloc_oa_regs(perf,
4545 perf->ops.is_valid_b_counter_reg,
4546 u64_to_user_ptr(args->boolean_regs_ptr),
4547 args->n_boolean_regs);
4548
4549 if (IS_ERR(regs)) {
4550 drm_dbg(&perf->i915->drm,
4551 "Failed to create OA config for b_counter_regs\n");
4552 err = PTR_ERR(regs);
4553 goto reg_err;
4554 }
4555 oa_config->b_counter_regs = regs;
4556
4557 if (GRAPHICS_VER(perf->i915) < 8) {
4558 if (args->n_flex_regs != 0) {
4559 err = -EINVAL;
4560 goto reg_err;
4561 }
4562 } else {
4563 oa_config->flex_regs_len = args->n_flex_regs;
4564 regs = alloc_oa_regs(perf,
4565 perf->ops.is_valid_flex_reg,
4566 u64_to_user_ptr(args->flex_regs_ptr),
4567 args->n_flex_regs);
4568
4569 if (IS_ERR(regs)) {
4570 drm_dbg(&perf->i915->drm,
4571 "Failed to create OA config for flex_regs\n");
4572 err = PTR_ERR(regs);
4573 goto reg_err;
4574 }
4575 oa_config->flex_regs = regs;
4576 }
4577
4578 err = mutex_lock_interruptible(&perf->metrics_lock);
4579 if (err)
4580 goto reg_err;
4581
4582 /* We shouldn't have too many configs, so this iteration shouldn't be
4583 * too costly.
4584 */
4585 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
4586 if (!strcmp(tmp->uuid, oa_config->uuid)) {
4587 drm_dbg(&perf->i915->drm,
4588 "OA config already exists with this uuid\n");
4589 err = -EADDRINUSE;
4590 goto sysfs_err;
4591 }
4592 }
4593
4594 err = create_dynamic_oa_sysfs_entry(perf, oa_config);
4595 if (err) {
4596 drm_dbg(&perf->i915->drm,
4597 "Failed to create sysfs entry for OA config\n");
4598 goto sysfs_err;
4599 }
4600
4601 /* Config id 0 is invalid, id 1 for kernel stored test config. */
4602 oa_config->id = idr_alloc(&perf->metrics_idr,
4603 oa_config, 2,
4604 0, GFP_KERNEL);
4605 if (oa_config->id < 0) {
4606 drm_dbg(&perf->i915->drm,
4607 "Failed to create sysfs entry for OA config\n");
4608 err = oa_config->id;
4609 goto sysfs_err;
4610 }
4611
4612 mutex_unlock(&perf->metrics_lock);
4613
4614 drm_dbg(&perf->i915->drm,
4615 "Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4616
4617 return oa_config->id;
4618
4619sysfs_err:
4620 mutex_unlock(&perf->metrics_lock);
4621reg_err:
4622 i915_oa_config_put(oa_config);
4623 drm_dbg(&perf->i915->drm,
4624 "Failed to add new OA config\n");
4625 return err;
4626}
4627
4628/**
4629 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
4630 * @dev: drm device
4631 * @data: ioctl data (pointer to u64 integer) copied from userspace
4632 * @file: drm file
4633 *
4634 * Configs can be removed while being used, the will stop appearing in sysfs
4635 * and their content will be freed when the stream using the config is closed.
4636 *
4637 * Returns: 0 on success or a negative error code on failure.
4638 */
4639int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
4640 struct drm_file *file)
4641{
4642 struct i915_perf *perf = &to_i915(dev)->perf;
4643 u64 *arg = data;
4644 struct i915_oa_config *oa_config;
4645 int ret;
4646
4647 if (!perf->i915) {
4648 drm_dbg(&perf->i915->drm,
4649 "i915 perf interface not available for this system\n");
4650 return -ENOTSUPP;
4651 }
4652
4653 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4654 drm_dbg(&perf->i915->drm,
4655 "Insufficient privileges to remove i915 OA config\n");
4656 return -EACCES;
4657 }
4658
4659 ret = mutex_lock_interruptible(&perf->metrics_lock);
4660 if (ret)
4661 return ret;
4662
4663 oa_config = idr_find(&perf->metrics_idr, *arg);
4664 if (!oa_config) {
4665 drm_dbg(&perf->i915->drm,
4666 "Failed to remove unknown OA config\n");
4667 ret = -ENOENT;
4668 goto err_unlock;
4669 }
4670
4671 GEM_BUG_ON(*arg != oa_config->id);
4672
4673 sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric);
4674
4675 idr_remove(&perf->metrics_idr, *arg);
4676
4677 mutex_unlock(&perf->metrics_lock);
4678
4679 drm_dbg(&perf->i915->drm,
4680 "Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
4681
4682 i915_oa_config_put(oa_config);
4683
4684 return 0;
4685
4686err_unlock:
4687 mutex_unlock(&perf->metrics_lock);
4688 return ret;
4689}
4690
4691static struct ctl_table oa_table[] = {
4692 {
4693 .procname = "perf_stream_paranoid",
4694 .data = &i915_perf_stream_paranoid,
4695 .maxlen = sizeof(i915_perf_stream_paranoid),
4696 .mode = 0644,
4697 .proc_handler = proc_dointvec_minmax,
4698 .extra1 = SYSCTL_ZERO,
4699 .extra2 = SYSCTL_ONE,
4700 },
4701 {
4702 .procname = "oa_max_sample_rate",
4703 .data = &i915_oa_max_sample_rate,
4704 .maxlen = sizeof(i915_oa_max_sample_rate),
4705 .mode = 0644,
4706 .proc_handler = proc_dointvec_minmax,
4707 .extra1 = SYSCTL_ZERO,
4708 .extra2 = &oa_sample_rate_hard_limit,
4709 },
4710 {}
4711};
4712
4713static void oa_init_supported_formats(struct i915_perf *perf)
4714{
4715 struct drm_i915_private *i915 = perf->i915;
4716 enum intel_platform platform = INTEL_INFO(i915)->platform;
4717
4718 switch (platform) {
4719 case INTEL_HASWELL:
4720 oa_format_add(perf, I915_OA_FORMAT_A13);
4721 oa_format_add(perf, I915_OA_FORMAT_A13);
4722 oa_format_add(perf, I915_OA_FORMAT_A29);
4723 oa_format_add(perf, I915_OA_FORMAT_A13_B8_C8);
4724 oa_format_add(perf, I915_OA_FORMAT_B4_C8);
4725 oa_format_add(perf, I915_OA_FORMAT_A45_B8_C8);
4726 oa_format_add(perf, I915_OA_FORMAT_B4_C8_A16);
4727 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4728 break;
4729
4730 case INTEL_BROADWELL:
4731 case INTEL_CHERRYVIEW:
4732 case INTEL_SKYLAKE:
4733 case INTEL_BROXTON:
4734 case INTEL_KABYLAKE:
4735 case INTEL_GEMINILAKE:
4736 case INTEL_COFFEELAKE:
4737 case INTEL_COMETLAKE:
4738 case INTEL_ICELAKE:
4739 case INTEL_ELKHARTLAKE:
4740 case INTEL_JASPERLAKE:
4741 case INTEL_TIGERLAKE:
4742 case INTEL_ROCKETLAKE:
4743 case INTEL_DG1:
4744 case INTEL_ALDERLAKE_S:
4745 case INTEL_ALDERLAKE_P:
4746 oa_format_add(perf, I915_OA_FORMAT_A12);
4747 oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
4748 oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
4749 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4750 break;
4751
4752 case INTEL_DG2:
4753 oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
4754 oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
4755 break;
4756
4757 default:
4758 MISSING_CASE(platform);
4759 }
4760}
4761
4762static void i915_perf_init_info(struct drm_i915_private *i915)
4763{
4764 struct i915_perf *perf = &i915->perf;
4765
4766 switch (GRAPHICS_VER(i915)) {
4767 case 8:
4768 perf->ctx_oactxctrl_offset = 0x120;
4769 perf->ctx_flexeu0_offset = 0x2ce;
4770 perf->gen8_valid_ctx_bit = BIT(25);
4771 break;
4772 case 9:
4773 perf->ctx_oactxctrl_offset = 0x128;
4774 perf->ctx_flexeu0_offset = 0x3de;
4775 perf->gen8_valid_ctx_bit = BIT(16);
4776 break;
4777 case 11:
4778 perf->ctx_oactxctrl_offset = 0x124;
4779 perf->ctx_flexeu0_offset = 0x78e;
4780 perf->gen8_valid_ctx_bit = BIT(16);
4781 break;
4782 case 12:
4783 /*
4784 * Calculate offset at runtime in oa_pin_context for gen12 and
4785 * cache the value in perf->ctx_oactxctrl_offset.
4786 */
4787 break;
4788 default:
4789 MISSING_CASE(GRAPHICS_VER(i915));
4790 }
4791}
4792
4793/**
4794 * i915_perf_init - initialize i915-perf state on module bind
4795 * @i915: i915 device instance
4796 *
4797 * Initializes i915-perf state without exposing anything to userspace.
4798 *
4799 * Note: i915-perf initialization is split into an 'init' and 'register'
4800 * phase with the i915_perf_register() exposing state to userspace.
4801 */
4802void i915_perf_init(struct drm_i915_private *i915)
4803{
4804 struct i915_perf *perf = &i915->perf;
4805
4806 perf->oa_formats = oa_formats;
4807 if (IS_HASWELL(i915)) {
4808 perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
4809 perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
4810 perf->ops.is_valid_flex_reg = NULL;
4811 perf->ops.enable_metric_set = hsw_enable_metric_set;
4812 perf->ops.disable_metric_set = hsw_disable_metric_set;
4813 perf->ops.oa_enable = gen7_oa_enable;
4814 perf->ops.oa_disable = gen7_oa_disable;
4815 perf->ops.read = gen7_oa_read;
4816 perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
4817 } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
4818 /* Note: that although we could theoretically also support the
4819 * legacy ringbuffer mode on BDW (and earlier iterations of
4820 * this driver, before upstreaming did this) it didn't seem
4821 * worth the complexity to maintain now that BDW+ enable
4822 * execlist mode by default.
4823 */
4824 perf->ops.read = gen8_oa_read;
4825 i915_perf_init_info(i915);
4826
4827 if (IS_GRAPHICS_VER(i915, 8, 9)) {
4828 perf->ops.is_valid_b_counter_reg =
4829 gen7_is_valid_b_counter_addr;
4830 perf->ops.is_valid_mux_reg =
4831 gen8_is_valid_mux_addr;
4832 perf->ops.is_valid_flex_reg =
4833 gen8_is_valid_flex_addr;
4834
4835 if (IS_CHERRYVIEW(i915)) {
4836 perf->ops.is_valid_mux_reg =
4837 chv_is_valid_mux_addr;
4838 }
4839
4840 perf->ops.oa_enable = gen8_oa_enable;
4841 perf->ops.oa_disable = gen8_oa_disable;
4842 perf->ops.enable_metric_set = gen8_enable_metric_set;
4843 perf->ops.disable_metric_set = gen8_disable_metric_set;
4844 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4845 } else if (GRAPHICS_VER(i915) == 11) {
4846 perf->ops.is_valid_b_counter_reg =
4847 gen7_is_valid_b_counter_addr;
4848 perf->ops.is_valid_mux_reg =
4849 gen11_is_valid_mux_addr;
4850 perf->ops.is_valid_flex_reg =
4851 gen8_is_valid_flex_addr;
4852
4853 perf->ops.oa_enable = gen8_oa_enable;
4854 perf->ops.oa_disable = gen8_oa_disable;
4855 perf->ops.enable_metric_set = gen8_enable_metric_set;
4856 perf->ops.disable_metric_set = gen11_disable_metric_set;
4857 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4858 } else if (GRAPHICS_VER(i915) == 12) {
4859 perf->ops.is_valid_b_counter_reg =
4860 HAS_OA_SLICE_CONTRIB_LIMITS(i915) ?
4861 xehp_is_valid_b_counter_addr :
4862 gen12_is_valid_b_counter_addr;
4863 perf->ops.is_valid_mux_reg =
4864 gen12_is_valid_mux_addr;
4865 perf->ops.is_valid_flex_reg =
4866 gen8_is_valid_flex_addr;
4867
4868 perf->ops.oa_enable = gen12_oa_enable;
4869 perf->ops.oa_disable = gen12_oa_disable;
4870 perf->ops.enable_metric_set = gen12_enable_metric_set;
4871 perf->ops.disable_metric_set = gen12_disable_metric_set;
4872 perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
4873 }
4874 }
4875
4876 if (perf->ops.enable_metric_set) {
4877 struct intel_gt *gt;
4878 int i;
4879
4880 for_each_gt(gt, i915, i)
4881 mutex_init(>->perf.lock);
4882
4883 /* Choose a representative limit */
4884 oa_sample_rate_hard_limit = to_gt(i915)->clock_frequency / 2;
4885
4886 mutex_init(&perf->metrics_lock);
4887 idr_init_base(&perf->metrics_idr, 1);
4888
4889 /* We set up some ratelimit state to potentially throttle any
4890 * _NOTES about spurious, invalid OA reports which we don't
4891 * forward to userspace.
4892 *
4893 * We print a _NOTE about any throttling when closing the
4894 * stream instead of waiting until driver _fini which no one
4895 * would ever see.
4896 *
4897 * Using the same limiting factors as printk_ratelimit()
4898 */
4899 ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10);
4900 /* Since we use a DRM_NOTE for spurious reports it would be
4901 * inconsistent to let __ratelimit() automatically print a
4902 * warning for throttling.
4903 */
4904 ratelimit_set_flags(&perf->spurious_report_rs,
4905 RATELIMIT_MSG_ON_RELEASE);
4906
4907 ratelimit_state_init(&perf->tail_pointer_race,
4908 5 * HZ, 10);
4909 ratelimit_set_flags(&perf->tail_pointer_race,
4910 RATELIMIT_MSG_ON_RELEASE);
4911
4912 atomic64_set(&perf->noa_programming_delay,
4913 500 * 1000 /* 500us */);
4914
4915 perf->i915 = i915;
4916
4917 oa_init_supported_formats(perf);
4918 }
4919}
4920
4921static int destroy_config(int id, void *p, void *data)
4922{
4923 i915_oa_config_put(p);
4924 return 0;
4925}
4926
4927int i915_perf_sysctl_register(void)
4928{
4929 sysctl_header = register_sysctl("dev/i915", oa_table);
4930 return 0;
4931}
4932
4933void i915_perf_sysctl_unregister(void)
4934{
4935 unregister_sysctl_table(sysctl_header);
4936}
4937
4938/**
4939 * i915_perf_fini - Counter part to i915_perf_init()
4940 * @i915: i915 device instance
4941 */
4942void i915_perf_fini(struct drm_i915_private *i915)
4943{
4944 struct i915_perf *perf = &i915->perf;
4945
4946 if (!perf->i915)
4947 return;
4948
4949 idr_for_each(&perf->metrics_idr, destroy_config, perf);
4950 idr_destroy(&perf->metrics_idr);
4951
4952 memset(&perf->ops, 0, sizeof(perf->ops));
4953 perf->i915 = NULL;
4954}
4955
4956/**
4957 * i915_perf_ioctl_version - Version of the i915-perf subsystem
4958 *
4959 * This version number is used by userspace to detect available features.
4960 */
4961int i915_perf_ioctl_version(void)
4962{
4963 /*
4964 * 1: Initial version
4965 * I915_PERF_IOCTL_ENABLE
4966 * I915_PERF_IOCTL_DISABLE
4967 *
4968 * 2: Added runtime modification of OA config.
4969 * I915_PERF_IOCTL_CONFIG
4970 *
4971 * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
4972 * preemption on a particular context so that performance data is
4973 * accessible from a delta of MI_RPC reports without looking at the
4974 * OA buffer.
4975 *
4976 * 4: Add DRM_I915_PERF_PROP_ALLOWED_SSEU to limit what contexts can
4977 * be run for the duration of the performance recording based on
4978 * their SSEU configuration.
4979 *
4980 * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
4981 * interval for the hrtimer used to check for OA data.
4982 */
4983 return 5;
4984}
4985
4986#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
4987#include "selftests/i915_perf.c"
4988#endif