1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2019 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_GT__
  7#define __INTEL_GT__
  8
  9#include "intel_engine_types.h"
 10#include "intel_gt_types.h"
 11#include "intel_reset.h"
 12
 13struct drm_i915_private;
 14struct drm_printer;
 15
 16#define GT_TRACE(gt, fmt, ...) do {					\
 17	const struct intel_gt *gt__ __maybe_unused = (gt);		\
 18	GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),		\
 19		  ##__VA_ARGS__);					\
 20} while (0)
 21
 22static inline bool gt_is_root(struct intel_gt *gt)
 23{
 24	return !gt->info.id;
 25}
 26
 27static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
 28{
 29	return container_of(uc, struct intel_gt, uc);
 30}
 31
 32static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
 33{
 34	return container_of(guc, struct intel_gt, uc.guc);
 35}
 36
 37static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
 38{
 39	return container_of(huc, struct intel_gt, uc.huc);
 40}
 41
 42static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
 43{
 44	return container_of(gsc, struct intel_gt, gsc);
 45}
 46
 47void intel_gt_common_init_early(struct intel_gt *gt);
 48int intel_root_gt_init_early(struct drm_i915_private *i915);
 49int intel_gt_assign_ggtt(struct intel_gt *gt);
 50int intel_gt_init_mmio(struct intel_gt *gt);
 51int __must_check intel_gt_init_hw(struct intel_gt *gt);
 52int intel_gt_init(struct intel_gt *gt);
 53void intel_gt_driver_register(struct intel_gt *gt);
 54
 55void intel_gt_driver_unregister(struct intel_gt *gt);
 56void intel_gt_driver_remove(struct intel_gt *gt);
 57void intel_gt_driver_release(struct intel_gt *gt);
 58void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
 59
 60int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
 61
 62void intel_gt_check_and_clear_faults(struct intel_gt *gt);
 63i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
 64void intel_gt_clear_error_registers(struct intel_gt *gt,
 65				    intel_engine_mask_t engine_mask);
 66
 67void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
 68void intel_gt_chipset_flush(struct intel_gt *gt);
 69
 70static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
 71					  enum intel_gt_scratch_field field)
 72{
 73	return i915_ggtt_offset(gt->scratch) + field;
 74}
 75
 76static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt)
 77{
 78	return test_bit(I915_WEDGED_ON_INIT, &gt->reset.flags) ||
 79	       test_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
 80}
 81
 82static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
 83{
 84	GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) &&
 85		   !test_bit(I915_WEDGED, &gt->reset.flags));
 86
 87	return unlikely(test_bit(I915_WEDGED, &gt->reset.flags));
 88}
 89
 90int intel_gt_probe_all(struct drm_i915_private *i915);
 91int intel_gt_tiles_init(struct drm_i915_private *i915);
 92void intel_gt_release_all(struct drm_i915_private *i915);
 93
 94#define for_each_gt(gt__, i915__, id__) \
 95	for ((id__) = 0; \
 96	     (id__) < I915_MAX_GT; \
 97	     (id__)++) \
 98		for_each_if(((gt__) = (i915__)->gt[(id__)]))
 99
100void intel_gt_info_print(const struct intel_gt_info *info,
101			 struct drm_printer *p);
102
103void intel_gt_watchdog_work(struct work_struct *work);
104
105static inline u32 intel_gt_tlb_seqno(const struct intel_gt *gt)
106{
107	return seqprop_sequence(&gt->tlb.seqno);
108}
109
110static inline u32 intel_gt_next_invalidate_tlb_full(const struct intel_gt *gt)
111{
112	return intel_gt_tlb_seqno(gt) | 1;
113}
114
115void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno);
116
117#endif /* __INTEL_GT_H__ */