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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2014 Intel Corporation
4 */
5
6#include "gen8_engine_cs.h"
7#include "i915_drv.h"
8#include "intel_engine_regs.h"
9#include "intel_gpu_commands.h"
10#include "intel_lrc.h"
11#include "intel_ring.h"
12
13int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
14{
15 bool vf_flush_wa = false, dc_flush_wa = false;
16 u32 *cs, flags = 0;
17 int len;
18
19 flags |= PIPE_CONTROL_CS_STALL;
20
21 if (mode & EMIT_FLUSH) {
22 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
23 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
24 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
25 flags |= PIPE_CONTROL_FLUSH_ENABLE;
26 }
27
28 if (mode & EMIT_INVALIDATE) {
29 flags |= PIPE_CONTROL_TLB_INVALIDATE;
30 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
31 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
32 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
33 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
34 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
35 flags |= PIPE_CONTROL_QW_WRITE;
36 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
37
38 /*
39 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
40 * pipe control.
41 */
42 if (GRAPHICS_VER(rq->engine->i915) == 9)
43 vf_flush_wa = true;
44
45 /* WaForGAMHang:kbl */
46 if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
47 dc_flush_wa = true;
48 }
49
50 len = 6;
51
52 if (vf_flush_wa)
53 len += 6;
54
55 if (dc_flush_wa)
56 len += 12;
57
58 cs = intel_ring_begin(rq, len);
59 if (IS_ERR(cs))
60 return PTR_ERR(cs);
61
62 if (vf_flush_wa)
63 cs = gen8_emit_pipe_control(cs, 0, 0);
64
65 if (dc_flush_wa)
66 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
67 0);
68
69 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
70
71 if (dc_flush_wa)
72 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
73
74 intel_ring_advance(rq, cs);
75
76 return 0;
77}
78
79int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode)
80{
81 u32 cmd, *cs;
82
83 cs = intel_ring_begin(rq, 4);
84 if (IS_ERR(cs))
85 return PTR_ERR(cs);
86
87 cmd = MI_FLUSH_DW + 1;
88
89 /*
90 * We always require a command barrier so that subsequent
91 * commands, such as breadcrumb interrupts, are strictly ordered
92 * wrt the contents of the write cache being flushed to memory
93 * (and thus being coherent from the CPU).
94 */
95 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
96
97 if (mode & EMIT_INVALIDATE) {
98 cmd |= MI_INVALIDATE_TLB;
99 if (rq->engine->class == VIDEO_DECODE_CLASS)
100 cmd |= MI_INVALIDATE_BSD;
101 }
102
103 *cs++ = cmd;
104 *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
105 *cs++ = 0; /* upper addr */
106 *cs++ = 0; /* value */
107 intel_ring_advance(rq, cs);
108
109 return 0;
110}
111
112int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode)
113{
114 if (mode & EMIT_FLUSH) {
115 u32 *cs;
116 u32 flags = 0;
117
118 flags |= PIPE_CONTROL_CS_STALL;
119
120 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
121 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
122 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
123 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
124 flags |= PIPE_CONTROL_FLUSH_ENABLE;
125 flags |= PIPE_CONTROL_QW_WRITE;
126 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
127
128 cs = intel_ring_begin(rq, 6);
129 if (IS_ERR(cs))
130 return PTR_ERR(cs);
131
132 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
133 intel_ring_advance(rq, cs);
134 }
135
136 if (mode & EMIT_INVALIDATE) {
137 u32 *cs;
138 u32 flags = 0;
139
140 flags |= PIPE_CONTROL_CS_STALL;
141
142 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
143 flags |= PIPE_CONTROL_TLB_INVALIDATE;
144 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
145 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
146 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
147 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
148 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
149 flags |= PIPE_CONTROL_QW_WRITE;
150 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
151
152 cs = intel_ring_begin(rq, 6);
153 if (IS_ERR(cs))
154 return PTR_ERR(cs);
155
156 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
157 intel_ring_advance(rq, cs);
158 }
159
160 return 0;
161}
162
163static u32 preparser_disable(bool state)
164{
165 return MI_ARB_CHECK | 1 << 8 | state;
166}
167
168u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg)
169{
170 u32 gsi_offset = gt->uncore->gsi_offset;
171
172 *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
173 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
174 *cs++ = AUX_INV;
175 *cs++ = MI_NOOP;
176
177 return cs;
178}
179
180int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
181{
182 struct intel_engine_cs *engine = rq->engine;
183
184 if (mode & EMIT_FLUSH) {
185 u32 flags = 0;
186 u32 *cs;
187
188 flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
189 flags |= PIPE_CONTROL_FLUSH_L3;
190 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
191 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
192 /* Wa_1409600907:tgl,adl-p */
193 flags |= PIPE_CONTROL_DEPTH_STALL;
194 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
195 flags |= PIPE_CONTROL_FLUSH_ENABLE;
196
197 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
198 flags |= PIPE_CONTROL_QW_WRITE;
199
200 flags |= PIPE_CONTROL_CS_STALL;
201
202 if (!HAS_3D_PIPELINE(engine->i915))
203 flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
204 else if (engine->class == COMPUTE_CLASS)
205 flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
206
207 cs = intel_ring_begin(rq, 6);
208 if (IS_ERR(cs))
209 return PTR_ERR(cs);
210
211 cs = gen12_emit_pipe_control(cs,
212 PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
213 flags, LRC_PPHWSP_SCRATCH_ADDR);
214 intel_ring_advance(rq, cs);
215 }
216
217 if (mode & EMIT_INVALIDATE) {
218 u32 flags = 0;
219 u32 *cs, count;
220
221 flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
222 flags |= PIPE_CONTROL_TLB_INVALIDATE;
223 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
224 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
225 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
226 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
227 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
228
229 flags |= PIPE_CONTROL_STORE_DATA_INDEX;
230 flags |= PIPE_CONTROL_QW_WRITE;
231
232 flags |= PIPE_CONTROL_CS_STALL;
233
234 if (!HAS_3D_PIPELINE(engine->i915))
235 flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
236 else if (engine->class == COMPUTE_CLASS)
237 flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
238
239 if (!HAS_FLAT_CCS(rq->engine->i915))
240 count = 8 + 4;
241 else
242 count = 8;
243
244 cs = intel_ring_begin(rq, count);
245 if (IS_ERR(cs))
246 return PTR_ERR(cs);
247
248 /*
249 * Prevent the pre-parser from skipping past the TLB
250 * invalidate and loading a stale page for the batch
251 * buffer / request payload.
252 */
253 *cs++ = preparser_disable(true);
254
255 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
256
257 if (!HAS_FLAT_CCS(rq->engine->i915)) {
258 /* hsdes: 1809175790 */
259 cs = gen12_emit_aux_table_inv(rq->engine->gt,
260 cs, GEN12_GFX_CCS_AUX_NV);
261 }
262
263 *cs++ = preparser_disable(false);
264 intel_ring_advance(rq, cs);
265 }
266
267 return 0;
268}
269
270int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
271{
272 intel_engine_mask_t aux_inv = 0;
273 u32 cmd, *cs;
274
275 cmd = 4;
276 if (mode & EMIT_INVALIDATE) {
277 cmd += 2;
278
279 if (!HAS_FLAT_CCS(rq->engine->i915) &&
280 (rq->engine->class == VIDEO_DECODE_CLASS ||
281 rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
282 aux_inv = rq->engine->mask &
283 ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
284 if (aux_inv)
285 cmd += 4;
286 }
287 }
288
289 cs = intel_ring_begin(rq, cmd);
290 if (IS_ERR(cs))
291 return PTR_ERR(cs);
292
293 if (mode & EMIT_INVALIDATE)
294 *cs++ = preparser_disable(true);
295
296 cmd = MI_FLUSH_DW + 1;
297
298 /*
299 * We always require a command barrier so that subsequent
300 * commands, such as breadcrumb interrupts, are strictly ordered
301 * wrt the contents of the write cache being flushed to memory
302 * (and thus being coherent from the CPU).
303 */
304 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
305
306 if (mode & EMIT_INVALIDATE) {
307 cmd |= MI_INVALIDATE_TLB;
308 if (rq->engine->class == VIDEO_DECODE_CLASS)
309 cmd |= MI_INVALIDATE_BSD;
310 }
311
312 *cs++ = cmd;
313 *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
314 *cs++ = 0; /* upper addr */
315 *cs++ = 0; /* value */
316
317 if (aux_inv) { /* hsdes: 1809175790 */
318 if (rq->engine->class == VIDEO_DECODE_CLASS)
319 cs = gen12_emit_aux_table_inv(rq->engine->gt,
320 cs, GEN12_VD0_AUX_NV);
321 else
322 cs = gen12_emit_aux_table_inv(rq->engine->gt,
323 cs, GEN12_VE0_AUX_NV);
324 }
325
326 if (mode & EMIT_INVALIDATE)
327 *cs++ = preparser_disable(false);
328
329 intel_ring_advance(rq, cs);
330
331 return 0;
332}
333
334static u32 preempt_address(struct intel_engine_cs *engine)
335{
336 return (i915_ggtt_offset(engine->status_page.vma) +
337 I915_GEM_HWS_PREEMPT_ADDR);
338}
339
340static u32 hwsp_offset(const struct i915_request *rq)
341{
342 const struct intel_timeline *tl;
343
344 /* Before the request is executed, the timeline is fixed */
345 tl = rcu_dereference_protected(rq->timeline,
346 !i915_request_signaled(rq));
347
348 /* See the comment in i915_request_active_seqno(). */
349 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno);
350}
351
352int gen8_emit_init_breadcrumb(struct i915_request *rq)
353{
354 u32 *cs;
355
356 GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq));
357 if (!i915_request_timeline(rq)->has_initial_breadcrumb)
358 return 0;
359
360 cs = intel_ring_begin(rq, 6);
361 if (IS_ERR(cs))
362 return PTR_ERR(cs);
363
364 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
365 *cs++ = hwsp_offset(rq);
366 *cs++ = 0;
367 *cs++ = rq->fence.seqno - 1;
368
369 /*
370 * Check if we have been preempted before we even get started.
371 *
372 * After this point i915_request_started() reports true, even if
373 * we get preempted and so are no longer running.
374 *
375 * i915_request_started() is used during preemption processing
376 * to decide if the request is currently inside the user payload
377 * or spinning on a kernel semaphore (or earlier). For no-preemption
378 * requests, we do allow preemption on the semaphore before the user
379 * payload, but do not allow preemption once the request is started.
380 *
381 * i915_request_started() is similarly used during GPU hangs to
382 * determine if the user's payload was guilty, and if so, the
383 * request is banned. Before the request is started, it is assumed
384 * to be unharmed and an innocent victim of another's hang.
385 */
386 *cs++ = MI_NOOP;
387 *cs++ = MI_ARB_CHECK;
388
389 intel_ring_advance(rq, cs);
390
391 /* Record the updated position of the request's payload */
392 rq->infix = intel_ring_offset(rq, cs);
393
394 __set_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags);
395
396 return 0;
397}
398
399static int __xehp_emit_bb_start(struct i915_request *rq,
400 u64 offset, u32 len,
401 const unsigned int flags,
402 u32 arb)
403{
404 struct intel_context *ce = rq->context;
405 u32 wa_offset = lrc_indirect_bb(ce);
406 u32 *cs;
407
408 GEM_BUG_ON(!ce->wa_bb_page);
409
410 cs = intel_ring_begin(rq, 12);
411 if (IS_ERR(cs))
412 return PTR_ERR(cs);
413
414 *cs++ = MI_ARB_ON_OFF | arb;
415
416 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 |
417 MI_SRM_LRM_GLOBAL_GTT |
418 MI_LRI_LRM_CS_MMIO;
419 *cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0));
420 *cs++ = wa_offset + DG2_PREDICATE_RESULT_WA;
421 *cs++ = 0;
422
423 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
424 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
425 *cs++ = lower_32_bits(offset);
426 *cs++ = upper_32_bits(offset);
427
428 /* Fixup stray MI_SET_PREDICATE as it prevents us executing the ring */
429 *cs++ = MI_BATCH_BUFFER_START_GEN8;
430 *cs++ = wa_offset + DG2_PREDICATE_RESULT_BB;
431 *cs++ = 0;
432
433 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
434
435 intel_ring_advance(rq, cs);
436
437 return 0;
438}
439
440int xehp_emit_bb_start_noarb(struct i915_request *rq,
441 u64 offset, u32 len,
442 const unsigned int flags)
443{
444 return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_DISABLE);
445}
446
447int xehp_emit_bb_start(struct i915_request *rq,
448 u64 offset, u32 len,
449 const unsigned int flags)
450{
451 return __xehp_emit_bb_start(rq, offset, len, flags, MI_ARB_ENABLE);
452}
453
454int gen8_emit_bb_start_noarb(struct i915_request *rq,
455 u64 offset, u32 len,
456 const unsigned int flags)
457{
458 u32 *cs;
459
460 cs = intel_ring_begin(rq, 4);
461 if (IS_ERR(cs))
462 return PTR_ERR(cs);
463
464 /*
465 * WaDisableCtxRestoreArbitration:bdw,chv
466 *
467 * We don't need to perform MI_ARB_ENABLE as often as we do (in
468 * particular all the gen that do not need the w/a at all!), if we
469 * took care to make sure that on every switch into this context
470 * (both ordinary and for preemption) that arbitrartion was enabled
471 * we would be fine. However, for gen8 there is another w/a that
472 * requires us to not preempt inside GPGPU execution, so we keep
473 * arbitration disabled for gen8 batches. Arbitration will be
474 * re-enabled before we close the request
475 * (engine->emit_fini_breadcrumb).
476 */
477 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
478
479 /* FIXME(BDW+): Address space and security selectors. */
480 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
481 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
482 *cs++ = lower_32_bits(offset);
483 *cs++ = upper_32_bits(offset);
484
485 intel_ring_advance(rq, cs);
486
487 return 0;
488}
489
490int gen8_emit_bb_start(struct i915_request *rq,
491 u64 offset, u32 len,
492 const unsigned int flags)
493{
494 u32 *cs;
495
496 if (unlikely(i915_request_has_nopreempt(rq)))
497 return gen8_emit_bb_start_noarb(rq, offset, len, flags);
498
499 cs = intel_ring_begin(rq, 6);
500 if (IS_ERR(cs))
501 return PTR_ERR(cs);
502
503 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
504
505 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
506 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
507 *cs++ = lower_32_bits(offset);
508 *cs++ = upper_32_bits(offset);
509
510 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
511 *cs++ = MI_NOOP;
512
513 intel_ring_advance(rq, cs);
514
515 return 0;
516}
517
518static void assert_request_valid(struct i915_request *rq)
519{
520 struct intel_ring *ring __maybe_unused = rq->ring;
521
522 /* Can we unwind this request without appearing to go forwards? */
523 GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0);
524}
525
526/*
527 * Reserve space for 2 NOOPs at the end of each request to be
528 * used as a workaround for not being allowed to do lite
529 * restore with HEAD==TAIL (WaIdleLiteRestore).
530 */
531static u32 *gen8_emit_wa_tail(struct i915_request *rq, u32 *cs)
532{
533 /* Ensure there's always at least one preemption point per-request. */
534 *cs++ = MI_ARB_CHECK;
535 *cs++ = MI_NOOP;
536 rq->wa_tail = intel_ring_offset(rq, cs);
537
538 /* Check that entire request is less than half the ring */
539 assert_request_valid(rq);
540
541 return cs;
542}
543
544static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs)
545{
546 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */
547 *cs++ = MI_SEMAPHORE_WAIT |
548 MI_SEMAPHORE_GLOBAL_GTT |
549 MI_SEMAPHORE_POLL |
550 MI_SEMAPHORE_SAD_EQ_SDD;
551 *cs++ = 0;
552 *cs++ = preempt_address(rq->engine);
553 *cs++ = 0;
554 *cs++ = MI_NOOP;
555
556 return cs;
557}
558
559static __always_inline u32*
560gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
561{
562 *cs++ = MI_USER_INTERRUPT;
563
564 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
565 if (intel_engine_has_semaphores(rq->engine) &&
566 !intel_uc_uses_guc_submission(&rq->engine->gt->uc))
567 cs = emit_preempt_busywait(rq, cs);
568
569 rq->tail = intel_ring_offset(rq, cs);
570 assert_ring_tail_valid(rq->ring, rq->tail);
571
572 return gen8_emit_wa_tail(rq, cs);
573}
574
575static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
576{
577 return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
578}
579
580u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
581{
582 return gen8_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
583}
584
585u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
586{
587 cs = gen8_emit_pipe_control(cs,
588 PIPE_CONTROL_CS_STALL |
589 PIPE_CONTROL_TLB_INVALIDATE |
590 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
591 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
592 PIPE_CONTROL_DC_FLUSH_ENABLE,
593 0);
594
595 /* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
596 cs = gen8_emit_ggtt_write_rcs(cs,
597 rq->fence.seqno,
598 hwsp_offset(rq),
599 PIPE_CONTROL_FLUSH_ENABLE |
600 PIPE_CONTROL_CS_STALL);
601
602 return gen8_emit_fini_breadcrumb_tail(rq, cs);
603}
604
605u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
606{
607 cs = gen8_emit_pipe_control(cs,
608 PIPE_CONTROL_CS_STALL |
609 PIPE_CONTROL_TLB_INVALIDATE |
610 PIPE_CONTROL_TILE_CACHE_FLUSH |
611 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
612 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
613 PIPE_CONTROL_DC_FLUSH_ENABLE,
614 0);
615
616 /*XXX: Look at gen8_emit_fini_breadcrumb_rcs */
617 cs = gen8_emit_ggtt_write_rcs(cs,
618 rq->fence.seqno,
619 hwsp_offset(rq),
620 PIPE_CONTROL_FLUSH_ENABLE |
621 PIPE_CONTROL_CS_STALL);
622
623 return gen8_emit_fini_breadcrumb_tail(rq, cs);
624}
625
626/*
627 * Note that the CS instruction pre-parser will not stall on the breadcrumb
628 * flush and will continue pre-fetching the instructions after it before the
629 * memory sync is completed. On pre-gen12 HW, the pre-parser will stop at
630 * BB_START/END instructions, so, even though we might pre-fetch the pre-amble
631 * of the next request before the memory has been flushed, we're guaranteed that
632 * we won't access the batch itself too early.
633 * However, on gen12+ the parser can pre-fetch across the BB_START/END commands,
634 * so, if the current request is modifying an instruction in the next request on
635 * the same intel_context, we might pre-fetch and then execute the pre-update
636 * instruction. To avoid this, the users of self-modifying code should either
637 * disable the parser around the code emitting the memory writes, via a new flag
638 * added to MI_ARB_CHECK, or emit the writes from a different intel_context. For
639 * the in-kernel use-cases we've opted to use a separate context, see
640 * reloc_gpu() as an example.
641 * All the above applies only to the instructions themselves. Non-inline data
642 * used by the instructions is not pre-fetched.
643 */
644
645static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)
646{
647 *cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */
648 *cs++ = MI_SEMAPHORE_WAIT_TOKEN |
649 MI_SEMAPHORE_GLOBAL_GTT |
650 MI_SEMAPHORE_POLL |
651 MI_SEMAPHORE_SAD_EQ_SDD;
652 *cs++ = 0;
653 *cs++ = preempt_address(rq->engine);
654 *cs++ = 0;
655 *cs++ = 0;
656
657 return cs;
658}
659
660/* Wa_14014475959:dg2 */
661#define CCS_SEMAPHORE_PPHWSP_OFFSET 0x540
662static u32 ccs_semaphore_offset(struct i915_request *rq)
663{
664 return i915_ggtt_offset(rq->context->state) +
665 (LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET;
666}
667
668/* Wa_14014475959:dg2 */
669static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)
670{
671 int i;
672
673 *cs++ = MI_ATOMIC_INLINE | MI_ATOMIC_GLOBAL_GTT | MI_ATOMIC_CS_STALL |
674 MI_ATOMIC_MOVE;
675 *cs++ = ccs_semaphore_offset(rq);
676 *cs++ = 0;
677 *cs++ = 1;
678
679 /*
680 * When MI_ATOMIC_INLINE_DATA set this command must be 11 DW + (1 NOP)
681 * to align. 4 DWs above + 8 filler DWs here.
682 */
683 for (i = 0; i < 8; ++i)
684 *cs++ = 0;
685
686 *cs++ = MI_SEMAPHORE_WAIT |
687 MI_SEMAPHORE_GLOBAL_GTT |
688 MI_SEMAPHORE_POLL |
689 MI_SEMAPHORE_SAD_EQ_SDD;
690 *cs++ = 0;
691 *cs++ = ccs_semaphore_offset(rq);
692 *cs++ = 0;
693
694 return cs;
695}
696
697static __always_inline u32*
698gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
699{
700 *cs++ = MI_USER_INTERRUPT;
701
702 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
703 if (intel_engine_has_semaphores(rq->engine) &&
704 !intel_uc_uses_guc_submission(&rq->engine->gt->uc))
705 cs = gen12_emit_preempt_busywait(rq, cs);
706
707 /* Wa_14014475959:dg2 */
708 if (intel_engine_uses_wa_hold_ccs_switchout(rq->engine))
709 cs = ccs_emit_wa_busywait(rq, cs);
710
711 rq->tail = intel_ring_offset(rq, cs);
712 assert_ring_tail_valid(rq->ring, rq->tail);
713
714 return gen8_emit_wa_tail(rq, cs);
715}
716
717u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
718{
719 /* XXX Stalling flush before seqno write; post-sync not */
720 cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
721 return gen12_emit_fini_breadcrumb_tail(rq, cs);
722}
723
724u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
725{
726 struct drm_i915_private *i915 = rq->engine->i915;
727 u32 flags = (PIPE_CONTROL_CS_STALL |
728 PIPE_CONTROL_TLB_INVALIDATE |
729 PIPE_CONTROL_TILE_CACHE_FLUSH |
730 PIPE_CONTROL_FLUSH_L3 |
731 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
732 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
733 PIPE_CONTROL_DC_FLUSH_ENABLE |
734 PIPE_CONTROL_FLUSH_ENABLE);
735
736 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
737 /* Wa_1409600907 */
738 flags |= PIPE_CONTROL_DEPTH_STALL;
739
740 if (!HAS_3D_PIPELINE(rq->engine->i915))
741 flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
742 else if (rq->engine->class == COMPUTE_CLASS)
743 flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
744
745 cs = gen12_emit_pipe_control(cs, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0);
746
747 /*XXX: Look at gen8_emit_fini_breadcrumb_rcs */
748 cs = gen12_emit_ggtt_write_rcs(cs,
749 rq->fence.seqno,
750 hwsp_offset(rq),
751 0,
752 PIPE_CONTROL_FLUSH_ENABLE |
753 PIPE_CONTROL_CS_STALL);
754
755 return gen12_emit_fini_breadcrumb_tail(rq, cs);
756}