1/*
  2 * SPDX-License-Identifier: MIT
  3 *
  4 * Copyright 2012 Red Hat Inc
  5 */
  6
  7#include <linux/dma-buf.h>
  8#include <linux/highmem.h>
  9#include <linux/dma-resv.h>
 10#include <linux/module.h>
 11
 12#include <asm/smp.h>
 13
 14#include "gem/i915_gem_dmabuf.h"
 15#include "i915_drv.h"
 16#include "i915_gem_object.h"
 17#include "i915_scatterlist.h"
 18
 19MODULE_IMPORT_NS(DMA_BUF);
 20
 21I915_SELFTEST_DECLARE(static bool force_different_devices;)
 22
 23static struct drm_i915_gem_object *dma_buf_to_obj(struct dma_buf *buf)
 24{
 25	return to_intel_bo(buf->priv);
 26}
 27
 28static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attach,
 29					     enum dma_data_direction dir)
 30{
 31	struct drm_i915_gem_object *obj = dma_buf_to_obj(attach->dmabuf);
 32	struct sg_table *sgt;
 33	struct scatterlist *src, *dst;
 34	int ret, i;
 35
 36	/*
 37	 * Make a copy of the object's sgt, so that we can make an independent
 38	 * mapping
 39	 */
 40	sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
 41	if (!sgt) {
 42		ret = -ENOMEM;
 43		goto err;
 44	}
 45
 46	ret = sg_alloc_table(sgt, obj->mm.pages->orig_nents, GFP_KERNEL);
 47	if (ret)
 48		goto err_free;
 49
 50	dst = sgt->sgl;
 51	for_each_sg(obj->mm.pages->sgl, src, obj->mm.pages->orig_nents, i) {
 52		sg_set_page(dst, sg_page(src), src->length, 0);
 53		dst = sg_next(dst);
 54	}
 55
 56	ret = dma_map_sgtable(attach->dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC);
 57	if (ret)
 58		goto err_free_sg;
 59
 60	return sgt;
 61
 62err_free_sg:
 63	sg_free_table(sgt);
 64err_free:
 65	kfree(sgt);
 66err:
 67	return ERR_PTR(ret);
 68}
 69
 70static int i915_gem_dmabuf_vmap(struct dma_buf *dma_buf,
 71				struct iosys_map *map)
 72{
 73	struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
 74	void *vaddr;
 75
 76	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
 77	if (IS_ERR(vaddr))
 78		return PTR_ERR(vaddr);
 79
 80	iosys_map_set_vaddr(map, vaddr);
 81
 82	return 0;
 83}
 84
 85static void i915_gem_dmabuf_vunmap(struct dma_buf *dma_buf,
 86				   struct iosys_map *map)
 87{
 88	struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
 89
 90	i915_gem_object_flush_map(obj);
 91	i915_gem_object_unpin_map(obj);
 92}
 93
 94static int i915_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
 95{
 96	struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
 97	struct drm_i915_private *i915 = to_i915(obj->base.dev);
 98	int ret;
 99
100	dma_resv_assert_held(dma_buf->resv);
101
102	if (obj->base.size < vma->vm_end - vma->vm_start)
103		return -EINVAL;
104
105	if (HAS_LMEM(i915))
106		return drm_gem_prime_mmap(&obj->base, vma);
107
108	if (!obj->base.filp)
109		return -ENODEV;
110
111	ret = call_mmap(obj->base.filp, vma);
112	if (ret)
113		return ret;
114
115	vma_set_file(vma, obj->base.filp);
116
117	return 0;
118}
119
120static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)
121{
122	struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
123	bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE);
124	struct i915_gem_ww_ctx ww;
125	int err;
126
127	i915_gem_ww_ctx_init(&ww, true);
128retry:
129	err = i915_gem_object_lock(obj, &ww);
130	if (!err)
131		err = i915_gem_object_pin_pages(obj);
132	if (!err) {
133		err = i915_gem_object_set_to_cpu_domain(obj, write);
134		i915_gem_object_unpin_pages(obj);
135	}
136	if (err == -EDEADLK) {
137		err = i915_gem_ww_ctx_backoff(&ww);
138		if (!err)
139			goto retry;
140	}
141	i915_gem_ww_ctx_fini(&ww);
142	return err;
143}
144
145static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direction direction)
146{
147	struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf);
148	struct i915_gem_ww_ctx ww;
149	int err;
150
151	i915_gem_ww_ctx_init(&ww, true);
152retry:
153	err = i915_gem_object_lock(obj, &ww);
154	if (!err)
155		err = i915_gem_object_pin_pages(obj);
156	if (!err) {
157		err = i915_gem_object_set_to_gtt_domain(obj, false);
158		i915_gem_object_unpin_pages(obj);
159	}
160	if (err == -EDEADLK) {
161		err = i915_gem_ww_ctx_backoff(&ww);
162		if (!err)
163			goto retry;
164	}
165	i915_gem_ww_ctx_fini(&ww);
166	return err;
167}
168
169static int i915_gem_dmabuf_attach(struct dma_buf *dmabuf,
170				  struct dma_buf_attachment *attach)
171{
172	struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf);
173	struct i915_gem_ww_ctx ww;
174	int err;
175
176	if (!i915_gem_object_can_migrate(obj, INTEL_REGION_SMEM))
177		return -EOPNOTSUPP;
178
179	for_i915_gem_ww(&ww, err, true) {
180		err = i915_gem_object_lock(obj, &ww);
181		if (err)
182			continue;
183
184		err = i915_gem_object_migrate(obj, &ww, INTEL_REGION_SMEM);
185		if (err)
186			continue;
187
188		err = i915_gem_object_wait_migration(obj, 0);
189		if (err)
190			continue;
191
192		err = i915_gem_object_pin_pages(obj);
193	}
194
195	return err;
196}
197
198static void i915_gem_dmabuf_detach(struct dma_buf *dmabuf,
199				   struct dma_buf_attachment *attach)
200{
201	struct drm_i915_gem_object *obj = dma_buf_to_obj(dmabuf);
202
203	i915_gem_object_unpin_pages(obj);
204}
205
206static const struct dma_buf_ops i915_dmabuf_ops =  {
207	.attach = i915_gem_dmabuf_attach,
208	.detach = i915_gem_dmabuf_detach,
209	.map_dma_buf = i915_gem_map_dma_buf,
210	.unmap_dma_buf = drm_gem_unmap_dma_buf,
211	.release = drm_gem_dmabuf_release,
212	.mmap = i915_gem_dmabuf_mmap,
213	.vmap = i915_gem_dmabuf_vmap,
214	.vunmap = i915_gem_dmabuf_vunmap,
215	.begin_cpu_access = i915_gem_begin_cpu_access,
216	.end_cpu_access = i915_gem_end_cpu_access,
217};
218
219struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags)
220{
221	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
222	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
223
224	exp_info.ops = &i915_dmabuf_ops;
225	exp_info.size = gem_obj->size;
226	exp_info.flags = flags;
227	exp_info.priv = gem_obj;
228	exp_info.resv = obj->base.resv;
229
230	if (obj->ops->dmabuf_export) {
231		int ret = obj->ops->dmabuf_export(obj);
232		if (ret)
233			return ERR_PTR(ret);
234	}
235
236	return drm_gem_dmabuf_export(gem_obj->dev, &exp_info);
237}
238
239static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
240{
241	struct drm_i915_private *i915 = to_i915(obj->base.dev);
242	struct sg_table *sgt;
243
244	assert_object_held(obj);
245
246	sgt = dma_buf_map_attachment(obj->base.import_attach,
247				     DMA_BIDIRECTIONAL);
248	if (IS_ERR(sgt))
249		return PTR_ERR(sgt);
250
251	/*
252	 * DG1 is special here since it still snoops transactions even with
253	 * CACHE_NONE. This is not the case with other HAS_SNOOP platforms. We
254	 * might need to revisit this as we add new discrete platforms.
255	 *
256	 * XXX: Consider doing a vmap flush or something, where possible.
257	 * Currently we just do a heavy handed wbinvd_on_all_cpus() here since
258	 * the underlying sg_table might not even point to struct pages, so we
259	 * can't just call drm_clflush_sg or similar, like we do elsewhere in
260	 * the driver.
261	 */
262	if (i915_gem_object_can_bypass_llc(obj) ||
263	    (!HAS_LLC(i915) && !IS_DG1(i915)))
264		wbinvd_on_all_cpus();
265
266	__i915_gem_object_set_pages(obj, sgt);
267
268	return 0;
269}
270
271static void i915_gem_object_put_pages_dmabuf(struct drm_i915_gem_object *obj,
272					     struct sg_table *sgt)
273{
274	dma_buf_unmap_attachment(obj->base.import_attach, sgt,
275				 DMA_BIDIRECTIONAL);
276}
277
278static const struct drm_i915_gem_object_ops i915_gem_object_dmabuf_ops = {
279	.name = "i915_gem_object_dmabuf",
280	.get_pages = i915_gem_object_get_pages_dmabuf,
281	.put_pages = i915_gem_object_put_pages_dmabuf,
282};
283
284struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
285					     struct dma_buf *dma_buf)
286{
287	static struct lock_class_key lock_class;
288	struct dma_buf_attachment *attach;
289	struct drm_i915_gem_object *obj;
290	int ret;
291
292	/* is this one of own objects? */
293	if (dma_buf->ops == &i915_dmabuf_ops) {
294		obj = dma_buf_to_obj(dma_buf);
295		/* is it from our device? */
296		if (obj->base.dev == dev &&
297		    !I915_SELFTEST_ONLY(force_different_devices)) {
298			/*
299			 * Importing dmabuf exported from out own gem increases
300			 * refcount on gem itself instead of f_count of dmabuf.
301			 */
302			return &i915_gem_object_get(obj)->base;
303		}
304	}
305
306	if (i915_gem_object_size_2big(dma_buf->size))
307		return ERR_PTR(-E2BIG);
308
309	/* need to attach */
310	attach = dma_buf_attach(dma_buf, dev->dev);
311	if (IS_ERR(attach))
312		return ERR_CAST(attach);
313
314	get_dma_buf(dma_buf);
315
316	obj = i915_gem_object_alloc();
317	if (!obj) {
318		ret = -ENOMEM;
319		goto fail_detach;
320	}
321
322	drm_gem_private_object_init(dev, &obj->base, dma_buf->size);
323	i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops, &lock_class,
324			     I915_BO_ALLOC_USER);
325	obj->base.import_attach = attach;
326	obj->base.resv = dma_buf->resv;
327
328	/* We use GTT as shorthand for a coherent domain, one that is
329	 * neither in the GPU cache nor in the CPU cache, where all
330	 * writes are immediately visible in memory. (That's not strictly
331	 * true, but it's close! There are internal buffers such as the
332	 * write-combined buffer or a delay through the chipset for GTT
333	 * writes that do require us to treat GTT as a separate cache domain.)
334	 */
335	obj->read_domains = I915_GEM_DOMAIN_GTT;
336	obj->write_domain = 0;
337
338	return &obj->base;
339
340fail_detach:
341	dma_buf_detach(dma_buf, attach);
342	dma_buf_put(dma_buf);
343
344	return ERR_PTR(ret);
345}
346
347#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
348#include "selftests/mock_dmabuf.c"
349#include "selftests/i915_gem_dmabuf.c"
350#endif