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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <linux/slab.h>
27
28#include <drm/drm_atomic_helper.h>
29#include <drm/drm_crtc.h>
30#include <drm/drm_edid.h>
31#include <drm/drm_mipi_dsi.h>
32
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_atomic.h"
36#include "intel_backlight.h"
37#include "intel_connector.h"
38#include "intel_crtc.h"
39#include "intel_de.h"
40#include "intel_display_types.h"
41#include "intel_dsi.h"
42#include "intel_dsi_vbt.h"
43#include "intel_fifo_underrun.h"
44#include "intel_panel.h"
45#include "skl_scaler.h"
46#include "vlv_dsi.h"
47#include "vlv_dsi_pll.h"
48#include "vlv_dsi_regs.h"
49#include "vlv_sideband.h"
50
51/* return pixels in terms of txbyteclkhs */
52static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
53 u16 burst_mode_ratio)
54{
55 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
56 8 * 100), lane_count);
57}
58
59/* return pixels equvalent to txbyteclkhs */
60static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
61 u16 burst_mode_ratio)
62{
63 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
64 (bpp * burst_mode_ratio));
65}
66
67enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
68{
69 /* It just so happens the VBT matches register contents. */
70 switch (fmt) {
71 case VID_MODE_FORMAT_RGB888:
72 return MIPI_DSI_FMT_RGB888;
73 case VID_MODE_FORMAT_RGB666:
74 return MIPI_DSI_FMT_RGB666;
75 case VID_MODE_FORMAT_RGB666_PACKED:
76 return MIPI_DSI_FMT_RGB666_PACKED;
77 case VID_MODE_FORMAT_RGB565:
78 return MIPI_DSI_FMT_RGB565;
79 default:
80 MISSING_CASE(fmt);
81 return MIPI_DSI_FMT_RGB666;
82 }
83}
84
85void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
86{
87 struct drm_encoder *encoder = &intel_dsi->base.base;
88 struct drm_device *dev = encoder->dev;
89 struct drm_i915_private *dev_priv = to_i915(dev);
90 u32 mask;
91
92 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
93 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
94
95 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
96 mask, 100))
97 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
98}
99
100static void write_data(struct drm_i915_private *dev_priv,
101 i915_reg_t reg,
102 const u8 *data, u32 len)
103{
104 u32 i, j;
105
106 for (i = 0; i < len; i += 4) {
107 u32 val = 0;
108
109 for (j = 0; j < min_t(u32, len - i, 4); j++)
110 val |= *data++ << 8 * j;
111
112 intel_de_write(dev_priv, reg, val);
113 }
114}
115
116static void read_data(struct drm_i915_private *dev_priv,
117 i915_reg_t reg,
118 u8 *data, u32 len)
119{
120 u32 i, j;
121
122 for (i = 0; i < len; i += 4) {
123 u32 val = intel_de_read(dev_priv, reg);
124
125 for (j = 0; j < min_t(u32, len - i, 4); j++)
126 *data++ = val >> 8 * j;
127 }
128}
129
130static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
131 const struct mipi_dsi_msg *msg)
132{
133 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
134 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
135 struct drm_i915_private *dev_priv = to_i915(dev);
136 enum port port = intel_dsi_host->port;
137 struct mipi_dsi_packet packet;
138 ssize_t ret;
139 const u8 *header, *data;
140 i915_reg_t data_reg, ctrl_reg;
141 u32 data_mask, ctrl_mask;
142
143 ret = mipi_dsi_create_packet(&packet, msg);
144 if (ret < 0)
145 return ret;
146
147 header = packet.header;
148 data = packet.payload;
149
150 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
151 data_reg = MIPI_LP_GEN_DATA(port);
152 data_mask = LP_DATA_FIFO_FULL;
153 ctrl_reg = MIPI_LP_GEN_CTRL(port);
154 ctrl_mask = LP_CTRL_FIFO_FULL;
155 } else {
156 data_reg = MIPI_HS_GEN_DATA(port);
157 data_mask = HS_DATA_FIFO_FULL;
158 ctrl_reg = MIPI_HS_GEN_CTRL(port);
159 ctrl_mask = HS_CTRL_FIFO_FULL;
160 }
161
162 /* note: this is never true for reads */
163 if (packet.payload_length) {
164 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
165 data_mask, 50))
166 drm_err(&dev_priv->drm,
167 "Timeout waiting for HS/LP DATA FIFO !full\n");
168
169 write_data(dev_priv, data_reg, packet.payload,
170 packet.payload_length);
171 }
172
173 if (msg->rx_len) {
174 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
175 GEN_READ_DATA_AVAIL);
176 }
177
178 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
179 ctrl_mask, 50)) {
180 drm_err(&dev_priv->drm,
181 "Timeout waiting for HS/LP CTRL FIFO !full\n");
182 }
183
184 intel_de_write(dev_priv, ctrl_reg,
185 header[2] << 16 | header[1] << 8 | header[0]);
186
187 /* ->rx_len is set only for reads */
188 if (msg->rx_len) {
189 data_mask = GEN_READ_DATA_AVAIL;
190 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
191 data_mask, 50))
192 drm_err(&dev_priv->drm,
193 "Timeout waiting for read data.\n");
194
195 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
196 }
197
198 /* XXX: fix for reads and writes */
199 return 4 + packet.payload_length;
200}
201
202static int intel_dsi_host_attach(struct mipi_dsi_host *host,
203 struct mipi_dsi_device *dsi)
204{
205 return 0;
206}
207
208static int intel_dsi_host_detach(struct mipi_dsi_host *host,
209 struct mipi_dsi_device *dsi)
210{
211 return 0;
212}
213
214static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
215 .attach = intel_dsi_host_attach,
216 .detach = intel_dsi_host_detach,
217 .transfer = intel_dsi_host_transfer,
218};
219
220/*
221 * send a video mode command
222 *
223 * XXX: commands with data in MIPI_DPI_DATA?
224 */
225static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
226 enum port port)
227{
228 struct drm_encoder *encoder = &intel_dsi->base.base;
229 struct drm_device *dev = encoder->dev;
230 struct drm_i915_private *dev_priv = to_i915(dev);
231 u32 mask;
232
233 /* XXX: pipe, hs */
234 if (hs)
235 cmd &= ~DPI_LP_MODE;
236 else
237 cmd |= DPI_LP_MODE;
238
239 /* clear bit */
240 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
241
242 /* XXX: old code skips write if control unchanged */
243 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
244 drm_dbg_kms(&dev_priv->drm,
245 "Same special packet %02x twice in a row.\n", cmd);
246
247 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
248
249 mask = SPL_PKT_SENT_INTERRUPT;
250 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
251 drm_err(&dev_priv->drm,
252 "Video mode command 0x%08x send failed.\n", cmd);
253
254 return 0;
255}
256
257static void band_gap_reset(struct drm_i915_private *dev_priv)
258{
259 vlv_flisdsi_get(dev_priv);
260
261 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
263 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
264 udelay(150);
265 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
266 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
267
268 vlv_flisdsi_put(dev_priv);
269}
270
271static int intel_dsi_compute_config(struct intel_encoder *encoder,
272 struct intel_crtc_state *pipe_config,
273 struct drm_connector_state *conn_state)
274{
275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
276 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
277 base);
278 struct intel_connector *intel_connector = intel_dsi->attached_connector;
279 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
280 int ret;
281
282 drm_dbg_kms(&dev_priv->drm, "\n");
283 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
284
285 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
286 if (ret)
287 return ret;
288
289 ret = intel_panel_fitting(pipe_config, conn_state);
290 if (ret)
291 return ret;
292
293 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
294 return -EINVAL;
295
296 /* DSI uses short packets for sync events, so clear mode flags for DSI */
297 adjusted_mode->flags = 0;
298
299 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
300 pipe_config->pipe_bpp = 24;
301 else
302 pipe_config->pipe_bpp = 18;
303
304 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
305 /* Enable Frame time stamp based scanline reporting */
306 pipe_config->mode_flags |=
307 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
308
309 /* Dual link goes to DSI transcoder A. */
310 if (intel_dsi->ports == BIT(PORT_C))
311 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
312 else
313 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
314
315 ret = bxt_dsi_pll_compute(encoder, pipe_config);
316 if (ret)
317 return -EINVAL;
318 } else {
319 ret = vlv_dsi_pll_compute(encoder, pipe_config);
320 if (ret)
321 return -EINVAL;
322 }
323
324 pipe_config->clock_set = true;
325
326 return 0;
327}
328
329static bool glk_dsi_enable_io(struct intel_encoder *encoder)
330{
331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
332 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
333 enum port port;
334 u32 tmp;
335 bool cold_boot = false;
336
337 /* Set the MIPI mode
338 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
339 * Power ON MIPI IO first and then write into IO reset and LP wake bits
340 */
341 for_each_dsi_port(port, intel_dsi->ports) {
342 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
343 intel_de_write(dev_priv, MIPI_CTRL(port),
344 tmp | GLK_MIPIIO_ENABLE);
345 }
346
347 /* Put the IO into reset */
348 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
349 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
350 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
351
352 /* Program LP Wake */
353 for_each_dsi_port(port, intel_dsi->ports) {
354 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
355 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
356 tmp &= ~GLK_LP_WAKE;
357 else
358 tmp |= GLK_LP_WAKE;
359 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
360 }
361
362 /* Wait for Pwr ACK */
363 for_each_dsi_port(port, intel_dsi->ports) {
364 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
365 GLK_MIPIIO_PORT_POWERED, 20))
366 drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
367 }
368
369 /* Check for cold boot scenario */
370 for_each_dsi_port(port, intel_dsi->ports) {
371 cold_boot |=
372 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
373 }
374
375 return cold_boot;
376}
377
378static void glk_dsi_device_ready(struct intel_encoder *encoder)
379{
380 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
381 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
382 enum port port;
383 u32 val;
384
385 /* Wait for MIPI PHY status bit to set */
386 for_each_dsi_port(port, intel_dsi->ports) {
387 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
388 GLK_PHY_STATUS_PORT_READY, 20))
389 drm_err(&dev_priv->drm, "PHY is not ON\n");
390 }
391
392 /* Get IO out of reset */
393 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
394 intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
395 val | GLK_MIPIIO_RESET_RELEASED);
396
397 /* Get IO out of Low power state*/
398 for_each_dsi_port(port, intel_dsi->ports) {
399 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
400 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
401 val &= ~ULPS_STATE_MASK;
402 val |= DEVICE_READY;
403 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
404 usleep_range(10, 15);
405 } else {
406 /* Enter ULPS */
407 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
408 val &= ~ULPS_STATE_MASK;
409 val |= (ULPS_STATE_ENTER | DEVICE_READY);
410 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
411
412 /* Wait for ULPS active */
413 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
414 GLK_ULPS_NOT_ACTIVE, 20))
415 drm_err(&dev_priv->drm, "ULPS not active\n");
416
417 /* Exit ULPS */
418 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
419 val &= ~ULPS_STATE_MASK;
420 val |= (ULPS_STATE_EXIT | DEVICE_READY);
421 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
422
423 /* Enter Normal Mode */
424 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
425 val &= ~ULPS_STATE_MASK;
426 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
427 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
428
429 val = intel_de_read(dev_priv, MIPI_CTRL(port));
430 val &= ~GLK_LP_WAKE;
431 intel_de_write(dev_priv, MIPI_CTRL(port), val);
432 }
433 }
434
435 /* Wait for Stop state */
436 for_each_dsi_port(port, intel_dsi->ports) {
437 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
438 GLK_DATA_LANE_STOP_STATE, 20))
439 drm_err(&dev_priv->drm,
440 "Date lane not in STOP state\n");
441 }
442
443 /* Wait for AFE LATCH */
444 for_each_dsi_port(port, intel_dsi->ports) {
445 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
446 AFE_LATCHOUT, 20))
447 drm_err(&dev_priv->drm,
448 "D-PHY not entering LP-11 state\n");
449 }
450}
451
452static void bxt_dsi_device_ready(struct intel_encoder *encoder)
453{
454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
455 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
456 enum port port;
457 u32 val;
458
459 drm_dbg_kms(&dev_priv->drm, "\n");
460
461 /* Enable MIPI PHY transparent latch */
462 for_each_dsi_port(port, intel_dsi->ports) {
463 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
464 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port),
465 val | LP_OUTPUT_HOLD);
466 usleep_range(2000, 2500);
467 }
468
469 /* Clear ULPS and set device ready */
470 for_each_dsi_port(port, intel_dsi->ports) {
471 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
472 val &= ~ULPS_STATE_MASK;
473 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
474 usleep_range(2000, 2500);
475 val |= DEVICE_READY;
476 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
477 }
478}
479
480static void vlv_dsi_device_ready(struct intel_encoder *encoder)
481{
482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
483 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
484 enum port port;
485 u32 val;
486
487 drm_dbg_kms(&dev_priv->drm, "\n");
488
489 vlv_flisdsi_get(dev_priv);
490 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
491 * needed everytime after power gate */
492 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
493 vlv_flisdsi_put(dev_priv);
494
495 /* bandgap reset is needed after everytime we do power gate */
496 band_gap_reset(dev_priv);
497
498 for_each_dsi_port(port, intel_dsi->ports) {
499
500 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
501 ULPS_STATE_ENTER);
502 usleep_range(2500, 3000);
503
504 /* Enable MIPI PHY transparent latch
505 * Common bit for both MIPI Port A & MIPI Port C
506 * No similar bit in MIPI Port C reg
507 */
508 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A));
509 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A),
510 val | LP_OUTPUT_HOLD);
511 usleep_range(1000, 1500);
512
513 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
514 ULPS_STATE_EXIT);
515 usleep_range(2500, 3000);
516
517 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
518 DEVICE_READY);
519 usleep_range(2500, 3000);
520 }
521}
522
523static void intel_dsi_device_ready(struct intel_encoder *encoder)
524{
525 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
526
527 if (IS_GEMINILAKE(dev_priv))
528 glk_dsi_device_ready(encoder);
529 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
530 bxt_dsi_device_ready(encoder);
531 else
532 vlv_dsi_device_ready(encoder);
533}
534
535static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
536{
537 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
538 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
539 enum port port;
540 u32 val;
541
542 /* Enter ULPS */
543 for_each_dsi_port(port, intel_dsi->ports) {
544 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
545 val &= ~ULPS_STATE_MASK;
546 val |= (ULPS_STATE_ENTER | DEVICE_READY);
547 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
548 }
549
550 /* Wait for MIPI PHY status bit to unset */
551 for_each_dsi_port(port, intel_dsi->ports) {
552 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
553 GLK_PHY_STATUS_PORT_READY, 20))
554 drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
555 }
556
557 /* Wait for Pwr ACK bit to unset */
558 for_each_dsi_port(port, intel_dsi->ports) {
559 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
560 GLK_MIPIIO_PORT_POWERED, 20))
561 drm_err(&dev_priv->drm,
562 "MIPI IO Port is not powergated\n");
563 }
564}
565
566static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
567{
568 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
569 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
570 enum port port;
571 u32 tmp;
572
573 /* Put the IO into reset */
574 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
575 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
576 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp);
577
578 /* Wait for MIPI PHY status bit to unset */
579 for_each_dsi_port(port, intel_dsi->ports) {
580 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
581 GLK_PHY_STATUS_PORT_READY, 20))
582 drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
583 }
584
585 /* Clear MIPI mode */
586 for_each_dsi_port(port, intel_dsi->ports) {
587 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
588 tmp &= ~GLK_MIPIIO_ENABLE;
589 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
590 }
591}
592
593static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
594{
595 glk_dsi_enter_low_power_mode(encoder);
596 glk_dsi_disable_mipi_io(encoder);
597}
598
599static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
600{
601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
602 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
603 enum port port;
604
605 drm_dbg_kms(&dev_priv->drm, "\n");
606 for_each_dsi_port(port, intel_dsi->ports) {
607 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
608 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
609 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
610 u32 val;
611
612 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
613 DEVICE_READY | ULPS_STATE_ENTER);
614 usleep_range(2000, 2500);
615
616 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
617 DEVICE_READY | ULPS_STATE_EXIT);
618 usleep_range(2000, 2500);
619
620 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
621 DEVICE_READY | ULPS_STATE_ENTER);
622 usleep_range(2000, 2500);
623
624 /*
625 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
626 * Port A only. MIPI Port C has no similar bit for checking.
627 */
628 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
629 intel_de_wait_for_clear(dev_priv, port_ctrl,
630 AFE_LATCHOUT, 30))
631 drm_err(&dev_priv->drm, "DSI LP not going Low\n");
632
633 /* Disable MIPI PHY transparent latch */
634 val = intel_de_read(dev_priv, port_ctrl);
635 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD);
636 usleep_range(1000, 1500);
637
638 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
639 usleep_range(2000, 2500);
640 }
641}
642
643static void intel_dsi_port_enable(struct intel_encoder *encoder,
644 const struct intel_crtc_state *crtc_state)
645{
646 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
648 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
649 enum port port;
650
651 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
652 u32 temp;
653 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
654 for_each_dsi_port(port, intel_dsi->ports) {
655 temp = intel_de_read(dev_priv,
656 MIPI_CTRL(port));
657 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
658 intel_dsi->pixel_overlap <<
659 BXT_PIXEL_OVERLAP_CNT_SHIFT;
660 intel_de_write(dev_priv, MIPI_CTRL(port),
661 temp);
662 }
663 } else {
664 temp = intel_de_read(dev_priv, VLV_CHICKEN_3);
665 temp &= ~PIXEL_OVERLAP_CNT_MASK |
666 intel_dsi->pixel_overlap <<
667 PIXEL_OVERLAP_CNT_SHIFT;
668 intel_de_write(dev_priv, VLV_CHICKEN_3, temp);
669 }
670 }
671
672 for_each_dsi_port(port, intel_dsi->ports) {
673 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
674 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
675 u32 temp;
676
677 temp = intel_de_read(dev_priv, port_ctrl);
678
679 temp &= ~LANE_CONFIGURATION_MASK;
680 temp &= ~DUAL_LINK_MODE_MASK;
681
682 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
683 temp |= (intel_dsi->dual_link - 1)
684 << DUAL_LINK_MODE_SHIFT;
685 if (IS_BROXTON(dev_priv))
686 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
687 else
688 temp |= crtc->pipe ?
689 LANE_CONFIGURATION_DUAL_LINK_B :
690 LANE_CONFIGURATION_DUAL_LINK_A;
691 }
692
693 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
694 temp |= DITHERING_ENABLE;
695
696 /* assert ip_tg_enable signal */
697 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
698 intel_de_posting_read(dev_priv, port_ctrl);
699 }
700}
701
702static void intel_dsi_port_disable(struct intel_encoder *encoder)
703{
704 struct drm_device *dev = encoder->base.dev;
705 struct drm_i915_private *dev_priv = to_i915(dev);
706 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
707 enum port port;
708
709 for_each_dsi_port(port, intel_dsi->ports) {
710 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
711 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
712 u32 temp;
713
714 /* de-assert ip_tg_enable signal */
715 temp = intel_de_read(dev_priv, port_ctrl);
716 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE);
717 intel_de_posting_read(dev_priv, port_ctrl);
718 }
719}
720
721static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
722{
723 ktime_t panel_power_on_time;
724 s64 panel_power_off_duration;
725
726 panel_power_on_time = ktime_get_boottime();
727 panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
728 intel_dsi->panel_power_off_time);
729
730 if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
731 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration);
732}
733
734static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
735 const struct intel_crtc_state *pipe_config);
736static void intel_dsi_unprepare(struct intel_encoder *encoder);
737
738/*
739 * Panel enable/disable sequences from the VBT spec.
740 *
741 * Note the spec has AssertReset / DeassertReset swapped from their
742 * usual naming. We use the normal names to avoid confusion (so below
743 * they are swapped compared to the spec).
744 *
745 * Steps starting with MIPI refer to VBT sequences, note that for v2
746 * VBTs several steps which have a VBT in v2 are expected to be handled
747 * directly by the driver, by directly driving gpios for example.
748 *
749 * v2 video mode seq v3 video mode seq command mode seq
750 * - power on - MIPIPanelPowerOn - power on
751 * - wait t1+t2 - wait t1+t2
752 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
753 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
754 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
755 * - MIPITearOn
756 * - MIPIDisplayOn
757 * - turn on DPI - turn on DPI - set pipe to dsr mode
758 * - MIPIDisplayOn - MIPIDisplayOn
759 * - wait t5 - wait t5
760 * - backlight on - MIPIBacklightOn - backlight on
761 * ... ... ... issue mem cmds ...
762 * - backlight off - MIPIBacklightOff - backlight off
763 * - wait t6 - wait t6
764 * - MIPIDisplayOff
765 * - turn off DPI - turn off DPI - disable pipe dsr mode
766 * - MIPITearOff
767 * - MIPIDisplayOff - MIPIDisplayOff
768 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
769 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
770 * - wait t3 - wait t3
771 * - power off - MIPIPanelPowerOff - power off
772 * - wait t4 - wait t4
773 */
774
775/*
776 * DSI port enable has to be done before pipe and plane enable, so we do it in
777 * the pre_enable hook instead of the enable hook.
778 */
779static void intel_dsi_pre_enable(struct intel_atomic_state *state,
780 struct intel_encoder *encoder,
781 const struct intel_crtc_state *pipe_config,
782 const struct drm_connector_state *conn_state)
783{
784 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
785 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
786 struct intel_connector *connector = to_intel_connector(conn_state->connector);
787 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
788 enum pipe pipe = crtc->pipe;
789 enum port port;
790 u32 val;
791 bool glk_cold_boot = false;
792
793 drm_dbg_kms(&dev_priv->drm, "\n");
794
795 intel_dsi_wait_panel_power_cycle(intel_dsi);
796
797 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
798
799 /*
800 * The BIOS may leave the PLL in a wonky state where it doesn't
801 * lock. It needs to be fully powered down to fix it.
802 */
803 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
804 bxt_dsi_pll_disable(encoder);
805 bxt_dsi_pll_enable(encoder, pipe_config);
806 } else {
807 vlv_dsi_pll_disable(encoder);
808 vlv_dsi_pll_enable(encoder, pipe_config);
809 }
810
811 if (IS_BROXTON(dev_priv)) {
812 /* Add MIPI IO reset programming for modeset */
813 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
814 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
815 val | MIPIO_RST_CTRL);
816
817 /* Power up DSI regulator */
818 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
819 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
820 }
821
822 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
823 u32 val;
824
825 /* Disable DPOunit clock gating, can stall pipe */
826 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
827 val |= DPOUNIT_CLOCK_GATE_DISABLE;
828 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
829 }
830
831 if (!IS_GEMINILAKE(dev_priv))
832 intel_dsi_prepare(encoder, pipe_config);
833
834 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
835
836 /*
837 * Give the panel time to power-on and then deassert its reset.
838 * Depending on the VBT MIPI sequences version the deassert-seq
839 * may contain the necessary delay, intel_dsi_msleep() will skip
840 * the delay in that case. If there is no deassert-seq, then an
841 * unconditional msleep is used to give the panel time to power-on.
842 */
843 if (connector->panel.vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
844 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
845 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
846 } else {
847 msleep(intel_dsi->panel_on_delay);
848 }
849
850 if (IS_GEMINILAKE(dev_priv)) {
851 glk_cold_boot = glk_dsi_enable_io(encoder);
852
853 /* Prepare port in cold boot(s3/s4) scenario */
854 if (glk_cold_boot)
855 intel_dsi_prepare(encoder, pipe_config);
856 }
857
858 /* Put device in ready state (LP-11) */
859 intel_dsi_device_ready(encoder);
860
861 /* Prepare port in normal boot scenario */
862 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
863 intel_dsi_prepare(encoder, pipe_config);
864
865 /* Send initialization commands in LP mode */
866 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
867
868 /*
869 * Enable port in pre-enable phase itself because as per hw team
870 * recommendation, port should be enabled before plane & pipe
871 */
872 if (is_cmd_mode(intel_dsi)) {
873 for_each_dsi_port(port, intel_dsi->ports)
874 intel_de_write(dev_priv,
875 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
876 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
877 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
878 } else {
879 msleep(20); /* XXX */
880 for_each_dsi_port(port, intel_dsi->ports)
881 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
882 intel_dsi_msleep(intel_dsi, 100);
883
884 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
885
886 intel_dsi_port_enable(encoder, pipe_config);
887 }
888
889 intel_backlight_enable(pipe_config, conn_state);
890 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
891}
892
893static void bxt_dsi_enable(struct intel_atomic_state *state,
894 struct intel_encoder *encoder,
895 const struct intel_crtc_state *crtc_state,
896 const struct drm_connector_state *conn_state)
897{
898 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
899
900 intel_crtc_vblank_on(crtc_state);
901}
902
903/*
904 * DSI port disable has to be done after pipe and plane disable, so we do it in
905 * the post_disable hook.
906 */
907static void intel_dsi_disable(struct intel_atomic_state *state,
908 struct intel_encoder *encoder,
909 const struct intel_crtc_state *old_crtc_state,
910 const struct drm_connector_state *old_conn_state)
911{
912 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
913 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
914 enum port port;
915
916 drm_dbg_kms(&i915->drm, "\n");
917
918 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
919 intel_backlight_disable(old_conn_state);
920
921 /*
922 * According to the spec we should send SHUTDOWN before
923 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
924 * has shown that the v3 sequence works for v2 VBTs too
925 */
926 if (is_vid_mode(intel_dsi)) {
927 /* Send Shutdown command to the panel in LP mode */
928 for_each_dsi_port(port, intel_dsi->ports)
929 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
930 msleep(10);
931 }
932}
933
934static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
935{
936 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
937
938 if (IS_GEMINILAKE(dev_priv))
939 glk_dsi_clear_device_ready(encoder);
940 else
941 vlv_dsi_clear_device_ready(encoder);
942}
943
944static void intel_dsi_post_disable(struct intel_atomic_state *state,
945 struct intel_encoder *encoder,
946 const struct intel_crtc_state *old_crtc_state,
947 const struct drm_connector_state *old_conn_state)
948{
949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
950 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
951 enum port port;
952 u32 val;
953
954 drm_dbg_kms(&dev_priv->drm, "\n");
955
956 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
957 intel_crtc_vblank_off(old_crtc_state);
958
959 skl_scaler_disable(old_crtc_state);
960 }
961
962 if (is_vid_mode(intel_dsi)) {
963 for_each_dsi_port(port, intel_dsi->ports)
964 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
965
966 intel_dsi_port_disable(encoder);
967 usleep_range(2000, 5000);
968 }
969
970 intel_dsi_unprepare(encoder);
971
972 /*
973 * if disable packets are sent before sending shutdown packet then in
974 * some next enable sequence send turn on packet error is observed
975 */
976 if (is_cmd_mode(intel_dsi))
977 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
978 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
979
980 /* Transition to LP-00 */
981 intel_dsi_clear_device_ready(encoder);
982
983 if (IS_BROXTON(dev_priv)) {
984 /* Power down DSI regulator to save power */
985 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
986 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
987 HS_IO_CTRL_SELECT);
988
989 /* Add MIPI IO reset programming for modeset */
990 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
991 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON,
992 val & ~MIPIO_RST_CTRL);
993 }
994
995 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
996 bxt_dsi_pll_disable(encoder);
997 } else {
998 u32 val;
999
1000 vlv_dsi_pll_disable(encoder);
1001
1002 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));
1003 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
1004 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);
1005 }
1006
1007 /* Assert reset */
1008 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1009
1010 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
1011 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1012
1013 intel_dsi->panel_power_off_time = ktime_get_boottime();
1014}
1015
1016static void intel_dsi_shutdown(struct intel_encoder *encoder)
1017{
1018 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1019
1020 intel_dsi_wait_panel_power_cycle(intel_dsi);
1021}
1022
1023static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1024 enum pipe *pipe)
1025{
1026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1027 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1028 intel_wakeref_t wakeref;
1029 enum port port;
1030 bool active = false;
1031
1032 drm_dbg_kms(&dev_priv->drm, "\n");
1033
1034 wakeref = intel_display_power_get_if_enabled(dev_priv,
1035 encoder->power_domain);
1036 if (!wakeref)
1037 return false;
1038
1039 /*
1040 * On Broxton the PLL needs to be enabled with a valid divider
1041 * configuration, otherwise accessing DSI registers will hang the
1042 * machine. See BSpec North Display Engine registers/MIPI[BXT].
1043 */
1044 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1045 !bxt_dsi_pll_is_enabled(dev_priv))
1046 goto out_put_power;
1047
1048 /* XXX: this only works for one DSI output */
1049 for_each_dsi_port(port, intel_dsi->ports) {
1050 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
1051 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1052 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
1053
1054 /*
1055 * Due to some hardware limitations on VLV/CHV, the DPI enable
1056 * bit in port C control register does not get set. As a
1057 * workaround, check pipe B conf instead.
1058 */
1059 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1060 port == PORT_C)
1061 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1062
1063 /* Try command mode if video mode not enabled */
1064 if (!enabled) {
1065 u32 tmp = intel_de_read(dev_priv,
1066 MIPI_DSI_FUNC_PRG(port));
1067 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1068 }
1069
1070 if (!enabled)
1071 continue;
1072
1073 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
1074 continue;
1075
1076 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1077 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1078 tmp &= BXT_PIPE_SELECT_MASK;
1079 tmp >>= BXT_PIPE_SELECT_SHIFT;
1080
1081 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
1082 continue;
1083
1084 *pipe = tmp;
1085 } else {
1086 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1087 }
1088
1089 active = true;
1090 break;
1091 }
1092
1093out_put_power:
1094 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1095
1096 return active;
1097}
1098
1099static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1100 struct intel_crtc_state *pipe_config)
1101{
1102 struct drm_device *dev = encoder->base.dev;
1103 struct drm_i915_private *dev_priv = to_i915(dev);
1104 struct drm_display_mode *adjusted_mode =
1105 &pipe_config->hw.adjusted_mode;
1106 struct drm_display_mode *adjusted_mode_sw;
1107 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1108 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1109 unsigned int lane_count = intel_dsi->lane_count;
1110 unsigned int bpp, fmt;
1111 enum port port;
1112 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1113 u16 hfp_sw, hsync_sw, hbp_sw;
1114 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1115 crtc_hblank_start_sw, crtc_hblank_end_sw;
1116
1117 /* FIXME: hw readout should not depend on SW state */
1118 adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1119
1120 /*
1121 * Atleast one port is active as encoder->get_config called only if
1122 * encoder->get_hw_state() returns true.
1123 */
1124 for_each_dsi_port(port, intel_dsi->ports) {
1125 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1126 break;
1127 }
1128
1129 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1130 bpp = mipi_dsi_pixel_format_to_bpp(
1131 pixel_format_from_register_bits(fmt));
1132
1133 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1134
1135 /* Enable Frame time stamo based scanline reporting */
1136 pipe_config->mode_flags |=
1137 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1138
1139 /* In terms of pixels */
1140 adjusted_mode->crtc_hdisplay =
1141 intel_de_read(dev_priv,
1142 BXT_MIPI_TRANS_HACTIVE(port));
1143 adjusted_mode->crtc_vdisplay =
1144 intel_de_read(dev_priv,
1145 BXT_MIPI_TRANS_VACTIVE(port));
1146 adjusted_mode->crtc_vtotal =
1147 intel_de_read(dev_priv,
1148 BXT_MIPI_TRANS_VTOTAL(port));
1149
1150 hactive = adjusted_mode->crtc_hdisplay;
1151 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1152
1153 /*
1154 * Meaningful for video mode non-burst sync pulse mode only,
1155 * can be zero for non-burst sync events and burst modes
1156 */
1157 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1158 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1159
1160 /* harizontal values are in terms of high speed byte clock */
1161 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1162 intel_dsi->burst_mode_ratio);
1163 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1164 intel_dsi->burst_mode_ratio);
1165 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1166 intel_dsi->burst_mode_ratio);
1167
1168 if (intel_dsi->dual_link) {
1169 hfp *= 2;
1170 hsync *= 2;
1171 hbp *= 2;
1172 }
1173
1174 /* vertical values are in terms of lines */
1175 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1176 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1177 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port));
1178
1179 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1180 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1181 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1182 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1183 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1184
1185 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1186 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1187 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1188 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1189
1190 /*
1191 * In BXT DSI there is no regs programmed with few horizontal timings
1192 * in Pixels but txbyteclkhs.. So retrieval process adds some
1193 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1194 * Actually here for the given adjusted_mode, we are calculating the
1195 * value programmed to the port and then back to the horizontal timing
1196 * param in pixels. This is the expected value, including roundup errors
1197 * And if that is same as retrieved value from port, then
1198 * (HW state) adjusted_mode's horizontal timings are corrected to
1199 * match with SW state to nullify the errors.
1200 */
1201 /* Calculating the value programmed to the Port register */
1202 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1203 adjusted_mode_sw->crtc_hdisplay;
1204 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1205 adjusted_mode_sw->crtc_hsync_start;
1206 hbp_sw = adjusted_mode_sw->crtc_htotal -
1207 adjusted_mode_sw->crtc_hsync_end;
1208
1209 if (intel_dsi->dual_link) {
1210 hfp_sw /= 2;
1211 hsync_sw /= 2;
1212 hbp_sw /= 2;
1213 }
1214
1215 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1216 intel_dsi->burst_mode_ratio);
1217 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1218 intel_dsi->burst_mode_ratio);
1219 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1220 intel_dsi->burst_mode_ratio);
1221
1222 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1223 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1224 intel_dsi->burst_mode_ratio);
1225 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1226 intel_dsi->burst_mode_ratio);
1227 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1228 intel_dsi->burst_mode_ratio);
1229
1230 if (intel_dsi->dual_link) {
1231 hfp_sw *= 2;
1232 hsync_sw *= 2;
1233 hbp_sw *= 2;
1234 }
1235
1236 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1237 hsync_sw + hbp_sw;
1238 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1239 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1240 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1241 crtc_hblank_end_sw = crtc_htotal_sw;
1242
1243 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1244 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1245
1246 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1247 adjusted_mode->crtc_hsync_start =
1248 adjusted_mode_sw->crtc_hsync_start;
1249
1250 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1251 adjusted_mode->crtc_hsync_end =
1252 adjusted_mode_sw->crtc_hsync_end;
1253
1254 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1255 adjusted_mode->crtc_hblank_start =
1256 adjusted_mode_sw->crtc_hblank_start;
1257
1258 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1259 adjusted_mode->crtc_hblank_end =
1260 adjusted_mode_sw->crtc_hblank_end;
1261}
1262
1263static void intel_dsi_get_config(struct intel_encoder *encoder,
1264 struct intel_crtc_state *pipe_config)
1265{
1266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1267 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1268 u32 pclk;
1269
1270 drm_dbg_kms(&dev_priv->drm, "\n");
1271
1272 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1273
1274 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1275 bxt_dsi_get_pipe_config(encoder, pipe_config);
1276 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1277 } else {
1278 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1279 }
1280
1281 pipe_config->port_clock = pclk;
1282
1283 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1284 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1285 if (intel_dsi->dual_link)
1286 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1287}
1288
1289/* return txclkesc cycles in terms of divider and duration in us */
1290static u16 txclkesc(u32 divider, unsigned int us)
1291{
1292 switch (divider) {
1293 case ESCAPE_CLOCK_DIVIDER_1:
1294 default:
1295 return 20 * us;
1296 case ESCAPE_CLOCK_DIVIDER_2:
1297 return 10 * us;
1298 case ESCAPE_CLOCK_DIVIDER_4:
1299 return 5 * us;
1300 }
1301}
1302
1303static void set_dsi_timings(struct drm_encoder *encoder,
1304 const struct drm_display_mode *adjusted_mode)
1305{
1306 struct drm_device *dev = encoder->dev;
1307 struct drm_i915_private *dev_priv = to_i915(dev);
1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1309 enum port port;
1310 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1311 unsigned int lane_count = intel_dsi->lane_count;
1312
1313 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1314
1315 hactive = adjusted_mode->crtc_hdisplay;
1316 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1317 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1318 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1319
1320 if (intel_dsi->dual_link) {
1321 hactive /= 2;
1322 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1323 hactive += intel_dsi->pixel_overlap;
1324 hfp /= 2;
1325 hsync /= 2;
1326 hbp /= 2;
1327 }
1328
1329 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1330 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1331 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1332
1333 /* horizontal values are in terms of high speed byte clock */
1334 hactive = txbyteclkhs(hactive, bpp, lane_count,
1335 intel_dsi->burst_mode_ratio);
1336 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1337 hsync = txbyteclkhs(hsync, bpp, lane_count,
1338 intel_dsi->burst_mode_ratio);
1339 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1340
1341 for_each_dsi_port(port, intel_dsi->ports) {
1342 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1343 /*
1344 * Program hdisplay and vdisplay on MIPI transcoder.
1345 * This is different from calculated hactive and
1346 * vactive, as they are calculated per channel basis,
1347 * whereas these values should be based on resolution.
1348 */
1349 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1350 adjusted_mode->crtc_hdisplay);
1351 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1352 adjusted_mode->crtc_vdisplay);
1353 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1354 adjusted_mode->crtc_vtotal);
1355 }
1356
1357 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1358 hactive);
1359 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1360
1361 /* meaningful for video mode non-burst sync pulse mode only,
1362 * can be zero for non-burst sync events and burst modes */
1363 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1364 hsync);
1365 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1366
1367 /* vertical values are in terms of lines */
1368 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1369 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1370 vsync);
1371 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1372 }
1373}
1374
1375static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1376{
1377 switch (fmt) {
1378 case MIPI_DSI_FMT_RGB888:
1379 return VID_MODE_FORMAT_RGB888;
1380 case MIPI_DSI_FMT_RGB666:
1381 return VID_MODE_FORMAT_RGB666;
1382 case MIPI_DSI_FMT_RGB666_PACKED:
1383 return VID_MODE_FORMAT_RGB666_PACKED;
1384 case MIPI_DSI_FMT_RGB565:
1385 return VID_MODE_FORMAT_RGB565;
1386 default:
1387 MISSING_CASE(fmt);
1388 return VID_MODE_FORMAT_RGB666;
1389 }
1390}
1391
1392static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1393 const struct intel_crtc_state *pipe_config)
1394{
1395 struct drm_encoder *encoder = &intel_encoder->base;
1396 struct drm_device *dev = encoder->dev;
1397 struct drm_i915_private *dev_priv = to_i915(dev);
1398 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1399 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1400 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1401 enum port port;
1402 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1403 u32 val, tmp;
1404 u16 mode_hdisplay;
1405
1406 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1407
1408 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1409
1410 if (intel_dsi->dual_link) {
1411 mode_hdisplay /= 2;
1412 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1413 mode_hdisplay += intel_dsi->pixel_overlap;
1414 }
1415
1416 for_each_dsi_port(port, intel_dsi->ports) {
1417 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1418 /*
1419 * escape clock divider, 20MHz, shared for A and C.
1420 * device ready must be off when doing this! txclkesc?
1421 */
1422 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1423 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1424 intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1425 tmp | ESCAPE_CLOCK_DIVIDER_1);
1426
1427 /* read request priority is per pipe */
1428 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1429 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1430 intel_de_write(dev_priv, MIPI_CTRL(port),
1431 tmp | READ_REQUEST_PRIORITY_HIGH);
1432 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1433 enum pipe pipe = crtc->pipe;
1434
1435 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1436 tmp &= ~BXT_PIPE_SELECT_MASK;
1437
1438 tmp |= BXT_PIPE_SELECT(pipe);
1439 intel_de_write(dev_priv, MIPI_CTRL(port), tmp);
1440 }
1441
1442 /* XXX: why here, why like this? handling in irq handler?! */
1443 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1444 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1445
1446 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1447 intel_dsi->dphy_reg);
1448
1449 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1450 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1451 }
1452
1453 set_dsi_timings(encoder, adjusted_mode);
1454
1455 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1456 if (is_cmd_mode(intel_dsi)) {
1457 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1458 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1459 } else {
1460 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1461 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1462 }
1463
1464 tmp = 0;
1465 if (intel_dsi->eotp_pkt == 0)
1466 tmp |= EOT_DISABLE;
1467 if (intel_dsi->clock_stop)
1468 tmp |= CLOCKSTOP;
1469
1470 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1471 tmp |= BXT_DPHY_DEFEATURE_EN;
1472 if (!is_cmd_mode(intel_dsi))
1473 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1474 }
1475
1476 for_each_dsi_port(port, intel_dsi->ports) {
1477 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1478
1479 /* timeouts for recovery. one frame IIUC. if counter expires,
1480 * EOT and stop state. */
1481
1482 /*
1483 * In burst mode, value greater than one DPI line Time in byte
1484 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1485 * said value is recommended.
1486 *
1487 * In non-burst mode, Value greater than one DPI frame time in
1488 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1489 * said value is recommended.
1490 *
1491 * In DBI only mode, value greater than one DBI frame time in
1492 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1493 * said value is recommended.
1494 */
1495
1496 if (is_vid_mode(intel_dsi) &&
1497 intel_dsi->video_mode == BURST_MODE) {
1498 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1499 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1500 } else {
1501 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1502 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1503 }
1504 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1505 intel_dsi->lp_rx_timeout);
1506 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1507 intel_dsi->turn_arnd_val);
1508 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1509 intel_dsi->rst_timer_val);
1510
1511 /* dphy stuff */
1512
1513 /* in terms of low power clock */
1514 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1515 txclkesc(intel_dsi->escape_clk_div, 100));
1516
1517 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1518 !intel_dsi->dual_link) {
1519 /*
1520 * BXT spec says write MIPI_INIT_COUNT for
1521 * both the ports, even if only one is
1522 * getting used. So write the other port
1523 * if not in dual link mode.
1524 */
1525 intel_de_write(dev_priv,
1526 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1527 intel_dsi->init_count);
1528 }
1529
1530 /* recovery disables */
1531 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1532
1533 /* in terms of low power clock */
1534 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1535 intel_dsi->init_count);
1536
1537 /* in terms of txbyteclkhs. actual high to low switch +
1538 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1539 *
1540 * XXX: write MIPI_STOP_STATE_STALL?
1541 */
1542 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1543 intel_dsi->hs_to_lp_count);
1544
1545 /* XXX: low power clock equivalence in terms of byte clock.
1546 * the number of byte clocks occupied in one low power clock.
1547 * based on txbyteclkhs and txclkesc.
1548 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1549 * ) / 105.???
1550 */
1551 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1552 intel_dsi->lp_byte_clk);
1553
1554 if (IS_GEMINILAKE(dev_priv)) {
1555 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1556 intel_dsi->lp_byte_clk);
1557 /* Shadow of DPHY reg */
1558 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1559 intel_dsi->dphy_reg);
1560 }
1561
1562 /* the bw essential for transmitting 16 long packets containing
1563 * 252 bytes meant for dcs write memory command is programmed in
1564 * this register in terms of byte clocks. based on dsi transfer
1565 * rate and the number of lanes configured the time taken to
1566 * transmit 16 long packets in a dsi stream varies. */
1567 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1568 intel_dsi->bw_timer);
1569
1570 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1571 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1572
1573 if (is_vid_mode(intel_dsi)) {
1574 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1575
1576 /*
1577 * Some panels might have resolution which is not a
1578 * multiple of 64 like 1366 x 768. Enable RANDOM
1579 * resolution support for such panels by default.
1580 */
1581 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1582
1583 switch (intel_dsi->video_mode) {
1584 default:
1585 MISSING_CASE(intel_dsi->video_mode);
1586 fallthrough;
1587 case NON_BURST_SYNC_EVENTS:
1588 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1589 break;
1590 case NON_BURST_SYNC_PULSE:
1591 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1592 break;
1593 case BURST_MODE:
1594 fmt |= VIDEO_MODE_BURST;
1595 break;
1596 }
1597
1598 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
1599 }
1600 }
1601}
1602
1603static void intel_dsi_unprepare(struct intel_encoder *encoder)
1604{
1605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1606 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1607 enum port port;
1608 u32 val;
1609
1610 if (IS_GEMINILAKE(dev_priv))
1611 return;
1612
1613 for_each_dsi_port(port, intel_dsi->ports) {
1614 /* Panel commands can be sent when clock is in LP11 */
1615 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1616
1617 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1618 bxt_dsi_reset_clocks(encoder, port);
1619 else
1620 vlv_dsi_reset_clocks(encoder, port);
1621 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1622
1623 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port));
1624 val &= ~VID_MODE_FORMAT_MASK;
1625 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1626
1627 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1628 }
1629}
1630
1631static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1632{
1633 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1634
1635 intel_dsi_vbt_gpio_cleanup(intel_dsi);
1636 intel_encoder_destroy(encoder);
1637}
1638
1639static const struct drm_encoder_funcs intel_dsi_funcs = {
1640 .destroy = intel_dsi_encoder_destroy,
1641};
1642
1643static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1644 .get_modes = intel_dsi_get_modes,
1645 .mode_valid = intel_dsi_mode_valid,
1646 .atomic_check = intel_digital_connector_atomic_check,
1647};
1648
1649static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1650 .detect = intel_panel_detect,
1651 .late_register = intel_connector_register,
1652 .early_unregister = intel_connector_unregister,
1653 .destroy = intel_connector_destroy,
1654 .fill_modes = drm_helper_probe_single_connector_modes,
1655 .atomic_get_property = intel_digital_connector_atomic_get_property,
1656 .atomic_set_property = intel_digital_connector_atomic_set_property,
1657 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1658 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1659};
1660
1661static void vlv_dsi_add_properties(struct intel_connector *connector)
1662{
1663 const struct drm_display_mode *fixed_mode =
1664 intel_panel_preferred_fixed_mode(connector);
1665
1666 intel_attach_scaling_mode_property(&connector->base);
1667
1668 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1669 intel_dsi_get_panel_orientation(connector),
1670 fixed_mode->hdisplay,
1671 fixed_mode->vdisplay);
1672}
1673
1674#define NS_KHZ_RATIO 1000000
1675
1676#define PREPARE_CNT_MAX 0x3F
1677#define EXIT_ZERO_CNT_MAX 0x3F
1678#define CLK_ZERO_CNT_MAX 0xFF
1679#define TRAIL_CNT_MAX 0x1F
1680
1681static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1682{
1683 struct drm_device *dev = intel_dsi->base.base.dev;
1684 struct drm_i915_private *dev_priv = to_i915(dev);
1685 struct intel_connector *connector = intel_dsi->attached_connector;
1686 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1687 u32 tlpx_ns, extra_byte_count, tlpx_ui;
1688 u32 ui_num, ui_den;
1689 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1690 u32 ths_prepare_ns, tclk_trail_ns;
1691 u32 tclk_prepare_clkzero, ths_prepare_hszero;
1692 u32 lp_to_hs_switch, hs_to_lp_switch;
1693 u32 mul;
1694
1695 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1696
1697 switch (intel_dsi->lane_count) {
1698 case 1:
1699 case 2:
1700 extra_byte_count = 2;
1701 break;
1702 case 3:
1703 extra_byte_count = 4;
1704 break;
1705 case 4:
1706 default:
1707 extra_byte_count = 3;
1708 break;
1709 }
1710
1711 /* in Kbps */
1712 ui_num = NS_KHZ_RATIO;
1713 ui_den = intel_dsi_bitrate(intel_dsi);
1714
1715 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1716 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1717
1718 /*
1719 * B060
1720 * LP byte clock = TLPX/ (8UI)
1721 */
1722 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1723
1724 /* DDR clock period = 2 * UI
1725 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1726 * UI(nsec) = 10^6 / bitrate
1727 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1728 * DDR clock count = ns_value / DDR clock period
1729 *
1730 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1731 * HS byte clock count for other platform in HS ddr clock count
1732 */
1733 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1734 ths_prepare_ns = max(mipi_config->ths_prepare,
1735 mipi_config->tclk_prepare);
1736
1737 /* prepare count */
1738 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1739
1740 if (prepare_cnt > PREPARE_CNT_MAX) {
1741 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1742 prepare_cnt);
1743 prepare_cnt = PREPARE_CNT_MAX;
1744 }
1745
1746 /* exit zero count */
1747 exit_zero_cnt = DIV_ROUND_UP(
1748 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1749 ui_num * mul
1750 );
1751
1752 /*
1753 * Exit zero is unified val ths_zero and ths_exit
1754 * minimum value for ths_exit = 110ns
1755 * min (exit_zero_cnt * 2) = 110/UI
1756 * exit_zero_cnt = 55/UI
1757 */
1758 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1759 exit_zero_cnt += 1;
1760
1761 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1762 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1763 exit_zero_cnt);
1764 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1765 }
1766
1767 /* clk zero count */
1768 clk_zero_cnt = DIV_ROUND_UP(
1769 (tclk_prepare_clkzero - ths_prepare_ns)
1770 * ui_den, ui_num * mul);
1771
1772 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1773 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1774 clk_zero_cnt);
1775 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1776 }
1777
1778 /* trail count */
1779 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1780 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1781
1782 if (trail_cnt > TRAIL_CNT_MAX) {
1783 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1784 trail_cnt);
1785 trail_cnt = TRAIL_CNT_MAX;
1786 }
1787
1788 /* B080 */
1789 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1790 clk_zero_cnt << 8 | prepare_cnt;
1791
1792 /*
1793 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1794 * mul + 10UI + Extra Byte Count
1795 *
1796 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1797 * Extra Byte Count is calculated according to number of lanes.
1798 * High Low Switch Count is the Max of LP to HS and
1799 * HS to LP switch count
1800 *
1801 */
1802 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1803
1804 /* B044 */
1805 /* FIXME:
1806 * The comment above does not match with the code */
1807 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1808 exit_zero_cnt * mul + 10, 8);
1809
1810 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1811
1812 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1813 intel_dsi->hs_to_lp_count += extra_byte_count;
1814
1815 /* B088 */
1816 /* LP -> HS for clock lanes
1817 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1818 * extra byte count
1819 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1820 * 2(in UI) + extra byte count
1821 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1822 * 8 + extra byte count
1823 */
1824 intel_dsi->clk_lp_to_hs_count =
1825 DIV_ROUND_UP(
1826 4 * tlpx_ui + prepare_cnt * 2 +
1827 clk_zero_cnt * 2,
1828 8);
1829
1830 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1831
1832 /* HS->LP for Clock Lanes
1833 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1834 * Extra byte count
1835 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1836 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1837 * Extra byte count
1838 */
1839 intel_dsi->clk_hs_to_lp_count =
1840 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1841 8);
1842 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1843
1844 intel_dsi_log_params(intel_dsi);
1845}
1846
1847void vlv_dsi_init(struct drm_i915_private *dev_priv)
1848{
1849 struct intel_dsi *intel_dsi;
1850 struct intel_encoder *intel_encoder;
1851 struct drm_encoder *encoder;
1852 struct intel_connector *intel_connector;
1853 struct drm_connector *connector;
1854 struct drm_display_mode *current_mode;
1855 enum port port;
1856 enum pipe pipe;
1857
1858 drm_dbg_kms(&dev_priv->drm, "\n");
1859
1860 /* There is no detection method for MIPI so rely on VBT */
1861 if (!intel_bios_is_dsi_present(dev_priv, &port))
1862 return;
1863
1864 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1865 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1866 else
1867 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1868
1869 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1870 if (!intel_dsi)
1871 return;
1872
1873 intel_connector = intel_connector_alloc();
1874 if (!intel_connector) {
1875 kfree(intel_dsi);
1876 return;
1877 }
1878
1879 intel_encoder = &intel_dsi->base;
1880 encoder = &intel_encoder->base;
1881 intel_dsi->attached_connector = intel_connector;
1882
1883 connector = &intel_connector->base;
1884
1885 drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1886 "DSI %c", port_name(port));
1887
1888 intel_encoder->compute_config = intel_dsi_compute_config;
1889 intel_encoder->pre_enable = intel_dsi_pre_enable;
1890 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1891 intel_encoder->enable = bxt_dsi_enable;
1892 intel_encoder->disable = intel_dsi_disable;
1893 intel_encoder->post_disable = intel_dsi_post_disable;
1894 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1895 intel_encoder->get_config = intel_dsi_get_config;
1896 intel_encoder->update_pipe = intel_backlight_update;
1897 intel_encoder->shutdown = intel_dsi_shutdown;
1898
1899 intel_connector->get_hw_state = intel_connector_get_hw_state;
1900
1901 intel_encoder->port = port;
1902 intel_encoder->type = INTEL_OUTPUT_DSI;
1903 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1904 intel_encoder->cloneable = 0;
1905
1906 /*
1907 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1908 * port C. BXT isn't limited like this.
1909 */
1910 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1911 intel_encoder->pipe_mask = ~0;
1912 else if (port == PORT_A)
1913 intel_encoder->pipe_mask = BIT(PIPE_A);
1914 else
1915 intel_encoder->pipe_mask = BIT(PIPE_B);
1916
1917 intel_dsi->panel_power_off_time = ktime_get_boottime();
1918
1919 intel_bios_init_panel(dev_priv, &intel_connector->panel, NULL, NULL);
1920
1921 if (intel_connector->panel.vbt.dsi.config->dual_link)
1922 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1923 else
1924 intel_dsi->ports = BIT(port);
1925
1926 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1927 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1928
1929 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1930 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1931
1932 /* Create a DSI host (and a device) for each port. */
1933 for_each_dsi_port(port, intel_dsi->ports) {
1934 struct intel_dsi_host *host;
1935
1936 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1937 port);
1938 if (!host)
1939 goto err;
1940
1941 intel_dsi->dsi_hosts[port] = host;
1942 }
1943
1944 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1945 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1946 goto err;
1947 }
1948
1949 /* Use clock read-back from current hw-state for fastboot */
1950 current_mode = intel_encoder_current_mode(intel_encoder);
1951 if (current_mode) {
1952 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1953 intel_dsi->pclk, current_mode->clock);
1954 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1955 current_mode->clock)) {
1956 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1957 intel_dsi->pclk = current_mode->clock;
1958 }
1959
1960 kfree(current_mode);
1961 }
1962
1963 vlv_dphy_param_init(intel_dsi);
1964
1965 intel_dsi_vbt_gpio_init(intel_dsi,
1966 intel_dsi_get_hw_state(intel_encoder, &pipe));
1967
1968 drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs,
1969 DRM_MODE_CONNECTOR_DSI);
1970
1971 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1972
1973 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1974
1975 intel_connector_attach_encoder(intel_connector, intel_encoder);
1976
1977 mutex_lock(&dev_priv->drm.mode_config.mutex);
1978 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1979 mutex_unlock(&dev_priv->drm.mode_config.mutex);
1980
1981 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1982 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
1983 goto err_cleanup_connector;
1984 }
1985
1986 intel_panel_init(intel_connector);
1987
1988 intel_backlight_setup(intel_connector, INVALID_PIPE);
1989
1990 vlv_dsi_add_properties(intel_connector);
1991
1992 return;
1993
1994err_cleanup_connector:
1995 drm_connector_cleanup(&intel_connector->base);
1996err:
1997 drm_encoder_cleanup(&intel_encoder->base);
1998 kfree(intel_dsi);
1999 kfree(intel_connector);
2000}