1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2022 Intel Corporation
 4 */
 5
 6#ifndef __SKL_WATERMARK_H__
 7#define __SKL_WATERMARK_H__
 8
 9#include <linux/types.h>
10
11#include "intel_display.h"
12#include "intel_global_state.h"
13#include "intel_pm_types.h"
14
15struct drm_i915_private;
16struct intel_atomic_state;
17struct intel_bw_state;
18struct intel_crtc;
19struct intel_crtc_state;
20struct intel_plane;
21
22u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
23
24void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
25void intel_sagv_post_plane_update(struct intel_atomic_state *state);
26bool intel_can_enable_sagv(struct drm_i915_private *i915,
27			   const struct intel_bw_state *bw_state);
28
29u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
30			    const struct skl_ddb_entry *entry);
31
32void skl_write_plane_wm(struct intel_plane *plane,
33			const struct intel_crtc_state *crtc_state);
34void skl_write_cursor_wm(struct intel_plane *plane,
35			 const struct intel_crtc_state *crtc_state);
36
37bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
38				 const struct skl_ddb_entry *entries,
39				 int num_entries, int ignore_idx);
40
41void skl_wm_get_hw_state(struct drm_i915_private *i915);
42void skl_wm_sanitize(struct drm_i915_private *i915);
43
44void intel_wm_state_verify(struct intel_crtc *crtc,
45			   struct intel_crtc_state *new_crtc_state);
46
47void skl_watermark_ipc_init(struct drm_i915_private *i915);
48void skl_watermark_ipc_update(struct drm_i915_private *i915);
49bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
50void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915);
51
52void skl_wm_init(struct drm_i915_private *i915);
53
54struct intel_dbuf_state {
55	struct intel_global_state base;
56
57	struct skl_ddb_entry ddb[I915_MAX_PIPES];
58	unsigned int weight[I915_MAX_PIPES];
59	u8 slices[I915_MAX_PIPES];
60	u8 enabled_slices;
61	u8 active_pipes;
62	bool joined_mbus;
63};
64
65struct intel_dbuf_state *
66intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
67
68#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
69#define intel_atomic_get_old_dbuf_state(state) \
70	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
71#define intel_atomic_get_new_dbuf_state(state) \
72	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
73
74int intel_dbuf_init(struct drm_i915_private *i915);
75void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
76void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
77void intel_mbus_dbox_update(struct intel_atomic_state *state);
78
79#endif /* __SKL_WATERMARK_H__ */
80