Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8#include <linux/limits.h>
9
10#include <drm/display/drm_dsc_helper.h>
11
12#include "i915_drv.h"
13#include "i915_reg.h"
14#include "intel_crtc.h"
15#include "intel_de.h"
16#include "intel_display_types.h"
17#include "intel_dsi.h"
18#include "intel_qp_tables.h"
19#include "intel_vdsc.h"
20
21enum ROW_INDEX_BPP {
22 ROW_INDEX_6BPP = 0,
23 ROW_INDEX_8BPP,
24 ROW_INDEX_10BPP,
25 ROW_INDEX_12BPP,
26 ROW_INDEX_15BPP,
27 MAX_ROW_INDEX
28};
29
30enum COLUMN_INDEX_BPC {
31 COLUMN_INDEX_8BPC = 0,
32 COLUMN_INDEX_10BPC,
33 COLUMN_INDEX_12BPC,
34 COLUMN_INDEX_14BPC,
35 COLUMN_INDEX_16BPC,
36 MAX_COLUMN_INDEX
37};
38
39/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
40static const u16 rc_buf_thresh[] = {
41 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
42 7744, 7872, 8000, 8064
43};
44
45struct rc_parameters {
46 u16 initial_xmit_delay;
47 u8 first_line_bpg_offset;
48 u16 initial_offset;
49 u8 flatness_min_qp;
50 u8 flatness_max_qp;
51 u8 rc_quant_incr_limit0;
52 u8 rc_quant_incr_limit1;
53 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
54};
55
56/*
57 * Selected Rate Control Related Parameter Recommended Values
58 * from DSC_v1.11 spec & C Model release: DSC_model_20161212
59 */
60static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
61{
62 /* 6BPP/8BPC */
63 { 768, 15, 6144, 3, 13, 11, 11, {
64 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
65 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
66 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
67 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
68 }
69 },
70 /* 6BPP/10BPC */
71 { 768, 15, 6144, 7, 17, 15, 15, {
72 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
73 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
74 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
75 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
76 { 17, 18, -12 }
77 }
78 },
79 /* 6BPP/12BPC */
80 { 768, 15, 6144, 11, 21, 19, 19, {
81 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
82 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
83 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
84 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
85 { 21, 22, -12 }
86 }
87 },
88 /* 6BPP/14BPC */
89 { 768, 15, 6144, 15, 25, 23, 27, {
90 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
91 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
92 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
93 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
94 { 25, 26, -12 }
95 }
96 },
97 /* 6BPP/16BPC */
98 { 768, 15, 6144, 19, 29, 27, 27, {
99 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
100 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
101 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
102 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
103 { 29, 30, -12 }
104 }
105 },
106},
107{
108 /* 8BPP/8BPC */
109 { 512, 12, 6144, 3, 12, 11, 11, {
110 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
111 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
112 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
113 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
114 }
115 },
116 /* 8BPP/10BPC */
117 { 512, 12, 6144, 7, 16, 15, 15, {
118 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
119 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
120 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
121 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
122 }
123 },
124 /* 8BPP/12BPC */
125 { 512, 12, 6144, 11, 20, 19, 19, {
126 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
127 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
128 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
129 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
130 { 21, 23, -12 }
131 }
132 },
133 /* 8BPP/14BPC */
134 { 512, 12, 6144, 15, 24, 23, 23, {
135 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
136 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
137 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
138 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
139 { 24, 25, -12 }
140 }
141 },
142 /* 8BPP/16BPC */
143 { 512, 12, 6144, 19, 28, 27, 27, {
144 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
145 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
146 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
147 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
148 { 28, 29, -12 }
149 }
150 },
151},
152{
153 /* 10BPP/8BPC */
154 { 410, 15, 5632, 3, 12, 11, 11, {
155 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
156 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
157 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
158 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
159 }
160 },
161 /* 10BPP/10BPC */
162 { 410, 15, 5632, 7, 16, 15, 15, {
163 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
164 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
165 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
166 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
167 }
168 },
169 /* 10BPP/12BPC */
170 { 410, 15, 5632, 11, 20, 19, 19, {
171 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
172 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
173 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
174 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
175 { 19, 20, -12 }
176 }
177 },
178 /* 10BPP/14BPC */
179 { 410, 15, 5632, 15, 24, 23, 23, {
180 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
181 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
182 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
183 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
184 { 23, 24, -12 }
185 }
186 },
187 /* 10BPP/16BPC */
188 { 410, 15, 5632, 19, 28, 27, 27, {
189 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
190 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
191 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
192 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
193 { 27, 28, -12 }
194 }
195 },
196},
197{
198 /* 12BPP/8BPC */
199 { 341, 15, 2048, 3, 12, 11, 11, {
200 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
201 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
202 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
203 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
204 }
205 },
206 /* 12BPP/10BPC */
207 { 341, 15, 2048, 7, 16, 15, 15, {
208 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
209 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
210 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
211 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
212 }
213 },
214 /* 12BPP/12BPC */
215 { 341, 15, 2048, 11, 20, 19, 19, {
216 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
217 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
218 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
219 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
220 { 21, 23, -12 }
221 }
222 },
223 /* 12BPP/14BPC */
224 { 341, 15, 2048, 15, 24, 23, 23, {
225 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
226 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
227 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
228 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
229 { 22, 23, -12 }
230 }
231 },
232 /* 12BPP/16BPC */
233 { 341, 15, 2048, 19, 28, 27, 27, {
234 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
235 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
236 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
237 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
238 { 26, 27, -12 }
239 }
240 },
241},
242{
243 /* 15BPP/8BPC */
244 { 273, 15, 2048, 3, 12, 11, 11, {
245 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
246 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
247 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
248 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
249 }
250 },
251 /* 15BPP/10BPC */
252 { 273, 15, 2048, 7, 16, 15, 15, {
253 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
254 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
255 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
256 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
257 }
258 },
259 /* 15BPP/12BPC */
260 { 273, 15, 2048, 11, 20, 19, 19, {
261 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
262 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
263 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
264 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
265 { 16, 17, -12 }
266 }
267 },
268 /* 15BPP/14BPC */
269 { 273, 15, 2048, 15, 24, 23, 23, {
270 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
271 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
272 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
273 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
274 { 20, 21, -12 }
275 }
276 },
277 /* 15BPP/16BPC */
278 { 273, 15, 2048, 19, 28, 27, 27, {
279 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
280 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
281 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
282 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
283 { 24, 25, -12 }
284 }
285 }
286}
287
288};
289
290static int get_row_index_for_rc_params(u16 compressed_bpp)
291{
292 switch (compressed_bpp) {
293 case 6:
294 return ROW_INDEX_6BPP;
295 case 8:
296 return ROW_INDEX_8BPP;
297 case 10:
298 return ROW_INDEX_10BPP;
299 case 12:
300 return ROW_INDEX_12BPP;
301 case 15:
302 return ROW_INDEX_15BPP;
303 default:
304 return -EINVAL;
305 }
306}
307
308static int get_column_index_for_rc_params(u8 bits_per_component)
309{
310 switch (bits_per_component) {
311 case 8:
312 return COLUMN_INDEX_8BPC;
313 case 10:
314 return COLUMN_INDEX_10BPC;
315 case 12:
316 return COLUMN_INDEX_12BPC;
317 case 14:
318 return COLUMN_INDEX_14BPC;
319 case 16:
320 return COLUMN_INDEX_16BPC;
321 default:
322 return -EINVAL;
323 }
324}
325
326static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
327 u8 bits_per_component)
328{
329 int row_index, column_index;
330
331 row_index = get_row_index_for_rc_params(compressed_bpp);
332 if (row_index < 0)
333 return NULL;
334
335 column_index = get_column_index_for_rc_params(bits_per_component);
336 if (column_index < 0)
337 return NULL;
338
339 return &rc_parameters[row_index][column_index];
340}
341
342bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
343{
344 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
345 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
346 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
347
348 if (!RUNTIME_INFO(i915)->has_dsc)
349 return false;
350
351 if (DISPLAY_VER(i915) >= 12)
352 return true;
353
354 if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
355 return true;
356
357 return false;
358}
359
360static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
361{
362 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
363
364 if (DISPLAY_VER(i915) >= 12)
365 return true;
366
367 if (cpu_transcoder == TRANSCODER_EDP ||
368 cpu_transcoder == TRANSCODER_DSI_0 ||
369 cpu_transcoder == TRANSCODER_DSI_1)
370 return false;
371
372 /* There's no pipe A DSC engine on ICL */
373 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A);
374
375 return true;
376}
377
378static void
379calculate_rc_params(struct rc_parameters *rc,
380 struct drm_dsc_config *vdsc_cfg)
381{
382 int bpc = vdsc_cfg->bits_per_component;
383 int bpp = vdsc_cfg->bits_per_pixel >> 4;
384 static const s8 ofs_und6[] = {
385 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
386 };
387 static const s8 ofs_und8[] = {
388 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
389 };
390 static const s8 ofs_und12[] = {
391 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
392 };
393 static const s8 ofs_und15[] = {
394 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
395 };
396 int qp_bpc_modifier = (bpc - 8) * 2;
397 u32 res, buf_i, bpp_i;
398
399 if (vdsc_cfg->slice_height >= 8)
400 rc->first_line_bpg_offset =
401 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
402 else
403 rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
404
405 /* Our hw supports only 444 modes as of today */
406 if (bpp >= 12)
407 rc->initial_offset = 2048;
408 else if (bpp >= 10)
409 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
410 else if (bpp >= 8)
411 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
412 else
413 rc->initial_offset = 6144;
414
415 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
416 rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
417
418 rc->flatness_min_qp = 3 + qp_bpc_modifier;
419 rc->flatness_max_qp = 12 + qp_bpc_modifier;
420
421 rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
422 rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
423
424 bpp_i = (2 * (bpp - 6));
425 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
426 /* Read range_minqp and range_max_qp from qp tables */
427 rc->rc_range_params[buf_i].range_min_qp =
428 intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
429 rc->rc_range_params[buf_i].range_max_qp =
430 intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
431
432 /* Calculate range_bgp_offset */
433 if (bpp <= 6) {
434 rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
435 } else if (bpp <= 8) {
436 res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
437 rc->rc_range_params[buf_i].range_bpg_offset =
438 ofs_und6[buf_i] + res;
439 } else if (bpp <= 12) {
440 rc->rc_range_params[buf_i].range_bpg_offset =
441 ofs_und8[buf_i];
442 } else if (bpp <= 15) {
443 res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
444 rc->rc_range_params[buf_i].range_bpg_offset =
445 ofs_und12[buf_i] + res;
446 } else {
447 rc->rc_range_params[buf_i].range_bpg_offset =
448 ofs_und15[buf_i];
449 }
450 }
451}
452
453int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
454{
455 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
456 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
457 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
458 u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
459 const struct rc_parameters *rc_params;
460 struct rc_parameters *rc = NULL;
461 u8 i = 0;
462
463 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
464 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
465 pipe_config->dsc.slice_count);
466
467 /* Gen 11 does not support YCbCr */
468 vdsc_cfg->simple_422 = false;
469 /* Gen 11 does not support VBR */
470 vdsc_cfg->vbr_enable = false;
471
472 /* Gen 11 only supports integral values of bpp */
473 vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
474 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
475
476 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
477 /*
478 * six 0s are appended to the lsb of each threshold value
479 * internally in h/w.
480 * Only 8 bits are allowed for programming RcBufThreshold
481 */
482 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
483 }
484
485 /*
486 * For 6bpp, RC Buffer threshold 12 and 13 need a different value
487 * as per C Model
488 */
489 if (compressed_bpp == 6) {
490 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
491 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
492 }
493
494 /*
495 * From XE_LPD onwards we supports compression bpps in steps of 1
496 * upto uncompressed bpp-1, hence add calculations for all the rc
497 * parameters
498 */
499 if (DISPLAY_VER(dev_priv) >= 13) {
500 rc = kmalloc(sizeof(*rc), GFP_KERNEL);
501 if (!rc)
502 return -ENOMEM;
503
504 calculate_rc_params(rc, vdsc_cfg);
505 rc_params = rc;
506 } else {
507 rc_params = get_rc_params(compressed_bpp,
508 vdsc_cfg->bits_per_component);
509 if (!rc_params)
510 return -EINVAL;
511 }
512
513 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
514 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
515 vdsc_cfg->initial_offset = rc_params->initial_offset;
516 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
517 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
518 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
519 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
520
521 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
522 vdsc_cfg->rc_range_params[i].range_min_qp =
523 rc_params->rc_range_params[i].range_min_qp;
524 vdsc_cfg->rc_range_params[i].range_max_qp =
525 rc_params->rc_range_params[i].range_max_qp;
526 /*
527 * Range BPG Offset uses 2's complement and is only a 6 bits. So
528 * mask it to get only 6 bits.
529 */
530 vdsc_cfg->rc_range_params[i].range_bpg_offset =
531 rc_params->rc_range_params[i].range_bpg_offset &
532 DSC_RANGE_BPG_OFFSET_MASK;
533 }
534
535 /*
536 * BitsPerComponent value determines mux_word_size:
537 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
538 * 48 bits otherwise 64
539 */
540 if (vdsc_cfg->bits_per_component <= 10)
541 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
542 else
543 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
544
545 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
546 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
547 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
548
549 kfree(rc);
550
551 return 0;
552}
553
554enum intel_display_power_domain
555intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
556{
557 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
558 enum pipe pipe = crtc->pipe;
559
560 /*
561 * VDSC/joining uses a separate power well, PW2, and requires
562 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
563 *
564 * - ICL eDP/DSI transcoder
565 * - Display version 12 (except RKL) pipe A
566 *
567 * For any other pipe, VDSC/joining uses the power well associated with
568 * the pipe in use. Hence another reference on the pipe power domain
569 * will suffice. (Except no VDSC/joining on ICL pipe A.)
570 */
571 if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
572 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
573 else if (is_pipe_dsc(crtc, cpu_transcoder))
574 return POWER_DOMAIN_PIPE(pipe);
575 else
576 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
577}
578
579static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
580{
581 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
582 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
583 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
584 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
585 enum pipe pipe = crtc->pipe;
586 u32 pps_val = 0;
587 u32 rc_buf_thresh_dword[4];
588 u32 rc_range_params_dword[8];
589 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
590 int i = 0;
591
592 if (crtc_state->bigjoiner_pipes)
593 num_vdsc_instances *= 2;
594
595 /* Populate PICTURE_PARAMETER_SET_0 registers */
596 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
597 DSC_VER_MIN_SHIFT |
598 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
599 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
600 if (vdsc_cfg->dsc_version_minor == 2)
601 pps_val |= DSC_ALT_ICH_SEL;
602 if (vdsc_cfg->block_pred_enable)
603 pps_val |= DSC_BLOCK_PREDICTION;
604 if (vdsc_cfg->convert_rgb)
605 pps_val |= DSC_COLOR_SPACE_CONVERSION;
606 if (vdsc_cfg->simple_422)
607 pps_val |= DSC_422_ENABLE;
608 if (vdsc_cfg->vbr_enable)
609 pps_val |= DSC_VBR_ENABLE;
610 drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
611 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
612 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
613 pps_val);
614 /*
615 * If 2 VDSC instances are needed, configure PPS for second
616 * VDSC
617 */
618 if (crtc_state->dsc.dsc_split)
619 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
620 pps_val);
621 } else {
622 intel_de_write(dev_priv,
623 ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
624 pps_val);
625 if (crtc_state->dsc.dsc_split)
626 intel_de_write(dev_priv,
627 ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
628 pps_val);
629 }
630
631 /* Populate PICTURE_PARAMETER_SET_1 registers */
632 pps_val = 0;
633 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
634 drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
635 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
636 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
637 pps_val);
638 /*
639 * If 2 VDSC instances are needed, configure PPS for second
640 * VDSC
641 */
642 if (crtc_state->dsc.dsc_split)
643 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
644 pps_val);
645 } else {
646 intel_de_write(dev_priv,
647 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
648 pps_val);
649 if (crtc_state->dsc.dsc_split)
650 intel_de_write(dev_priv,
651 ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
652 pps_val);
653 }
654
655 /* Populate PICTURE_PARAMETER_SET_2 registers */
656 pps_val = 0;
657 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
658 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
659 drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
660 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
661 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
662 pps_val);
663 /*
664 * If 2 VDSC instances are needed, configure PPS for second
665 * VDSC
666 */
667 if (crtc_state->dsc.dsc_split)
668 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
669 pps_val);
670 } else {
671 intel_de_write(dev_priv,
672 ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
673 pps_val);
674 if (crtc_state->dsc.dsc_split)
675 intel_de_write(dev_priv,
676 ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
677 pps_val);
678 }
679
680 /* Populate PICTURE_PARAMETER_SET_3 registers */
681 pps_val = 0;
682 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
683 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
684 drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
685 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
686 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
687 pps_val);
688 /*
689 * If 2 VDSC instances are needed, configure PPS for second
690 * VDSC
691 */
692 if (crtc_state->dsc.dsc_split)
693 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
694 pps_val);
695 } else {
696 intel_de_write(dev_priv,
697 ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
698 pps_val);
699 if (crtc_state->dsc.dsc_split)
700 intel_de_write(dev_priv,
701 ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
702 pps_val);
703 }
704
705 /* Populate PICTURE_PARAMETER_SET_4 registers */
706 pps_val = 0;
707 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
708 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
709 drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
710 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
711 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
712 pps_val);
713 /*
714 * If 2 VDSC instances are needed, configure PPS for second
715 * VDSC
716 */
717 if (crtc_state->dsc.dsc_split)
718 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
719 pps_val);
720 } else {
721 intel_de_write(dev_priv,
722 ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
723 pps_val);
724 if (crtc_state->dsc.dsc_split)
725 intel_de_write(dev_priv,
726 ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
727 pps_val);
728 }
729
730 /* Populate PICTURE_PARAMETER_SET_5 registers */
731 pps_val = 0;
732 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
733 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
734 drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
735 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
736 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
737 pps_val);
738 /*
739 * If 2 VDSC instances are needed, configure PPS for second
740 * VDSC
741 */
742 if (crtc_state->dsc.dsc_split)
743 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
744 pps_val);
745 } else {
746 intel_de_write(dev_priv,
747 ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
748 pps_val);
749 if (crtc_state->dsc.dsc_split)
750 intel_de_write(dev_priv,
751 ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
752 pps_val);
753 }
754
755 /* Populate PICTURE_PARAMETER_SET_6 registers */
756 pps_val = 0;
757 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
758 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
759 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
760 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
761 drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
762 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
763 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
764 pps_val);
765 /*
766 * If 2 VDSC instances are needed, configure PPS for second
767 * VDSC
768 */
769 if (crtc_state->dsc.dsc_split)
770 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
771 pps_val);
772 } else {
773 intel_de_write(dev_priv,
774 ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
775 pps_val);
776 if (crtc_state->dsc.dsc_split)
777 intel_de_write(dev_priv,
778 ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
779 pps_val);
780 }
781
782 /* Populate PICTURE_PARAMETER_SET_7 registers */
783 pps_val = 0;
784 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
785 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
786 drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
787 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
788 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
789 pps_val);
790 /*
791 * If 2 VDSC instances are needed, configure PPS for second
792 * VDSC
793 */
794 if (crtc_state->dsc.dsc_split)
795 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
796 pps_val);
797 } else {
798 intel_de_write(dev_priv,
799 ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
800 pps_val);
801 if (crtc_state->dsc.dsc_split)
802 intel_de_write(dev_priv,
803 ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
804 pps_val);
805 }
806
807 /* Populate PICTURE_PARAMETER_SET_8 registers */
808 pps_val = 0;
809 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
810 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
811 drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
812 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
813 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
814 pps_val);
815 /*
816 * If 2 VDSC instances are needed, configure PPS for second
817 * VDSC
818 */
819 if (crtc_state->dsc.dsc_split)
820 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
821 pps_val);
822 } else {
823 intel_de_write(dev_priv,
824 ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
825 pps_val);
826 if (crtc_state->dsc.dsc_split)
827 intel_de_write(dev_priv,
828 ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
829 pps_val);
830 }
831
832 /* Populate PICTURE_PARAMETER_SET_9 registers */
833 pps_val = 0;
834 pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
835 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
836 drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
837 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
838 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
839 pps_val);
840 /*
841 * If 2 VDSC instances are needed, configure PPS for second
842 * VDSC
843 */
844 if (crtc_state->dsc.dsc_split)
845 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
846 pps_val);
847 } else {
848 intel_de_write(dev_priv,
849 ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
850 pps_val);
851 if (crtc_state->dsc.dsc_split)
852 intel_de_write(dev_priv,
853 ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
854 pps_val);
855 }
856
857 /* Populate PICTURE_PARAMETER_SET_10 registers */
858 pps_val = 0;
859 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
860 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
861 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
862 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
863 drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
864 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
865 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
866 pps_val);
867 /*
868 * If 2 VDSC instances are needed, configure PPS for second
869 * VDSC
870 */
871 if (crtc_state->dsc.dsc_split)
872 intel_de_write(dev_priv,
873 DSCC_PICTURE_PARAMETER_SET_10, pps_val);
874 } else {
875 intel_de_write(dev_priv,
876 ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
877 pps_val);
878 if (crtc_state->dsc.dsc_split)
879 intel_de_write(dev_priv,
880 ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
881 pps_val);
882 }
883
884 /* Populate Picture parameter set 16 */
885 pps_val = 0;
886 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
887 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
888 vdsc_cfg->slice_width) |
889 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
890 vdsc_cfg->slice_height);
891 drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
892 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
893 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
894 pps_val);
895 /*
896 * If 2 VDSC instances are needed, configure PPS for second
897 * VDSC
898 */
899 if (crtc_state->dsc.dsc_split)
900 intel_de_write(dev_priv,
901 DSCC_PICTURE_PARAMETER_SET_16, pps_val);
902 } else {
903 intel_de_write(dev_priv,
904 ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
905 pps_val);
906 if (crtc_state->dsc.dsc_split)
907 intel_de_write(dev_priv,
908 ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
909 pps_val);
910 }
911
912 /* Populate the RC_BUF_THRESH registers */
913 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
914 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
915 rc_buf_thresh_dword[i / 4] |=
916 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
917 BITS_PER_BYTE * (i % 4));
918 drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
919 rc_buf_thresh_dword[i / 4]);
920 }
921 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
922 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
923 rc_buf_thresh_dword[0]);
924 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
925 rc_buf_thresh_dword[1]);
926 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
927 rc_buf_thresh_dword[2]);
928 intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
929 rc_buf_thresh_dword[3]);
930 if (crtc_state->dsc.dsc_split) {
931 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
932 rc_buf_thresh_dword[0]);
933 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
934 rc_buf_thresh_dword[1]);
935 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
936 rc_buf_thresh_dword[2]);
937 intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
938 rc_buf_thresh_dword[3]);
939 }
940 } else {
941 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
942 rc_buf_thresh_dword[0]);
943 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
944 rc_buf_thresh_dword[1]);
945 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
946 rc_buf_thresh_dword[2]);
947 intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
948 rc_buf_thresh_dword[3]);
949 if (crtc_state->dsc.dsc_split) {
950 intel_de_write(dev_priv,
951 ICL_DSC1_RC_BUF_THRESH_0(pipe),
952 rc_buf_thresh_dword[0]);
953 intel_de_write(dev_priv,
954 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
955 rc_buf_thresh_dword[1]);
956 intel_de_write(dev_priv,
957 ICL_DSC1_RC_BUF_THRESH_1(pipe),
958 rc_buf_thresh_dword[2]);
959 intel_de_write(dev_priv,
960 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
961 rc_buf_thresh_dword[3]);
962 }
963 }
964
965 /* Populate the RC_RANGE_PARAMETERS registers */
966 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
967 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
968 rc_range_params_dword[i / 2] |=
969 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
970 RC_BPG_OFFSET_SHIFT) |
971 (vdsc_cfg->rc_range_params[i].range_max_qp <<
972 RC_MAX_QP_SHIFT) |
973 (vdsc_cfg->rc_range_params[i].range_min_qp <<
974 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
975 drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
976 rc_range_params_dword[i / 2]);
977 }
978 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
979 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
980 rc_range_params_dword[0]);
981 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
982 rc_range_params_dword[1]);
983 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
984 rc_range_params_dword[2]);
985 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
986 rc_range_params_dword[3]);
987 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
988 rc_range_params_dword[4]);
989 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
990 rc_range_params_dword[5]);
991 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
992 rc_range_params_dword[6]);
993 intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
994 rc_range_params_dword[7]);
995 if (crtc_state->dsc.dsc_split) {
996 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
997 rc_range_params_dword[0]);
998 intel_de_write(dev_priv,
999 DSCC_RC_RANGE_PARAMETERS_0_UDW,
1000 rc_range_params_dword[1]);
1001 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
1002 rc_range_params_dword[2]);
1003 intel_de_write(dev_priv,
1004 DSCC_RC_RANGE_PARAMETERS_1_UDW,
1005 rc_range_params_dword[3]);
1006 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
1007 rc_range_params_dword[4]);
1008 intel_de_write(dev_priv,
1009 DSCC_RC_RANGE_PARAMETERS_2_UDW,
1010 rc_range_params_dword[5]);
1011 intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
1012 rc_range_params_dword[6]);
1013 intel_de_write(dev_priv,
1014 DSCC_RC_RANGE_PARAMETERS_3_UDW,
1015 rc_range_params_dword[7]);
1016 }
1017 } else {
1018 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
1019 rc_range_params_dword[0]);
1020 intel_de_write(dev_priv,
1021 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
1022 rc_range_params_dword[1]);
1023 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
1024 rc_range_params_dword[2]);
1025 intel_de_write(dev_priv,
1026 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
1027 rc_range_params_dword[3]);
1028 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
1029 rc_range_params_dword[4]);
1030 intel_de_write(dev_priv,
1031 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
1032 rc_range_params_dword[5]);
1033 intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
1034 rc_range_params_dword[6]);
1035 intel_de_write(dev_priv,
1036 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
1037 rc_range_params_dword[7]);
1038 if (crtc_state->dsc.dsc_split) {
1039 intel_de_write(dev_priv,
1040 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
1041 rc_range_params_dword[0]);
1042 intel_de_write(dev_priv,
1043 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
1044 rc_range_params_dword[1]);
1045 intel_de_write(dev_priv,
1046 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
1047 rc_range_params_dword[2]);
1048 intel_de_write(dev_priv,
1049 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
1050 rc_range_params_dword[3]);
1051 intel_de_write(dev_priv,
1052 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
1053 rc_range_params_dword[4]);
1054 intel_de_write(dev_priv,
1055 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
1056 rc_range_params_dword[5]);
1057 intel_de_write(dev_priv,
1058 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
1059 rc_range_params_dword[6]);
1060 intel_de_write(dev_priv,
1061 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
1062 rc_range_params_dword[7]);
1063 }
1064 }
1065}
1066
1067void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
1068 const struct intel_crtc_state *crtc_state)
1069{
1070 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1071 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1072 struct mipi_dsi_device *dsi;
1073 struct drm_dsc_picture_parameter_set pps;
1074 enum port port;
1075
1076 if (!crtc_state->dsc.compression_enable)
1077 return;
1078
1079 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
1080
1081 for_each_dsi_port(port, intel_dsi->ports) {
1082 dsi = intel_dsi->dsi_hosts[port]->device;
1083
1084 mipi_dsi_picture_parameter_set(dsi, &pps);
1085 mipi_dsi_compression_mode(dsi, true);
1086 }
1087}
1088
1089void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
1090 const struct intel_crtc_state *crtc_state)
1091{
1092 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1093 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1094 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1095
1096 if (!crtc_state->dsc.compression_enable)
1097 return;
1098
1099 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1100 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
1101
1102 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1103 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
1104
1105 dig_port->write_infoframe(encoder, crtc_state,
1106 DP_SDP_PPS, &dp_dsc_pps_sdp,
1107 sizeof(dp_dsc_pps_sdp));
1108}
1109
1110static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1111{
1112 return is_pipe_dsc(crtc, cpu_transcoder) ?
1113 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
1114}
1115
1116static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
1117{
1118 return is_pipe_dsc(crtc, cpu_transcoder) ?
1119 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
1120}
1121
1122void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
1123{
1124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1125 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1126 u32 dss_ctl1_val = 0;
1127
1128 if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) {
1129 if (intel_crtc_is_bigjoiner_slave(crtc_state))
1130 dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE;
1131 else
1132 dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER;
1133
1134 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1135 }
1136}
1137
1138void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
1139{
1140 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1141 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1142 u32 dss_ctl1_val = 0;
1143 u32 dss_ctl2_val = 0;
1144
1145 if (!crtc_state->dsc.compression_enable)
1146 return;
1147
1148 intel_dsc_pps_configure(crtc_state);
1149
1150 dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1151 if (crtc_state->dsc.dsc_split) {
1152 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1153 dss_ctl1_val |= JOINER_ENABLE;
1154 }
1155 if (crtc_state->bigjoiner_pipes) {
1156 dss_ctl1_val |= BIG_JOINER_ENABLE;
1157 if (!intel_crtc_is_bigjoiner_slave(crtc_state))
1158 dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE;
1159 }
1160 intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
1161 intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
1162}
1163
1164void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1165{
1166 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1167 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1168
1169 /* Disable only if either of them is enabled */
1170 if (old_crtc_state->dsc.compression_enable ||
1171 old_crtc_state->bigjoiner_pipes) {
1172 intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1173 intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
1174 }
1175}
1176
1177void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1178{
1179 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1181 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1182 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1183 enum pipe pipe = crtc->pipe;
1184 enum intel_display_power_domain power_domain;
1185 intel_wakeref_t wakeref;
1186 u32 dss_ctl1, dss_ctl2, val;
1187
1188 if (!intel_dsc_source_support(crtc_state))
1189 return;
1190
1191 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
1192
1193 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1194 if (!wakeref)
1195 return;
1196
1197 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
1198 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
1199
1200 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
1201 if (!crtc_state->dsc.compression_enable)
1202 goto out;
1203
1204 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
1205 (dss_ctl1 & JOINER_ENABLE);
1206
1207 /* FIXME: add more state readout as needed */
1208
1209 /* PPS1 */
1210 if (!is_pipe_dsc(crtc, cpu_transcoder))
1211 val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
1212 else
1213 val = intel_de_read(dev_priv,
1214 ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
1215 vdsc_cfg->bits_per_pixel = val;
1216 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
1217out:
1218 intel_display_power_put(dev_priv, power_domain, wakeref);
1219}