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1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29
30#include <linux/export.h>
31#include <linux/i2c-algo-bit.h>
32#include <linux/i2c.h>
33
34#include <drm/display/drm_hdcp_helper.h>
35
36#include "i915_drv.h"
37#include "i915_irq.h"
38#include "i915_reg.h"
39#include "intel_de.h"
40#include "intel_display_types.h"
41#include "intel_gmbus.h"
42#include "intel_gmbus_regs.h"
43
44struct intel_gmbus {
45 struct i2c_adapter adapter;
46#define GMBUS_FORCE_BIT_RETRY (1U << 31)
47 u32 force_bit;
48 u32 reg0;
49 i915_reg_t gpio_reg;
50 struct i2c_algo_bit_data bit_algo;
51 struct drm_i915_private *i915;
52};
53
54enum gmbus_gpio {
55 GPIOA,
56 GPIOB,
57 GPIOC,
58 GPIOD,
59 GPIOE,
60 GPIOF,
61 GPIOG,
62 GPIOH,
63 __GPIOI_UNUSED,
64 GPIOJ,
65 GPIOK,
66 GPIOL,
67 GPIOM,
68 GPION,
69 GPIOO,
70};
71
72struct gmbus_pin {
73 const char *name;
74 enum gmbus_gpio gpio;
75};
76
77/* Map gmbus pin pairs to names and registers. */
78static const struct gmbus_pin gmbus_pins[] = {
79 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
81 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
82 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
83 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
84 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
85};
86
87static const struct gmbus_pin gmbus_pins_bdw[] = {
88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
89 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
90 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
91 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
92};
93
94static const struct gmbus_pin gmbus_pins_skl[] = {
95 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
96 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
97 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
98};
99
100static const struct gmbus_pin gmbus_pins_bxt[] = {
101 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
102 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
103 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
104};
105
106static const struct gmbus_pin gmbus_pins_cnp[] = {
107 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
108 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
109 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
110 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
111};
112
113static const struct gmbus_pin gmbus_pins_icp[] = {
114 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
115 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
116 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
118 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
119 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
120 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
121 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
122 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
123};
124
125static const struct gmbus_pin gmbus_pins_dg1[] = {
126 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
127 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
128 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
129 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
130};
131
132static const struct gmbus_pin gmbus_pins_dg2[] = {
133 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
134 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
135 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
136 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
137 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
138};
139
140static const struct gmbus_pin gmbus_pins_mtp[] = {
141 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
142 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
143 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
144 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
145 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
146 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
147 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
148 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
149 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
150};
151
152static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
153 unsigned int pin)
154{
155 const struct gmbus_pin *pins;
156 size_t size;
157
158 if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
159 pins = gmbus_pins_dg2;
160 size = ARRAY_SIZE(gmbus_pins_dg2);
161 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
162 pins = gmbus_pins_dg1;
163 size = ARRAY_SIZE(gmbus_pins_dg1);
164 } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
165 pins = gmbus_pins_mtp;
166 size = ARRAY_SIZE(gmbus_pins_mtp);
167 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
168 pins = gmbus_pins_icp;
169 size = ARRAY_SIZE(gmbus_pins_icp);
170 } else if (HAS_PCH_CNP(i915)) {
171 pins = gmbus_pins_cnp;
172 size = ARRAY_SIZE(gmbus_pins_cnp);
173 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
174 pins = gmbus_pins_bxt;
175 size = ARRAY_SIZE(gmbus_pins_bxt);
176 } else if (DISPLAY_VER(i915) == 9) {
177 pins = gmbus_pins_skl;
178 size = ARRAY_SIZE(gmbus_pins_skl);
179 } else if (IS_BROADWELL(i915)) {
180 pins = gmbus_pins_bdw;
181 size = ARRAY_SIZE(gmbus_pins_bdw);
182 } else {
183 pins = gmbus_pins;
184 size = ARRAY_SIZE(gmbus_pins);
185 }
186
187 if (pin >= size || !pins[pin].name)
188 return NULL;
189
190 return &pins[pin];
191}
192
193bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
194{
195 return get_gmbus_pin(i915, pin);
196}
197
198/* Intel GPIO access functions */
199
200#define I2C_RISEFALL_TIME 10
201
202static inline struct intel_gmbus *
203to_intel_gmbus(struct i2c_adapter *i2c)
204{
205 return container_of(i2c, struct intel_gmbus, adapter);
206}
207
208void
209intel_gmbus_reset(struct drm_i915_private *i915)
210{
211 intel_de_write(i915, GMBUS0(i915), 0);
212 intel_de_write(i915, GMBUS4(i915), 0);
213}
214
215static void pnv_gmbus_clock_gating(struct drm_i915_private *i915,
216 bool enable)
217{
218 u32 val;
219
220 /* When using bit bashing for I2C, this bit needs to be set to 1 */
221 val = intel_de_read(i915, DSPCLK_GATE_D(i915));
222 if (!enable)
223 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
224 else
225 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
226 intel_de_write(i915, DSPCLK_GATE_D(i915), val);
227}
228
229static void pch_gmbus_clock_gating(struct drm_i915_private *i915,
230 bool enable)
231{
232 u32 val;
233
234 val = intel_de_read(i915, SOUTH_DSPCLK_GATE_D);
235 if (!enable)
236 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
237 else
238 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
239 intel_de_write(i915, SOUTH_DSPCLK_GATE_D, val);
240}
241
242static void bxt_gmbus_clock_gating(struct drm_i915_private *i915,
243 bool enable)
244{
245 u32 val;
246
247 val = intel_de_read(i915, GEN9_CLKGATE_DIS_4);
248 if (!enable)
249 val |= BXT_GMBUS_GATING_DIS;
250 else
251 val &= ~BXT_GMBUS_GATING_DIS;
252 intel_de_write(i915, GEN9_CLKGATE_DIS_4, val);
253}
254
255static u32 get_reserved(struct intel_gmbus *bus)
256{
257 struct drm_i915_private *i915 = bus->i915;
258 struct intel_uncore *uncore = &i915->uncore;
259 u32 reserved = 0;
260
261 /* On most chips, these bits must be preserved in software. */
262 if (!IS_I830(i915) && !IS_I845G(i915))
263 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
264 (GPIO_DATA_PULLUP_DISABLE |
265 GPIO_CLOCK_PULLUP_DISABLE);
266
267 return reserved;
268}
269
270static int get_clock(void *data)
271{
272 struct intel_gmbus *bus = data;
273 struct intel_uncore *uncore = &bus->i915->uncore;
274 u32 reserved = get_reserved(bus);
275
276 intel_uncore_write_notrace(uncore,
277 bus->gpio_reg,
278 reserved | GPIO_CLOCK_DIR_MASK);
279 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
280
281 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
282 GPIO_CLOCK_VAL_IN) != 0;
283}
284
285static int get_data(void *data)
286{
287 struct intel_gmbus *bus = data;
288 struct intel_uncore *uncore = &bus->i915->uncore;
289 u32 reserved = get_reserved(bus);
290
291 intel_uncore_write_notrace(uncore,
292 bus->gpio_reg,
293 reserved | GPIO_DATA_DIR_MASK);
294 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
295
296 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
297 GPIO_DATA_VAL_IN) != 0;
298}
299
300static void set_clock(void *data, int state_high)
301{
302 struct intel_gmbus *bus = data;
303 struct intel_uncore *uncore = &bus->i915->uncore;
304 u32 reserved = get_reserved(bus);
305 u32 clock_bits;
306
307 if (state_high)
308 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
309 else
310 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
311 GPIO_CLOCK_VAL_MASK;
312
313 intel_uncore_write_notrace(uncore,
314 bus->gpio_reg,
315 reserved | clock_bits);
316 intel_uncore_posting_read(uncore, bus->gpio_reg);
317}
318
319static void set_data(void *data, int state_high)
320{
321 struct intel_gmbus *bus = data;
322 struct intel_uncore *uncore = &bus->i915->uncore;
323 u32 reserved = get_reserved(bus);
324 u32 data_bits;
325
326 if (state_high)
327 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
328 else
329 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
330 GPIO_DATA_VAL_MASK;
331
332 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
333 intel_uncore_posting_read(uncore, bus->gpio_reg);
334}
335
336static int
337intel_gpio_pre_xfer(struct i2c_adapter *adapter)
338{
339 struct intel_gmbus *bus = to_intel_gmbus(adapter);
340 struct drm_i915_private *i915 = bus->i915;
341
342 intel_gmbus_reset(i915);
343
344 if (IS_PINEVIEW(i915))
345 pnv_gmbus_clock_gating(i915, false);
346
347 set_data(bus, 1);
348 set_clock(bus, 1);
349 udelay(I2C_RISEFALL_TIME);
350 return 0;
351}
352
353static void
354intel_gpio_post_xfer(struct i2c_adapter *adapter)
355{
356 struct intel_gmbus *bus = to_intel_gmbus(adapter);
357 struct drm_i915_private *i915 = bus->i915;
358
359 set_data(bus, 1);
360 set_clock(bus, 1);
361
362 if (IS_PINEVIEW(i915))
363 pnv_gmbus_clock_gating(i915, true);
364}
365
366static void
367intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
368{
369 struct i2c_algo_bit_data *algo;
370
371 algo = &bus->bit_algo;
372
373 bus->gpio_reg = gpio_reg;
374 bus->adapter.algo_data = algo;
375 algo->setsda = set_data;
376 algo->setscl = set_clock;
377 algo->getsda = get_data;
378 algo->getscl = get_clock;
379 algo->pre_xfer = intel_gpio_pre_xfer;
380 algo->post_xfer = intel_gpio_post_xfer;
381 algo->udelay = I2C_RISEFALL_TIME;
382 algo->timeout = usecs_to_jiffies(2200);
383 algo->data = bus;
384}
385
386static bool has_gmbus_irq(struct drm_i915_private *i915)
387{
388 /*
389 * encoder->shutdown() may want to use GMBUS
390 * after irqs have already been disabled.
391 */
392 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
393}
394
395static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
396{
397 DEFINE_WAIT(wait);
398 u32 gmbus2;
399 int ret;
400
401 /* Important: The hw handles only the first bit, so set only one! Since
402 * we also need to check for NAKs besides the hw ready/idle signal, we
403 * need to wake up periodically and check that ourselves.
404 */
405 if (!has_gmbus_irq(i915))
406 irq_en = 0;
407
408 add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
409 intel_de_write_fw(i915, GMBUS4(i915), irq_en);
410
411 status |= GMBUS_SATOER;
412 ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
413 2);
414 if (ret)
415 ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
416 50);
417
418 intel_de_write_fw(i915, GMBUS4(i915), 0);
419 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
420
421 if (gmbus2 & GMBUS_SATOER)
422 return -ENXIO;
423
424 return ret;
425}
426
427static int
428gmbus_wait_idle(struct drm_i915_private *i915)
429{
430 DEFINE_WAIT(wait);
431 u32 irq_enable;
432 int ret;
433
434 /* Important: The hw handles only the first bit, so set only one! */
435 irq_enable = 0;
436 if (has_gmbus_irq(i915))
437 irq_enable = GMBUS_IDLE_EN;
438
439 add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
440 intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
441
442 ret = intel_wait_for_register_fw(&i915->uncore,
443 GMBUS2(i915), GMBUS_ACTIVE, 0,
444 10);
445
446 intel_de_write_fw(i915, GMBUS4(i915), 0);
447 remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
448
449 return ret;
450}
451
452static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915)
453{
454 return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
455 GMBUS_BYTE_COUNT_MAX;
456}
457
458static int
459gmbus_xfer_read_chunk(struct drm_i915_private *i915,
460 unsigned short addr, u8 *buf, unsigned int len,
461 u32 gmbus0_reg, u32 gmbus1_index)
462{
463 unsigned int size = len;
464 bool burst_read = len > gmbus_max_xfer_size(i915);
465 bool extra_byte_added = false;
466
467 if (burst_read) {
468 /*
469 * As per HW Spec, for 512Bytes need to read extra Byte and
470 * Ignore the extra byte read.
471 */
472 if (len == 512) {
473 extra_byte_added = true;
474 len++;
475 }
476 size = len % 256 + 256;
477 intel_de_write_fw(i915, GMBUS0(i915),
478 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
479 }
480
481 intel_de_write_fw(i915, GMBUS1(i915),
482 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
483 while (len) {
484 int ret;
485 u32 val, loop = 0;
486
487 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
488 if (ret)
489 return ret;
490
491 val = intel_de_read_fw(i915, GMBUS3(i915));
492 do {
493 if (extra_byte_added && len == 1)
494 break;
495
496 *buf++ = val & 0xff;
497 val >>= 8;
498 } while (--len && ++loop < 4);
499
500 if (burst_read && len == size - 4)
501 /* Reset the override bit */
502 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg);
503 }
504
505 return 0;
506}
507
508/*
509 * HW spec says that 512Bytes in Burst read need special treatment.
510 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
511 * an I2C slave, which supports such a lengthy burst read too for experiments.
512 *
513 * So until things get clarified on HW support, to avoid the burst read length
514 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
515 */
516#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
517
518static int
519gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
520 u32 gmbus0_reg, u32 gmbus1_index)
521{
522 u8 *buf = msg->buf;
523 unsigned int rx_size = msg->len;
524 unsigned int len;
525 int ret;
526
527 do {
528 if (HAS_GMBUS_BURST_READ(i915))
529 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
530 else
531 len = min(rx_size, gmbus_max_xfer_size(i915));
532
533 ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len,
534 gmbus0_reg, gmbus1_index);
535 if (ret)
536 return ret;
537
538 rx_size -= len;
539 buf += len;
540 } while (rx_size != 0);
541
542 return 0;
543}
544
545static int
546gmbus_xfer_write_chunk(struct drm_i915_private *i915,
547 unsigned short addr, u8 *buf, unsigned int len,
548 u32 gmbus1_index)
549{
550 unsigned int chunk_size = len;
551 u32 val, loop;
552
553 val = loop = 0;
554 while (len && loop < 4) {
555 val |= *buf++ << (8 * loop++);
556 len -= 1;
557 }
558
559 intel_de_write_fw(i915, GMBUS3(i915), val);
560 intel_de_write_fw(i915, GMBUS1(i915),
561 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
562 while (len) {
563 int ret;
564
565 val = loop = 0;
566 do {
567 val |= *buf++ << (8 * loop);
568 } while (--len && ++loop < 4);
569
570 intel_de_write_fw(i915, GMBUS3(i915), val);
571
572 ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
573 if (ret)
574 return ret;
575 }
576
577 return 0;
578}
579
580static int
581gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
582 u32 gmbus1_index)
583{
584 u8 *buf = msg->buf;
585 unsigned int tx_size = msg->len;
586 unsigned int len;
587 int ret;
588
589 do {
590 len = min(tx_size, gmbus_max_xfer_size(i915));
591
592 ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len,
593 gmbus1_index);
594 if (ret)
595 return ret;
596
597 buf += len;
598 tx_size -= len;
599 } while (tx_size != 0);
600
601 return 0;
602}
603
604/*
605 * The gmbus controller can combine a 1 or 2 byte write with another read/write
606 * that immediately follows it by using an "INDEX" cycle.
607 */
608static bool
609gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
610{
611 return (i + 1 < num &&
612 msgs[i].addr == msgs[i + 1].addr &&
613 !(msgs[i].flags & I2C_M_RD) &&
614 (msgs[i].len == 1 || msgs[i].len == 2) &&
615 msgs[i + 1].len > 0);
616}
617
618static int
619gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
620 u32 gmbus0_reg)
621{
622 u32 gmbus1_index = 0;
623 u32 gmbus5 = 0;
624 int ret;
625
626 if (msgs[0].len == 2)
627 gmbus5 = GMBUS_2BYTE_INDEX_EN |
628 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
629 if (msgs[0].len == 1)
630 gmbus1_index = GMBUS_CYCLE_INDEX |
631 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
632
633 /* GMBUS5 holds 16-bit index */
634 if (gmbus5)
635 intel_de_write_fw(i915, GMBUS5(i915), gmbus5);
636
637 if (msgs[1].flags & I2C_M_RD)
638 ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg,
639 gmbus1_index);
640 else
641 ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index);
642
643 /* Clear GMBUS5 after each index transfer */
644 if (gmbus5)
645 intel_de_write_fw(i915, GMBUS5(i915), 0);
646
647 return ret;
648}
649
650static int
651do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
652 u32 gmbus0_source)
653{
654 struct intel_gmbus *bus = to_intel_gmbus(adapter);
655 struct drm_i915_private *i915 = bus->i915;
656 int i = 0, inc, try = 0;
657 int ret = 0;
658
659 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
660 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
661 bxt_gmbus_clock_gating(i915, false);
662 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
663 pch_gmbus_clock_gating(i915, false);
664
665retry:
666 intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0);
667
668 for (; i < num; i += inc) {
669 inc = 1;
670 if (gmbus_is_index_xfer(msgs, i, num)) {
671 ret = gmbus_index_xfer(i915, &msgs[i],
672 gmbus0_source | bus->reg0);
673 inc = 2; /* an index transmission is two msgs */
674 } else if (msgs[i].flags & I2C_M_RD) {
675 ret = gmbus_xfer_read(i915, &msgs[i],
676 gmbus0_source | bus->reg0, 0);
677 } else {
678 ret = gmbus_xfer_write(i915, &msgs[i], 0);
679 }
680
681 if (!ret)
682 ret = gmbus_wait(i915,
683 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
684 if (ret == -ETIMEDOUT)
685 goto timeout;
686 else if (ret)
687 goto clear_err;
688 }
689
690 /* Generate a STOP condition on the bus. Note that gmbus can't generata
691 * a STOP on the very first cycle. To simplify the code we
692 * unconditionally generate the STOP condition with an additional gmbus
693 * cycle. */
694 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
695
696 /* Mark the GMBUS interface as disabled after waiting for idle.
697 * We will re-enable it at the start of the next xfer,
698 * till then let it sleep.
699 */
700 if (gmbus_wait_idle(i915)) {
701 drm_dbg_kms(&i915->drm,
702 "GMBUS [%s] timed out waiting for idle\n",
703 adapter->name);
704 ret = -ETIMEDOUT;
705 }
706 intel_de_write_fw(i915, GMBUS0(i915), 0);
707 ret = ret ?: i;
708 goto out;
709
710clear_err:
711 /*
712 * Wait for bus to IDLE before clearing NAK.
713 * If we clear the NAK while bus is still active, then it will stay
714 * active and the next transaction may fail.
715 *
716 * If no ACK is received during the address phase of a transaction, the
717 * adapter must report -ENXIO. It is not clear what to return if no ACK
718 * is received at other times. But we have to be careful to not return
719 * spurious -ENXIO because that will prevent i2c and drm edid functions
720 * from retrying. So return -ENXIO only when gmbus properly quiescents -
721 * timing out seems to happen when there _is_ a ddc chip present, but
722 * it's slow responding and only answers on the 2nd retry.
723 */
724 ret = -ENXIO;
725 if (gmbus_wait_idle(i915)) {
726 drm_dbg_kms(&i915->drm,
727 "GMBUS [%s] timed out after NAK\n",
728 adapter->name);
729 ret = -ETIMEDOUT;
730 }
731
732 /* Toggle the Software Clear Interrupt bit. This has the effect
733 * of resetting the GMBUS controller and so clearing the
734 * BUS_ERROR raised by the slave's NAK.
735 */
736 intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
737 intel_de_write_fw(i915, GMBUS1(i915), 0);
738 intel_de_write_fw(i915, GMBUS0(i915), 0);
739
740 drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
741 adapter->name, msgs[i].addr,
742 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
743
744 /*
745 * Passive adapters sometimes NAK the first probe. Retry the first
746 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
747 * has retries internally. See also the retry loop in
748 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
749 */
750 if (ret == -ENXIO && i == 0 && try++ == 0) {
751 drm_dbg_kms(&i915->drm,
752 "GMBUS [%s] NAK on first message, retry\n",
753 adapter->name);
754 goto retry;
755 }
756
757 goto out;
758
759timeout:
760 drm_dbg_kms(&i915->drm,
761 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
762 bus->adapter.name, bus->reg0 & 0xff);
763 intel_de_write_fw(i915, GMBUS0(i915), 0);
764
765 /*
766 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
767 * instead. Use EAGAIN to have i2c core retry.
768 */
769 ret = -EAGAIN;
770
771out:
772 /* Display WA #0868: skl,bxt,kbl,cfl,glk */
773 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
774 bxt_gmbus_clock_gating(i915, true);
775 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
776 pch_gmbus_clock_gating(i915, true);
777
778 return ret;
779}
780
781static int
782gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
783{
784 struct intel_gmbus *bus = to_intel_gmbus(adapter);
785 struct drm_i915_private *i915 = bus->i915;
786 intel_wakeref_t wakeref;
787 int ret;
788
789 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
790
791 if (bus->force_bit) {
792 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
793 if (ret < 0)
794 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
795 } else {
796 ret = do_gmbus_xfer(adapter, msgs, num, 0);
797 if (ret == -EAGAIN)
798 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
799 }
800
801 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
802
803 return ret;
804}
805
806int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
807{
808 struct intel_gmbus *bus = to_intel_gmbus(adapter);
809 struct drm_i915_private *i915 = bus->i915;
810 u8 cmd = DRM_HDCP_DDC_AKSV;
811 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
812 struct i2c_msg msgs[] = {
813 {
814 .addr = DRM_HDCP_DDC_ADDR,
815 .flags = 0,
816 .len = sizeof(cmd),
817 .buf = &cmd,
818 },
819 {
820 .addr = DRM_HDCP_DDC_ADDR,
821 .flags = 0,
822 .len = sizeof(buf),
823 .buf = buf,
824 }
825 };
826 intel_wakeref_t wakeref;
827 int ret;
828
829 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
830 mutex_lock(&i915->display.gmbus.mutex);
831
832 /*
833 * In order to output Aksv to the receiver, use an indexed write to
834 * pass the i2c command, and tell GMBUS to use the HW-provided value
835 * instead of sourcing GMBUS3 for the data.
836 */
837 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
838
839 mutex_unlock(&i915->display.gmbus.mutex);
840 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
841
842 return ret;
843}
844
845static u32 gmbus_func(struct i2c_adapter *adapter)
846{
847 return i2c_bit_algo.functionality(adapter) &
848 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
849 /* I2C_FUNC_10BIT_ADDR | */
850 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
851 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
852}
853
854static const struct i2c_algorithm gmbus_algorithm = {
855 .master_xfer = gmbus_xfer,
856 .functionality = gmbus_func
857};
858
859static void gmbus_lock_bus(struct i2c_adapter *adapter,
860 unsigned int flags)
861{
862 struct intel_gmbus *bus = to_intel_gmbus(adapter);
863 struct drm_i915_private *i915 = bus->i915;
864
865 mutex_lock(&i915->display.gmbus.mutex);
866}
867
868static int gmbus_trylock_bus(struct i2c_adapter *adapter,
869 unsigned int flags)
870{
871 struct intel_gmbus *bus = to_intel_gmbus(adapter);
872 struct drm_i915_private *i915 = bus->i915;
873
874 return mutex_trylock(&i915->display.gmbus.mutex);
875}
876
877static void gmbus_unlock_bus(struct i2c_adapter *adapter,
878 unsigned int flags)
879{
880 struct intel_gmbus *bus = to_intel_gmbus(adapter);
881 struct drm_i915_private *i915 = bus->i915;
882
883 mutex_unlock(&i915->display.gmbus.mutex);
884}
885
886static const struct i2c_lock_operations gmbus_lock_ops = {
887 .lock_bus = gmbus_lock_bus,
888 .trylock_bus = gmbus_trylock_bus,
889 .unlock_bus = gmbus_unlock_bus,
890};
891
892/**
893 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
894 * @i915: i915 device private
895 */
896int intel_gmbus_setup(struct drm_i915_private *i915)
897{
898 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
899 unsigned int pin;
900 int ret;
901
902 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
903 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
904 else if (!HAS_GMCH(i915))
905 /*
906 * Broxton uses the same PCH offsets for South Display Engine,
907 * even though it doesn't have a PCH.
908 */
909 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
910
911 mutex_init(&i915->display.gmbus.mutex);
912 init_waitqueue_head(&i915->display.gmbus.wait_queue);
913
914 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
915 const struct gmbus_pin *gmbus_pin;
916 struct intel_gmbus *bus;
917
918 gmbus_pin = get_gmbus_pin(i915, pin);
919 if (!gmbus_pin)
920 continue;
921
922 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
923 if (!bus) {
924 ret = -ENOMEM;
925 goto err;
926 }
927
928 bus->adapter.owner = THIS_MODULE;
929 bus->adapter.class = I2C_CLASS_DDC;
930 snprintf(bus->adapter.name,
931 sizeof(bus->adapter.name),
932 "i915 gmbus %s", gmbus_pin->name);
933
934 bus->adapter.dev.parent = &pdev->dev;
935 bus->i915 = i915;
936
937 bus->adapter.algo = &gmbus_algorithm;
938 bus->adapter.lock_ops = &gmbus_lock_ops;
939
940 /*
941 * We wish to retry with bit banging
942 * after a timed out GMBUS attempt.
943 */
944 bus->adapter.retries = 1;
945
946 /* By default use a conservative clock rate */
947 bus->reg0 = pin | GMBUS_RATE_100KHZ;
948
949 /* gmbus seems to be broken on i830 */
950 if (IS_I830(i915))
951 bus->force_bit = 1;
952
953 intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio));
954
955 ret = i2c_add_adapter(&bus->adapter);
956 if (ret) {
957 kfree(bus);
958 goto err;
959 }
960
961 i915->display.gmbus.bus[pin] = bus;
962 }
963
964 intel_gmbus_reset(i915);
965
966 return 0;
967
968err:
969 intel_gmbus_teardown(i915);
970
971 return ret;
972}
973
974struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915,
975 unsigned int pin)
976{
977 if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
978 !i915->display.gmbus.bus[pin]))
979 return NULL;
980
981 return &i915->display.gmbus.bus[pin]->adapter;
982}
983
984void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
985{
986 struct intel_gmbus *bus = to_intel_gmbus(adapter);
987 struct drm_i915_private *i915 = bus->i915;
988
989 mutex_lock(&i915->display.gmbus.mutex);
990
991 bus->force_bit += force_bit ? 1 : -1;
992 drm_dbg_kms(&i915->drm,
993 "%sabling bit-banging on %s. force bit now %d\n",
994 force_bit ? "en" : "dis", adapter->name,
995 bus->force_bit);
996
997 mutex_unlock(&i915->display.gmbus.mutex);
998}
999
1000bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1001{
1002 struct intel_gmbus *bus = to_intel_gmbus(adapter);
1003
1004 return bus->force_bit;
1005}
1006
1007void intel_gmbus_teardown(struct drm_i915_private *i915)
1008{
1009 unsigned int pin;
1010
1011 for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
1012 struct intel_gmbus *bus;
1013
1014 bus = i915->display.gmbus.bus[pin];
1015 if (!bus)
1016 continue;
1017
1018 i2c_del_adapter(&bus->adapter);
1019
1020 kfree(bus);
1021 i915->display.gmbus.bus[pin] = NULL;
1022 }
1023}