1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2022 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_DMC_REGS_H__
 7#define __INTEL_DMC_REGS_H__
 8
 9#include "i915_reg_defs.h"
10
11#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
12#define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
13
14#define _ADLP_PIPEDMC_REG_MMIO_BASE_A	0x5f000
15#define _TGL_PIPEDMC_REG_MMIO_BASE_A	0x92000
16
17#define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \
18	((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \
19				    _TGL_PIPEDMC_REG_MMIO_BASE_A) + \
20	 0x400 * ((dmc_id) - 1))
21
22#define __DMC_REG_MMIO_BASE		0x8f000
23
24#define _DMC_REG_MMIO_BASE(i915, dmc_id) \
25	((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \
26				   __PIPEDMC_REG_MMIO_BASE(i915, dmc_id))
27
28#define _DMC_REG(i915, dmc_id, reg) \
29	((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id))
30
31#define DMC_EVENT_HANDLER_COUNT_GEN12	8
32
33#define _DMC_EVT_HTP_0			0x8f004
34
35#define DMC_EVT_HTP(i915, dmc_id, handler) \
36	_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))
37
38#define _DMC_EVT_CTL_0			0x8f034
39
40#define DMC_EVT_CTL(i915, dmc_id, handler) \
41	_MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))
42
43#define DMC_EVT_CTL_ENABLE		REG_BIT(31)
44#define DMC_EVT_CTL_RECURRING		REG_BIT(30)
45#define DMC_EVT_CTL_TYPE_MASK		REG_GENMASK(17, 16)
46#define DMC_EVT_CTL_TYPE_LEVEL_0	0
47#define DMC_EVT_CTL_TYPE_LEVEL_1	1
48#define DMC_EVT_CTL_TYPE_EDGE_1_0	2
49#define DMC_EVT_CTL_TYPE_EDGE_0_1	3
50
51#define DMC_EVT_CTL_EVENT_ID_MASK	REG_GENMASK(15, 8)
52#define DMC_EVT_CTL_EVENT_ID_FALSE	0x01
53/* An event handler scheduled to run at a 1 kHz frequency. */
54#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC	0xbf
55
56#define DMC_HTP_ADDR_SKL	0x00500034
57#define DMC_SSP_BASE		_MMIO(0x8F074)
58#define DMC_HTP_SKL		_MMIO(0x8F004)
59#define DMC_LAST_WRITE		_MMIO(0x8F034)
60#define DMC_LAST_WRITE_VALUE	0xc003b400
61#define DMC_MMIO_START_RANGE	0x80000
62#define DMC_MMIO_END_RANGE     0x8FFFF
63#define DMC_V1_MMIO_START_RANGE		0x80000
64#define TGL_MAIN_MMIO_START		0x8F000
65#define TGL_MAIN_MMIO_END		0x8FFFF
66#define _TGL_PIPEA_MMIO_START		0x92000
67#define _TGL_PIPEA_MMIO_END		0x93FFF
68#define _TGL_PIPEB_MMIO_START		0x96000
69#define _TGL_PIPEB_MMIO_END		0x97FFF
70#define ADLP_PIPE_MMIO_START		0x5F000
71#define ADLP_PIPE_MMIO_END		0x5FFFF
72
73#define TGL_PIPE_MMIO_START(dmc_id)	_PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\
74					      _TGL_PIPEB_MMIO_START)
75
76#define TGL_PIPE_MMIO_END(dmc_id)	_PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\
77					      _TGL_PIPEB_MMIO_END)
78
79#define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
80#define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
81#define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
82#define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
83#define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
84#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
85
86#define TGL_DMC_DEBUG3		_MMIO(0x101090)
87#define DG1_DMC_DEBUG3		_MMIO(0x13415c)
88
89#endif /* __INTEL_DMC_REGS_H__ */