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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#include "i915_drv.h"
7#include "intel_crtc_state_dump.h"
8#include "intel_display_types.h"
9#include "intel_hdmi.h"
10#include "intel_vrr.h"
11
12static void intel_dump_crtc_timings(struct drm_i915_private *i915,
13 const struct drm_display_mode *mode)
14{
15 drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
16 "type: 0x%x flags: 0x%x\n",
17 mode->crtc_clock,
18 mode->crtc_hdisplay, mode->crtc_hsync_start,
19 mode->crtc_hsync_end, mode->crtc_htotal,
20 mode->crtc_vdisplay, mode->crtc_vsync_start,
21 mode->crtc_vsync_end, mode->crtc_vtotal,
22 mode->type, mode->flags);
23}
24
25static void
26intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
27 const char *id, unsigned int lane_count,
28 const struct intel_link_m_n *m_n)
29{
30 struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
31
32 drm_dbg_kms(&i915->drm,
33 "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
34 id, lane_count,
35 m_n->data_m, m_n->data_n,
36 m_n->link_m, m_n->link_n, m_n->tu);
37}
38
39static void
40intel_dump_infoframe(struct drm_i915_private *i915,
41 const union hdmi_infoframe *frame)
42{
43 if (!drm_debug_enabled(DRM_UT_KMS))
44 return;
45
46 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);
47}
48
49static void
50intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
51 const struct drm_dp_vsc_sdp *vsc)
52{
53 if (!drm_debug_enabled(DRM_UT_KMS))
54 return;
55
56 drm_dp_vsc_sdp_log(KERN_DEBUG, i915->drm.dev, vsc);
57}
58
59#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
60
61static const char * const output_type_str[] = {
62 OUTPUT_TYPE(UNUSED),
63 OUTPUT_TYPE(ANALOG),
64 OUTPUT_TYPE(DVO),
65 OUTPUT_TYPE(SDVO),
66 OUTPUT_TYPE(LVDS),
67 OUTPUT_TYPE(TVOUT),
68 OUTPUT_TYPE(HDMI),
69 OUTPUT_TYPE(DP),
70 OUTPUT_TYPE(EDP),
71 OUTPUT_TYPE(DSI),
72 OUTPUT_TYPE(DDI),
73 OUTPUT_TYPE(DP_MST),
74};
75
76#undef OUTPUT_TYPE
77
78static void snprintf_output_types(char *buf, size_t len,
79 unsigned int output_types)
80{
81 char *str = buf;
82 int i;
83
84 str[0] = '\0';
85
86 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
87 int r;
88
89 if ((output_types & BIT(i)) == 0)
90 continue;
91
92 r = snprintf(str, len, "%s%s",
93 str != buf ? "," : "", output_type_str[i]);
94 if (r >= len)
95 break;
96 str += r;
97 len -= r;
98
99 output_types &= ~BIT(i);
100 }
101
102 WARN_ON_ONCE(output_types != 0);
103}
104
105static const char * const output_format_str[] = {
106 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
107 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
108 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
109};
110
111static const char *output_formats(enum intel_output_format format)
112{
113 if (format >= ARRAY_SIZE(output_format_str))
114 return "invalid";
115 return output_format_str[format];
116}
117
118static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
119{
120 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
121 struct drm_i915_private *i915 = to_i915(plane->base.dev);
122 const struct drm_framebuffer *fb = plane_state->hw.fb;
123
124 if (!fb) {
125 drm_dbg_kms(&i915->drm,
126 "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
127 plane->base.base.id, plane->base.name,
128 str_yes_no(plane_state->uapi.visible));
129 return;
130 }
131
132 drm_dbg_kms(&i915->drm,
133 "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
134 plane->base.base.id, plane->base.name,
135 fb->base.id, fb->width, fb->height, &fb->format->format,
136 fb->modifier, str_yes_no(plane_state->uapi.visible));
137 drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n",
138 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter);
139 if (plane_state->uapi.visible)
140 drm_dbg_kms(&i915->drm,
141 "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
142 DRM_RECT_FP_ARG(&plane_state->uapi.src),
143 DRM_RECT_ARG(&plane_state->uapi.dst));
144}
145
146void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
147 struct intel_atomic_state *state,
148 const char *context)
149{
150 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
151 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
152 const struct intel_plane_state *plane_state;
153 struct intel_plane *plane;
154 char buf[64];
155 int i;
156
157 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] enable: %s [%s]\n",
158 crtc->base.base.id, crtc->base.name,
159 str_yes_no(pipe_config->hw.enable), context);
160
161 if (!pipe_config->hw.enable)
162 goto dump_planes;
163
164 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
165 drm_dbg_kms(&i915->drm,
166 "active: %s, output_types: %s (0x%x), output format: %s\n",
167 str_yes_no(pipe_config->hw.active),
168 buf, pipe_config->output_types,
169 output_formats(pipe_config->output_format));
170
171 drm_dbg_kms(&i915->drm,
172 "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
173 transcoder_name(pipe_config->cpu_transcoder),
174 pipe_config->pipe_bpp, pipe_config->dither);
175
176 drm_dbg_kms(&i915->drm, "MST master transcoder: %s\n",
177 transcoder_name(pipe_config->mst_master_transcoder));
178
179 drm_dbg_kms(&i915->drm,
180 "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
181 transcoder_name(pipe_config->master_transcoder),
182 pipe_config->sync_mode_slaves_mask);
183
184 drm_dbg_kms(&i915->drm, "bigjoiner: %s, pipes: 0x%x\n",
185 intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
186 intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
187 pipe_config->bigjoiner_pipes);
188
189 drm_dbg_kms(&i915->drm, "splitter: %s, link count %d, overlap %d\n",
190 str_enabled_disabled(pipe_config->splitter.enable),
191 pipe_config->splitter.link_count,
192 pipe_config->splitter.pixel_overlap);
193
194 if (pipe_config->has_pch_encoder)
195 intel_dump_m_n_config(pipe_config, "fdi",
196 pipe_config->fdi_lanes,
197 &pipe_config->fdi_m_n);
198
199 if (intel_crtc_has_dp_encoder(pipe_config)) {
200 intel_dump_m_n_config(pipe_config, "dp m_n",
201 pipe_config->lane_count,
202 &pipe_config->dp_m_n);
203 intel_dump_m_n_config(pipe_config, "dp m2_n2",
204 pipe_config->lane_count,
205 &pipe_config->dp_m2_n2);
206 }
207
208 drm_dbg_kms(&i915->drm, "framestart delay: %d, MSA timing delay: %d\n",
209 pipe_config->framestart_delay, pipe_config->msa_timing_delay);
210
211 drm_dbg_kms(&i915->drm,
212 "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
213 pipe_config->has_audio, pipe_config->has_infoframe,
214 pipe_config->infoframes.enable);
215
216 if (pipe_config->infoframes.enable &
217 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
218 drm_dbg_kms(&i915->drm, "GCP: 0x%x\n",
219 pipe_config->infoframes.gcp);
220 if (pipe_config->infoframes.enable &
221 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
222 intel_dump_infoframe(i915, &pipe_config->infoframes.avi);
223 if (pipe_config->infoframes.enable &
224 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
225 intel_dump_infoframe(i915, &pipe_config->infoframes.spd);
226 if (pipe_config->infoframes.enable &
227 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
228 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi);
229 if (pipe_config->infoframes.enable &
230 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
231 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
232 if (pipe_config->infoframes.enable &
233 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
234 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
235 if (pipe_config->infoframes.enable &
236 intel_hdmi_infoframe_enable(DP_SDP_VSC))
237 intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc);
238
239 drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
240 str_yes_no(pipe_config->vrr.enable),
241 pipe_config->vrr.vmin, pipe_config->vrr.vmax,
242 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
243 pipe_config->vrr.flipline,
244 intel_vrr_vmin_vblank_start(pipe_config),
245 intel_vrr_vmax_vblank_start(pipe_config));
246
247 drm_dbg_kms(&i915->drm, "requested mode: " DRM_MODE_FMT "\n",
248 DRM_MODE_ARG(&pipe_config->hw.mode));
249 drm_dbg_kms(&i915->drm, "adjusted mode: " DRM_MODE_FMT "\n",
250 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
251 intel_dump_crtc_timings(i915, &pipe_config->hw.adjusted_mode);
252 drm_dbg_kms(&i915->drm, "pipe mode: " DRM_MODE_FMT "\n",
253 DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
254 intel_dump_crtc_timings(i915, &pipe_config->hw.pipe_mode);
255 drm_dbg_kms(&i915->drm,
256 "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
257 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
258 pipe_config->pixel_rate);
259
260 drm_dbg_kms(&i915->drm, "linetime: %d, ips linetime: %d\n",
261 pipe_config->linetime, pipe_config->ips_linetime);
262
263 if (DISPLAY_VER(i915) >= 9)
264 drm_dbg_kms(&i915->drm,
265 "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n",
266 crtc->num_scalers,
267 pipe_config->scaler_state.scaler_users,
268 pipe_config->scaler_state.scaler_id,
269 pipe_config->hw.scaling_filter);
270
271 if (HAS_GMCH(i915))
272 drm_dbg_kms(&i915->drm,
273 "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
274 pipe_config->gmch_pfit.control,
275 pipe_config->gmch_pfit.pgm_ratios,
276 pipe_config->gmch_pfit.lvds_border_bits);
277 else
278 drm_dbg_kms(&i915->drm,
279 "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
280 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
281 str_enabled_disabled(pipe_config->pch_pfit.enabled),
282 str_yes_no(pipe_config->pch_pfit.force_thru));
283
284 drm_dbg_kms(&i915->drm, "ips: %i, double wide: %i, drrs: %i\n",
285 pipe_config->ips_enabled, pipe_config->double_wide,
286 pipe_config->has_drrs);
287
288 intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state);
289
290 if (IS_CHERRYVIEW(i915))
291 drm_dbg_kms(&i915->drm,
292 "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
293 pipe_config->cgm_mode, pipe_config->gamma_mode,
294 pipe_config->gamma_enable, pipe_config->csc_enable);
295 else
296 drm_dbg_kms(&i915->drm,
297 "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
298 pipe_config->csc_mode, pipe_config->gamma_mode,
299 pipe_config->gamma_enable, pipe_config->csc_enable);
300
301 drm_dbg_kms(&i915->drm, "pre csc lut: %s%d entries, post csc lut: %d entries\n",
302 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut ==
303 i915->display.color.glk_linear_degamma_lut ? "(linear) " : "",
304 pipe_config->pre_csc_lut ?
305 drm_color_lut_size(pipe_config->pre_csc_lut) : 0,
306 pipe_config->post_csc_lut ?
307 drm_color_lut_size(pipe_config->post_csc_lut) : 0);
308
309dump_planes:
310 if (!state)
311 return;
312
313 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
314 if (plane->pipe == crtc->pipe)
315 intel_dump_plane_state(plane_state);
316 }
317}