1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2022 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_BACKLIGHT_REGS_H__
  7#define __INTEL_BACKLIGHT_REGS_H__
  8
  9#include "intel_display_reg_defs.h"
 10
 11#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
 12#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
 13#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
 14					 _VLV_BLC_PWM_CTL2_B)
 15
 16#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
 17#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
 18#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
 19					_VLV_BLC_PWM_CTL_B)
 20
 21#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
 22#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
 23#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
 24					 _VLV_BLC_HIST_CTL_B)
 25
 26/* Backlight control */
 27#define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
 28#define   BLM_PWM_ENABLE		(1 << 31)
 29#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
 30#define   BLM_PIPE_SELECT		(1 << 29)
 31#define   BLM_PIPE_SELECT_IVB		(3 << 29)
 32#define   BLM_PIPE_A			(0 << 29)
 33#define   BLM_PIPE_B			(1 << 29)
 34#define   BLM_PIPE_C			(2 << 29) /* ivb + */
 35#define   BLM_TRANSCODER_A		BLM_PIPE_A /* hsw */
 36#define   BLM_TRANSCODER_B		BLM_PIPE_B
 37#define   BLM_TRANSCODER_C		BLM_PIPE_C
 38#define   BLM_TRANSCODER_EDP		(3 << 29)
 39#define   BLM_PIPE(pipe)		((pipe) << 29)
 40#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
 41#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
 42#define   BLM_PHASE_IN_ENABLE		(1 << 25)
 43#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
 44#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
 45#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
 46#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
 47#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
 48#define   BLM_PHASE_IN_INCR_SHIFT	(0)
 49#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
 50#define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
 51/*
 52 * This is the most significant 15 bits of the number of backlight cycles in a
 53 * complete cycle of the modulated backlight control.
 54 *
 55 * The actual value is this field multiplied by two.
 56 */
 57#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
 58#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
 59#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
 60/*
 61 * This is the number of cycles out of the backlight modulation cycle for which
 62 * the backlight is on.
 63 *
 64 * This field must be no greater than the number of cycles in the complete
 65 * backlight modulation cycle.
 66 */
 67#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
 68#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
 69#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
 70#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
 71
 72#define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
 73#define  BLM_HISTOGRAM_ENABLE			(1 << 31)
 74
 75/* New registers for PCH-split platforms. Safe where new bits show up, the
 76 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
 77#define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
 78#define BLC_PWM_CPU_CTL		_MMIO(0x48254)
 79
 80#define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
 81
 82/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
 83 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
 84#define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
 85#define   BLM_PCH_PWM_ENABLE			(1 << 31)
 86#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
 87#define   BLM_PCH_POLARITY			(1 << 29)
 88#define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
 89
 90/* BXT backlight register definition. */
 91#define _BXT_BLC_PWM_CTL1			0xC8250
 92#define   BXT_BLC_PWM_ENABLE			(1 << 31)
 93#define   BXT_BLC_PWM_POLARITY			(1 << 29)
 94#define _BXT_BLC_PWM_FREQ1			0xC8254
 95#define _BXT_BLC_PWM_DUTY1			0xC8258
 96
 97#define _BXT_BLC_PWM_CTL2			0xC8350
 98#define _BXT_BLC_PWM_FREQ2			0xC8354
 99#define _BXT_BLC_PWM_DUTY2			0xC8358
100
101#define BXT_BLC_PWM_CTL(controller)    _MMIO_PIPE(controller,		\
102					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
103#define BXT_BLC_PWM_FREQ(controller)   _MMIO_PIPE(controller, \
104					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
105#define BXT_BLC_PWM_DUTY(controller)   _MMIO_PIPE(controller, \
106					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
107
108/* Utility pin */
109#define UTIL_PIN_CTL			_MMIO(0x48400)
110#define   UTIL_PIN_ENABLE		(1 << 31)
111#define   UTIL_PIN_PIPE_MASK		(3 << 29)
112#define   UTIL_PIN_PIPE(x)		((x) << 29)
113#define   UTIL_PIN_MODE_MASK		(0xf << 24)
114#define   UTIL_PIN_MODE_DATA		(0 << 24)
115#define   UTIL_PIN_MODE_PWM		(1 << 24)
116#define   UTIL_PIN_MODE_VBLANK		(4 << 24)
117#define   UTIL_PIN_MODE_VSYNC		(5 << 24)
118#define   UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
119#define   UTIL_PIN_OUTPUT_DATA		(1 << 23)
120#define   UTIL_PIN_POLARITY		(1 << 22)
121#define   UTIL_PIN_DIRECTION_INPUT	(1 << 19)
122#define   UTIL_PIN_INPUT_DATA		(1 << 16)
123
124#endif /* __INTEL_BACKLIGHT_REGS_H__ */