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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: atomic plane helpers
26 *
27 * The functions here are used by the atomic plane helper functions to
28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
29 * drm_plane->disable_plane()). This allows plane updates to use the
30 * atomic state infrastructure and perform plane updates as separate
31 * prepare/check/commit/cleanup steps.
32 */
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_fourcc.h>
36
37#include "gt/intel_rps.h"
38
39#include "intel_atomic_plane.h"
40#include "intel_cdclk.h"
41#include "intel_display_trace.h"
42#include "intel_display_types.h"
43#include "intel_fb.h"
44#include "intel_fb_pin.h"
45#include "intel_sprite.h"
46#include "skl_scaler.h"
47#include "skl_watermark.h"
48
49static void intel_plane_state_reset(struct intel_plane_state *plane_state,
50 struct intel_plane *plane)
51{
52 memset(plane_state, 0, sizeof(*plane_state));
53
54 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
55
56 plane_state->scaler_id = -1;
57}
58
59struct intel_plane *intel_plane_alloc(void)
60{
61 struct intel_plane_state *plane_state;
62 struct intel_plane *plane;
63
64 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
65 if (!plane)
66 return ERR_PTR(-ENOMEM);
67
68 plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
69 if (!plane_state) {
70 kfree(plane);
71 return ERR_PTR(-ENOMEM);
72 }
73
74 intel_plane_state_reset(plane_state, plane);
75
76 plane->base.state = &plane_state->uapi;
77
78 return plane;
79}
80
81void intel_plane_free(struct intel_plane *plane)
82{
83 intel_plane_destroy_state(&plane->base, plane->base.state);
84 kfree(plane);
85}
86
87/**
88 * intel_plane_duplicate_state - duplicate plane state
89 * @plane: drm plane
90 *
91 * Allocates and returns a copy of the plane state (both common and
92 * Intel-specific) for the specified plane.
93 *
94 * Returns: The newly allocated plane state, or NULL on failure.
95 */
96struct drm_plane_state *
97intel_plane_duplicate_state(struct drm_plane *plane)
98{
99 struct intel_plane_state *intel_state;
100
101 intel_state = to_intel_plane_state(plane->state);
102 intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
103
104 if (!intel_state)
105 return NULL;
106
107 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
108
109 intel_state->ggtt_vma = NULL;
110 intel_state->dpt_vma = NULL;
111 intel_state->flags = 0;
112
113 /* add reference to fb */
114 if (intel_state->hw.fb)
115 drm_framebuffer_get(intel_state->hw.fb);
116
117 return &intel_state->uapi;
118}
119
120/**
121 * intel_plane_destroy_state - destroy plane state
122 * @plane: drm plane
123 * @state: state object to destroy
124 *
125 * Destroys the plane state (both common and Intel-specific) for the
126 * specified plane.
127 */
128void
129intel_plane_destroy_state(struct drm_plane *plane,
130 struct drm_plane_state *state)
131{
132 struct intel_plane_state *plane_state = to_intel_plane_state(state);
133
134 drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
135 drm_WARN_ON(plane->dev, plane_state->dpt_vma);
136
137 __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
138 if (plane_state->hw.fb)
139 drm_framebuffer_put(plane_state->hw.fb);
140 kfree(plane_state);
141}
142
143unsigned int intel_adjusted_rate(const struct drm_rect *src,
144 const struct drm_rect *dst,
145 unsigned int rate)
146{
147 unsigned int src_w, src_h, dst_w, dst_h;
148
149 src_w = drm_rect_width(src) >> 16;
150 src_h = drm_rect_height(src) >> 16;
151 dst_w = drm_rect_width(dst);
152 dst_h = drm_rect_height(dst);
153
154 /* Downscaling limits the maximum pixel rate */
155 dst_w = min(src_w, dst_w);
156 dst_h = min(src_h, dst_h);
157
158 return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
159 dst_w * dst_h);
160}
161
162unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
163 const struct intel_plane_state *plane_state)
164{
165 /*
166 * Note we don't check for plane visibility here as
167 * we want to use this when calculating the cursor
168 * watermarks even if the cursor is fully offscreen.
169 * That depends on the src/dst rectangles being
170 * correctly populated whenever the watermark code
171 * considers the cursor to be visible, whether or not
172 * it is actually visible.
173 *
174 * See: intel_wm_plane_visible() and intel_check_cursor()
175 */
176
177 return intel_adjusted_rate(&plane_state->uapi.src,
178 &plane_state->uapi.dst,
179 crtc_state->pixel_rate);
180}
181
182unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
183 const struct intel_plane_state *plane_state,
184 int color_plane)
185{
186 const struct drm_framebuffer *fb = plane_state->hw.fb;
187
188 if (!plane_state->uapi.visible)
189 return 0;
190
191 return intel_plane_pixel_rate(crtc_state, plane_state) *
192 fb->format->cpp[color_plane];
193}
194
195static bool
196use_min_ddb(const struct intel_crtc_state *crtc_state,
197 struct intel_plane *plane)
198{
199 struct drm_i915_private *i915 = to_i915(plane->base.dev);
200
201 return DISPLAY_VER(i915) >= 13 &&
202 crtc_state->uapi.async_flip &&
203 plane->async_flip;
204}
205
206static unsigned int
207intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
208 const struct intel_plane_state *plane_state,
209 int color_plane)
210{
211 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
212 const struct drm_framebuffer *fb = plane_state->hw.fb;
213 int width, height;
214
215 if (plane->id == PLANE_CURSOR)
216 return 0;
217
218 if (!plane_state->uapi.visible)
219 return 0;
220
221 /*
222 * We calculate extra ddb based on ratio plane rate/total data rate
223 * in case, in some cases we should not allocate extra ddb for the plane,
224 * so do not count its data rate, if this is the case.
225 */
226 if (use_min_ddb(crtc_state, plane))
227 return 0;
228
229 /*
230 * Src coordinates are already rotated by 270 degrees for
231 * the 90/270 degree plane rotation cases (to match the
232 * GTT mapping), hence no need to account for rotation here.
233 */
234 width = drm_rect_width(&plane_state->uapi.src) >> 16;
235 height = drm_rect_height(&plane_state->uapi.src) >> 16;
236
237 /* UV plane does 1/2 pixel sub-sampling */
238 if (color_plane == 1) {
239 width /= 2;
240 height /= 2;
241 }
242
243 return width * height * fb->format->cpp[color_plane];
244}
245
246int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
247 struct intel_plane *plane,
248 bool *need_cdclk_calc)
249{
250 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
251 const struct intel_plane_state *plane_state =
252 intel_atomic_get_new_plane_state(state, plane);
253 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
254 const struct intel_cdclk_state *cdclk_state;
255 const struct intel_crtc_state *old_crtc_state;
256 struct intel_crtc_state *new_crtc_state;
257
258 if (!plane_state->uapi.visible || !plane->min_cdclk)
259 return 0;
260
261 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
262 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
263
264 new_crtc_state->min_cdclk[plane->id] =
265 plane->min_cdclk(new_crtc_state, plane_state);
266
267 /*
268 * No need to check against the cdclk state if
269 * the min cdclk for the plane doesn't increase.
270 *
271 * Ie. we only ever increase the cdclk due to plane
272 * requirements. This can reduce back and forth
273 * display blinking due to constant cdclk changes.
274 */
275 if (new_crtc_state->min_cdclk[plane->id] <=
276 old_crtc_state->min_cdclk[plane->id])
277 return 0;
278
279 cdclk_state = intel_atomic_get_cdclk_state(state);
280 if (IS_ERR(cdclk_state))
281 return PTR_ERR(cdclk_state);
282
283 /*
284 * No need to recalculate the cdclk state if
285 * the min cdclk for the pipe doesn't increase.
286 *
287 * Ie. we only ever increase the cdclk due to plane
288 * requirements. This can reduce back and forth
289 * display blinking due to constant cdclk changes.
290 */
291 if (new_crtc_state->min_cdclk[plane->id] <=
292 cdclk_state->min_cdclk[crtc->pipe])
293 return 0;
294
295 drm_dbg_kms(&dev_priv->drm,
296 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
297 plane->base.base.id, plane->base.name,
298 new_crtc_state->min_cdclk[plane->id],
299 crtc->base.base.id, crtc->base.name,
300 cdclk_state->min_cdclk[crtc->pipe]);
301 *need_cdclk_calc = true;
302
303 return 0;
304}
305
306static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
307{
308 if (plane_state->hw.fb)
309 drm_framebuffer_put(plane_state->hw.fb);
310
311 memset(&plane_state->hw, 0, sizeof(plane_state->hw));
312}
313
314void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
315 const struct intel_plane_state *from_plane_state,
316 struct intel_crtc *crtc)
317{
318 intel_plane_clear_hw_state(plane_state);
319
320 /*
321 * For the bigjoiner slave uapi.crtc will point at
322 * the master crtc. So we explicitly assign the right
323 * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
324 * the plane is logically enabled on the uapi level.
325 */
326 plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
327
328 plane_state->hw.fb = from_plane_state->uapi.fb;
329 if (plane_state->hw.fb)
330 drm_framebuffer_get(plane_state->hw.fb);
331
332 plane_state->hw.alpha = from_plane_state->uapi.alpha;
333 plane_state->hw.pixel_blend_mode =
334 from_plane_state->uapi.pixel_blend_mode;
335 plane_state->hw.rotation = from_plane_state->uapi.rotation;
336 plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
337 plane_state->hw.color_range = from_plane_state->uapi.color_range;
338 plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
339
340 plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
341 plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
342}
343
344void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
345 const struct intel_plane_state *from_plane_state)
346{
347 intel_plane_clear_hw_state(plane_state);
348
349 memcpy(&plane_state->hw, &from_plane_state->hw,
350 sizeof(plane_state->hw));
351
352 if (plane_state->hw.fb)
353 drm_framebuffer_get(plane_state->hw.fb);
354}
355
356void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
357 struct intel_plane_state *plane_state)
358{
359 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
360
361 crtc_state->active_planes &= ~BIT(plane->id);
362 crtc_state->scaled_planes &= ~BIT(plane->id);
363 crtc_state->nv12_planes &= ~BIT(plane->id);
364 crtc_state->c8_planes &= ~BIT(plane->id);
365 crtc_state->data_rate[plane->id] = 0;
366 crtc_state->data_rate_y[plane->id] = 0;
367 crtc_state->rel_data_rate[plane->id] = 0;
368 crtc_state->rel_data_rate_y[plane->id] = 0;
369 crtc_state->min_cdclk[plane->id] = 0;
370
371 plane_state->uapi.visible = false;
372}
373
374/* FIXME nuke when all wm code is atomic */
375static bool intel_wm_need_update(const struct intel_plane_state *cur,
376 struct intel_plane_state *new)
377{
378 /* Update watermarks on tiling or size changes. */
379 if (new->uapi.visible != cur->uapi.visible)
380 return true;
381
382 if (!cur->hw.fb || !new->hw.fb)
383 return false;
384
385 if (cur->hw.fb->modifier != new->hw.fb->modifier ||
386 cur->hw.rotation != new->hw.rotation ||
387 drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
388 drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
389 drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
390 drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
391 return true;
392
393 return false;
394}
395
396static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
397{
398 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
399 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
400 int dst_w = drm_rect_width(&plane_state->uapi.dst);
401 int dst_h = drm_rect_height(&plane_state->uapi.dst);
402
403 return src_w != dst_w || src_h != dst_h;
404}
405
406static bool intel_plane_do_async_flip(struct intel_plane *plane,
407 const struct intel_crtc_state *old_crtc_state,
408 const struct intel_crtc_state *new_crtc_state)
409{
410 struct drm_i915_private *i915 = to_i915(plane->base.dev);
411
412 if (!plane->async_flip)
413 return false;
414
415 if (!new_crtc_state->uapi.async_flip)
416 return false;
417
418 /*
419 * In platforms after DISPLAY13, we might need to override
420 * first async flip in order to change watermark levels
421 * as part of optimization.
422 * So for those, we are checking if this is a first async flip.
423 * For platforms earlier than DISPLAY13 we always do async flip.
424 */
425 return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
426}
427
428static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
429 const struct intel_plane_state *old_plane_state,
430 const struct intel_plane_state *new_plane_state)
431{
432 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
433 bool old_visible = old_plane_state->uapi.visible;
434 bool new_visible = new_plane_state->uapi.visible;
435 u32 old_ctl = old_plane_state->ctl;
436 u32 new_ctl = new_plane_state->ctl;
437 bool modeset, turn_on, turn_off;
438
439 if (plane->id == PLANE_CURSOR)
440 return false;
441
442 modeset = intel_crtc_needs_modeset(new_crtc_state);
443 turn_off = old_visible && (!new_visible || modeset);
444 turn_on = new_visible && (!old_visible || modeset);
445
446 /* Must disable CxSR around plane enable/disable */
447 if (turn_on || turn_off)
448 return true;
449
450 if (!old_visible || !new_visible)
451 return false;
452
453 /*
454 * Most plane control register updates are blocked while in CxSR.
455 *
456 * Tiling mode is one exception where the primary plane can
457 * apparently handle it, whereas the sprites can not (the
458 * sprite issue being only relevant on VLV/CHV where CxSR
459 * is actually possible with a sprite enabled).
460 */
461 if (plane->id == PLANE_PRIMARY) {
462 old_ctl &= ~DISP_TILED;
463 new_ctl &= ~DISP_TILED;
464 }
465
466 return old_ctl != new_ctl;
467}
468
469static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
470 struct intel_crtc_state *new_crtc_state,
471 const struct intel_plane_state *old_plane_state,
472 struct intel_plane_state *new_plane_state)
473{
474 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
475 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
476 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
477 bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
478 bool was_crtc_enabled = old_crtc_state->hw.active;
479 bool is_crtc_enabled = new_crtc_state->hw.active;
480 bool turn_off, turn_on, visible, was_visible;
481 int ret;
482
483 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
484 ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
485 if (ret)
486 return ret;
487 }
488
489 was_visible = old_plane_state->uapi.visible;
490 visible = new_plane_state->uapi.visible;
491
492 if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
493 was_visible = false;
494
495 /*
496 * Visibility is calculated as if the crtc was on, but
497 * after scaler setup everything depends on it being off
498 * when the crtc isn't active.
499 *
500 * FIXME this is wrong for watermarks. Watermarks should also
501 * be computed as if the pipe would be active. Perhaps move
502 * per-plane wm computation to the .check_plane() hook, and
503 * only combine the results from all planes in the current place?
504 */
505 if (!is_crtc_enabled) {
506 intel_plane_set_invisible(new_crtc_state, new_plane_state);
507 visible = false;
508 }
509
510 if (!was_visible && !visible)
511 return 0;
512
513 turn_off = was_visible && (!visible || mode_changed);
514 turn_on = visible && (!was_visible || mode_changed);
515
516 drm_dbg_atomic(&dev_priv->drm,
517 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
518 crtc->base.base.id, crtc->base.name,
519 plane->base.base.id, plane->base.name,
520 was_visible, visible,
521 turn_off, turn_on, mode_changed);
522
523 if (turn_on) {
524 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
525 new_crtc_state->update_wm_pre = true;
526 } else if (turn_off) {
527 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
528 new_crtc_state->update_wm_post = true;
529 } else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
530 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
531 /* FIXME bollocks */
532 new_crtc_state->update_wm_pre = true;
533 new_crtc_state->update_wm_post = true;
534 }
535 }
536
537 if (visible || was_visible)
538 new_crtc_state->fb_bits |= plane->frontbuffer_bit;
539
540 if (HAS_GMCH(dev_priv) &&
541 i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
542 new_crtc_state->disable_cxsr = true;
543
544 /*
545 * ILK/SNB DVSACNTR/Sprite Enable
546 * IVB SPR_CTL/Sprite Enable
547 * "When in Self Refresh Big FIFO mode, a write to enable the
548 * plane will be internally buffered and delayed while Big FIFO
549 * mode is exiting."
550 *
551 * Which means that enabling the sprite can take an extra frame
552 * when we start in big FIFO mode (LP1+). Thus we need to drop
553 * down to LP0 and wait for vblank in order to make sure the
554 * sprite gets enabled on the next vblank after the register write.
555 * Doing otherwise would risk enabling the sprite one frame after
556 * we've already signalled flip completion. We can resume LP1+
557 * once the sprite has been enabled.
558 *
559 *
560 * WaCxSRDisabledForSpriteScaling:ivb
561 * IVB SPR_SCALE/Scaling Enable
562 * "Low Power watermarks must be disabled for at least one
563 * frame before enabling sprite scaling, and kept disabled
564 * until sprite scaling is disabled."
565 *
566 * ILK/SNB DVSASCALE/Scaling Enable
567 * "When in Self Refresh Big FIFO mode, scaling enable will be
568 * masked off while Big FIFO mode is exiting."
569 *
570 * Despite the w/a only being listed for IVB we assume that
571 * the ILK/SNB note has similar ramifications, hence we apply
572 * the w/a on all three platforms.
573 *
574 * With experimental results seems this is needed also for primary
575 * plane, not only sprite plane.
576 */
577 if (plane->id != PLANE_CURSOR &&
578 (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
579 IS_IVYBRIDGE(dev_priv)) &&
580 (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
581 intel_plane_is_scaled(new_plane_state))))
582 new_crtc_state->disable_lp_wm = true;
583
584 if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
585 new_crtc_state->do_async_flip = true;
586
587 return 0;
588}
589
590int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
591 struct intel_crtc_state *new_crtc_state,
592 const struct intel_plane_state *old_plane_state,
593 struct intel_plane_state *new_plane_state)
594{
595 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
596 const struct drm_framebuffer *fb = new_plane_state->hw.fb;
597 int ret;
598
599 intel_plane_set_invisible(new_crtc_state, new_plane_state);
600 new_crtc_state->enabled_planes &= ~BIT(plane->id);
601
602 if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
603 return 0;
604
605 ret = plane->check_plane(new_crtc_state, new_plane_state);
606 if (ret)
607 return ret;
608
609 if (fb)
610 new_crtc_state->enabled_planes |= BIT(plane->id);
611
612 /* FIXME pre-g4x don't work like this */
613 if (new_plane_state->uapi.visible)
614 new_crtc_state->active_planes |= BIT(plane->id);
615
616 if (new_plane_state->uapi.visible &&
617 intel_plane_is_scaled(new_plane_state))
618 new_crtc_state->scaled_planes |= BIT(plane->id);
619
620 if (new_plane_state->uapi.visible &&
621 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
622 new_crtc_state->nv12_planes |= BIT(plane->id);
623
624 if (new_plane_state->uapi.visible &&
625 fb->format->format == DRM_FORMAT_C8)
626 new_crtc_state->c8_planes |= BIT(plane->id);
627
628 if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
629 new_crtc_state->update_planes |= BIT(plane->id);
630
631 if (new_plane_state->uapi.visible &&
632 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
633 new_crtc_state->data_rate_y[plane->id] =
634 intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
635 new_crtc_state->data_rate[plane->id] =
636 intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
637
638 new_crtc_state->rel_data_rate_y[plane->id] =
639 intel_plane_relative_data_rate(new_crtc_state,
640 new_plane_state, 0);
641 new_crtc_state->rel_data_rate[plane->id] =
642 intel_plane_relative_data_rate(new_crtc_state,
643 new_plane_state, 1);
644 } else if (new_plane_state->uapi.visible) {
645 new_crtc_state->data_rate[plane->id] =
646 intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
647
648 new_crtc_state->rel_data_rate[plane->id] =
649 intel_plane_relative_data_rate(new_crtc_state,
650 new_plane_state, 0);
651 }
652
653 return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
654 old_plane_state, new_plane_state);
655}
656
657static struct intel_plane *
658intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
659{
660 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
661 struct intel_plane *plane;
662
663 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
664 if (plane->id == plane_id)
665 return plane;
666 }
667
668 return NULL;
669}
670
671int intel_plane_atomic_check(struct intel_atomic_state *state,
672 struct intel_plane *plane)
673{
674 struct drm_i915_private *i915 = to_i915(state->base.dev);
675 struct intel_plane_state *new_plane_state =
676 intel_atomic_get_new_plane_state(state, plane);
677 const struct intel_plane_state *old_plane_state =
678 intel_atomic_get_old_plane_state(state, plane);
679 const struct intel_plane_state *new_master_plane_state;
680 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
681 const struct intel_crtc_state *old_crtc_state =
682 intel_atomic_get_old_crtc_state(state, crtc);
683 struct intel_crtc_state *new_crtc_state =
684 intel_atomic_get_new_crtc_state(state, crtc);
685
686 if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
687 struct intel_crtc *master_crtc =
688 intel_master_crtc(new_crtc_state);
689 struct intel_plane *master_plane =
690 intel_crtc_get_plane(master_crtc, plane->id);
691
692 new_master_plane_state =
693 intel_atomic_get_new_plane_state(state, master_plane);
694 } else {
695 new_master_plane_state = new_plane_state;
696 }
697
698 intel_plane_copy_uapi_to_hw_state(new_plane_state,
699 new_master_plane_state,
700 crtc);
701
702 new_plane_state->uapi.visible = false;
703 if (!new_crtc_state)
704 return 0;
705
706 return intel_plane_atomic_check_with_state(old_crtc_state,
707 new_crtc_state,
708 old_plane_state,
709 new_plane_state);
710}
711
712static struct intel_plane *
713skl_next_plane_to_commit(struct intel_atomic_state *state,
714 struct intel_crtc *crtc,
715 struct skl_ddb_entry ddb[I915_MAX_PLANES],
716 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
717 unsigned int *update_mask)
718{
719 struct intel_crtc_state *crtc_state =
720 intel_atomic_get_new_crtc_state(state, crtc);
721 struct intel_plane_state *plane_state;
722 struct intel_plane *plane;
723 int i;
724
725 if (*update_mask == 0)
726 return NULL;
727
728 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
729 enum plane_id plane_id = plane->id;
730
731 if (crtc->pipe != plane->pipe ||
732 !(*update_mask & BIT(plane_id)))
733 continue;
734
735 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
736 ddb, I915_MAX_PLANES, plane_id) ||
737 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
738 ddb_y, I915_MAX_PLANES, plane_id))
739 continue;
740
741 *update_mask &= ~BIT(plane_id);
742 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
743 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
744
745 return plane;
746 }
747
748 /* should never happen */
749 drm_WARN_ON(state->base.dev, 1);
750
751 return NULL;
752}
753
754void intel_plane_update_noarm(struct intel_plane *plane,
755 const struct intel_crtc_state *crtc_state,
756 const struct intel_plane_state *plane_state)
757{
758 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
759
760 trace_intel_plane_update_noarm(plane, crtc);
761
762 if (plane->update_noarm)
763 plane->update_noarm(plane, crtc_state, plane_state);
764}
765
766void intel_plane_update_arm(struct intel_plane *plane,
767 const struct intel_crtc_state *crtc_state,
768 const struct intel_plane_state *plane_state)
769{
770 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
771
772 trace_intel_plane_update_arm(plane, crtc);
773
774 if (crtc_state->do_async_flip && plane->async_flip)
775 plane->async_flip(plane, crtc_state, plane_state, true);
776 else
777 plane->update_arm(plane, crtc_state, plane_state);
778}
779
780void intel_plane_disable_arm(struct intel_plane *plane,
781 const struct intel_crtc_state *crtc_state)
782{
783 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
784
785 trace_intel_plane_disable_arm(plane, crtc);
786 plane->disable_arm(plane, crtc_state);
787}
788
789void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
790 struct intel_crtc *crtc)
791{
792 struct intel_crtc_state *new_crtc_state =
793 intel_atomic_get_new_crtc_state(state, crtc);
794 u32 update_mask = new_crtc_state->update_planes;
795 struct intel_plane_state *new_plane_state;
796 struct intel_plane *plane;
797 int i;
798
799 if (new_crtc_state->do_async_flip)
800 return;
801
802 /*
803 * Since we only write non-arming registers here,
804 * the order does not matter even for skl+.
805 */
806 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
807 if (crtc->pipe != plane->pipe ||
808 !(update_mask & BIT(plane->id)))
809 continue;
810
811 /* TODO: for mailbox updates this should be skipped */
812 if (new_plane_state->uapi.visible ||
813 new_plane_state->planar_slave)
814 intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
815 }
816}
817
818static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
819 struct intel_crtc *crtc)
820{
821 struct intel_crtc_state *old_crtc_state =
822 intel_atomic_get_old_crtc_state(state, crtc);
823 struct intel_crtc_state *new_crtc_state =
824 intel_atomic_get_new_crtc_state(state, crtc);
825 struct skl_ddb_entry ddb[I915_MAX_PLANES];
826 struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
827 u32 update_mask = new_crtc_state->update_planes;
828 struct intel_plane *plane;
829
830 memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
831 sizeof(old_crtc_state->wm.skl.plane_ddb));
832 memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
833 sizeof(old_crtc_state->wm.skl.plane_ddb_y));
834
835 while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
836 struct intel_plane_state *new_plane_state =
837 intel_atomic_get_new_plane_state(state, plane);
838
839 /*
840 * TODO: for mailbox updates intel_plane_update_noarm()
841 * would have to be called here as well.
842 */
843 if (new_plane_state->uapi.visible ||
844 new_plane_state->planar_slave)
845 intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
846 else
847 intel_plane_disable_arm(plane, new_crtc_state);
848 }
849}
850
851static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
852 struct intel_crtc *crtc)
853{
854 struct intel_crtc_state *new_crtc_state =
855 intel_atomic_get_new_crtc_state(state, crtc);
856 u32 update_mask = new_crtc_state->update_planes;
857 struct intel_plane_state *new_plane_state;
858 struct intel_plane *plane;
859 int i;
860
861 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
862 if (crtc->pipe != plane->pipe ||
863 !(update_mask & BIT(plane->id)))
864 continue;
865
866 /*
867 * TODO: for mailbox updates intel_plane_update_noarm()
868 * would have to be called here as well.
869 */
870 if (new_plane_state->uapi.visible)
871 intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
872 else
873 intel_plane_disable_arm(plane, new_crtc_state);
874 }
875}
876
877void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
878 struct intel_crtc *crtc)
879{
880 struct drm_i915_private *i915 = to_i915(state->base.dev);
881
882 if (DISPLAY_VER(i915) >= 9)
883 skl_crtc_planes_update_arm(state, crtc);
884 else
885 i9xx_crtc_planes_update_arm(state, crtc);
886}
887
888int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
889 struct intel_crtc_state *crtc_state,
890 int min_scale, int max_scale,
891 bool can_position)
892{
893 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
894 struct drm_framebuffer *fb = plane_state->hw.fb;
895 struct drm_rect *src = &plane_state->uapi.src;
896 struct drm_rect *dst = &plane_state->uapi.dst;
897 const struct drm_rect *clip = &crtc_state->pipe_src;
898 unsigned int rotation = plane_state->hw.rotation;
899 int hscale, vscale;
900
901 if (!fb) {
902 plane_state->uapi.visible = false;
903 return 0;
904 }
905
906 drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
907
908 /* Check scaling */
909 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
910 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
911 if (hscale < 0 || vscale < 0) {
912 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
913 drm_rect_debug_print("src: ", src, true);
914 drm_rect_debug_print("dst: ", dst, false);
915 return -ERANGE;
916 }
917
918 /*
919 * FIXME: This might need further adjustment for seamless scaling
920 * with phase information, for the 2p2 and 2p1 scenarios.
921 */
922 plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
923
924 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
925
926 if (!can_position && plane_state->uapi.visible &&
927 !drm_rect_equals(dst, clip)) {
928 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
929 drm_rect_debug_print("dst: ", dst, false);
930 drm_rect_debug_print("clip: ", clip, false);
931 return -EINVAL;
932 }
933
934 /* final plane coordinates will be relative to the plane's pipe */
935 drm_rect_translate(dst, -clip->x1, -clip->y1);
936
937 return 0;
938}
939
940struct wait_rps_boost {
941 struct wait_queue_entry wait;
942
943 struct drm_crtc *crtc;
944 struct i915_request *request;
945};
946
947static int do_rps_boost(struct wait_queue_entry *_wait,
948 unsigned mode, int sync, void *key)
949{
950 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
951 struct i915_request *rq = wait->request;
952
953 /*
954 * If we missed the vblank, but the request is already running it
955 * is reasonable to assume that it will complete before the next
956 * vblank without our intervention, so leave RPS alone.
957 */
958 if (!i915_request_started(rq))
959 intel_rps_boost(rq);
960 i915_request_put(rq);
961
962 drm_crtc_vblank_put(wait->crtc);
963
964 list_del(&wait->wait.entry);
965 kfree(wait);
966 return 1;
967}
968
969static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
970 struct dma_fence *fence)
971{
972 struct wait_rps_boost *wait;
973
974 if (!dma_fence_is_i915(fence))
975 return;
976
977 if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
978 return;
979
980 if (drm_crtc_vblank_get(crtc))
981 return;
982
983 wait = kmalloc(sizeof(*wait), GFP_KERNEL);
984 if (!wait) {
985 drm_crtc_vblank_put(crtc);
986 return;
987 }
988
989 wait->request = to_request(dma_fence_get(fence));
990 wait->crtc = crtc;
991
992 wait->wait.func = do_rps_boost;
993 wait->wait.flags = 0;
994
995 add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
996}
997
998/**
999 * intel_prepare_plane_fb - Prepare fb for usage on plane
1000 * @_plane: drm plane to prepare for
1001 * @_new_plane_state: the plane state being prepared
1002 *
1003 * Prepares a framebuffer for usage on a display plane. Generally this
1004 * involves pinning the underlying object and updating the frontbuffer tracking
1005 * bits. Some older platforms need special physical address handling for
1006 * cursor planes.
1007 *
1008 * Returns 0 on success, negative error code on failure.
1009 */
1010static int
1011intel_prepare_plane_fb(struct drm_plane *_plane,
1012 struct drm_plane_state *_new_plane_state)
1013{
1014 struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
1015 struct intel_plane *plane = to_intel_plane(_plane);
1016 struct intel_plane_state *new_plane_state =
1017 to_intel_plane_state(_new_plane_state);
1018 struct intel_atomic_state *state =
1019 to_intel_atomic_state(new_plane_state->uapi.state);
1020 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1021 const struct intel_plane_state *old_plane_state =
1022 intel_atomic_get_old_plane_state(state, plane);
1023 struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
1024 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
1025 int ret;
1026
1027 if (old_obj) {
1028 const struct intel_crtc_state *crtc_state =
1029 intel_atomic_get_new_crtc_state(state,
1030 to_intel_crtc(old_plane_state->hw.crtc));
1031
1032 /* Big Hammer, we also need to ensure that any pending
1033 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1034 * current scanout is retired before unpinning the old
1035 * framebuffer. Note that we rely on userspace rendering
1036 * into the buffer attached to the pipe they are waiting
1037 * on. If not, userspace generates a GPU hang with IPEHR
1038 * point to the MI_WAIT_FOR_EVENT.
1039 *
1040 * This should only fail upon a hung GPU, in which case we
1041 * can safely continue.
1042 */
1043 if (intel_crtc_needs_modeset(crtc_state)) {
1044 ret = i915_sw_fence_await_reservation(&state->commit_ready,
1045 old_obj->base.resv,
1046 false, 0,
1047 GFP_KERNEL);
1048 if (ret < 0)
1049 return ret;
1050 }
1051 }
1052
1053 if (new_plane_state->uapi.fence) { /* explicit fencing */
1054 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
1055 &attr);
1056 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
1057 new_plane_state->uapi.fence,
1058 i915_fence_timeout(dev_priv),
1059 GFP_KERNEL);
1060 if (ret < 0)
1061 return ret;
1062 }
1063
1064 if (!obj)
1065 return 0;
1066
1067
1068 ret = intel_plane_pin_fb(new_plane_state);
1069 if (ret)
1070 return ret;
1071
1072 i915_gem_object_wait_priority(obj, 0, &attr);
1073
1074 if (!new_plane_state->uapi.fence) { /* implicit fencing */
1075 struct dma_resv_iter cursor;
1076 struct dma_fence *fence;
1077
1078 ret = i915_sw_fence_await_reservation(&state->commit_ready,
1079 obj->base.resv, false,
1080 i915_fence_timeout(dev_priv),
1081 GFP_KERNEL);
1082 if (ret < 0)
1083 goto unpin_fb;
1084
1085 dma_resv_iter_begin(&cursor, obj->base.resv,
1086 DMA_RESV_USAGE_WRITE);
1087 dma_resv_for_each_fence_unlocked(&cursor, fence) {
1088 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
1089 fence);
1090 }
1091 dma_resv_iter_end(&cursor);
1092 } else {
1093 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
1094 new_plane_state->uapi.fence);
1095 }
1096
1097 /*
1098 * We declare pageflips to be interactive and so merit a small bias
1099 * towards upclocking to deliver the frame on time. By only changing
1100 * the RPS thresholds to sample more regularly and aim for higher
1101 * clocks we can hopefully deliver low power workloads (like kodi)
1102 * that are not quite steady state without resorting to forcing
1103 * maximum clocks following a vblank miss (see do_rps_boost()).
1104 */
1105 if (!state->rps_interactive) {
1106 intel_rps_mark_interactive(&to_gt(dev_priv)->rps, true);
1107 state->rps_interactive = true;
1108 }
1109
1110 return 0;
1111
1112unpin_fb:
1113 intel_plane_unpin_fb(new_plane_state);
1114
1115 return ret;
1116}
1117
1118/**
1119 * intel_cleanup_plane_fb - Cleans up an fb after plane use
1120 * @plane: drm plane to clean up for
1121 * @_old_plane_state: the state from the previous modeset
1122 *
1123 * Cleans up a framebuffer that has just been removed from a plane.
1124 */
1125static void
1126intel_cleanup_plane_fb(struct drm_plane *plane,
1127 struct drm_plane_state *_old_plane_state)
1128{
1129 struct intel_plane_state *old_plane_state =
1130 to_intel_plane_state(_old_plane_state);
1131 struct intel_atomic_state *state =
1132 to_intel_atomic_state(old_plane_state->uapi.state);
1133 struct drm_i915_private *dev_priv = to_i915(plane->dev);
1134 struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
1135
1136 if (!obj)
1137 return;
1138
1139 if (state->rps_interactive) {
1140 intel_rps_mark_interactive(&to_gt(dev_priv)->rps, false);
1141 state->rps_interactive = false;
1142 }
1143
1144 /* Should only be called after a successful intel_prepare_plane_fb()! */
1145 intel_plane_unpin_fb(old_plane_state);
1146}
1147
1148static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1149 .prepare_fb = intel_prepare_plane_fb,
1150 .cleanup_fb = intel_cleanup_plane_fb,
1151};
1152
1153void intel_plane_helper_add(struct intel_plane *plane)
1154{
1155 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1156}