1/*
  2 * Copyright 2015 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 */
 24
 25#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
 26#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
 27
 28#include "core_types.h"
 29#include "core_status.h"
 30#include "dal_asic_id.h"
 31#include "dm_pp_smu.h"
 32
 33#define MEMORY_TYPE_MULTIPLIER_CZ 4
 34#define MEMORY_TYPE_HBM 2
 35
 36
 37#define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)->pipe_idx_syncd) & 0x80)?1:0)
 38#define GET_PIPE_SYNCD_FROM_PIPE(pipe) ((pipe)->pipe_idx_syncd & 0x7F)
 39#define SET_PIPE_SYNCD_TO_PIPE(pipe, pipe_syncd) ((pipe)->pipe_idx_syncd = (0x80 | pipe_syncd))
 40
 41enum dce_version resource_parse_asic_id(
 42		struct hw_asic_id asic_id);
 43
 44struct resource_caps {
 45	int num_timing_generator;
 46	int num_opp;
 47	int num_video_plane;
 48	int num_audio;
 49	int num_stream_encoder;
 50	int num_pll;
 51	int num_dwb;
 52	int num_ddc;
 53	int num_vmid;
 54	int num_dsc;
 55	unsigned int num_dig_link_enc; // Total number of DIGs (digital encoders) in DIO (Display Input/Output).
 56	unsigned int num_usb4_dpia; // Total number of USB4 DPIA (DisplayPort Input Adapters).
 57	int num_hpo_dp_stream_encoder;
 58	int num_hpo_dp_link_encoder;
 59	int num_mpc_3dlut;
 60};
 61
 62struct resource_straps {
 63	uint32_t hdmi_disable;
 64	uint32_t dc_pinstraps_audio;
 65	uint32_t audio_stream_number;
 66};
 67
 68struct resource_create_funcs {
 69	void (*read_dce_straps)(
 70			struct dc_context *ctx, struct resource_straps *straps);
 71
 72	struct audio *(*create_audio)(
 73			struct dc_context *ctx, unsigned int inst);
 74
 75	struct stream_encoder *(*create_stream_encoder)(
 76			enum engine_id eng_id, struct dc_context *ctx);
 77
 78	struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)(
 79			enum engine_id eng_id, struct dc_context *ctx);
 80
 81	struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)(
 82			uint8_t inst,
 83			struct dc_context *ctx);
 84
 85	struct dce_hwseq *(*create_hwseq)(
 86			struct dc_context *ctx);
 87};
 88
 89bool resource_construct(
 90	unsigned int num_virtual_links,
 91	struct dc *dc,
 92	struct resource_pool *pool,
 93	const struct resource_create_funcs *create_funcs);
 94
 95struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 96					      const struct dc_init_data *init_data,
 97					      enum dce_version dc_version);
 98
 99void dc_destroy_resource_pool(struct dc *dc);
100
101enum dc_status resource_map_pool_resources(
102		const struct dc *dc,
103		struct dc_state *context,
104		struct dc_stream_state *stream);
105
106bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
107
108enum dc_status resource_build_scaling_params_for_context(
109		const struct dc *dc,
110		struct dc_state *context);
111
112void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
113
114void resource_unreference_clock_source(
115		struct resource_context *res_ctx,
116		const struct resource_pool *pool,
117		struct clock_source *clock_source);
118
119void resource_reference_clock_source(
120		struct resource_context *res_ctx,
121		const struct resource_pool *pool,
122		struct clock_source *clock_source);
123
124int resource_get_clock_source_reference(
125		struct resource_context *res_ctx,
126		const struct resource_pool *pool,
127		struct clock_source *clock_source);
128
129bool resource_are_streams_timing_synchronizable(
130		struct dc_stream_state *stream1,
131		struct dc_stream_state *stream2);
132
133bool resource_are_vblanks_synchronizable(
134		struct dc_stream_state *stream1,
135		struct dc_stream_state *stream2);
136
137struct clock_source *resource_find_used_clk_src_for_sharing(
138		struct resource_context *res_ctx,
139		struct pipe_ctx *pipe_ctx);
140
141struct clock_source *dc_resource_find_first_free_pll(
142		struct resource_context *res_ctx,
143		const struct resource_pool *pool);
144
145struct pipe_ctx *resource_get_head_pipe_for_stream(
146		struct resource_context *res_ctx,
147		struct dc_stream_state *stream);
148
149bool resource_attach_surfaces_to_context(
150		struct dc_plane_state *const *plane_state,
151		int surface_count,
152		struct dc_stream_state *dc_stream,
153		struct dc_state *context,
154		const struct resource_pool *pool);
155
156struct pipe_ctx *find_idle_secondary_pipe(
157		struct resource_context *res_ctx,
158		const struct resource_pool *pool,
159		const struct pipe_ctx *primary_pipe);
160
161bool resource_validate_attach_surfaces(
162		const struct dc_validation_set set[],
163		int set_count,
164		const struct dc_state *old_context,
165		struct dc_state *context,
166		const struct resource_pool *pool);
167
168void resource_validate_ctx_update_pointer_after_copy(
169		const struct dc_state *src_ctx,
170		struct dc_state *dst_ctx);
171
172enum dc_status resource_map_clock_resources(
173		const struct dc *dc,
174		struct dc_state *context,
175		struct dc_stream_state *stream);
176
177enum dc_status resource_map_phy_clock_resources(
178		const struct dc *dc,
179		struct dc_state *context,
180		struct dc_stream_state *stream);
181
182bool pipe_need_reprogram(
183		struct pipe_ctx *pipe_ctx_old,
184		struct pipe_ctx *pipe_ctx);
185
186void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
187		struct bit_depth_reduction_params *fmt_bit_depth);
188
189void update_audio_usage(
190		struct resource_context *res_ctx,
191		const struct resource_pool *pool,
192		struct audio *audio,
193		bool acquired);
194
195unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
196
197void get_audio_check(struct audio_info *aud_modes,
198	struct audio_check *aud_chk);
199
200int get_num_mpc_splits(struct pipe_ctx *pipe);
201
202int get_num_odm_splits(struct pipe_ctx *pipe);
203
204bool get_temp_dp_link_res(struct dc_link *link,
205		struct link_resource *link_res,
206		struct dc_link_settings *link_settings);
207
208#if defined(CONFIG_DRM_AMD_DC_DCN)
209struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
210		const struct resource_context *res_ctx,
211		const struct resource_pool *pool,
212		const struct dc_link *link);
213#endif
214
215void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
216	struct dc_state *context);
217
218void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
219	struct dc_state *context,
220	uint8_t disabled_master_pipe_idx);
221
222void reset_sync_context_for_pipe(const struct dc *dc,
223	struct dc_state *context,
224	uint8_t pipe_idx);
225
226uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter);
227
228const struct link_hwss *get_link_hwss(const struct dc_link *link,
229		const struct link_resource *link_res);
230
231bool is_h_timing_divisible_by_2(struct dc_stream_state *stream);
232
233bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
234		const struct dc *dc,
235		struct dc_state *state,
236		struct pipe_ctx *pri_pipe,
237		struct pipe_ctx *sec_pipe,
238		bool odm);
239#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */