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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek UART APDMA driver.
4 *
5 * Copyright (c) 2019 MediaTek Inc.
6 * Author: Long Cheng <long.cheng@mediatek.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/dmaengine.h>
11#include <linux/dma-mapping.h>
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/iopoll.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/of_dma.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25
26#include "../virt-dma.h"
27
28/* The default number of virtual channel */
29#define MTK_UART_APDMA_NR_VCHANS 8
30
31#define VFF_EN_B BIT(0)
32#define VFF_STOP_B BIT(0)
33#define VFF_FLUSH_B BIT(0)
34#define VFF_4G_EN_B BIT(0)
35/* rx valid size >= vff thre */
36#define VFF_RX_INT_EN_B (BIT(0) | BIT(1))
37/* tx left size >= vff thre */
38#define VFF_TX_INT_EN_B BIT(0)
39#define VFF_WARM_RST_B BIT(0)
40#define VFF_RX_INT_CLR_B (BIT(0) | BIT(1))
41#define VFF_TX_INT_CLR_B 0
42#define VFF_STOP_CLR_B 0
43#define VFF_EN_CLR_B 0
44#define VFF_INT_EN_CLR_B 0
45#define VFF_4G_SUPPORT_CLR_B 0
46
47/*
48 * interrupt trigger level for tx
49 * if threshold is n, no polling is required to start tx.
50 * otherwise need polling VFF_FLUSH.
51 */
52#define VFF_TX_THRE(n) (n)
53/* interrupt trigger level for rx */
54#define VFF_RX_THRE(n) ((n) * 3 / 4)
55
56#define VFF_RING_SIZE 0xffff
57/* invert this bit when wrap ring head again */
58#define VFF_RING_WRAP 0x10000
59
60#define VFF_INT_FLAG 0x00
61#define VFF_INT_EN 0x04
62#define VFF_EN 0x08
63#define VFF_RST 0x0c
64#define VFF_STOP 0x10
65#define VFF_FLUSH 0x14
66#define VFF_ADDR 0x1c
67#define VFF_LEN 0x24
68#define VFF_THRE 0x28
69#define VFF_WPT 0x2c
70#define VFF_RPT 0x30
71/* TX: the buffer size HW can read. RX: the buffer size SW can read. */
72#define VFF_VALID_SIZE 0x3c
73/* TX: the buffer size SW can write. RX: the buffer size HW can write. */
74#define VFF_LEFT_SIZE 0x40
75#define VFF_DEBUG_STATUS 0x50
76#define VFF_4G_SUPPORT 0x54
77
78struct mtk_uart_apdmadev {
79 struct dma_device ddev;
80 struct clk *clk;
81 bool support_33bits;
82 unsigned int dma_requests;
83};
84
85struct mtk_uart_apdma_desc {
86 struct virt_dma_desc vd;
87
88 dma_addr_t addr;
89 unsigned int avail_len;
90};
91
92struct mtk_chan {
93 struct virt_dma_chan vc;
94 struct dma_slave_config cfg;
95 struct mtk_uart_apdma_desc *desc;
96 enum dma_transfer_direction dir;
97
98 void __iomem *base;
99 unsigned int irq;
100
101 unsigned int rx_status;
102};
103
104static inline struct mtk_uart_apdmadev *
105to_mtk_uart_apdma_dev(struct dma_device *d)
106{
107 return container_of(d, struct mtk_uart_apdmadev, ddev);
108}
109
110static inline struct mtk_chan *to_mtk_uart_apdma_chan(struct dma_chan *c)
111{
112 return container_of(c, struct mtk_chan, vc.chan);
113}
114
115static inline struct mtk_uart_apdma_desc *to_mtk_uart_apdma_desc
116 (struct dma_async_tx_descriptor *t)
117{
118 return container_of(t, struct mtk_uart_apdma_desc, vd.tx);
119}
120
121static void mtk_uart_apdma_write(struct mtk_chan *c,
122 unsigned int reg, unsigned int val)
123{
124 writel(val, c->base + reg);
125}
126
127static unsigned int mtk_uart_apdma_read(struct mtk_chan *c, unsigned int reg)
128{
129 return readl(c->base + reg);
130}
131
132static void mtk_uart_apdma_desc_free(struct virt_dma_desc *vd)
133{
134 kfree(container_of(vd, struct mtk_uart_apdma_desc, vd));
135}
136
137static void mtk_uart_apdma_start_tx(struct mtk_chan *c)
138{
139 struct mtk_uart_apdmadev *mtkd =
140 to_mtk_uart_apdma_dev(c->vc.chan.device);
141 struct mtk_uart_apdma_desc *d = c->desc;
142 unsigned int wpt, vff_sz;
143
144 vff_sz = c->cfg.dst_port_window_size;
145 if (!mtk_uart_apdma_read(c, VFF_LEN)) {
146 mtk_uart_apdma_write(c, VFF_ADDR, d->addr);
147 mtk_uart_apdma_write(c, VFF_LEN, vff_sz);
148 mtk_uart_apdma_write(c, VFF_THRE, VFF_TX_THRE(vff_sz));
149 mtk_uart_apdma_write(c, VFF_WPT, 0);
150 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
151
152 if (mtkd->support_33bits)
153 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
154 }
155
156 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
157 if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B)
158 dev_err(c->vc.chan.device->dev, "Enable TX fail\n");
159
160 if (!mtk_uart_apdma_read(c, VFF_LEFT_SIZE)) {
161 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
162 return;
163 }
164
165 wpt = mtk_uart_apdma_read(c, VFF_WPT);
166
167 wpt += c->desc->avail_len;
168 if ((wpt & VFF_RING_SIZE) == vff_sz)
169 wpt = (wpt & VFF_RING_WRAP) ^ VFF_RING_WRAP;
170
171 /* Let DMA start moving data */
172 mtk_uart_apdma_write(c, VFF_WPT, wpt);
173
174 /* HW auto set to 0 when left size >= threshold */
175 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
176 if (!mtk_uart_apdma_read(c, VFF_FLUSH))
177 mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B);
178}
179
180static void mtk_uart_apdma_start_rx(struct mtk_chan *c)
181{
182 struct mtk_uart_apdmadev *mtkd =
183 to_mtk_uart_apdma_dev(c->vc.chan.device);
184 struct mtk_uart_apdma_desc *d = c->desc;
185 unsigned int vff_sz;
186
187 vff_sz = c->cfg.src_port_window_size;
188 if (!mtk_uart_apdma_read(c, VFF_LEN)) {
189 mtk_uart_apdma_write(c, VFF_ADDR, d->addr);
190 mtk_uart_apdma_write(c, VFF_LEN, vff_sz);
191 mtk_uart_apdma_write(c, VFF_THRE, VFF_RX_THRE(vff_sz));
192 mtk_uart_apdma_write(c, VFF_RPT, 0);
193 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
194
195 if (mtkd->support_33bits)
196 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
197 }
198
199 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_RX_INT_EN_B);
200 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
201 if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B)
202 dev_err(c->vc.chan.device->dev, "Enable RX fail\n");
203}
204
205static void mtk_uart_apdma_tx_handler(struct mtk_chan *c)
206{
207 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
208 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
209 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
210}
211
212static void mtk_uart_apdma_rx_handler(struct mtk_chan *c)
213{
214 struct mtk_uart_apdma_desc *d = c->desc;
215 unsigned int len, wg, rg;
216 int cnt;
217
218 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
219
220 if (!mtk_uart_apdma_read(c, VFF_VALID_SIZE))
221 return;
222
223 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
224 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
225
226 len = c->cfg.src_port_window_size;
227 rg = mtk_uart_apdma_read(c, VFF_RPT);
228 wg = mtk_uart_apdma_read(c, VFF_WPT);
229 cnt = (wg & VFF_RING_SIZE) - (rg & VFF_RING_SIZE);
230
231 /*
232 * The buffer is ring buffer. If wrap bit different,
233 * represents the start of the next cycle for WPT
234 */
235 if ((rg ^ wg) & VFF_RING_WRAP)
236 cnt += len;
237
238 c->rx_status = d->avail_len - cnt;
239 mtk_uart_apdma_write(c, VFF_RPT, wg);
240}
241
242static void mtk_uart_apdma_chan_complete_handler(struct mtk_chan *c)
243{
244 struct mtk_uart_apdma_desc *d = c->desc;
245
246 if (d) {
247 list_del(&d->vd.node);
248 vchan_cookie_complete(&d->vd);
249 c->desc = NULL;
250 }
251}
252
253static irqreturn_t mtk_uart_apdma_irq_handler(int irq, void *dev_id)
254{
255 struct dma_chan *chan = (struct dma_chan *)dev_id;
256 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
257 unsigned long flags;
258
259 spin_lock_irqsave(&c->vc.lock, flags);
260 if (c->dir == DMA_DEV_TO_MEM)
261 mtk_uart_apdma_rx_handler(c);
262 else if (c->dir == DMA_MEM_TO_DEV)
263 mtk_uart_apdma_tx_handler(c);
264 mtk_uart_apdma_chan_complete_handler(c);
265 spin_unlock_irqrestore(&c->vc.lock, flags);
266
267 return IRQ_HANDLED;
268}
269
270static int mtk_uart_apdma_alloc_chan_resources(struct dma_chan *chan)
271{
272 struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device);
273 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
274 unsigned int status;
275 int ret;
276
277 ret = pm_runtime_resume_and_get(mtkd->ddev.dev);
278 if (ret < 0) {
279 pm_runtime_put_noidle(chan->device->dev);
280 return ret;
281 }
282
283 mtk_uart_apdma_write(c, VFF_ADDR, 0);
284 mtk_uart_apdma_write(c, VFF_THRE, 0);
285 mtk_uart_apdma_write(c, VFF_LEN, 0);
286 mtk_uart_apdma_write(c, VFF_RST, VFF_WARM_RST_B);
287
288 ret = readx_poll_timeout(readl, c->base + VFF_EN,
289 status, !status, 10, 100);
290 if (ret)
291 goto err_pm;
292
293 ret = request_irq(c->irq, mtk_uart_apdma_irq_handler,
294 IRQF_TRIGGER_NONE, KBUILD_MODNAME, chan);
295 if (ret < 0) {
296 dev_err(chan->device->dev, "Can't request dma IRQ\n");
297 ret = -EINVAL;
298 goto err_pm;
299 }
300
301 if (mtkd->support_33bits)
302 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B);
303
304err_pm:
305 pm_runtime_put_noidle(mtkd->ddev.dev);
306 return ret;
307}
308
309static void mtk_uart_apdma_free_chan_resources(struct dma_chan *chan)
310{
311 struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device);
312 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
313
314 free_irq(c->irq, chan);
315
316 tasklet_kill(&c->vc.task);
317
318 vchan_free_chan_resources(&c->vc);
319
320 pm_runtime_put_sync(mtkd->ddev.dev);
321}
322
323static enum dma_status mtk_uart_apdma_tx_status(struct dma_chan *chan,
324 dma_cookie_t cookie,
325 struct dma_tx_state *txstate)
326{
327 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
328 enum dma_status ret;
329
330 ret = dma_cookie_status(chan, cookie, txstate);
331 if (!txstate)
332 return ret;
333
334 dma_set_residue(txstate, c->rx_status);
335
336 return ret;
337}
338
339/*
340 * dmaengine_prep_slave_single will call the function. and sglen is 1.
341 * 8250 uart using one ring buffer, and deal with one sg.
342 */
343static struct dma_async_tx_descriptor *mtk_uart_apdma_prep_slave_sg
344 (struct dma_chan *chan, struct scatterlist *sgl,
345 unsigned int sglen, enum dma_transfer_direction dir,
346 unsigned long tx_flags, void *context)
347{
348 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
349 struct mtk_uart_apdma_desc *d;
350
351 if (!is_slave_direction(dir) || sglen != 1)
352 return NULL;
353
354 /* Now allocate and setup the descriptor */
355 d = kzalloc(sizeof(*d), GFP_NOWAIT);
356 if (!d)
357 return NULL;
358
359 d->avail_len = sg_dma_len(sgl);
360 d->addr = sg_dma_address(sgl);
361 c->dir = dir;
362
363 return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
364}
365
366static void mtk_uart_apdma_issue_pending(struct dma_chan *chan)
367{
368 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
369 struct virt_dma_desc *vd;
370 unsigned long flags;
371
372 spin_lock_irqsave(&c->vc.lock, flags);
373 if (vchan_issue_pending(&c->vc) && !c->desc) {
374 vd = vchan_next_desc(&c->vc);
375 c->desc = to_mtk_uart_apdma_desc(&vd->tx);
376
377 if (c->dir == DMA_DEV_TO_MEM)
378 mtk_uart_apdma_start_rx(c);
379 else if (c->dir == DMA_MEM_TO_DEV)
380 mtk_uart_apdma_start_tx(c);
381 }
382
383 spin_unlock_irqrestore(&c->vc.lock, flags);
384}
385
386static int mtk_uart_apdma_slave_config(struct dma_chan *chan,
387 struct dma_slave_config *config)
388{
389 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
390
391 memcpy(&c->cfg, config, sizeof(*config));
392
393 return 0;
394}
395
396static int mtk_uart_apdma_terminate_all(struct dma_chan *chan)
397{
398 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
399 unsigned long flags;
400 unsigned int status;
401 LIST_HEAD(head);
402 int ret;
403
404 mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B);
405
406 ret = readx_poll_timeout(readl, c->base + VFF_FLUSH,
407 status, status != VFF_FLUSH_B, 10, 100);
408 if (ret)
409 dev_err(c->vc.chan.device->dev, "flush: fail, status=0x%x\n",
410 mtk_uart_apdma_read(c, VFF_DEBUG_STATUS));
411
412 /*
413 * Stop need 3 steps.
414 * 1. set stop to 1
415 * 2. wait en to 0
416 * 3. set stop as 0
417 */
418 mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_B);
419 ret = readx_poll_timeout(readl, c->base + VFF_EN,
420 status, !status, 10, 100);
421 if (ret)
422 dev_err(c->vc.chan.device->dev, "stop: fail, status=0x%x\n",
423 mtk_uart_apdma_read(c, VFF_DEBUG_STATUS));
424
425 mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_CLR_B);
426 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
427
428 if (c->dir == DMA_DEV_TO_MEM)
429 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
430 else if (c->dir == DMA_MEM_TO_DEV)
431 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
432
433 synchronize_irq(c->irq);
434
435 spin_lock_irqsave(&c->vc.lock, flags);
436 vchan_get_all_descriptors(&c->vc, &head);
437 spin_unlock_irqrestore(&c->vc.lock, flags);
438
439 vchan_dma_desc_free_list(&c->vc, &head);
440
441 return 0;
442}
443
444static int mtk_uart_apdma_device_pause(struct dma_chan *chan)
445{
446 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
447 unsigned long flags;
448
449 spin_lock_irqsave(&c->vc.lock, flags);
450
451 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
452 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
453
454 synchronize_irq(c->irq);
455
456 spin_unlock_irqrestore(&c->vc.lock, flags);
457
458 return 0;
459}
460
461static void mtk_uart_apdma_free(struct mtk_uart_apdmadev *mtkd)
462{
463 while (!list_empty(&mtkd->ddev.channels)) {
464 struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels,
465 struct mtk_chan, vc.chan.device_node);
466
467 list_del(&c->vc.chan.device_node);
468 tasklet_kill(&c->vc.task);
469 }
470}
471
472static const struct of_device_id mtk_uart_apdma_match[] = {
473 { .compatible = "mediatek,mt6577-uart-dma", },
474 { /* sentinel */ },
475};
476MODULE_DEVICE_TABLE(of, mtk_uart_apdma_match);
477
478static int mtk_uart_apdma_probe(struct platform_device *pdev)
479{
480 struct device_node *np = pdev->dev.of_node;
481 struct mtk_uart_apdmadev *mtkd;
482 int bit_mask = 32, rc;
483 struct mtk_chan *c;
484 unsigned int i;
485
486 mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL);
487 if (!mtkd)
488 return -ENOMEM;
489
490 mtkd->clk = devm_clk_get(&pdev->dev, NULL);
491 if (IS_ERR(mtkd->clk)) {
492 dev_err(&pdev->dev, "No clock specified\n");
493 rc = PTR_ERR(mtkd->clk);
494 return rc;
495 }
496
497 if (of_property_read_bool(np, "mediatek,dma-33bits"))
498 mtkd->support_33bits = true;
499
500 if (mtkd->support_33bits)
501 bit_mask = 33;
502
503 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(bit_mask));
504 if (rc)
505 return rc;
506
507 dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask);
508 mtkd->ddev.device_alloc_chan_resources =
509 mtk_uart_apdma_alloc_chan_resources;
510 mtkd->ddev.device_free_chan_resources =
511 mtk_uart_apdma_free_chan_resources;
512 mtkd->ddev.device_tx_status = mtk_uart_apdma_tx_status;
513 mtkd->ddev.device_issue_pending = mtk_uart_apdma_issue_pending;
514 mtkd->ddev.device_prep_slave_sg = mtk_uart_apdma_prep_slave_sg;
515 mtkd->ddev.device_config = mtk_uart_apdma_slave_config;
516 mtkd->ddev.device_pause = mtk_uart_apdma_device_pause;
517 mtkd->ddev.device_terminate_all = mtk_uart_apdma_terminate_all;
518 mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
519 mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
520 mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
521 mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
522 mtkd->ddev.dev = &pdev->dev;
523 INIT_LIST_HEAD(&mtkd->ddev.channels);
524
525 mtkd->dma_requests = MTK_UART_APDMA_NR_VCHANS;
526 if (of_property_read_u32(np, "dma-requests", &mtkd->dma_requests)) {
527 dev_info(&pdev->dev,
528 "Using %u as missing dma-requests property\n",
529 MTK_UART_APDMA_NR_VCHANS);
530 }
531
532 for (i = 0; i < mtkd->dma_requests; i++) {
533 c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL);
534 if (!c) {
535 rc = -ENODEV;
536 goto err_no_dma;
537 }
538
539 c->base = devm_platform_ioremap_resource(pdev, i);
540 if (IS_ERR(c->base)) {
541 rc = PTR_ERR(c->base);
542 goto err_no_dma;
543 }
544 c->vc.desc_free = mtk_uart_apdma_desc_free;
545 vchan_init(&c->vc, &mtkd->ddev);
546
547 rc = platform_get_irq(pdev, i);
548 if (rc < 0)
549 goto err_no_dma;
550 c->irq = rc;
551 }
552
553 pm_runtime_enable(&pdev->dev);
554 pm_runtime_set_active(&pdev->dev);
555
556 rc = dma_async_device_register(&mtkd->ddev);
557 if (rc)
558 goto rpm_disable;
559
560 platform_set_drvdata(pdev, mtkd);
561
562 /* Device-tree DMA controller registration */
563 rc = of_dma_controller_register(np, of_dma_xlate_by_chan_id, mtkd);
564 if (rc)
565 goto dma_remove;
566
567 return rc;
568
569dma_remove:
570 dma_async_device_unregister(&mtkd->ddev);
571rpm_disable:
572 pm_runtime_disable(&pdev->dev);
573err_no_dma:
574 mtk_uart_apdma_free(mtkd);
575 return rc;
576}
577
578static int mtk_uart_apdma_remove(struct platform_device *pdev)
579{
580 struct mtk_uart_apdmadev *mtkd = platform_get_drvdata(pdev);
581
582 of_dma_controller_free(pdev->dev.of_node);
583
584 mtk_uart_apdma_free(mtkd);
585
586 dma_async_device_unregister(&mtkd->ddev);
587
588 pm_runtime_disable(&pdev->dev);
589
590 return 0;
591}
592
593#ifdef CONFIG_PM_SLEEP
594static int mtk_uart_apdma_suspend(struct device *dev)
595{
596 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
597
598 if (!pm_runtime_suspended(dev))
599 clk_disable_unprepare(mtkd->clk);
600
601 return 0;
602}
603
604static int mtk_uart_apdma_resume(struct device *dev)
605{
606 int ret;
607 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
608
609 if (!pm_runtime_suspended(dev)) {
610 ret = clk_prepare_enable(mtkd->clk);
611 if (ret)
612 return ret;
613 }
614
615 return 0;
616}
617#endif /* CONFIG_PM_SLEEP */
618
619#ifdef CONFIG_PM
620static int mtk_uart_apdma_runtime_suspend(struct device *dev)
621{
622 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
623
624 clk_disable_unprepare(mtkd->clk);
625
626 return 0;
627}
628
629static int mtk_uart_apdma_runtime_resume(struct device *dev)
630{
631 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
632
633 return clk_prepare_enable(mtkd->clk);
634}
635#endif /* CONFIG_PM */
636
637static const struct dev_pm_ops mtk_uart_apdma_pm_ops = {
638 SET_SYSTEM_SLEEP_PM_OPS(mtk_uart_apdma_suspend, mtk_uart_apdma_resume)
639 SET_RUNTIME_PM_OPS(mtk_uart_apdma_runtime_suspend,
640 mtk_uart_apdma_runtime_resume, NULL)
641};
642
643static struct platform_driver mtk_uart_apdma_driver = {
644 .probe = mtk_uart_apdma_probe,
645 .remove = mtk_uart_apdma_remove,
646 .driver = {
647 .name = KBUILD_MODNAME,
648 .pm = &mtk_uart_apdma_pm_ops,
649 .of_match_table = of_match_ptr(mtk_uart_apdma_match),
650 },
651};
652
653module_platform_driver(mtk_uart_apdma_driver);
654
655MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver");
656MODULE_AUTHOR("Long Cheng <long.cheng@mediatek.com>");
657MODULE_LICENSE("GPL v2");