1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  4 * Author: Tomasz Figa <t.figa@samsung.com>
  5 *
  6 * Clock driver for Exynos clock output
  7 */
  8
  9#include <linux/slab.h>
 10#include <linux/clk.h>
 11#include <linux/clk-provider.h>
 12#include <linux/module.h>
 13#include <linux/io.h>
 14#include <linux/of.h>
 15#include <linux/of_address.h>
 16#include <linux/of_device.h>
 17#include <linux/platform_device.h>
 18#include <linux/pm.h>
 19
 20#define EXYNOS_CLKOUT_NR_CLKS		1
 21#define EXYNOS_CLKOUT_PARENTS		32
 22
 23#define EXYNOS_PMU_DEBUG_REG		0xa00
 24#define EXYNOS_CLKOUT_DISABLE_SHIFT	0
 25#define EXYNOS_CLKOUT_MUX_SHIFT		8
 26#define EXYNOS4_CLKOUT_MUX_MASK		0xf
 27#define EXYNOS5_CLKOUT_MUX_MASK		0x1f
 28
 29struct exynos_clkout {
 30	struct clk_gate gate;
 31	struct clk_mux mux;
 32	spinlock_t slock;
 33	void __iomem *reg;
 34	struct device_node *np;
 35	u32 pmu_debug_save;
 36	struct clk_hw_onecell_data data;
 37};
 38
 39struct exynos_clkout_variant {
 40	u32 mux_mask;
 41};
 42
 43static const struct exynos_clkout_variant exynos_clkout_exynos4 = {
 44	.mux_mask	= EXYNOS4_CLKOUT_MUX_MASK,
 45};
 46
 47static const struct exynos_clkout_variant exynos_clkout_exynos5 = {
 48	.mux_mask	= EXYNOS5_CLKOUT_MUX_MASK,
 49};
 50
 51static const struct of_device_id exynos_clkout_ids[] = {
 52	{
 53		.compatible = "samsung,exynos3250-pmu",
 54		.data = &exynos_clkout_exynos4,
 55	}, {
 56		.compatible = "samsung,exynos4210-pmu",
 57		.data = &exynos_clkout_exynos4,
 58	}, {
 59		.compatible = "samsung,exynos4412-pmu",
 60		.data = &exynos_clkout_exynos4,
 61	}, {
 62		.compatible = "samsung,exynos5250-pmu",
 63		.data = &exynos_clkout_exynos5,
 64	}, {
 65		.compatible = "samsung,exynos5410-pmu",
 66		.data = &exynos_clkout_exynos5,
 67	}, {
 68		.compatible = "samsung,exynos5420-pmu",
 69		.data = &exynos_clkout_exynos5,
 70	}, {
 71		.compatible = "samsung,exynos5433-pmu",
 72		.data = &exynos_clkout_exynos5,
 73	}, { }
 74};
 75MODULE_DEVICE_TABLE(of, exynos_clkout_ids);
 76
 77/*
 78 * Device will be instantiated as child of PMU device without its own
 79 * device node.  Therefore match compatibles against parent.
 80 */
 81static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask)
 82{
 83	const struct exynos_clkout_variant *variant;
 84	const struct of_device_id *match;
 85
 86	if (!dev->parent) {
 87		dev_err(dev, "not instantiated from MFD\n");
 88		return -EINVAL;
 89	}
 90
 91	match = of_match_device(exynos_clkout_ids, dev->parent);
 92	if (!match) {
 93		dev_err(dev, "cannot match parent device\n");
 94		return -EINVAL;
 95	}
 96	variant = match->data;
 97
 98	*mux_mask = variant->mux_mask;
 99
100	return 0;
101}
102
103static int exynos_clkout_probe(struct platform_device *pdev)
104{
105	const char *parent_names[EXYNOS_CLKOUT_PARENTS];
106	struct clk *parents[EXYNOS_CLKOUT_PARENTS];
107	struct exynos_clkout *clkout;
108	int parent_count, ret, i;
109	u32 mux_mask;
110
111	clkout = devm_kzalloc(&pdev->dev,
112			      struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
113			      GFP_KERNEL);
114	if (!clkout)
115		return -ENOMEM;
116
117	ret = exynos_clkout_match_parent_dev(&pdev->dev, &mux_mask);
118	if (ret)
119		return ret;
120
121	clkout->np = pdev->dev.of_node;
122	if (!clkout->np) {
123		/*
124		 * pdev->dev.parent was checked by exynos_clkout_match_parent_dev()
125		 * so it is not NULL.
126		 */
127		clkout->np = pdev->dev.parent->of_node;
128	}
129
130	platform_set_drvdata(pdev, clkout);
131
132	spin_lock_init(&clkout->slock);
133
134	parent_count = 0;
135	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
136		char name[] = "clkoutXX";
137
138		snprintf(name, sizeof(name), "clkout%d", i);
139		parents[i] = of_clk_get_by_name(clkout->np, name);
140		if (IS_ERR(parents[i])) {
141			parent_names[i] = "none";
142			continue;
143		}
144
145		parent_names[i] = __clk_get_name(parents[i]);
146		parent_count = i + 1;
147	}
148
149	if (!parent_count)
150		return -EINVAL;
151
152	clkout->reg = of_iomap(clkout->np, 0);
153	if (!clkout->reg) {
154		ret = -ENODEV;
155		goto clks_put;
156	}
157
158	clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
159	clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
160	clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
161	clkout->gate.lock = &clkout->slock;
162
163	clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
164	clkout->mux.mask = mux_mask;
165	clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
166	clkout->mux.lock = &clkout->slock;
167
168	clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
169				parent_names, parent_count, &clkout->mux.hw,
170				&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
171				&clk_gate_ops, CLK_SET_RATE_PARENT
172				| CLK_SET_RATE_NO_REPARENT);
173	if (IS_ERR(clkout->data.hws[0])) {
174		ret = PTR_ERR(clkout->data.hws[0]);
175		goto err_unmap;
176	}
177
178	clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
179	ret = of_clk_add_hw_provider(clkout->np, of_clk_hw_onecell_get, &clkout->data);
180	if (ret)
181		goto err_clk_unreg;
182
183	return 0;
184
185err_clk_unreg:
186	clk_hw_unregister(clkout->data.hws[0]);
187err_unmap:
188	iounmap(clkout->reg);
189clks_put:
190	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
191		if (!IS_ERR(parents[i]))
192			clk_put(parents[i]);
193
194	dev_err(&pdev->dev, "failed to register clkout clock\n");
195
196	return ret;
197}
198
199static int exynos_clkout_remove(struct platform_device *pdev)
200{
201	struct exynos_clkout *clkout = platform_get_drvdata(pdev);
202
203	of_clk_del_provider(clkout->np);
204	clk_hw_unregister(clkout->data.hws[0]);
205	iounmap(clkout->reg);
206
207	return 0;
208}
209
210static int __maybe_unused exynos_clkout_suspend(struct device *dev)
211{
212	struct exynos_clkout *clkout = dev_get_drvdata(dev);
213
214	clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
215
216	return 0;
217}
218
219static int __maybe_unused exynos_clkout_resume(struct device *dev)
220{
221	struct exynos_clkout *clkout = dev_get_drvdata(dev);
222
223	writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
224
225	return 0;
226}
227
228static SIMPLE_DEV_PM_OPS(exynos_clkout_pm_ops, exynos_clkout_suspend,
229			 exynos_clkout_resume);
230
231static struct platform_driver exynos_clkout_driver = {
232	.driver = {
233		.name = "exynos-clkout",
234		.of_match_table = exynos_clkout_ids,
235		.pm = &exynos_clkout_pm_ops,
236	},
237	.probe = exynos_clkout_probe,
238	.remove = exynos_clkout_remove,
239};
240module_platform_driver(exynos_clkout_driver);
241
242MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
243MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
244MODULE_DESCRIPTION("Samsung Exynos clock output driver");
245MODULE_LICENSE("GPL");