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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * pxa1928 clock framework source file
4 *
5 * Copyright (C) 2015 Linaro, Ltd.
6 * Rob Herring <robh@kernel.org>
7 *
8 * Based on drivers/clk/mmp/clk-of-mmp2.c:
9 * Copyright (C) 2012 Marvell
10 * Chao Xie <xiechao.mail@gmail.com>
11 */
12#include <linux/kernel.h>
13#include <linux/io.h>
14#include <linux/of_address.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17
18#include <dt-bindings/clock/marvell,pxa1928.h>
19
20#include "clk.h"
21#include "reset.h"
22
23#define MPMU_UART_PLL 0x14
24
25struct pxa1928_clk_unit {
26 struct mmp_clk_unit unit;
27 void __iomem *mpmu_base;
28 void __iomem *apmu_base;
29 void __iomem *apbc_base;
30 void __iomem *apbcp_base;
31};
32
33static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
34 {0, "clk32", NULL, 0, 32768},
35 {0, "vctcxo", NULL, 0, 26000000},
36 {0, "pll1_624", NULL, 0, 624000000},
37 {0, "pll5p", NULL, 0, 832000000},
38 {0, "pll5", NULL, 0, 1248000000},
39 {0, "usb_pll", NULL, 0, 480000000},
40};
41
42static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
43 {0, "pll1_d2", "pll1_624", 1, 2, 0},
44 {0, "pll1_d9", "pll1_624", 1, 9, 0},
45 {0, "pll1_d12", "pll1_624", 1, 12, 0},
46 {0, "pll1_d16", "pll1_624", 1, 16, 0},
47 {0, "pll1_d20", "pll1_624", 1, 20, 0},
48 {0, "pll1_416", "pll1_624", 2, 3, 0},
49 {0, "vctcxo_d2", "vctcxo", 1, 2, 0},
50 {0, "vctcxo_d4", "vctcxo", 1, 4, 0},
51};
52
53static struct mmp_clk_factor_masks uart_factor_masks = {
54 .factor = 2,
55 .num_mask = 0x1fff,
56 .den_mask = 0x1fff,
57 .num_shift = 16,
58 .den_shift = 0,
59};
60
61static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
62 {.num = 832, .den = 234}, /*58.5MHZ */
63 {.num = 1, .den = 1}, /*26MHZ */
64};
65
66static void pxa1928_pll_init(struct pxa1928_clk_unit *pxa_unit)
67{
68 struct mmp_clk_unit *unit = &pxa_unit->unit;
69
70 mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
71 ARRAY_SIZE(fixed_rate_clks));
72
73 mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
74 ARRAY_SIZE(fixed_factor_clks));
75
76 mmp_clk_register_factor("uart_pll", "pll1_416",
77 CLK_SET_RATE_PARENT,
78 pxa_unit->mpmu_base + MPMU_UART_PLL,
79 &uart_factor_masks, uart_factor_tbl,
80 ARRAY_SIZE(uart_factor_tbl), NULL);
81}
82
83static DEFINE_SPINLOCK(uart0_lock);
84static DEFINE_SPINLOCK(uart1_lock);
85static DEFINE_SPINLOCK(uart2_lock);
86static DEFINE_SPINLOCK(uart3_lock);
87static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
88
89static DEFINE_SPINLOCK(ssp0_lock);
90static DEFINE_SPINLOCK(ssp1_lock);
91static const char *ssp_parent_names[] = {"vctcxo_d4", "vctcxo_d2", "vctcxo", "pll1_d12"};
92
93static DEFINE_SPINLOCK(reset_lock);
94
95static struct mmp_param_mux_clk apbc_mux_clks[] = {
96 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
97 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
98 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
99 {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock},
100 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 4, 3, 0, &ssp0_lock},
101 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 4, 3, 0, &ssp1_lock},
102};
103
104static struct mmp_param_gate_clk apbc_gate_clks[] = {
105 {PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
106 {PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
107 {PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
108 {PXA1928_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
109 {PXA1928_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
110 {PXA1928_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI5 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
111 {PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
112 {PXA1928_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_KPC * 4, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
113 {PXA1928_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, PXA1928_CLK_RTC * 4, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
114 {PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
115 {PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
116 {PXA1928_CLK_PWM2, "pwm2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
117 {PXA1928_CLK_PWM3, "pwm3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
118 /* The gate clocks has mux parent. */
119 {PXA1928_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 0x3, 0x3, 0x0, 0, &uart0_lock},
120 {PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3, 0x0, 0, &uart1_lock},
121 {PXA1928_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 0x3, 0x3, 0x0, 0, &uart2_lock},
122 {PXA1928_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 0x3, 0x3, 0x0, 0, &uart3_lock},
123 {PXA1928_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 0x3, 0x3, 0x0, 0, &ssp0_lock},
124 {PXA1928_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 0x3, 0x3, 0x0, 0, &ssp1_lock},
125};
126
127static void pxa1928_apb_periph_clk_init(struct pxa1928_clk_unit *pxa_unit)
128{
129 struct mmp_clk_unit *unit = &pxa_unit->unit;
130
131 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
132 ARRAY_SIZE(apbc_mux_clks));
133
134 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
135 ARRAY_SIZE(apbc_gate_clks));
136}
137
138static DEFINE_SPINLOCK(sdh0_lock);
139static DEFINE_SPINLOCK(sdh1_lock);
140static DEFINE_SPINLOCK(sdh2_lock);
141static DEFINE_SPINLOCK(sdh3_lock);
142static DEFINE_SPINLOCK(sdh4_lock);
143static const char *sdh_parent_names[] = {"pll1_624", "pll5p", "pll5", "pll1_416"};
144
145static DEFINE_SPINLOCK(usb_lock);
146
147static struct mmp_param_mux_clk apmu_mux_clks[] = {
148 {0, "sdh_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 8, 2, 0, &sdh0_lock},
149};
150
151static struct mmp_param_div_clk apmu_div_clks[] = {
152 {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock},
153};
154
155static struct mmp_param_gate_clk apmu_gate_clks[] = {
156 {PXA1928_CLK_USB, "usb_clk", "usb_pll", 0, PXA1928_CLK_USB * 4, 0x9, 0x9, 0x0, 0, &usb_lock},
157 {PXA1928_CLK_HSIC, "hsic_clk", "usb_pll", 0, PXA1928_CLK_HSIC * 4, 0x9, 0x9, 0x0, 0, &usb_lock},
158 /* The gate clocks has mux parent. */
159 {PXA1928_CLK_SDH0, "sdh0_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
160 {PXA1928_CLK_SDH1, "sdh1_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH1 * 4, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
161 {PXA1928_CLK_SDH2, "sdh2_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH2 * 4, 0x1b, 0x1b, 0x0, 0, &sdh2_lock},
162 {PXA1928_CLK_SDH3, "sdh3_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH3 * 4, 0x1b, 0x1b, 0x0, 0, &sdh3_lock},
163 {PXA1928_CLK_SDH4, "sdh4_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH4 * 4, 0x1b, 0x1b, 0x0, 0, &sdh4_lock},
164};
165
166static void pxa1928_axi_periph_clk_init(struct pxa1928_clk_unit *pxa_unit)
167{
168 struct mmp_clk_unit *unit = &pxa_unit->unit;
169
170 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
171 ARRAY_SIZE(apmu_mux_clks));
172
173 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
174 ARRAY_SIZE(apmu_div_clks));
175
176 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
177 ARRAY_SIZE(apmu_gate_clks));
178}
179
180static void pxa1928_clk_reset_init(struct device_node *np,
181 struct pxa1928_clk_unit *pxa_unit)
182{
183 struct mmp_clk_reset_cell *cells;
184 int i, base, nr_resets;
185
186 nr_resets = ARRAY_SIZE(apbc_gate_clks);
187 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
188 if (!cells)
189 return;
190
191 base = 0;
192 for (i = 0; i < nr_resets; i++) {
193 cells[base + i].clk_id = apbc_gate_clks[i].id;
194 cells[base + i].reg =
195 pxa_unit->apbc_base + apbc_gate_clks[i].offset;
196 cells[base + i].flags = 0;
197 cells[base + i].lock = apbc_gate_clks[i].lock;
198 cells[base + i].bits = 0x4;
199 }
200
201 mmp_clk_reset_register(np, cells, nr_resets);
202}
203
204static void __init pxa1928_mpmu_clk_init(struct device_node *np)
205{
206 struct pxa1928_clk_unit *pxa_unit;
207
208 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
209 if (!pxa_unit)
210 return;
211
212 pxa_unit->mpmu_base = of_iomap(np, 0);
213 if (!pxa_unit->mpmu_base) {
214 pr_err("failed to map mpmu registers\n");
215 kfree(pxa_unit);
216 return;
217 }
218
219 pxa1928_pll_init(pxa_unit);
220}
221CLK_OF_DECLARE(pxa1928_mpmu_clk, "marvell,pxa1928-mpmu", pxa1928_mpmu_clk_init);
222
223static void __init pxa1928_apmu_clk_init(struct device_node *np)
224{
225 struct pxa1928_clk_unit *pxa_unit;
226
227 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
228 if (!pxa_unit)
229 return;
230
231 pxa_unit->apmu_base = of_iomap(np, 0);
232 if (!pxa_unit->apmu_base) {
233 pr_err("failed to map apmu registers\n");
234 kfree(pxa_unit);
235 return;
236 }
237
238 mmp_clk_init(np, &pxa_unit->unit, PXA1928_APMU_NR_CLKS);
239
240 pxa1928_axi_periph_clk_init(pxa_unit);
241}
242CLK_OF_DECLARE(pxa1928_apmu_clk, "marvell,pxa1928-apmu", pxa1928_apmu_clk_init);
243
244static void __init pxa1928_apbc_clk_init(struct device_node *np)
245{
246 struct pxa1928_clk_unit *pxa_unit;
247
248 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
249 if (!pxa_unit)
250 return;
251
252 pxa_unit->apbc_base = of_iomap(np, 0);
253 if (!pxa_unit->apbc_base) {
254 pr_err("failed to map apbc registers\n");
255 kfree(pxa_unit);
256 return;
257 }
258
259 mmp_clk_init(np, &pxa_unit->unit, PXA1928_APBC_NR_CLKS);
260
261 pxa1928_apb_periph_clk_init(pxa_unit);
262 pxa1928_clk_reset_init(np, pxa_unit);
263}
264CLK_OF_DECLARE(pxa1928_apbc_clk, "marvell,pxa1928-apbc", pxa1928_apbc_clk_init);