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1/*
2 * OpenRISC entry.S
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/linkage.h>
20
21#include <asm/processor.h>
22#include <asm/unistd.h>
23#include <asm/thread_info.h>
24#include <asm/errno.h>
25#include <asm/spr_defs.h>
26#include <asm/page.h>
27#include <asm/mmu.h>
28#include <asm/pgtable.h>
29#include <asm/asm-offsets.h>
30
31#define DISABLE_INTERRUPTS(t1,t2) \
32 l.mfspr t2,r0,SPR_SR ;\
33 l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
34 l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
35 l.and t2,t2,t1 ;\
36 l.mtspr r0,t2,SPR_SR
37
38#define ENABLE_INTERRUPTS(t1) \
39 l.mfspr t1,r0,SPR_SR ;\
40 l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\
41 l.mtspr r0,t1,SPR_SR
42
43/* =========================================================[ macros ]=== */
44
45/*
46 * We need to disable interrupts at beginning of RESTORE_ALL
47 * since interrupt might come in after we've loaded EPC return address
48 * and overwrite EPC with address somewhere in RESTORE_ALL
49 * which is of course wrong!
50 */
51
52#define RESTORE_ALL \
53 DISABLE_INTERRUPTS(r3,r4) ;\
54 l.lwz r3,PT_PC(r1) ;\
55 l.mtspr r0,r3,SPR_EPCR_BASE ;\
56 l.lwz r3,PT_SR(r1) ;\
57 l.mtspr r0,r3,SPR_ESR_BASE ;\
58 l.lwz r2,PT_GPR2(r1) ;\
59 l.lwz r3,PT_GPR3(r1) ;\
60 l.lwz r4,PT_GPR4(r1) ;\
61 l.lwz r5,PT_GPR5(r1) ;\
62 l.lwz r6,PT_GPR6(r1) ;\
63 l.lwz r7,PT_GPR7(r1) ;\
64 l.lwz r8,PT_GPR8(r1) ;\
65 l.lwz r9,PT_GPR9(r1) ;\
66 l.lwz r10,PT_GPR10(r1) ;\
67 l.lwz r11,PT_GPR11(r1) ;\
68 l.lwz r12,PT_GPR12(r1) ;\
69 l.lwz r13,PT_GPR13(r1) ;\
70 l.lwz r14,PT_GPR14(r1) ;\
71 l.lwz r15,PT_GPR15(r1) ;\
72 l.lwz r16,PT_GPR16(r1) ;\
73 l.lwz r17,PT_GPR17(r1) ;\
74 l.lwz r18,PT_GPR18(r1) ;\
75 l.lwz r19,PT_GPR19(r1) ;\
76 l.lwz r20,PT_GPR20(r1) ;\
77 l.lwz r21,PT_GPR21(r1) ;\
78 l.lwz r22,PT_GPR22(r1) ;\
79 l.lwz r23,PT_GPR23(r1) ;\
80 l.lwz r24,PT_GPR24(r1) ;\
81 l.lwz r25,PT_GPR25(r1) ;\
82 l.lwz r26,PT_GPR26(r1) ;\
83 l.lwz r27,PT_GPR27(r1) ;\
84 l.lwz r28,PT_GPR28(r1) ;\
85 l.lwz r29,PT_GPR29(r1) ;\
86 l.lwz r30,PT_GPR30(r1) ;\
87 l.lwz r31,PT_GPR31(r1) ;\
88 l.lwz r1,PT_SP(r1) ;\
89 l.rfe
90
91
92#define EXCEPTION_ENTRY(handler) \
93 .global handler ;\
94handler: ;\
95 /* r1, EPCR, ESR a already saved */ ;\
96 l.sw PT_GPR2(r1),r2 ;\
97 l.sw PT_GPR3(r1),r3 ;\
98 l.sw PT_ORIG_GPR11(r1),r11 ;\
99 /* r4 already save */ ;\
100 l.sw PT_GPR5(r1),r5 ;\
101 l.sw PT_GPR6(r1),r6 ;\
102 l.sw PT_GPR7(r1),r7 ;\
103 l.sw PT_GPR8(r1),r8 ;\
104 l.sw PT_GPR9(r1),r9 ;\
105 /* r10 already saved */ ;\
106 l.sw PT_GPR11(r1),r11 ;\
107 /* r12 already saved */ ;\
108 l.sw PT_GPR13(r1),r13 ;\
109 l.sw PT_GPR14(r1),r14 ;\
110 l.sw PT_GPR15(r1),r15 ;\
111 l.sw PT_GPR16(r1),r16 ;\
112 l.sw PT_GPR17(r1),r17 ;\
113 l.sw PT_GPR18(r1),r18 ;\
114 l.sw PT_GPR19(r1),r19 ;\
115 l.sw PT_GPR20(r1),r20 ;\
116 l.sw PT_GPR21(r1),r21 ;\
117 l.sw PT_GPR22(r1),r22 ;\
118 l.sw PT_GPR23(r1),r23 ;\
119 l.sw PT_GPR24(r1),r24 ;\
120 l.sw PT_GPR25(r1),r25 ;\
121 l.sw PT_GPR26(r1),r26 ;\
122 l.sw PT_GPR27(r1),r27 ;\
123 l.sw PT_GPR28(r1),r28 ;\
124 l.sw PT_GPR29(r1),r29 ;\
125 /* r30 already save */ ;\
126/* l.sw PT_GPR30(r1),r30*/ ;\
127 l.sw PT_GPR31(r1),r31 ;\
128 l.sw PT_SYSCALLNO(r1),r0
129
130#define UNHANDLED_EXCEPTION(handler,vector) \
131 .global handler ;\
132handler: ;\
133 /* r1, EPCR, ESR already saved */ ;\
134 l.sw PT_GPR2(r1),r2 ;\
135 l.sw PT_GPR3(r1),r3 ;\
136 l.sw PT_ORIG_GPR11(r1),r11 ;\
137 l.sw PT_GPR5(r1),r5 ;\
138 l.sw PT_GPR6(r1),r6 ;\
139 l.sw PT_GPR7(r1),r7 ;\
140 l.sw PT_GPR8(r1),r8 ;\
141 l.sw PT_GPR9(r1),r9 ;\
142 /* r10 already saved */ ;\
143 l.sw PT_GPR11(r1),r11 ;\
144 /* r12 already saved */ ;\
145 l.sw PT_GPR13(r1),r13 ;\
146 l.sw PT_GPR14(r1),r14 ;\
147 l.sw PT_GPR15(r1),r15 ;\
148 l.sw PT_GPR16(r1),r16 ;\
149 l.sw PT_GPR17(r1),r17 ;\
150 l.sw PT_GPR18(r1),r18 ;\
151 l.sw PT_GPR19(r1),r19 ;\
152 l.sw PT_GPR20(r1),r20 ;\
153 l.sw PT_GPR21(r1),r21 ;\
154 l.sw PT_GPR22(r1),r22 ;\
155 l.sw PT_GPR23(r1),r23 ;\
156 l.sw PT_GPR24(r1),r24 ;\
157 l.sw PT_GPR25(r1),r25 ;\
158 l.sw PT_GPR26(r1),r26 ;\
159 l.sw PT_GPR27(r1),r27 ;\
160 l.sw PT_GPR28(r1),r28 ;\
161 l.sw PT_GPR29(r1),r29 ;\
162 /* r31 already saved */ ;\
163 l.sw PT_GPR30(r1),r30 ;\
164/* l.sw PT_GPR31(r1),r31 */ ;\
165 l.sw PT_SYSCALLNO(r1),r0 ;\
166 l.addi r3,r1,0 ;\
167 /* r4 is exception EA */ ;\
168 l.addi r5,r0,vector ;\
169 l.jal unhandled_exception ;\
170 l.nop ;\
171 l.j _ret_from_exception ;\
172 l.nop
173
174/*
175 * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
176 * contain the same values as when exception we're handling
177 * occured. in fact they never do. if you need them use
178 * values saved on stack (for SPR_EPC, SPR_ESR) or content
179 * of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
180 * in 'arch/or32/kernel/head.S'
181 */
182
183/* =====================================================[ exceptions] === */
184
185/* ---[ 0x100: RESET exception ]----------------------------------------- */
186
187EXCEPTION_ENTRY(_tng_kernel_start)
188 l.jal _start
189 l.andi r0,r0,0
190
191/* ---[ 0x200: BUS exception ]------------------------------------------- */
192
193EXCEPTION_ENTRY(_bus_fault_handler)
194 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
195 l.jal do_bus_fault
196 l.addi r3,r1,0 /* pt_regs */
197
198 l.j _ret_from_exception
199 l.nop
200
201/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
202
203EXCEPTION_ENTRY(_data_page_fault_handler)
204 /* set up parameters for do_page_fault */
205 l.addi r3,r1,0 // pt_regs
206 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
207 l.ori r5,r0,0x300 // exception vector
208
209 /*
210 * __PHX__: TODO
211 *
212 * all this can be written much simpler. look at
213 * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
214 */
215#ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
216 l.lwz r6,PT_PC(r3) // address of an offending insn
217 l.lwz r6,0(r6) // instruction that caused pf
218
219 l.srli r6,r6,26 // check opcode for jump insn
220 l.sfeqi r6,0 // l.j
221 l.bf 8f
222 l.sfeqi r6,1 // l.jal
223 l.bf 8f
224 l.sfeqi r6,3 // l.bnf
225 l.bf 8f
226 l.sfeqi r6,4 // l.bf
227 l.bf 8f
228 l.sfeqi r6,0x11 // l.jr
229 l.bf 8f
230 l.sfeqi r6,0x12 // l.jalr
231 l.bf 8f
232
233 l.nop
234
235 l.j 9f
236 l.nop
2378:
238
239 l.lwz r6,PT_PC(r3) // address of an offending insn
240 l.addi r6,r6,4
241 l.lwz r6,0(r6) // instruction that caused pf
242 l.srli r6,r6,26 // get opcode
2439:
244
245#else
246
247 l.mfspr r6,r0,SPR_SR // SR
248// l.lwz r6,PT_SR(r3) // ESR
249 l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
250 l.sfeqi r6,0x1 // exception happened in delay slot
251 l.bnf 7f
252 l.lwz r6,PT_PC(r3) // address of an offending insn
253
254 l.addi r6,r6,4 // offending insn is in delay slot
2557:
256 l.lwz r6,0(r6) // instruction that caused pf
257 l.srli r6,r6,26 // check opcode for write access
258#endif
259
260 l.sfgeui r6,0x34 // check opcode for write access
261 l.bnf 1f
262 l.sfleui r6,0x37
263 l.bnf 1f
264 l.ori r6,r0,0x1 // write access
265 l.j 2f
266 l.nop
2671: l.ori r6,r0,0x0 // !write access
2682:
269
270 /* call fault.c handler in or32/mm/fault.c */
271 l.jal do_page_fault
272 l.nop
273 l.j _ret_from_exception
274 l.nop
275
276/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
277
278EXCEPTION_ENTRY(_insn_page_fault_handler)
279 /* set up parameters for do_page_fault */
280 l.addi r3,r1,0 // pt_regs
281 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
282 l.ori r5,r0,0x400 // exception vector
283 l.ori r6,r0,0x0 // !write access
284
285 /* call fault.c handler in or32/mm/fault.c */
286 l.jal do_page_fault
287 l.nop
288 l.j _ret_from_exception
289 l.nop
290
291
292/* ---[ 0x500: Timer exception ]----------------------------------------- */
293
294EXCEPTION_ENTRY(_timer_handler)
295 l.jal timer_interrupt
296 l.addi r3,r1,0 /* pt_regs */
297
298 l.j _ret_from_intr
299 l.nop
300
301/* ---[ 0x600: Aligment exception ]-------------------------------------- */
302
303EXCEPTION_ENTRY(_alignment_handler)
304 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
305 l.jal do_unaligned_access
306 l.addi r3,r1,0 /* pt_regs */
307
308 l.j _ret_from_exception
309 l.nop
310
311#if 0
312EXCEPTION_ENTRY(_aligment_handler)
313// l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
314 l.addi r2,r4,0
315// l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
316 l.lwz r5,PT_PC(r1)
317
318 l.lwz r3,0(r5) /* Load insn */
319 l.srli r4,r3,26 /* Shift left to get the insn opcode */
320
321 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
322 l.bf jmp
323 l.sfeqi r4,0x01
324 l.bf jmp
325 l.sfeqi r4,0x03
326 l.bf jmp
327 l.sfeqi r4,0x04
328 l.bf jmp
329 l.sfeqi r4,0x11
330 l.bf jr
331 l.sfeqi r4,0x12
332 l.bf jr
333 l.nop
334 l.j 1f
335 l.addi r5,r5,4 /* Increment PC to get return insn address */
336
337jmp:
338 l.slli r4,r3,6 /* Get the signed extended jump length */
339 l.srai r4,r4,4
340
341 l.lwz r3,4(r5) /* Load the real load/store insn */
342
343 l.add r5,r5,r4 /* Calculate jump target address */
344
345 l.j 1f
346 l.srli r4,r3,26 /* Shift left to get the insn opcode */
347
348jr:
349 l.slli r4,r3,9 /* Shift to get the reg nb */
350 l.andi r4,r4,0x7c
351
352 l.lwz r3,4(r5) /* Load the real load/store insn */
353
354 l.add r4,r4,r1 /* Load the jump register value from the stack */
355 l.lwz r5,0(r4)
356
357 l.srli r4,r3,26 /* Shift left to get the insn opcode */
358
359
3601:
361// l.mtspr r0,r5,SPR_EPCR_BASE
362 l.sw PT_PC(r1),r5
363
364 l.sfeqi r4,0x26
365 l.bf lhs
366 l.sfeqi r4,0x25
367 l.bf lhz
368 l.sfeqi r4,0x22
369 l.bf lws
370 l.sfeqi r4,0x21
371 l.bf lwz
372 l.sfeqi r4,0x37
373 l.bf sh
374 l.sfeqi r4,0x35
375 l.bf sw
376 l.nop
377
3781: l.j 1b /* I don't know what to do */
379 l.nop
380
381lhs: l.lbs r5,0(r2)
382 l.slli r5,r5,8
383 l.lbz r6,1(r2)
384 l.or r5,r5,r6
385 l.srli r4,r3,19
386 l.andi r4,r4,0x7c
387 l.add r4,r4,r1
388 l.j align_end
389 l.sw 0(r4),r5
390
391lhz: l.lbz r5,0(r2)
392 l.slli r5,r5,8
393 l.lbz r6,1(r2)
394 l.or r5,r5,r6
395 l.srli r4,r3,19
396 l.andi r4,r4,0x7c
397 l.add r4,r4,r1
398 l.j align_end
399 l.sw 0(r4),r5
400
401lws: l.lbs r5,0(r2)
402 l.slli r5,r5,24
403 l.lbz r6,1(r2)
404 l.slli r6,r6,16
405 l.or r5,r5,r6
406 l.lbz r6,2(r2)
407 l.slli r6,r6,8
408 l.or r5,r5,r6
409 l.lbz r6,3(r2)
410 l.or r5,r5,r6
411 l.srli r4,r3,19
412 l.andi r4,r4,0x7c
413 l.add r4,r4,r1
414 l.j align_end
415 l.sw 0(r4),r5
416
417lwz: l.lbz r5,0(r2)
418 l.slli r5,r5,24
419 l.lbz r6,1(r2)
420 l.slli r6,r6,16
421 l.or r5,r5,r6
422 l.lbz r6,2(r2)
423 l.slli r6,r6,8
424 l.or r5,r5,r6
425 l.lbz r6,3(r2)
426 l.or r5,r5,r6
427 l.srli r4,r3,19
428 l.andi r4,r4,0x7c
429 l.add r4,r4,r1
430 l.j align_end
431 l.sw 0(r4),r5
432
433sh:
434 l.srli r4,r3,9
435 l.andi r4,r4,0x7c
436 l.add r4,r4,r1
437 l.lwz r5,0(r4)
438 l.sb 1(r2),r5
439 l.srli r5,r5,8
440 l.j align_end
441 l.sb 0(r2),r5
442
443sw:
444 l.srli r4,r3,9
445 l.andi r4,r4,0x7c
446 l.add r4,r4,r1
447 l.lwz r5,0(r4)
448 l.sb 3(r2),r5
449 l.srli r5,r5,8
450 l.sb 2(r2),r5
451 l.srli r5,r5,8
452 l.sb 1(r2),r5
453 l.srli r5,r5,8
454 l.j align_end
455 l.sb 0(r2),r5
456
457align_end:
458 l.j _ret_from_intr
459 l.nop
460#endif
461
462/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
463
464EXCEPTION_ENTRY(_illegal_instruction_handler)
465 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
466 l.jal do_illegal_instruction
467 l.addi r3,r1,0 /* pt_regs */
468
469 l.j _ret_from_exception
470 l.nop
471
472/* ---[ 0x800: External interrupt exception ]---------------------------- */
473
474EXCEPTION_ENTRY(_external_irq_handler)
475#ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
476 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
477 l.andi r4,r4,SPR_SR_IEE
478 l.sfeqi r4,0
479 l.bnf 1f // ext irq enabled, all ok.
480 l.nop
481
482 l.addi r1,r1,-0x8
483 l.movhi r3,hi(42f)
484 l.ori r3,r3,lo(42f)
485 l.sw 0x0(r1),r3
486 l.jal printk
487 l.sw 0x4(r1),r4
488 l.addi r1,r1,0x8
489
490 .section .rodata, "a"
49142:
492 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
493 .align 4
494 .previous
495
496 l.ori r4,r4,SPR_SR_IEE // fix the bug
497// l.sw PT_SR(r1),r4
4981:
499#endif
500 l.addi r3,r1,0
501 l.movhi r8,hi(do_IRQ)
502 l.ori r8,r8,lo(do_IRQ)
503 l.jalr r8
504 l.nop
505 l.j _ret_from_intr
506 l.nop
507
508/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
509
510
511/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
512
513
514/* ---[ 0xb00: Range exception ]----------------------------------------- */
515
516UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
517
518/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
519
520/*
521 * Syscalls are a special type of exception in that they are
522 * _explicitly_ invoked by userspace and can therefore be
523 * held to conform to the same ABI as normal functions with
524 * respect to whether registers are preserved across the call
525 * or not.
526 */
527
528/* Upon syscall entry we just save the callee-saved registers
529 * and not the call-clobbered ones.
530 */
531
532_string_syscall_return:
533 .string "syscall return %ld \n\r\0"
534 .align 4
535
536ENTRY(_sys_call_handler)
537 /* syscalls run with interrupts enabled */
538 ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp
539
540 /* r1, EPCR, ESR a already saved */
541 l.sw PT_GPR2(r1),r2
542 /* r3-r8 must be saved because syscall restart relies
543 * on us being able to restart the syscall args... technically
544 * they should be clobbered, otherwise
545 */
546 l.sw PT_GPR3(r1),r3
547 /* r4 already saved */
548 /* r4 holds the EEAR address of the fault, load the original r4 */
549 l.lwz r4,PT_GPR4(r1)
550 l.sw PT_GPR5(r1),r5
551 l.sw PT_GPR6(r1),r6
552 l.sw PT_GPR7(r1),r7
553 l.sw PT_GPR8(r1),r8
554 l.sw PT_GPR9(r1),r9
555 /* r10 already saved */
556 l.sw PT_GPR11(r1),r11
557 l.sw PT_ORIG_GPR11(r1),r11
558 /* r12,r13 already saved */
559
560 /* r14-r28 (even) aren't touched by the syscall fast path below
561 * so we don't need to save them. However, the functions that return
562 * to userspace via a call to switch() DO need to save these because
563 * switch() effectively clobbers them... saving these registers for
564 * such functions is handled in their syscall wrappers (see fork, vfork,
565 * and clone, below).
566
567 /* r30 is the only register we clobber in the fast path */
568 /* r30 already saved */
569/* l.sw PT_GPR30(r1),r30 */
570 /* This is used by do_signal to determine whether to check for
571 * syscall restart or not */
572 l.sw PT_SYSCALLNO(r1),r11
573
574_syscall_check_trace_enter:
575 /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
576 l.lwz r30,TI_FLAGS(r10)
577 l.andi r30,r30,_TIF_SYSCALL_TRACE
578 l.sfne r30,r0
579 l.bf _syscall_trace_enter
580 l.nop
581
582_syscall_check:
583 /* Ensure that the syscall number is reasonable */
584 l.sfgeui r11,__NR_syscalls
585 l.bf _syscall_badsys
586 l.nop
587
588_syscall_call:
589 l.movhi r29,hi(sys_call_table)
590 l.ori r29,r29,lo(sys_call_table)
591 l.slli r11,r11,2
592 l.add r29,r29,r11
593 l.lwz r29,0(r29)
594
595 l.jalr r29
596 l.nop
597
598_syscall_return:
599 /* All syscalls return here... just pay attention to ret_from_fork
600 * which does it in a round-about way.
601 */
602 l.sw PT_GPR11(r1),r11 // save return value
603
604#if 0
605_syscall_debug:
606 l.movhi r3,hi(_string_syscall_return)
607 l.ori r3,r3,lo(_string_syscall_return)
608 l.ori r27,r0,1
609 l.sw -4(r1),r27
610 l.sw -8(r1),r11
611 l.addi r1,r1,-8
612 l.movhi r27,hi(printk)
613 l.ori r27,r27,lo(printk)
614 l.jalr r27
615 l.nop
616 l.addi r1,r1,8
617#endif
618
619_syscall_check_trace_leave:
620 /* r30 is a callee-saved register so this should still hold the
621 * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
622 * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
623 */
624 l.sfne r30,r0
625 l.bf _syscall_trace_leave
626 l.nop
627
628/* This is where the exception-return code begins... interrupts need to be
629 * disabled the rest of the way here because we can't afford to miss any
630 * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
631
632_syscall_check_work:
633 /* Here we need to disable interrupts */
634 DISABLE_INTERRUPTS(r27,r29)
635 l.lwz r30,TI_FLAGS(r10)
636 l.andi r30,r30,_TIF_WORK_MASK
637 l.sfne r30,r0
638
639 l.bnf _syscall_resume_userspace
640 l.nop
641
642 /* Work pending follows a different return path, so we need to
643 * make sure that all the call-saved registers get into pt_regs
644 * before branching...
645 */
646 l.sw PT_GPR14(r1),r14
647 l.sw PT_GPR16(r1),r16
648 l.sw PT_GPR18(r1),r18
649 l.sw PT_GPR20(r1),r20
650 l.sw PT_GPR22(r1),r22
651 l.sw PT_GPR24(r1),r24
652 l.sw PT_GPR26(r1),r26
653 l.sw PT_GPR28(r1),r28
654
655 /* _work_pending needs to be called with interrupts disabled */
656 l.j _work_pending
657 l.nop
658
659_syscall_resume_userspace:
660// ENABLE_INTERRUPTS(r29)
661
662
663/* This is the hot path for returning to userspace from a syscall. If there's
664 * work to be done and the branch to _work_pending was taken above, then the
665 * return to userspace will be done via the normal exception return path...
666 * that path restores _all_ registers and will overwrite the "clobbered"
667 * registers with whatever garbage is in pt_regs -- that's OK because those
668 * registers are clobbered anyway and because the extra work is insignificant
669 * in the context of the extra work that _work_pending is doing.
670
671/* Once again, syscalls are special and only guarantee to preserve the
672 * same registers as a normal function call */
673
674/* The assumption here is that the registers r14-r28 (even) are untouched and
675 * don't need to be restored... be sure that that's really the case!
676 */
677
678/* This is still too much... we should only be restoring what we actually
679 * clobbered... we should even be using 'scratch' (odd) regs above so that
680 * we don't need to restore anything, hardly...
681 */
682
683 l.lwz r2,PT_GPR2(r1)
684
685 /* Restore args */
686 /* r3-r8 are technically clobbered, but syscall restart needs these
687 * to be restored...
688 */
689 l.lwz r3,PT_GPR3(r1)
690 l.lwz r4,PT_GPR4(r1)
691 l.lwz r5,PT_GPR5(r1)
692 l.lwz r6,PT_GPR6(r1)
693 l.lwz r7,PT_GPR7(r1)
694 l.lwz r8,PT_GPR8(r1)
695
696 l.lwz r9,PT_GPR9(r1)
697 l.lwz r10,PT_GPR10(r1)
698 l.lwz r11,PT_GPR11(r1)
699
700 /* r30 is the only register we clobber in the fast path */
701 l.lwz r30,PT_GPR30(r1)
702
703 /* Here we use r13-r19 (odd) as scratch regs */
704 l.lwz r13,PT_PC(r1)
705 l.lwz r15,PT_SR(r1)
706 l.lwz r1,PT_SP(r1)
707 /* Interrupts need to be disabled for setting EPCR and ESR
708 * so that another interrupt doesn't come in here and clobber
709 * them before we can use them for our l.rfe */
710 DISABLE_INTERRUPTS(r17,r19)
711 l.mtspr r0,r13,SPR_EPCR_BASE
712 l.mtspr r0,r15,SPR_ESR_BASE
713 l.rfe
714
715/* End of hot path!
716 * Keep the below tracing and error handling out of the hot path...
717*/
718
719_syscall_trace_enter:
720 /* Here we pass pt_regs to do_syscall_trace_enter. Make sure
721 * that function is really getting all the info it needs as
722 * pt_regs isn't a complete set of userspace regs, just the
723 * ones relevant to the syscall...
724 *
725 * Note use of delay slot for setting argument.
726 */
727 l.jal do_syscall_trace_enter
728 l.addi r3,r1,0
729
730 /* Restore arguments (not preserved across do_syscall_trace_enter)
731 * so that we can do the syscall for real and return to the syscall
732 * hot path.
733 */
734 l.lwz r11,PT_SYSCALLNO(r1)
735 l.lwz r3,PT_GPR3(r1)
736 l.lwz r4,PT_GPR4(r1)
737 l.lwz r5,PT_GPR5(r1)
738 l.lwz r6,PT_GPR6(r1)
739 l.lwz r7,PT_GPR7(r1)
740
741 l.j _syscall_check
742 l.lwz r8,PT_GPR8(r1)
743
744_syscall_trace_leave:
745 l.jal do_syscall_trace_leave
746 l.addi r3,r1,0
747
748 l.j _syscall_check_work
749 l.nop
750
751_syscall_badsys:
752 /* Here we effectively pretend to have executed an imaginary
753 * syscall that returns -ENOSYS and then return to the regular
754 * syscall hot path.
755 * Note that "return value" is set in the delay slot...
756 */
757 l.j _syscall_return
758 l.addi r11,r0,-ENOSYS
759
760/******* END SYSCALL HANDLING *******/
761
762/* ---[ 0xd00: Trap exception ]------------------------------------------ */
763
764UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
765
766/* ---[ 0xe00: Trap exception ]------------------------------------------ */
767
768EXCEPTION_ENTRY(_trap_handler)
769 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
770 l.jal do_trap
771 l.addi r3,r1,0 /* pt_regs */
772
773 l.j _ret_from_exception
774 l.nop
775
776/* ---[ 0xf00: Reserved exception ]-------------------------------------- */
777
778UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
779
780/* ---[ 0x1000: Reserved exception ]------------------------------------- */
781
782UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
783
784/* ---[ 0x1100: Reserved exception ]------------------------------------- */
785
786UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
787
788/* ---[ 0x1200: Reserved exception ]------------------------------------- */
789
790UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
791
792/* ---[ 0x1300: Reserved exception ]------------------------------------- */
793
794UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
795
796/* ---[ 0x1400: Reserved exception ]------------------------------------- */
797
798UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
799
800/* ---[ 0x1500: Reserved exception ]------------------------------------- */
801
802UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
803
804/* ---[ 0x1600: Reserved exception ]------------------------------------- */
805
806UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
807
808/* ---[ 0x1700: Reserved exception ]------------------------------------- */
809
810UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
811
812/* ---[ 0x1800: Reserved exception ]------------------------------------- */
813
814UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
815
816/* ---[ 0x1900: Reserved exception ]------------------------------------- */
817
818UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
819
820/* ---[ 0x1a00: Reserved exception ]------------------------------------- */
821
822UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
823
824/* ---[ 0x1b00: Reserved exception ]------------------------------------- */
825
826UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
827
828/* ---[ 0x1c00: Reserved exception ]------------------------------------- */
829
830UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
831
832/* ---[ 0x1d00: Reserved exception ]------------------------------------- */
833
834UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
835
836/* ---[ 0x1e00: Reserved exception ]------------------------------------- */
837
838UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
839
840/* ---[ 0x1f00: Reserved exception ]------------------------------------- */
841
842UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
843
844/* ========================================================[ return ] === */
845
846_work_pending:
847 /*
848 * if (current_thread_info->flags & _TIF_NEED_RESCHED)
849 * schedule();
850 */
851 l.lwz r5,TI_FLAGS(r10)
852 l.andi r3,r5,_TIF_NEED_RESCHED
853 l.sfnei r3,0
854 l.bnf _work_notifysig
855 l.nop
856 l.jal schedule
857 l.nop
858 l.j _resume_userspace
859 l.nop
860
861/* Handle pending signals and notify-resume requests.
862 * do_notify_resume must be passed the latest pushed pt_regs, not
863 * necessarily the "userspace" ones. Also, pt_regs->syscallno
864 * must be set so that the syscall restart functionality works.
865 */
866_work_notifysig:
867 l.jal do_notify_resume
868 l.ori r3,r1,0 /* pt_regs */
869
870_resume_userspace:
871 DISABLE_INTERRUPTS(r3,r4)
872 l.lwz r3,TI_FLAGS(r10)
873 l.andi r3,r3,_TIF_WORK_MASK
874 l.sfnei r3,0
875 l.bf _work_pending
876 l.nop
877
878_restore_all:
879 RESTORE_ALL
880 /* This returns to userspace code */
881
882
883ENTRY(_ret_from_intr)
884ENTRY(_ret_from_exception)
885 l.lwz r4,PT_SR(r1)
886 l.andi r3,r4,SPR_SR_SM
887 l.sfeqi r3,0
888 l.bnf _restore_all
889 l.nop
890 l.j _resume_userspace
891 l.nop
892
893ENTRY(ret_from_fork)
894 l.jal schedule_tail
895 l.nop
896
897 /* _syscall_returns expect r11 to contain return value */
898 l.lwz r11,PT_GPR11(r1)
899
900 /* The syscall fast path return expects call-saved registers
901 * r12-r28 to be untouched, so we restore them here as they
902 * will have been effectively clobbered when arriving here
903 * via the call to switch()
904 */
905 l.lwz r12,PT_GPR12(r1)
906 l.lwz r14,PT_GPR14(r1)
907 l.lwz r16,PT_GPR16(r1)
908 l.lwz r18,PT_GPR18(r1)
909 l.lwz r20,PT_GPR20(r1)
910 l.lwz r22,PT_GPR22(r1)
911 l.lwz r24,PT_GPR24(r1)
912 l.lwz r26,PT_GPR26(r1)
913 l.lwz r28,PT_GPR28(r1)
914
915 l.j _syscall_return
916 l.nop
917
918/* Since syscalls don't save call-clobbered registers, the args to
919 * kernel_thread_helper will need to be passed through callee-saved
920 * registers and copied to the parameter registers when the thread
921 * begins running.
922 *
923 * See arch/openrisc/kernel/process.c:
924 * The args are passed as follows:
925 * arg1 (r3) : passed in r20
926 * arg2 (r4) : passed in r22
927 */
928
929ENTRY(_kernel_thread_helper)
930 l.or r3,r20,r0
931 l.or r4,r22,r0
932 l.movhi r31,hi(kernel_thread_helper)
933 l.ori r31,r31,lo(kernel_thread_helper)
934 l.jr r31
935 l.nop
936
937
938/* ========================================================[ switch ] === */
939
940/*
941 * This routine switches between two different tasks. The process
942 * state of one is saved on its kernel stack. Then the state
943 * of the other is restored from its kernel stack. The memory
944 * management hardware is updated to the second process's state.
945 * Finally, we can return to the second process, via the 'return'.
946 *
947 * Note: there are two ways to get to the "going out" portion
948 * of this code; either by coming in via the entry (_switch)
949 * or via "fork" which must set up an environment equivalent
950 * to the "_switch" path. If you change this (or in particular, the
951 * SAVE_REGS macro), you'll have to change the fork code also.
952 */
953
954
955/* _switch MUST never lay on page boundry, cause it runs from
956 * effective addresses and beeing interrupted by iTLB miss would kill it.
957 * dTLB miss seams to never accour in the bad place since data accesses
958 * are from task structures which are always page aligned.
959 *
960 * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
961 * register, then load the previous register values and only at the end call
962 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
963 * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
964 * holds for ESR)
965 *
966 * To avoid this problems it is sufficient to align _switch to
967 * some nice round number smaller than it's size...
968 */
969
970/* ABI rules apply here... we either enter _switch via schedule() or via
971 * an imaginary call to which we shall return at return_from_fork. Either
972 * way, we are a function call and only need to preserve the callee-saved
973 * registers when we return. As such, we don't need to save the registers
974 * on the stack that we won't be returning as they were...
975 */
976
977 .align 0x400
978ENTRY(_switch)
979 /* We don't store SR as _switch only gets called in a context where
980 * the SR will be the same going in and coming out... */
981
982 /* Set up new pt_regs struct for saving task state */
983 l.addi r1,r1,-(INT_FRAME_SIZE)
984
985 /* No need to store r1/PT_SP as it goes into KSP below */
986 l.sw PT_GPR2(r1),r2
987 l.sw PT_GPR9(r1),r9
988 /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
989 * and expects r12 to be callee-saved... */
990 l.sw PT_GPR12(r1),r12
991 l.sw PT_GPR14(r1),r14
992 l.sw PT_GPR16(r1),r16
993 l.sw PT_GPR18(r1),r18
994 l.sw PT_GPR20(r1),r20
995 l.sw PT_GPR22(r1),r22
996 l.sw PT_GPR24(r1),r24
997 l.sw PT_GPR26(r1),r26
998 l.sw PT_GPR28(r1),r28
999 l.sw PT_GPR30(r1),r30
1000
1001 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1002
1003 /* We use thread_info->ksp for storing the address of the above
1004 * structure so that we can get back to it later... we don't want
1005 * to lose the value of thread_info->ksp, though, so store it as
1006 * pt_regs->sp so that we can easily restore it when we are made
1007 * live again...
1008 */
1009
1010 /* Save the old value of thread_info->ksp as pt_regs->sp */
1011 l.lwz r29,TI_KSP(r10)
1012 l.sw PT_SP(r1),r29
1013
1014 /* Swap kernel stack pointers */
1015 l.sw TI_KSP(r10),r1 /* Save old stack pointer */
1016 l.or r10,r4,r0 /* Set up new current_thread_info */
1017 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
1018
1019 /* Restore the old value of thread_info->ksp */
1020 l.lwz r29,PT_SP(r1)
1021 l.sw TI_KSP(r10),r29
1022
1023 /* ...and restore the registers, except r11 because the return value
1024 * has already been set above.
1025 */
1026 l.lwz r2,PT_GPR2(r1)
1027 l.lwz r9,PT_GPR9(r1)
1028 /* No need to restore r10 */
1029 /* ...and do not restore r11 */
1030
1031 /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1032 * and expects r12 to be callee-saved... */
1033 l.lwz r12,PT_GPR12(r1)
1034 l.lwz r14,PT_GPR14(r1)
1035 l.lwz r16,PT_GPR16(r1)
1036 l.lwz r18,PT_GPR18(r1)
1037 l.lwz r20,PT_GPR20(r1)
1038 l.lwz r22,PT_GPR22(r1)
1039 l.lwz r24,PT_GPR24(r1)
1040 l.lwz r26,PT_GPR26(r1)
1041 l.lwz r28,PT_GPR28(r1)
1042 l.lwz r30,PT_GPR30(r1)
1043
1044 /* Unwind stack to pre-switch state */
1045 l.addi r1,r1,(INT_FRAME_SIZE)
1046
1047 /* Return via the link-register back to where we 'came from', where that can be
1048 * either schedule() or return_from_fork()... */
1049 l.jr r9
1050 l.nop
1051
1052/* ==================================================================== */
1053
1054/* These all use the delay slot for setting the argument register, so the
1055 * jump is always happening after the l.addi instruction.
1056 *
1057 * These are all just wrappers that don't touch the link-register r9, so the
1058 * return from the "real" syscall function will return back to the syscall
1059 * code that did the l.jal that brought us here.
1060 */
1061
1062/* fork requires that we save all the callee-saved registers because they
1063 * are all effectively clobbered by the call to _switch. Here we store
1064 * all the registers that aren't touched by the syscall fast path and thus
1065 * weren't saved there.
1066 */
1067
1068_fork_save_extra_regs_and_call:
1069 l.sw PT_GPR14(r1),r14
1070 l.sw PT_GPR16(r1),r16
1071 l.sw PT_GPR18(r1),r18
1072 l.sw PT_GPR20(r1),r20
1073 l.sw PT_GPR22(r1),r22
1074 l.sw PT_GPR24(r1),r24
1075 l.sw PT_GPR26(r1),r26
1076 l.jr r29
1077 l.sw PT_GPR28(r1),r28
1078
1079ENTRY(sys_clone)
1080 l.movhi r29,hi(_sys_clone)
1081 l.ori r29,r29,lo(_sys_clone)
1082 l.j _fork_save_extra_regs_and_call
1083 l.addi r7,r1,0
1084
1085ENTRY(sys_fork)
1086 l.movhi r29,hi(_sys_fork)
1087 l.ori r29,r29,lo(_sys_fork)
1088 l.j _fork_save_extra_regs_and_call
1089 l.addi r3,r1,0
1090
1091ENTRY(sys_execve)
1092 l.j _sys_execve
1093 l.addi r6,r1,0
1094
1095ENTRY(sys_sigaltstack)
1096 l.j _sys_sigaltstack
1097 l.addi r5,r1,0
1098
1099ENTRY(sys_rt_sigreturn)
1100 l.j _sys_rt_sigreturn
1101 l.addi r3,r1,0
1102
1103/* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1104 * The functions takes a variable number of parameters depending on which
1105 * particular flavour of atomic you want... parameter 1 is a flag identifying
1106 * the atomic in question. Currently, this function implements the
1107 * following variants:
1108 *
1109 * XCHG:
1110 * @flag: 1
1111 * @ptr1:
1112 * @ptr2:
1113 * Atomically exchange the values in pointers 1 and 2.
1114 *
1115 */
1116
1117ENTRY(sys_or1k_atomic)
1118 /* FIXME: This ignores r3 and always does an XCHG */
1119 DISABLE_INTERRUPTS(r17,r19)
1120 l.lwz r30,0(r4)
1121 l.lwz r28,0(r5)
1122 l.sw 0(r4),r28
1123 l.sw 0(r5),r30
1124 ENABLE_INTERRUPTS(r17)
1125 l.jr r9
1126 l.or r11,r0,r0
1127
1128/* ============================================================[ EOF ]=== */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * OpenRISC entry.S
4 *
5 * Linux architectural port borrowing liberally from similar works of
6 * others. All original copyrights apply as per the original source
7 * declaration.
8 *
9 * Modifications for the OpenRISC architecture:
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
11 * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
13 */
14
15#include <linux/linkage.h>
16#include <linux/pgtable.h>
17
18#include <asm/processor.h>
19#include <asm/unistd.h>
20#include <asm/thread_info.h>
21#include <asm/errno.h>
22#include <asm/spr_defs.h>
23#include <asm/page.h>
24#include <asm/mmu.h>
25#include <asm/asm-offsets.h>
26
27#define DISABLE_INTERRUPTS(t1,t2) \
28 l.mfspr t2,r0,SPR_SR ;\
29 l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
30 l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
31 l.and t2,t2,t1 ;\
32 l.mtspr r0,t2,SPR_SR
33
34#define ENABLE_INTERRUPTS(t1) \
35 l.mfspr t1,r0,SPR_SR ;\
36 l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\
37 l.mtspr r0,t1,SPR_SR
38
39/* =========================================================[ macros ]=== */
40
41#ifdef CONFIG_TRACE_IRQFLAGS
42/*
43 * Trace irq on/off creating a stack frame.
44 */
45#define TRACE_IRQS_OP(trace_op) \
46 l.sw -8(r1),r2 /* store frame pointer */ ;\
47 l.sw -4(r1),r9 /* store return address */ ;\
48 l.addi r2,r1,0 /* move sp to fp */ ;\
49 l.jal trace_op ;\
50 l.addi r1,r1,-8 ;\
51 l.ori r1,r2,0 /* restore sp */ ;\
52 l.lwz r9,-4(r1) /* restore return address */ ;\
53 l.lwz r2,-8(r1) /* restore fp */ ;\
54/*
55 * Trace irq on/off and save registers we need that would otherwise be
56 * clobbered.
57 */
58#define TRACE_IRQS_SAVE(t1,trace_op) \
59 l.sw -12(r1),t1 /* save extra reg */ ;\
60 l.sw -8(r1),r2 /* store frame pointer */ ;\
61 l.sw -4(r1),r9 /* store return address */ ;\
62 l.addi r2,r1,0 /* move sp to fp */ ;\
63 l.jal trace_op ;\
64 l.addi r1,r1,-12 ;\
65 l.ori r1,r2,0 /* restore sp */ ;\
66 l.lwz r9,-4(r1) /* restore return address */ ;\
67 l.lwz r2,-8(r1) /* restore fp */ ;\
68 l.lwz t1,-12(r1) /* restore extra reg */
69
70#define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_hardirqs_off)
71#define TRACE_IRQS_ON TRACE_IRQS_OP(trace_hardirqs_on)
72#define TRACE_IRQS_ON_SYSCALL \
73 TRACE_IRQS_SAVE(r10,trace_hardirqs_on) ;\
74 l.lwz r3,PT_GPR3(r1) ;\
75 l.lwz r4,PT_GPR4(r1) ;\
76 l.lwz r5,PT_GPR5(r1) ;\
77 l.lwz r6,PT_GPR6(r1) ;\
78 l.lwz r7,PT_GPR7(r1) ;\
79 l.lwz r8,PT_GPR8(r1) ;\
80 l.lwz r11,PT_GPR11(r1)
81#define TRACE_IRQS_OFF_ENTRY \
82 l.lwz r5,PT_SR(r1) ;\
83 l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) ;\
84 l.sfeq r5,r0 /* skip trace if irqs were already off */;\
85 l.bf 1f ;\
86 l.nop ;\
87 TRACE_IRQS_SAVE(r4,trace_hardirqs_off) ;\
881:
89#else
90#define TRACE_IRQS_OFF
91#define TRACE_IRQS_ON
92#define TRACE_IRQS_OFF_ENTRY
93#define TRACE_IRQS_ON_SYSCALL
94#endif
95
96/*
97 * We need to disable interrupts at beginning of RESTORE_ALL
98 * since interrupt might come in after we've loaded EPC return address
99 * and overwrite EPC with address somewhere in RESTORE_ALL
100 * which is of course wrong!
101 */
102
103#define RESTORE_ALL \
104 DISABLE_INTERRUPTS(r3,r4) ;\
105 l.lwz r3,PT_PC(r1) ;\
106 l.mtspr r0,r3,SPR_EPCR_BASE ;\
107 l.lwz r3,PT_SR(r1) ;\
108 l.mtspr r0,r3,SPR_ESR_BASE ;\
109 l.lwz r2,PT_GPR2(r1) ;\
110 l.lwz r3,PT_GPR3(r1) ;\
111 l.lwz r4,PT_GPR4(r1) ;\
112 l.lwz r5,PT_GPR5(r1) ;\
113 l.lwz r6,PT_GPR6(r1) ;\
114 l.lwz r7,PT_GPR7(r1) ;\
115 l.lwz r8,PT_GPR8(r1) ;\
116 l.lwz r9,PT_GPR9(r1) ;\
117 l.lwz r10,PT_GPR10(r1) ;\
118 l.lwz r11,PT_GPR11(r1) ;\
119 l.lwz r12,PT_GPR12(r1) ;\
120 l.lwz r13,PT_GPR13(r1) ;\
121 l.lwz r14,PT_GPR14(r1) ;\
122 l.lwz r15,PT_GPR15(r1) ;\
123 l.lwz r16,PT_GPR16(r1) ;\
124 l.lwz r17,PT_GPR17(r1) ;\
125 l.lwz r18,PT_GPR18(r1) ;\
126 l.lwz r19,PT_GPR19(r1) ;\
127 l.lwz r20,PT_GPR20(r1) ;\
128 l.lwz r21,PT_GPR21(r1) ;\
129 l.lwz r22,PT_GPR22(r1) ;\
130 l.lwz r23,PT_GPR23(r1) ;\
131 l.lwz r24,PT_GPR24(r1) ;\
132 l.lwz r25,PT_GPR25(r1) ;\
133 l.lwz r26,PT_GPR26(r1) ;\
134 l.lwz r27,PT_GPR27(r1) ;\
135 l.lwz r28,PT_GPR28(r1) ;\
136 l.lwz r29,PT_GPR29(r1) ;\
137 l.lwz r30,PT_GPR30(r1) ;\
138 l.lwz r31,PT_GPR31(r1) ;\
139 l.lwz r1,PT_SP(r1) ;\
140 l.rfe
141
142
143#define EXCEPTION_ENTRY(handler) \
144 .global handler ;\
145handler: ;\
146 /* r1, EPCR, ESR a already saved */ ;\
147 l.sw PT_GPR2(r1),r2 ;\
148 l.sw PT_GPR3(r1),r3 ;\
149 /* r4 already save */ ;\
150 l.sw PT_GPR5(r1),r5 ;\
151 l.sw PT_GPR6(r1),r6 ;\
152 l.sw PT_GPR7(r1),r7 ;\
153 l.sw PT_GPR8(r1),r8 ;\
154 l.sw PT_GPR9(r1),r9 ;\
155 /* r10 already saved */ ;\
156 l.sw PT_GPR11(r1),r11 ;\
157 /* r12 already saved */ ;\
158 l.sw PT_GPR13(r1),r13 ;\
159 l.sw PT_GPR14(r1),r14 ;\
160 l.sw PT_GPR15(r1),r15 ;\
161 l.sw PT_GPR16(r1),r16 ;\
162 l.sw PT_GPR17(r1),r17 ;\
163 l.sw PT_GPR18(r1),r18 ;\
164 l.sw PT_GPR19(r1),r19 ;\
165 l.sw PT_GPR20(r1),r20 ;\
166 l.sw PT_GPR21(r1),r21 ;\
167 l.sw PT_GPR22(r1),r22 ;\
168 l.sw PT_GPR23(r1),r23 ;\
169 l.sw PT_GPR24(r1),r24 ;\
170 l.sw PT_GPR25(r1),r25 ;\
171 l.sw PT_GPR26(r1),r26 ;\
172 l.sw PT_GPR27(r1),r27 ;\
173 l.sw PT_GPR28(r1),r28 ;\
174 l.sw PT_GPR29(r1),r29 ;\
175 /* r30 already save */ ;\
176/* l.sw PT_GPR30(r1),r30*/ ;\
177 l.sw PT_GPR31(r1),r31 ;\
178 TRACE_IRQS_OFF_ENTRY ;\
179 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
180 l.addi r30,r0,-1 ;\
181 l.sw PT_ORIG_GPR11(r1),r30
182
183#define UNHANDLED_EXCEPTION(handler,vector) \
184 .global handler ;\
185handler: ;\
186 /* r1, EPCR, ESR already saved */ ;\
187 l.sw PT_GPR2(r1),r2 ;\
188 l.sw PT_GPR3(r1),r3 ;\
189 l.sw PT_GPR5(r1),r5 ;\
190 l.sw PT_GPR6(r1),r6 ;\
191 l.sw PT_GPR7(r1),r7 ;\
192 l.sw PT_GPR8(r1),r8 ;\
193 l.sw PT_GPR9(r1),r9 ;\
194 /* r10 already saved */ ;\
195 l.sw PT_GPR11(r1),r11 ;\
196 /* r12 already saved */ ;\
197 l.sw PT_GPR13(r1),r13 ;\
198 l.sw PT_GPR14(r1),r14 ;\
199 l.sw PT_GPR15(r1),r15 ;\
200 l.sw PT_GPR16(r1),r16 ;\
201 l.sw PT_GPR17(r1),r17 ;\
202 l.sw PT_GPR18(r1),r18 ;\
203 l.sw PT_GPR19(r1),r19 ;\
204 l.sw PT_GPR20(r1),r20 ;\
205 l.sw PT_GPR21(r1),r21 ;\
206 l.sw PT_GPR22(r1),r22 ;\
207 l.sw PT_GPR23(r1),r23 ;\
208 l.sw PT_GPR24(r1),r24 ;\
209 l.sw PT_GPR25(r1),r25 ;\
210 l.sw PT_GPR26(r1),r26 ;\
211 l.sw PT_GPR27(r1),r27 ;\
212 l.sw PT_GPR28(r1),r28 ;\
213 l.sw PT_GPR29(r1),r29 ;\
214 /* r31 already saved */ ;\
215 l.sw PT_GPR30(r1),r30 ;\
216/* l.sw PT_GPR31(r1),r31 */ ;\
217 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
218 l.addi r30,r0,-1 ;\
219 l.sw PT_ORIG_GPR11(r1),r30 ;\
220 l.addi r3,r1,0 ;\
221 /* r4 is exception EA */ ;\
222 l.addi r5,r0,vector ;\
223 l.jal unhandled_exception ;\
224 l.nop ;\
225 l.j _ret_from_exception ;\
226 l.nop
227
228/* clobbers 'reg' */
229#define CLEAR_LWA_FLAG(reg) \
230 l.movhi reg,hi(lwa_flag) ;\
231 l.ori reg,reg,lo(lwa_flag) ;\
232 l.sw 0(reg),r0
233/*
234 * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
235 * contain the same values as when exception we're handling
236 * occured. in fact they never do. if you need them use
237 * values saved on stack (for SPR_EPC, SPR_ESR) or content
238 * of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
239 * in 'arch/openrisc/kernel/head.S'
240 */
241
242/* =====================================================[ exceptions] === */
243
244/* ---[ 0x100: RESET exception ]----------------------------------------- */
245
246EXCEPTION_ENTRY(_tng_kernel_start)
247 l.jal _start
248 l.andi r0,r0,0
249
250/* ---[ 0x200: BUS exception ]------------------------------------------- */
251
252EXCEPTION_ENTRY(_bus_fault_handler)
253 CLEAR_LWA_FLAG(r3)
254 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
255 l.jal do_bus_fault
256 l.addi r3,r1,0 /* pt_regs */
257
258 l.j _ret_from_exception
259 l.nop
260
261/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
262EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
263 CLEAR_LWA_FLAG(r3)
264 l.and r5,r5,r0
265 l.j 1f
266 l.nop
267
268EXCEPTION_ENTRY(_data_page_fault_handler)
269 CLEAR_LWA_FLAG(r3)
270 /* set up parameters for do_page_fault */
271 l.ori r5,r0,0x300 // exception vector
2721:
273 l.addi r3,r1,0 // pt_regs
274 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
275
276#ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
277 l.lwz r6,PT_PC(r3) // address of an offending insn
278 l.lwz r6,0(r6) // instruction that caused pf
279
280 l.srli r6,r6,26 // check opcode for jump insn
281 l.sfeqi r6,0 // l.j
282 l.bf 8f
283 l.sfeqi r6,1 // l.jal
284 l.bf 8f
285 l.sfeqi r6,3 // l.bnf
286 l.bf 8f
287 l.sfeqi r6,4 // l.bf
288 l.bf 8f
289 l.sfeqi r6,0x11 // l.jr
290 l.bf 8f
291 l.sfeqi r6,0x12 // l.jalr
292 l.bf 8f
293 l.nop
294
295 l.j 9f
296 l.nop
297
2988: // offending insn is in delay slot
299 l.lwz r6,PT_PC(r3) // address of an offending insn
300 l.addi r6,r6,4
301 l.lwz r6,0(r6) // instruction that caused pf
302 l.srli r6,r6,26 // get opcode
3039: // offending instruction opcode loaded in r6
304
305#else
306
307 l.mfspr r6,r0,SPR_SR // SR
308 l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
309 l.sfne r6,r0 // exception happened in delay slot
310 l.bnf 7f
311 l.lwz r6,PT_PC(r3) // address of an offending insn
312
313 l.addi r6,r6,4 // offending insn is in delay slot
3147:
315 l.lwz r6,0(r6) // instruction that caused pf
316 l.srli r6,r6,26 // check opcode for write access
317#endif
318
319 l.sfgeui r6,0x33 // check opcode for write access
320 l.bnf 1f
321 l.sfleui r6,0x37
322 l.bnf 1f
323 l.ori r6,r0,0x1 // write access
324 l.j 2f
325 l.nop
3261: l.ori r6,r0,0x0 // !write access
3272:
328
329 /* call fault.c handler in openrisc/mm/fault.c */
330 l.jal do_page_fault
331 l.nop
332 l.j _ret_from_exception
333 l.nop
334
335/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
336EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
337 CLEAR_LWA_FLAG(r3)
338 l.and r5,r5,r0
339 l.j 1f
340 l.nop
341
342EXCEPTION_ENTRY(_insn_page_fault_handler)
343 CLEAR_LWA_FLAG(r3)
344 /* set up parameters for do_page_fault */
345 l.ori r5,r0,0x400 // exception vector
3461:
347 l.addi r3,r1,0 // pt_regs
348 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault
349 l.ori r6,r0,0x0 // !write access
350
351 /* call fault.c handler in openrisc/mm/fault.c */
352 l.jal do_page_fault
353 l.nop
354 l.j _ret_from_exception
355 l.nop
356
357
358/* ---[ 0x500: Timer exception ]----------------------------------------- */
359
360EXCEPTION_ENTRY(_timer_handler)
361 CLEAR_LWA_FLAG(r3)
362 l.jal timer_interrupt
363 l.addi r3,r1,0 /* pt_regs */
364
365 l.j _ret_from_intr
366 l.nop
367
368/* ---[ 0x600: Alignment exception ]-------------------------------------- */
369
370EXCEPTION_ENTRY(_alignment_handler)
371 CLEAR_LWA_FLAG(r3)
372 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
373 l.jal do_unaligned_access
374 l.addi r3,r1,0 /* pt_regs */
375
376 l.j _ret_from_exception
377 l.nop
378
379#if 0
380EXCEPTION_ENTRY(_alignment_handler)
381// l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
382 l.addi r2,r4,0
383// l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
384 l.lwz r5,PT_PC(r1)
385
386 l.lwz r3,0(r5) /* Load insn */
387 l.srli r4,r3,26 /* Shift left to get the insn opcode */
388
389 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
390 l.bf jmp
391 l.sfeqi r4,0x01
392 l.bf jmp
393 l.sfeqi r4,0x03
394 l.bf jmp
395 l.sfeqi r4,0x04
396 l.bf jmp
397 l.sfeqi r4,0x11
398 l.bf jr
399 l.sfeqi r4,0x12
400 l.bf jr
401 l.nop
402 l.j 1f
403 l.addi r5,r5,4 /* Increment PC to get return insn address */
404
405jmp:
406 l.slli r4,r3,6 /* Get the signed extended jump length */
407 l.srai r4,r4,4
408
409 l.lwz r3,4(r5) /* Load the real load/store insn */
410
411 l.add r5,r5,r4 /* Calculate jump target address */
412
413 l.j 1f
414 l.srli r4,r3,26 /* Shift left to get the insn opcode */
415
416jr:
417 l.slli r4,r3,9 /* Shift to get the reg nb */
418 l.andi r4,r4,0x7c
419
420 l.lwz r3,4(r5) /* Load the real load/store insn */
421
422 l.add r4,r4,r1 /* Load the jump register value from the stack */
423 l.lwz r5,0(r4)
424
425 l.srli r4,r3,26 /* Shift left to get the insn opcode */
426
427
4281:
429// l.mtspr r0,r5,SPR_EPCR_BASE
430 l.sw PT_PC(r1),r5
431
432 l.sfeqi r4,0x26
433 l.bf lhs
434 l.sfeqi r4,0x25
435 l.bf lhz
436 l.sfeqi r4,0x22
437 l.bf lws
438 l.sfeqi r4,0x21
439 l.bf lwz
440 l.sfeqi r4,0x37
441 l.bf sh
442 l.sfeqi r4,0x35
443 l.bf sw
444 l.nop
445
4461: l.j 1b /* I don't know what to do */
447 l.nop
448
449lhs: l.lbs r5,0(r2)
450 l.slli r5,r5,8
451 l.lbz r6,1(r2)
452 l.or r5,r5,r6
453 l.srli r4,r3,19
454 l.andi r4,r4,0x7c
455 l.add r4,r4,r1
456 l.j align_end
457 l.sw 0(r4),r5
458
459lhz: l.lbz r5,0(r2)
460 l.slli r5,r5,8
461 l.lbz r6,1(r2)
462 l.or r5,r5,r6
463 l.srli r4,r3,19
464 l.andi r4,r4,0x7c
465 l.add r4,r4,r1
466 l.j align_end
467 l.sw 0(r4),r5
468
469lws: l.lbs r5,0(r2)
470 l.slli r5,r5,24
471 l.lbz r6,1(r2)
472 l.slli r6,r6,16
473 l.or r5,r5,r6
474 l.lbz r6,2(r2)
475 l.slli r6,r6,8
476 l.or r5,r5,r6
477 l.lbz r6,3(r2)
478 l.or r5,r5,r6
479 l.srli r4,r3,19
480 l.andi r4,r4,0x7c
481 l.add r4,r4,r1
482 l.j align_end
483 l.sw 0(r4),r5
484
485lwz: l.lbz r5,0(r2)
486 l.slli r5,r5,24
487 l.lbz r6,1(r2)
488 l.slli r6,r6,16
489 l.or r5,r5,r6
490 l.lbz r6,2(r2)
491 l.slli r6,r6,8
492 l.or r5,r5,r6
493 l.lbz r6,3(r2)
494 l.or r5,r5,r6
495 l.srli r4,r3,19
496 l.andi r4,r4,0x7c
497 l.add r4,r4,r1
498 l.j align_end
499 l.sw 0(r4),r5
500
501sh:
502 l.srli r4,r3,9
503 l.andi r4,r4,0x7c
504 l.add r4,r4,r1
505 l.lwz r5,0(r4)
506 l.sb 1(r2),r5
507 l.srli r5,r5,8
508 l.j align_end
509 l.sb 0(r2),r5
510
511sw:
512 l.srli r4,r3,9
513 l.andi r4,r4,0x7c
514 l.add r4,r4,r1
515 l.lwz r5,0(r4)
516 l.sb 3(r2),r5
517 l.srli r5,r5,8
518 l.sb 2(r2),r5
519 l.srli r5,r5,8
520 l.sb 1(r2),r5
521 l.srli r5,r5,8
522 l.j align_end
523 l.sb 0(r2),r5
524
525align_end:
526 l.j _ret_from_intr
527 l.nop
528#endif
529
530/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
531
532EXCEPTION_ENTRY(_illegal_instruction_handler)
533 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
534 l.jal do_illegal_instruction
535 l.addi r3,r1,0 /* pt_regs */
536
537 l.j _ret_from_exception
538 l.nop
539
540/* ---[ 0x800: External interrupt exception ]---------------------------- */
541
542EXCEPTION_ENTRY(_external_irq_handler)
543#ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
544 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
545 l.andi r4,r4,SPR_SR_IEE
546 l.sfeqi r4,0
547 l.bnf 1f // ext irq enabled, all ok.
548 l.nop
549
550#ifdef CONFIG_PRINTK
551 l.addi r1,r1,-0x8
552 l.movhi r3,hi(42f)
553 l.ori r3,r3,lo(42f)
554 l.sw 0x0(r1),r3
555 l.jal _printk
556 l.sw 0x4(r1),r4
557 l.addi r1,r1,0x8
558
559 .section .rodata, "a"
56042:
561 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
562 .align 4
563 .previous
564#endif
565
566 l.ori r4,r4,SPR_SR_IEE // fix the bug
567// l.sw PT_SR(r1),r4
5681:
569#endif
570 CLEAR_LWA_FLAG(r3)
571 l.addi r3,r1,0
572 l.movhi r8,hi(generic_handle_arch_irq)
573 l.ori r8,r8,lo(generic_handle_arch_irq)
574 l.jalr r8
575 l.nop
576 l.j _ret_from_intr
577 l.nop
578
579/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
580
581
582/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
583
584
585/* ---[ 0xb00: Range exception ]----------------------------------------- */
586
587UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
588
589/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
590
591/*
592 * Syscalls are a special type of exception in that they are
593 * _explicitly_ invoked by userspace and can therefore be
594 * held to conform to the same ABI as normal functions with
595 * respect to whether registers are preserved across the call
596 * or not.
597 */
598
599/* Upon syscall entry we just save the callee-saved registers
600 * and not the call-clobbered ones.
601 */
602
603_string_syscall_return:
604 .string "syscall r9:0x%08x -> syscall(%ld) return %ld\0"
605 .align 4
606
607ENTRY(_sys_call_handler)
608 /* r1, EPCR, ESR a already saved */
609 l.sw PT_GPR2(r1),r2
610 /* r3-r8 must be saved because syscall restart relies
611 * on us being able to restart the syscall args... technically
612 * they should be clobbered, otherwise
613 */
614 l.sw PT_GPR3(r1),r3
615 /*
616 * r4 already saved
617 * r4 holds the EEAR address of the fault, use it as screatch reg and
618 * then load the original r4
619 */
620 CLEAR_LWA_FLAG(r4)
621 l.lwz r4,PT_GPR4(r1)
622 l.sw PT_GPR5(r1),r5
623 l.sw PT_GPR6(r1),r6
624 l.sw PT_GPR7(r1),r7
625 l.sw PT_GPR8(r1),r8
626 l.sw PT_GPR9(r1),r9
627 /* r10 already saved */
628 l.sw PT_GPR11(r1),r11
629 /* orig_gpr11 must be set for syscalls */
630 l.sw PT_ORIG_GPR11(r1),r11
631 /* r12,r13 already saved */
632
633 /* r14-r28 (even) aren't touched by the syscall fast path below
634 * so we don't need to save them. However, the functions that return
635 * to userspace via a call to switch() DO need to save these because
636 * switch() effectively clobbers them... saving these registers for
637 * such functions is handled in their syscall wrappers (see fork, vfork,
638 * and clone, below).
639
640 /* r30 is the only register we clobber in the fast path */
641 /* r30 already saved */
642/* l.sw PT_GPR30(r1),r30 */
643
644_syscall_check_trace_enter:
645 /* syscalls run with interrupts enabled */
646 TRACE_IRQS_ON_SYSCALL
647 ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp
648
649 /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
650 l.lwz r30,TI_FLAGS(r10)
651 l.andi r30,r30,_TIF_SYSCALL_TRACE
652 l.sfne r30,r0
653 l.bf _syscall_trace_enter
654 l.nop
655
656_syscall_check:
657 /* Ensure that the syscall number is reasonable */
658 l.sfgeui r11,__NR_syscalls
659 l.bf _syscall_badsys
660 l.nop
661
662_syscall_call:
663 l.movhi r29,hi(sys_call_table)
664 l.ori r29,r29,lo(sys_call_table)
665 l.slli r11,r11,2
666 l.add r29,r29,r11
667 l.lwz r29,0(r29)
668
669 l.jalr r29
670 l.nop
671
672_syscall_return:
673 /* All syscalls return here... just pay attention to ret_from_fork
674 * which does it in a round-about way.
675 */
676 l.sw PT_GPR11(r1),r11 // save return value
677
678#if 0
679_syscall_debug:
680 l.movhi r3,hi(_string_syscall_return)
681 l.ori r3,r3,lo(_string_syscall_return)
682 l.ori r27,r0,2
683 l.sw -4(r1),r27
684 l.sw -8(r1),r11
685 l.lwz r29,PT_ORIG_GPR11(r1)
686 l.sw -12(r1),r29
687 l.lwz r29,PT_GPR9(r1)
688 l.sw -16(r1),r29
689 l.movhi r27,hi(_printk)
690 l.ori r27,r27,lo(_printk)
691 l.jalr r27
692 l.addi r1,r1,-16
693 l.addi r1,r1,16
694#endif
695#if 0
696_syscall_show_regs:
697 l.movhi r27,hi(show_registers)
698 l.ori r27,r27,lo(show_registers)
699 l.jalr r27
700 l.or r3,r1,r1
701#endif
702
703_syscall_check_trace_leave:
704 /* r30 is a callee-saved register so this should still hold the
705 * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
706 * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
707 */
708 l.sfne r30,r0
709 l.bf _syscall_trace_leave
710 l.nop
711
712/* This is where the exception-return code begins... interrupts need to be
713 * disabled the rest of the way here because we can't afford to miss any
714 * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
715
716_syscall_check_work:
717 /* Here we need to disable interrupts */
718 DISABLE_INTERRUPTS(r27,r29)
719 TRACE_IRQS_OFF
720 l.lwz r30,TI_FLAGS(r10)
721 l.andi r30,r30,_TIF_WORK_MASK
722 l.sfne r30,r0
723
724 l.bnf _syscall_resume_userspace
725 l.nop
726
727 /* Work pending follows a different return path, so we need to
728 * make sure that all the call-saved registers get into pt_regs
729 * before branching...
730 */
731 l.sw PT_GPR14(r1),r14
732 l.sw PT_GPR16(r1),r16
733 l.sw PT_GPR18(r1),r18
734 l.sw PT_GPR20(r1),r20
735 l.sw PT_GPR22(r1),r22
736 l.sw PT_GPR24(r1),r24
737 l.sw PT_GPR26(r1),r26
738 l.sw PT_GPR28(r1),r28
739
740 /* _work_pending needs to be called with interrupts disabled */
741 l.j _work_pending
742 l.nop
743
744_syscall_resume_userspace:
745// ENABLE_INTERRUPTS(r29)
746
747
748/* This is the hot path for returning to userspace from a syscall. If there's
749 * work to be done and the branch to _work_pending was taken above, then the
750 * return to userspace will be done via the normal exception return path...
751 * that path restores _all_ registers and will overwrite the "clobbered"
752 * registers with whatever garbage is in pt_regs -- that's OK because those
753 * registers are clobbered anyway and because the extra work is insignificant
754 * in the context of the extra work that _work_pending is doing.
755
756/* Once again, syscalls are special and only guarantee to preserve the
757 * same registers as a normal function call */
758
759/* The assumption here is that the registers r14-r28 (even) are untouched and
760 * don't need to be restored... be sure that that's really the case!
761 */
762
763/* This is still too much... we should only be restoring what we actually
764 * clobbered... we should even be using 'scratch' (odd) regs above so that
765 * we don't need to restore anything, hardly...
766 */
767
768 l.lwz r2,PT_GPR2(r1)
769
770 /* Restore args */
771 /* r3-r8 are technically clobbered, but syscall restart needs these
772 * to be restored...
773 */
774 l.lwz r3,PT_GPR3(r1)
775 l.lwz r4,PT_GPR4(r1)
776 l.lwz r5,PT_GPR5(r1)
777 l.lwz r6,PT_GPR6(r1)
778 l.lwz r7,PT_GPR7(r1)
779 l.lwz r8,PT_GPR8(r1)
780
781 l.lwz r9,PT_GPR9(r1)
782 l.lwz r10,PT_GPR10(r1)
783 l.lwz r11,PT_GPR11(r1)
784
785 /* r30 is the only register we clobber in the fast path */
786 l.lwz r30,PT_GPR30(r1)
787
788 /* Here we use r13-r19 (odd) as scratch regs */
789 l.lwz r13,PT_PC(r1)
790 l.lwz r15,PT_SR(r1)
791 l.lwz r1,PT_SP(r1)
792 /* Interrupts need to be disabled for setting EPCR and ESR
793 * so that another interrupt doesn't come in here and clobber
794 * them before we can use them for our l.rfe */
795 DISABLE_INTERRUPTS(r17,r19)
796 l.mtspr r0,r13,SPR_EPCR_BASE
797 l.mtspr r0,r15,SPR_ESR_BASE
798 l.rfe
799
800/* End of hot path!
801 * Keep the below tracing and error handling out of the hot path...
802*/
803
804_syscall_trace_enter:
805 /* Here we pass pt_regs to do_syscall_trace_enter. Make sure
806 * that function is really getting all the info it needs as
807 * pt_regs isn't a complete set of userspace regs, just the
808 * ones relevant to the syscall...
809 *
810 * Note use of delay slot for setting argument.
811 */
812 l.jal do_syscall_trace_enter
813 l.addi r3,r1,0
814
815 /* Restore arguments (not preserved across do_syscall_trace_enter)
816 * so that we can do the syscall for real and return to the syscall
817 * hot path.
818 */
819 l.lwz r11,PT_GPR11(r1)
820 l.lwz r3,PT_GPR3(r1)
821 l.lwz r4,PT_GPR4(r1)
822 l.lwz r5,PT_GPR5(r1)
823 l.lwz r6,PT_GPR6(r1)
824 l.lwz r7,PT_GPR7(r1)
825
826 l.j _syscall_check
827 l.lwz r8,PT_GPR8(r1)
828
829_syscall_trace_leave:
830 l.jal do_syscall_trace_leave
831 l.addi r3,r1,0
832
833 l.j _syscall_check_work
834 l.nop
835
836_syscall_badsys:
837 /* Here we effectively pretend to have executed an imaginary
838 * syscall that returns -ENOSYS and then return to the regular
839 * syscall hot path.
840 * Note that "return value" is set in the delay slot...
841 */
842 l.j _syscall_return
843 l.addi r11,r0,-ENOSYS
844
845/******* END SYSCALL HANDLING *******/
846
847/* ---[ 0xd00: Trap exception ]------------------------------------------ */
848
849UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
850
851/* ---[ 0xe00: Trap exception ]------------------------------------------ */
852
853EXCEPTION_ENTRY(_trap_handler)
854 CLEAR_LWA_FLAG(r3)
855 /* r4: EA of fault (set by EXCEPTION_HANDLE) */
856 l.jal do_trap
857 l.addi r3,r1,0 /* pt_regs */
858
859 l.j _ret_from_exception
860 l.nop
861
862/* ---[ 0xf00: Reserved exception ]-------------------------------------- */
863
864UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
865
866/* ---[ 0x1000: Reserved exception ]------------------------------------- */
867
868UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
869
870/* ---[ 0x1100: Reserved exception ]------------------------------------- */
871
872UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
873
874/* ---[ 0x1200: Reserved exception ]------------------------------------- */
875
876UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
877
878/* ---[ 0x1300: Reserved exception ]------------------------------------- */
879
880UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
881
882/* ---[ 0x1400: Reserved exception ]------------------------------------- */
883
884UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
885
886/* ---[ 0x1500: Reserved exception ]------------------------------------- */
887
888UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
889
890/* ---[ 0x1600: Reserved exception ]------------------------------------- */
891
892UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
893
894/* ---[ 0x1700: Reserved exception ]------------------------------------- */
895
896UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
897
898/* ---[ 0x1800: Reserved exception ]------------------------------------- */
899
900UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
901
902/* ---[ 0x1900: Reserved exception ]------------------------------------- */
903
904UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
905
906/* ---[ 0x1a00: Reserved exception ]------------------------------------- */
907
908UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
909
910/* ---[ 0x1b00: Reserved exception ]------------------------------------- */
911
912UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
913
914/* ---[ 0x1c00: Reserved exception ]------------------------------------- */
915
916UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
917
918/* ---[ 0x1d00: Reserved exception ]------------------------------------- */
919
920UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
921
922/* ---[ 0x1e00: Reserved exception ]------------------------------------- */
923
924UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
925
926/* ---[ 0x1f00: Reserved exception ]------------------------------------- */
927
928UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
929
930/* ========================================================[ return ] === */
931
932_resume_userspace:
933 DISABLE_INTERRUPTS(r3,r4)
934 TRACE_IRQS_OFF
935 l.lwz r4,TI_FLAGS(r10)
936 l.andi r13,r4,_TIF_WORK_MASK
937 l.sfeqi r13,0
938 l.bf _restore_all
939 l.nop
940
941_work_pending:
942 l.lwz r5,PT_ORIG_GPR11(r1)
943 l.sfltsi r5,0
944 l.bnf 1f
945 l.nop
946 l.andi r5,r5,0
9471:
948 l.jal do_work_pending
949 l.ori r3,r1,0 /* pt_regs */
950
951 l.sfeqi r11,0
952 l.bf _restore_all
953 l.nop
954 l.sfltsi r11,0
955 l.bnf 1f
956 l.nop
957 l.and r11,r11,r0
958 l.ori r11,r11,__NR_restart_syscall
959 l.j _syscall_check_trace_enter
960 l.nop
9611:
962 l.lwz r11,PT_ORIG_GPR11(r1)
963 /* Restore arg registers */
964 l.lwz r3,PT_GPR3(r1)
965 l.lwz r4,PT_GPR4(r1)
966 l.lwz r5,PT_GPR5(r1)
967 l.lwz r6,PT_GPR6(r1)
968 l.lwz r7,PT_GPR7(r1)
969 l.j _syscall_check_trace_enter
970 l.lwz r8,PT_GPR8(r1)
971
972_restore_all:
973#ifdef CONFIG_TRACE_IRQFLAGS
974 l.lwz r4,PT_SR(r1)
975 l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
976 l.sfeq r3,r0 /* skip trace if irqs were off */
977 l.bf skip_hardirqs_on
978 l.nop
979 TRACE_IRQS_ON
980skip_hardirqs_on:
981#endif
982 RESTORE_ALL
983 /* This returns to userspace code */
984
985
986ENTRY(_ret_from_intr)
987ENTRY(_ret_from_exception)
988 l.lwz r4,PT_SR(r1)
989 l.andi r3,r4,SPR_SR_SM
990 l.sfeqi r3,0
991 l.bnf _restore_all
992 l.nop
993 l.j _resume_userspace
994 l.nop
995
996ENTRY(ret_from_fork)
997 l.jal schedule_tail
998 l.nop
999
1000 /* Check if we are a kernel thread */
1001 l.sfeqi r20,0
1002 l.bf 1f
1003 l.nop
1004
1005 /* ...we are a kernel thread so invoke the requested callback */
1006 l.jalr r20
1007 l.or r3,r22,r0
1008
10091:
1010 /* _syscall_returns expect r11 to contain return value */
1011 l.lwz r11,PT_GPR11(r1)
1012
1013 /* The syscall fast path return expects call-saved registers
1014 * r14-r28 to be untouched, so we restore them here as they
1015 * will have been effectively clobbered when arriving here
1016 * via the call to switch()
1017 */
1018 l.lwz r14,PT_GPR14(r1)
1019 l.lwz r16,PT_GPR16(r1)
1020 l.lwz r18,PT_GPR18(r1)
1021 l.lwz r20,PT_GPR20(r1)
1022 l.lwz r22,PT_GPR22(r1)
1023 l.lwz r24,PT_GPR24(r1)
1024 l.lwz r26,PT_GPR26(r1)
1025 l.lwz r28,PT_GPR28(r1)
1026
1027 l.j _syscall_return
1028 l.nop
1029
1030/* ========================================================[ switch ] === */
1031
1032/*
1033 * This routine switches between two different tasks. The process
1034 * state of one is saved on its kernel stack. Then the state
1035 * of the other is restored from its kernel stack. The memory
1036 * management hardware is updated to the second process's state.
1037 * Finally, we can return to the second process, via the 'return'.
1038 *
1039 * Note: there are two ways to get to the "going out" portion
1040 * of this code; either by coming in via the entry (_switch)
1041 * or via "fork" which must set up an environment equivalent
1042 * to the "_switch" path. If you change this (or in particular, the
1043 * SAVE_REGS macro), you'll have to change the fork code also.
1044 */
1045
1046
1047/* _switch MUST never lay on page boundry, cause it runs from
1048 * effective addresses and beeing interrupted by iTLB miss would kill it.
1049 * dTLB miss seems to never accour in the bad place since data accesses
1050 * are from task structures which are always page aligned.
1051 *
1052 * The problem happens in RESTORE_ALL where we first set the EPCR
1053 * register, then load the previous register values and only at the end call
1054 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
1055 * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
1056 * holds for ESR)
1057 *
1058 * To avoid this problems it is sufficient to align _switch to
1059 * some nice round number smaller than it's size...
1060 */
1061
1062/* ABI rules apply here... we either enter _switch via schedule() or via
1063 * an imaginary call to which we shall return at return_from_fork. Either
1064 * way, we are a function call and only need to preserve the callee-saved
1065 * registers when we return. As such, we don't need to save the registers
1066 * on the stack that we won't be returning as they were...
1067 */
1068
1069 .align 0x400
1070ENTRY(_switch)
1071 /* We don't store SR as _switch only gets called in a context where
1072 * the SR will be the same going in and coming out... */
1073
1074 /* Set up new pt_regs struct for saving task state */
1075 l.addi r1,r1,-(INT_FRAME_SIZE)
1076
1077 /* No need to store r1/PT_SP as it goes into KSP below */
1078 l.sw PT_GPR2(r1),r2
1079 l.sw PT_GPR9(r1),r9
1080
1081 /* Save callee-saved registers to the new pt_regs */
1082 l.sw PT_GPR14(r1),r14
1083 l.sw PT_GPR16(r1),r16
1084 l.sw PT_GPR18(r1),r18
1085 l.sw PT_GPR20(r1),r20
1086 l.sw PT_GPR22(r1),r22
1087 l.sw PT_GPR24(r1),r24
1088 l.sw PT_GPR26(r1),r26
1089 l.sw PT_GPR28(r1),r28
1090 l.sw PT_GPR30(r1),r30
1091
1092 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1093
1094 /* We use thread_info->ksp for storing the address of the above
1095 * structure so that we can get back to it later... we don't want
1096 * to lose the value of thread_info->ksp, though, so store it as
1097 * pt_regs->sp so that we can easily restore it when we are made
1098 * live again...
1099 */
1100
1101 /* Save the old value of thread_info->ksp as pt_regs->sp */
1102 l.lwz r29,TI_KSP(r10)
1103 l.sw PT_SP(r1),r29
1104
1105 /* Swap kernel stack pointers */
1106 l.sw TI_KSP(r10),r1 /* Save old stack pointer */
1107 l.or r10,r4,r0 /* Set up new current_thread_info */
1108 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
1109
1110 /* Restore the old value of thread_info->ksp */
1111 l.lwz r29,PT_SP(r1)
1112 l.sw TI_KSP(r10),r29
1113
1114 /* ...and restore the registers, except r11 because the return value
1115 * has already been set above.
1116 */
1117 l.lwz r2,PT_GPR2(r1)
1118 l.lwz r9,PT_GPR9(r1)
1119 /* No need to restore r10 */
1120 /* ...and do not restore r11 */
1121
1122 /* Restore callee-saved registers */
1123 l.lwz r14,PT_GPR14(r1)
1124 l.lwz r16,PT_GPR16(r1)
1125 l.lwz r18,PT_GPR18(r1)
1126 l.lwz r20,PT_GPR20(r1)
1127 l.lwz r22,PT_GPR22(r1)
1128 l.lwz r24,PT_GPR24(r1)
1129 l.lwz r26,PT_GPR26(r1)
1130 l.lwz r28,PT_GPR28(r1)
1131 l.lwz r30,PT_GPR30(r1)
1132
1133 /* Unwind stack to pre-switch state */
1134 l.addi r1,r1,(INT_FRAME_SIZE)
1135
1136 /* Return via the link-register back to where we 'came from', where
1137 * that may be either schedule(), ret_from_fork(), or
1138 * ret_from_kernel_thread(). If we are returning to a new thread,
1139 * we are expected to have set up the arg to schedule_tail already,
1140 * hence we do so here unconditionally:
1141 */
1142 l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
1143 l.jr r9
1144 l.nop
1145
1146/* ==================================================================== */
1147
1148/* These all use the delay slot for setting the argument register, so the
1149 * jump is always happening after the l.addi instruction.
1150 *
1151 * These are all just wrappers that don't touch the link-register r9, so the
1152 * return from the "real" syscall function will return back to the syscall
1153 * code that did the l.jal that brought us here.
1154 */
1155
1156/* fork requires that we save all the callee-saved registers because they
1157 * are all effectively clobbered by the call to _switch. Here we store
1158 * all the registers that aren't touched by the syscall fast path and thus
1159 * weren't saved there.
1160 */
1161
1162_fork_save_extra_regs_and_call:
1163 l.sw PT_GPR14(r1),r14
1164 l.sw PT_GPR16(r1),r16
1165 l.sw PT_GPR18(r1),r18
1166 l.sw PT_GPR20(r1),r20
1167 l.sw PT_GPR22(r1),r22
1168 l.sw PT_GPR24(r1),r24
1169 l.sw PT_GPR26(r1),r26
1170 l.jr r29
1171 l.sw PT_GPR28(r1),r28
1172
1173ENTRY(__sys_clone)
1174 l.movhi r29,hi(sys_clone)
1175 l.j _fork_save_extra_regs_and_call
1176 l.ori r29,r29,lo(sys_clone)
1177
1178ENTRY(__sys_clone3)
1179 l.movhi r29,hi(sys_clone3)
1180 l.j _fork_save_extra_regs_and_call
1181 l.ori r29,r29,lo(sys_clone3)
1182
1183ENTRY(__sys_fork)
1184 l.movhi r29,hi(sys_fork)
1185 l.j _fork_save_extra_regs_and_call
1186 l.ori r29,r29,lo(sys_fork)
1187
1188ENTRY(sys_rt_sigreturn)
1189 l.jal _sys_rt_sigreturn
1190 l.addi r3,r1,0
1191 l.sfne r30,r0
1192 l.bnf _no_syscall_trace
1193 l.nop
1194 l.jal do_syscall_trace_leave
1195 l.addi r3,r1,0
1196_no_syscall_trace:
1197 l.j _resume_userspace
1198 l.nop
1199
1200/* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1201 * The functions takes a variable number of parameters depending on which
1202 * particular flavour of atomic you want... parameter 1 is a flag identifying
1203 * the atomic in question. Currently, this function implements the
1204 * following variants:
1205 *
1206 * XCHG:
1207 * @flag: 1
1208 * @ptr1:
1209 * @ptr2:
1210 * Atomically exchange the values in pointers 1 and 2.
1211 *
1212 */
1213
1214ENTRY(sys_or1k_atomic)
1215 /* FIXME: This ignores r3 and always does an XCHG */
1216 DISABLE_INTERRUPTS(r17,r19)
1217 l.lwz r29,0(r4)
1218 l.lwz r27,0(r5)
1219 l.sw 0(r4),r27
1220 l.sw 0(r5),r29
1221 ENABLE_INTERRUPTS(r17)
1222 l.jr r9
1223 l.or r11,r0,r0
1224
1225/* ============================================================[ EOF ]=== */