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1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * UART Constants File: sb1250_uart.h
5 *
6 * This module contains constants and macros useful for
7 * manipulating the SB1250's UARTs
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 *********************************************************************
12 *
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 ********************************************************************* */
31
32
33#ifndef _SB1250_UART_H
34#define _SB1250_UART_H
35
36#include "sb1250_defs.h"
37
38/* **********************************************************************
39 * DUART Registers
40 ********************************************************************** */
41
42/*
43 * DUART Mode Register #1 (Table 10-3)
44 * Register: DUART_MODE_REG_1_A
45 * Register: DUART_MODE_REG_1_B
46 */
47
48#define S_DUART_BITS_PER_CHAR 0
49#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
50#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
51
52#define K_DUART_BITS_PER_CHAR_RSV0 0
53#define K_DUART_BITS_PER_CHAR_RSV1 1
54#define K_DUART_BITS_PER_CHAR_7 2
55#define K_DUART_BITS_PER_CHAR_8 3
56
57#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
58#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
59#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
60#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
61
62
63#define M_DUART_PARITY_TYPE_EVEN 0x00
64#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
65
66#define S_DUART_PARITY_MODE 3
67#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
68#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
69
70#define K_DUART_PARITY_MODE_ADD 0
71#define K_DUART_PARITY_MODE_ADD_FIXED 1
72#define K_DUART_PARITY_MODE_NONE 2
73
74#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
75#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
76#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
77
78#define M_DUART_TX_IRQ_SEL_TXRDY 0
79#define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5)
80
81#define M_DUART_RX_IRQ_SEL_RXRDY 0
82#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6)
83
84#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7)
85
86/*
87 * DUART Mode Register #2 (Table 10-4)
88 * Register: DUART_MODE_REG_2_A
89 * Register: DUART_MODE_REG_2_B
90 */
91
92#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */
93
94#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
95#define M_DUART_STOP_BIT_LEN_1 0
96
97#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4)
98
99
100#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
101
102#define S_DUART_CHAN_MODE 6
103#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
104#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
105
106#define K_DUART_CHAN_MODE_NORMAL 0
107#define K_DUART_CHAN_MODE_LCL_LOOP 2
108#define K_DUART_CHAN_MODE_REM_LOOP 3
109
110#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
111#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
112#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
113
114/*
115 * DUART Command Register (Table 10-5)
116 * Register: DUART_CMD_A
117 * Register: DUART_CMD_B
118 */
119
120#define M_DUART_RX_EN _SB_MAKEMASK1(0)
121#define M_DUART_RX_DIS _SB_MAKEMASK1(1)
122#define M_DUART_TX_EN _SB_MAKEMASK1(2)
123#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
124
125#define S_DUART_MISC_CMD 4
126#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD)
127#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
128
129#define K_DUART_MISC_CMD_NOACTION0 0
130#define K_DUART_MISC_CMD_NOACTION1 1
131#define K_DUART_MISC_CMD_RESET_RX 2
132#define K_DUART_MISC_CMD_RESET_TX 3
133#define K_DUART_MISC_CMD_NOACTION4 4
134#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
135#define K_DUART_MISC_CMD_START_BREAK 6
136#define K_DUART_MISC_CMD_STOP_BREAK 7
137
138#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
139#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
140#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
141#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
142#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
143#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
144#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
145#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
146
147#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
148
149/*
150 * DUART Status Register (Table 10-6)
151 * Register: DUART_STATUS_A
152 * Register: DUART_STATUS_B
153 * READ-ONLY
154 */
155
156#define M_DUART_RX_RDY _SB_MAKEMASK1(0)
157#define M_DUART_RX_FFUL _SB_MAKEMASK1(1)
158#define M_DUART_TX_RDY _SB_MAKEMASK1(2)
159#define M_DUART_TX_EMT _SB_MAKEMASK1(3)
160#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4)
161#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5)
162#define M_DUART_FRM_ERR _SB_MAKEMASK1(6)
163#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7)
164
165/*
166 * DUART Baud Rate Register (Table 10-7)
167 * Register: DUART_CLK_SEL_A
168 * Register: DUART_CLK_SEL_B
169 */
170
171#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0)
172#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
173
174/*
175 * DUART Data Registers (Table 10-8 and 10-9)
176 * Register: DUART_RX_HOLD_A
177 * Register: DUART_RX_HOLD_B
178 * Register: DUART_TX_HOLD_A
179 * Register: DUART_TX_HOLD_B
180 */
181
182#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0)
183#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0)
184
185/*
186 * DUART Input Port Register (Table 10-10)
187 * Register: DUART_IN_PORT
188 */
189
190#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0)
191#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1)
192#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2)
193#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3)
194#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4)
195#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5)
196#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6)
197#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7)
198
199/*
200 * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
201 * Register: DUART_INPORT_CHNG
202 */
203
204#define S_DUART_IN_PIN_VAL 0
205#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
206
207#define S_DUART_IN_PIN_CHNG 4
208#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
209
210
211/*
212 * DUART Output port control register (Table 10-14)
213 * Register: DUART_OPCR
214 */
215
216#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */
217#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
218#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
219#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
220#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */
221
222/*
223 * DUART Aux Control Register (Table 10-15)
224 * Register: DUART_AUX_CTRL
225 */
226
227#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0)
228#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
229#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
230#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
231#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4)
232
233#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
234#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
235
236/*
237 * DUART Interrupt Status Register (Table 10-16)
238 * Register: DUART_ISR
239 */
240
241#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
242
243#define S_DUART_ISR_RX_A 1
244#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
245#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
246#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
247
248#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
249#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
250#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0)
251
252#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
253#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
254#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
255#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
256#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4)
257
258/*
259 * DUART Channel A Interrupt Status Register (Table 10-17)
260 * DUART Channel B Interrupt Status Register (Table 10-18)
261 * Register: DUART_ISR_A
262 * Register: DUART_ISR_B
263 */
264
265#define M_DUART_ISR_TX _SB_MAKEMASK1(0)
266#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
267#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
268#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
269#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0)
270#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4)
271
272/*
273 * DUART Interrupt Mask Register (Table 10-19)
274 * Register: DUART_IMR
275 */
276
277#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0)
278#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
279#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
280#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
281#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0)
282
283#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
284#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
285#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
286#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
287#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4)
288
289/*
290 * DUART Channel A Interrupt Mask Register (Table 10-20)
291 * DUART Channel B Interrupt Mask Register (Table 10-21)
292 * Register: DUART_IMR_A
293 * Register: DUART_IMR_B
294 */
295
296#define M_DUART_IMR_TX _SB_MAKEMASK1(0)
297#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
298#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
299#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
300#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0)
301#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4)
302
303
304/*
305 * DUART Output Port Set Register (Table 10-22)
306 * Register: DUART_SET_OPR
307 */
308
309#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0)
310#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
311#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
312#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
313#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4)
314
315/*
316 * DUART Output Port Clear Register (Table 10-23)
317 * Register: DUART_CLEAR_OPR
318 */
319
320#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0)
321#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
322#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
323#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
324#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4)
325
326/*
327 * DUART Output Port RTS Register (Table 10-24)
328 * Register: DUART_OUT_PORT
329 */
330
331#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0)
332#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
333#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
334#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
335#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4)
336
337#define M_DUART_OUT_PIN_SET(chan) \
338 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
339#define M_DUART_OUT_PIN_CLR(chan) \
340 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
341
342#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
343/*
344 * Full Interrupt Control Register
345 */
346
347#define S_DUART_SIG_FULL _SB_MAKE64(0)
348#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL)
349#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
350#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
351
352#define S_DUART_INT_TIME _SB_MAKE64(4)
353#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME)
354#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME)
355#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
356#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
357
358
359/* ********************************************************************** */
360
361
362#endif
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* *********************************************************************
3 * SB1250 Board Support Package
4 *
5 * UART Constants File: sb1250_uart.h
6 *
7 * This module contains constants and macros useful for
8 * manipulating the SB1250's UARTs
9 *
10 * SB1250 specification level: User's manual 1/02/02
11 *
12 *********************************************************************
13 *
14 * Copyright 2000,2001,2002,2003
15 * Broadcom Corporation. All rights reserved.
16 *
17 ********************************************************************* */
18
19
20#ifndef _SB1250_UART_H
21#define _SB1250_UART_H
22
23#include <asm/sibyte/sb1250_defs.h>
24
25/* **********************************************************************
26 * DUART Registers
27 ********************************************************************** */
28
29/*
30 * DUART Mode Register #1 (Table 10-3)
31 * Register: DUART_MODE_REG_1_A
32 * Register: DUART_MODE_REG_1_B
33 */
34
35#define S_DUART_BITS_PER_CHAR 0
36#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
37#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
38
39#define K_DUART_BITS_PER_CHAR_RSV0 0
40#define K_DUART_BITS_PER_CHAR_RSV1 1
41#define K_DUART_BITS_PER_CHAR_7 2
42#define K_DUART_BITS_PER_CHAR_8 3
43
44#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
45#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
46#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
47#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
48
49
50#define M_DUART_PARITY_TYPE_EVEN 0x00
51#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
52
53#define S_DUART_PARITY_MODE 3
54#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
55#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
56
57#define K_DUART_PARITY_MODE_ADD 0
58#define K_DUART_PARITY_MODE_ADD_FIXED 1
59#define K_DUART_PARITY_MODE_NONE 2
60
61#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
62#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
63#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
64
65#define M_DUART_TX_IRQ_SEL_TXRDY 0
66#define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5)
67
68#define M_DUART_RX_IRQ_SEL_RXRDY 0
69#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6)
70
71#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7)
72
73/*
74 * DUART Mode Register #2 (Table 10-4)
75 * Register: DUART_MODE_REG_2_A
76 * Register: DUART_MODE_REG_2_B
77 */
78
79#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */
80
81#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
82#define M_DUART_STOP_BIT_LEN_1 0
83
84#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4)
85
86
87#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
88
89#define S_DUART_CHAN_MODE 6
90#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
91#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
92
93#define K_DUART_CHAN_MODE_NORMAL 0
94#define K_DUART_CHAN_MODE_LCL_LOOP 2
95#define K_DUART_CHAN_MODE_REM_LOOP 3
96
97#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
98#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
99#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
100
101/*
102 * DUART Command Register (Table 10-5)
103 * Register: DUART_CMD_A
104 * Register: DUART_CMD_B
105 */
106
107#define M_DUART_RX_EN _SB_MAKEMASK1(0)
108#define M_DUART_RX_DIS _SB_MAKEMASK1(1)
109#define M_DUART_TX_EN _SB_MAKEMASK1(2)
110#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
111
112#define S_DUART_MISC_CMD 4
113#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD)
114#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
115
116#define K_DUART_MISC_CMD_NOACTION0 0
117#define K_DUART_MISC_CMD_NOACTION1 1
118#define K_DUART_MISC_CMD_RESET_RX 2
119#define K_DUART_MISC_CMD_RESET_TX 3
120#define K_DUART_MISC_CMD_NOACTION4 4
121#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
122#define K_DUART_MISC_CMD_START_BREAK 6
123#define K_DUART_MISC_CMD_STOP_BREAK 7
124
125#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
126#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
127#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
128#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
129#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
130#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
131#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
132#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
133
134#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
135
136/*
137 * DUART Status Register (Table 10-6)
138 * Register: DUART_STATUS_A
139 * Register: DUART_STATUS_B
140 * READ-ONLY
141 */
142
143#define M_DUART_RX_RDY _SB_MAKEMASK1(0)
144#define M_DUART_RX_FFUL _SB_MAKEMASK1(1)
145#define M_DUART_TX_RDY _SB_MAKEMASK1(2)
146#define M_DUART_TX_EMT _SB_MAKEMASK1(3)
147#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4)
148#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5)
149#define M_DUART_FRM_ERR _SB_MAKEMASK1(6)
150#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7)
151
152/*
153 * DUART Baud Rate Register (Table 10-7)
154 * Register: DUART_CLK_SEL_A
155 * Register: DUART_CLK_SEL_B
156 */
157
158#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0)
159#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
160
161/*
162 * DUART Data Registers (Table 10-8 and 10-9)
163 * Register: DUART_RX_HOLD_A
164 * Register: DUART_RX_HOLD_B
165 * Register: DUART_TX_HOLD_A
166 * Register: DUART_TX_HOLD_B
167 */
168
169#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0)
170#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0)
171
172/*
173 * DUART Input Port Register (Table 10-10)
174 * Register: DUART_IN_PORT
175 */
176
177#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0)
178#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1)
179#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2)
180#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3)
181#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4)
182#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5)
183#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6)
184#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7)
185
186/*
187 * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
188 * Register: DUART_INPORT_CHNG
189 */
190
191#define S_DUART_IN_PIN_VAL 0
192#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
193
194#define S_DUART_IN_PIN_CHNG 4
195#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
196
197
198/*
199 * DUART Output port control register (Table 10-14)
200 * Register: DUART_OPCR
201 */
202
203#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */
204#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
205#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
206#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
207#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */
208
209/*
210 * DUART Aux Control Register (Table 10-15)
211 * Register: DUART_AUX_CTRL
212 */
213
214#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0)
215#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
216#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
217#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
218#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4)
219
220#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
221#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
222
223/*
224 * DUART Interrupt Status Register (Table 10-16)
225 * Register: DUART_ISR
226 */
227
228#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
229
230#define S_DUART_ISR_RX_A 1
231#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
232#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
233#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
234
235#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
236#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
237#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0)
238
239#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
240#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
241#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
242#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
243#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4)
244
245/*
246 * DUART Channel A Interrupt Status Register (Table 10-17)
247 * DUART Channel B Interrupt Status Register (Table 10-18)
248 * Register: DUART_ISR_A
249 * Register: DUART_ISR_B
250 */
251
252#define M_DUART_ISR_TX _SB_MAKEMASK1(0)
253#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
254#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
255#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
256#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0)
257#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4)
258
259/*
260 * DUART Interrupt Mask Register (Table 10-19)
261 * Register: DUART_IMR
262 */
263
264#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0)
265#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
266#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
267#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
268#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0)
269
270#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
271#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
272#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
273#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
274#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4)
275
276/*
277 * DUART Channel A Interrupt Mask Register (Table 10-20)
278 * DUART Channel B Interrupt Mask Register (Table 10-21)
279 * Register: DUART_IMR_A
280 * Register: DUART_IMR_B
281 */
282
283#define M_DUART_IMR_TX _SB_MAKEMASK1(0)
284#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
285#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
286#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
287#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0)
288#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4)
289
290
291/*
292 * DUART Output Port Set Register (Table 10-22)
293 * Register: DUART_SET_OPR
294 */
295
296#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0)
297#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
298#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
299#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
300#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4)
301
302/*
303 * DUART Output Port Clear Register (Table 10-23)
304 * Register: DUART_CLEAR_OPR
305 */
306
307#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0)
308#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
309#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
310#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
311#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4)
312
313/*
314 * DUART Output Port RTS Register (Table 10-24)
315 * Register: DUART_OUT_PORT
316 */
317
318#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0)
319#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
320#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
321#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
322#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4)
323
324#define M_DUART_OUT_PIN_SET(chan) \
325 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
326#define M_DUART_OUT_PIN_CLR(chan) \
327 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
328
329#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
330/*
331 * Full Interrupt Control Register
332 */
333
334#define S_DUART_SIG_FULL _SB_MAKE64(0)
335#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL)
336#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
337#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
338
339#define S_DUART_INT_TIME _SB_MAKE64(4)
340#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME)
341#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME)
342#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
343#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
344
345
346/* ********************************************************************** */
347
348
349#endif