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1/*
2 * linux/arch/arm/mm/proc-sa1100.S
3 *
4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * MMU functions for SA110
12 *
13 * These are the low level assembler for performing cache and TLB
14 * functions on the StrongARM-1100 and StrongARM-1110.
15 *
16 * Note that SA1100 and SA1110 share everything but their name and CPU ID.
17 *
18 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
19 * Flush the read buffer at context switches
20 */
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <mach/hardware.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/pgtable.h>
29
30#include "proc-macros.S"
31
32/*
33 * the cache line size of the I and D cache
34 */
35#define DCACHELINESIZE 32
36
37 .section .text
38
39/*
40 * cpu_sa1100_proc_init()
41 */
42ENTRY(cpu_sa1100_proc_init)
43 mov r0, #0
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
46 mov pc, lr
47
48/*
49 * cpu_sa1100_proc_fin()
50 *
51 * Prepare the CPU for reset:
52 * - Disable interrupts
53 * - Clean and turn off caches.
54 */
55ENTRY(cpu_sa1100_proc_fin)
56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
57 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
58 bic r0, r0, #0x1000 @ ...i............
59 bic r0, r0, #0x000e @ ............wca.
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
61 mov pc, lr
62
63/*
64 * cpu_sa1100_reset(loc)
65 *
66 * Perform a soft reset of the system. Put the CPU into the
67 * same state as it would be if it had been reset, and branch
68 * to what would be the reset vector.
69 *
70 * loc: location to jump to for soft reset
71 */
72 .align 5
73ENTRY(cpu_sa1100_reset)
74 mov ip, #0
75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
76 mcr p15, 0, ip, c7, c10, 4 @ drain WB
77#ifdef CONFIG_MMU
78 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
79#endif
80 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
81 bic ip, ip, #0x000f @ ............wcam
82 bic ip, ip, #0x1100 @ ...i...s........
83 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
84 mov pc, r0
85
86/*
87 * cpu_sa1100_do_idle(type)
88 *
89 * Cause the processor to idle
90 *
91 * type: call type:
92 * 0 = slow idle
93 * 1 = fast idle
94 * 2 = switch to slow processor clock
95 * 3 = switch to fast processor clock
96 */
97 .align 5
98ENTRY(cpu_sa1100_do_idle)
99 mov r0, r0 @ 4 nop padding
100 mov r0, r0
101 mov r0, r0
102 mov r0, r0 @ 4 nop padding
103 mov r0, r0
104 mov r0, r0
105 mov r0, #0
106 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
107 @ --- aligned to a cache line
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
109 ldr r1, [r1, #0] @ force switch to MCLK
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
111 mov r0, r0 @ safety
112 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
113 mov pc, lr
114
115/* ================================= CACHE ================================ */
116
117/*
118 * cpu_sa1100_dcache_clean_area(addr,sz)
119 *
120 * Clean the specified entry of any caches such that the MMU
121 * translation fetches will obtain correct data.
122 *
123 * addr: cache-unaligned virtual address
124 */
125 .align 5
126ENTRY(cpu_sa1100_dcache_clean_area)
1271: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
128 add r0, r0, #DCACHELINESIZE
129 subs r1, r1, #DCACHELINESIZE
130 bhi 1b
131 mov pc, lr
132
133/* =============================== PageTable ============================== */
134
135/*
136 * cpu_sa1100_switch_mm(pgd)
137 *
138 * Set the translation base pointer to be as described by pgd.
139 *
140 * pgd: new page tables
141 */
142 .align 5
143ENTRY(cpu_sa1100_switch_mm)
144#ifdef CONFIG_MMU
145 str lr, [sp, #-4]!
146 bl v4wb_flush_kern_cache_all @ clears IP
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
150 ldr pc, [sp], #4
151#else
152 mov pc, lr
153#endif
154
155/*
156 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
157 *
158 * Set a PTE and flush it out
159 */
160 .align 5
161ENTRY(cpu_sa1100_set_pte_ext)
162#ifdef CONFIG_MMU
163 armv3_set_pte_ext wc_disable=0
164 mov r0, r0
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB
167#endif
168 mov pc, lr
169
170.globl cpu_sa1100_suspend_size
171.equ cpu_sa1100_suspend_size, 4*4
172#ifdef CONFIG_PM_SLEEP
173ENTRY(cpu_sa1100_do_suspend)
174 stmfd sp!, {r4 - r7, lr}
175 mrc p15, 0, r4, c3, c0, 0 @ domain ID
176 mrc p15, 0, r5, c2, c0, 0 @ translation table base addr
177 mrc p15, 0, r6, c13, c0, 0 @ PID
178 mrc p15, 0, r7, c1, c0, 0 @ control reg
179 stmia r0, {r4 - r7} @ store cp regs
180 ldmfd sp!, {r4 - r7, pc}
181ENDPROC(cpu_sa1100_do_suspend)
182
183ENTRY(cpu_sa1100_do_resume)
184 ldmia r0, {r4 - r7} @ load cp regs
185 mov ip, #0
186 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
187 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
188 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
189 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
190
191 mcr p15, 0, r4, c3, c0, 0 @ domain ID
192 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
193 mcr p15, 0, r6, c13, c0, 0 @ PID
194 mov r0, r7 @ control register
195 mov r2, r5, lsr #14 @ get TTB0 base
196 mov r2, r2, lsl #14
197 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
198 PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
199 b cpu_resume_mmu
200ENDPROC(cpu_sa1100_do_resume)
201#endif
202
203 __CPUINIT
204
205 .type __sa1100_setup, #function
206__sa1100_setup:
207 mov r0, #0
208 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
209 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
210#ifdef CONFIG_MMU
211 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
212#endif
213 adr r5, sa1100_crval
214 ldmia r5, {r5, r6}
215 mrc p15, 0, r0, c1, c0 @ get control register v4
216 bic r0, r0, r5
217 orr r0, r0, r6
218 mov pc, lr
219 .size __sa1100_setup, . - __sa1100_setup
220
221 /*
222 * R
223 * .RVI ZFRS BLDP WCAM
224 * ..11 0001 ..11 1101
225 *
226 */
227 .type sa1100_crval, #object
228sa1100_crval:
229 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
230
231 __INITDATA
232
233/*
234 * SA1100 and SA1110 share the same function calls
235 */
236
237 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
238 define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
239
240 .section ".rodata"
241
242 string cpu_arch_name, "armv4"
243 string cpu_elf_name, "v4"
244 string cpu_sa1100_name, "StrongARM-1100"
245 string cpu_sa1110_name, "StrongARM-1110"
246
247 .align
248
249 .section ".proc.info.init", #alloc, #execinstr
250
251.macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
252 .type __\name\()_proc_info,#object
253__\name\()_proc_info:
254 .long \cpu_val
255 .long \cpu_mask
256 .long PMD_TYPE_SECT | \
257 PMD_SECT_BUFFERABLE | \
258 PMD_SECT_CACHEABLE | \
259 PMD_SECT_AP_WRITE | \
260 PMD_SECT_AP_READ
261 .long PMD_TYPE_SECT | \
262 PMD_SECT_AP_WRITE | \
263 PMD_SECT_AP_READ
264 b __sa1100_setup
265 .long cpu_arch_name
266 .long cpu_elf_name
267 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
268 .long \cpu_name
269 .long sa1100_processor_functions
270 .long v4wb_tlb_fns
271 .long v4_mc_user_fns
272 .long v4wb_cache_fns
273 .size __\name\()_proc_info, . - __\name\()_proc_info
274.endm
275
276 sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
277 sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/proc-sa1100.S
4 *
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * MMU functions for SA110
9 *
10 * These are the low level assembler for performing cache and TLB
11 * functions on the StrongARM-1100 and StrongARM-1110.
12 *
13 * Note that SA1100 and SA1110 share everything but their name and CPU ID.
14 *
15 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
16 * Flush the read buffer at context switches
17 */
18#include <linux/linkage.h>
19#include <linux/init.h>
20#include <linux/pgtable.h>
21#include <asm/assembler.h>
22#include <asm/asm-offsets.h>
23#include <asm/hwcap.h>
24#include <mach/hardware.h>
25#include <asm/pgtable-hwdef.h>
26
27#include "proc-macros.S"
28
29/*
30 * the cache line size of the I and D cache
31 */
32#define DCACHELINESIZE 32
33
34 .section .text
35
36/*
37 * cpu_sa1100_proc_init()
38 */
39ENTRY(cpu_sa1100_proc_init)
40 mov r0, #0
41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
43 ret lr
44
45/*
46 * cpu_sa1100_proc_fin()
47 *
48 * Prepare the CPU for reset:
49 * - Disable interrupts
50 * - Clean and turn off caches.
51 */
52ENTRY(cpu_sa1100_proc_fin)
53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 bic r0, r0, #0x1000 @ ...i............
56 bic r0, r0, #0x000e @ ............wca.
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 ret lr
59
60/*
61 * cpu_sa1100_reset(loc)
62 *
63 * Perform a soft reset of the system. Put the CPU into the
64 * same state as it would be if it had been reset, and branch
65 * to what would be the reset vector.
66 *
67 * loc: location to jump to for soft reset
68 */
69 .align 5
70 .pushsection .idmap.text, "ax"
71ENTRY(cpu_sa1100_reset)
72 mov ip, #0
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
74 mcr p15, 0, ip, c7, c10, 4 @ drain WB
75#ifdef CONFIG_MMU
76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
77#endif
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
79 bic ip, ip, #0x000f @ ............wcam
80 bic ip, ip, #0x1100 @ ...i...s........
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
82 ret r0
83ENDPROC(cpu_sa1100_reset)
84 .popsection
85
86/*
87 * cpu_sa1100_do_idle(type)
88 *
89 * Cause the processor to idle
90 *
91 * type: call type:
92 * 0 = slow idle
93 * 1 = fast idle
94 * 2 = switch to slow processor clock
95 * 3 = switch to fast processor clock
96 */
97 .align 5
98ENTRY(cpu_sa1100_do_idle)
99 mov r0, r0 @ 4 nop padding
100 mov r0, r0
101 mov r0, r0
102 mov r0, r0 @ 4 nop padding
103 mov r0, r0
104 mov r0, r0
105 mov r0, #0
106 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
107 @ --- aligned to a cache line
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
109 ldr r1, [r1, #0] @ force switch to MCLK
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
111 mov r0, r0 @ safety
112 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
113 ret lr
114
115/* ================================= CACHE ================================ */
116
117/*
118 * cpu_sa1100_dcache_clean_area(addr,sz)
119 *
120 * Clean the specified entry of any caches such that the MMU
121 * translation fetches will obtain correct data.
122 *
123 * addr: cache-unaligned virtual address
124 */
125 .align 5
126ENTRY(cpu_sa1100_dcache_clean_area)
1271: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
128 add r0, r0, #DCACHELINESIZE
129 subs r1, r1, #DCACHELINESIZE
130 bhi 1b
131 ret lr
132
133/* =============================== PageTable ============================== */
134
135/*
136 * cpu_sa1100_switch_mm(pgd)
137 *
138 * Set the translation base pointer to be as described by pgd.
139 *
140 * pgd: new page tables
141 */
142 .align 5
143ENTRY(cpu_sa1100_switch_mm)
144#ifdef CONFIG_MMU
145 str lr, [sp, #-4]!
146 bl v4wb_flush_kern_cache_all @ clears IP
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
150 ldr pc, [sp], #4
151#else
152 ret lr
153#endif
154
155/*
156 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
157 *
158 * Set a PTE and flush it out
159 */
160 .align 5
161ENTRY(cpu_sa1100_set_pte_ext)
162#ifdef CONFIG_MMU
163 armv3_set_pte_ext wc_disable=0
164 mov r0, r0
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB
167#endif
168 ret lr
169
170.globl cpu_sa1100_suspend_size
171.equ cpu_sa1100_suspend_size, 4 * 3
172#ifdef CONFIG_ARM_CPU_SUSPEND
173ENTRY(cpu_sa1100_do_suspend)
174 stmfd sp!, {r4 - r6, lr}
175 mrc p15, 0, r4, c3, c0, 0 @ domain ID
176 mrc p15, 0, r5, c13, c0, 0 @ PID
177 mrc p15, 0, r6, c1, c0, 0 @ control reg
178 stmia r0, {r4 - r6} @ store cp regs
179 ldmfd sp!, {r4 - r6, pc}
180ENDPROC(cpu_sa1100_do_suspend)
181
182ENTRY(cpu_sa1100_do_resume)
183 ldmia r0, {r4 - r6} @ load cp regs
184 mov ip, #0
185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
186 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
187 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
188 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
189
190 mcr p15, 0, r4, c3, c0, 0 @ domain ID
191 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
192 mcr p15, 0, r5, c13, c0, 0 @ PID
193 mov r0, r6 @ control register
194 b cpu_resume_mmu
195ENDPROC(cpu_sa1100_do_resume)
196#endif
197
198 .type __sa1100_setup, #function
199__sa1100_setup:
200 mov r0, #0
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
202 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
203#ifdef CONFIG_MMU
204 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
205#endif
206 adr r5, sa1100_crval
207 ldmia r5, {r5, r6}
208 mrc p15, 0, r0, c1, c0 @ get control register v4
209 bic r0, r0, r5
210 orr r0, r0, r6
211 ret lr
212 .size __sa1100_setup, . - __sa1100_setup
213
214 /*
215 * R
216 * .RVI ZFRS BLDP WCAM
217 * ..11 0001 ..11 1101
218 *
219 */
220 .type sa1100_crval, #object
221sa1100_crval:
222 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
223
224 __INITDATA
225
226/*
227 * SA1100 and SA1110 share the same function calls
228 */
229
230 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
231 define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
232
233 .section ".rodata"
234
235 string cpu_arch_name, "armv4"
236 string cpu_elf_name, "v4"
237 string cpu_sa1100_name, "StrongARM-1100"
238 string cpu_sa1110_name, "StrongARM-1110"
239
240 .align
241
242 .section ".proc.info.init", "a"
243
244.macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
245 .type __\name\()_proc_info,#object
246__\name\()_proc_info:
247 .long \cpu_val
248 .long \cpu_mask
249 .long PMD_TYPE_SECT | \
250 PMD_SECT_BUFFERABLE | \
251 PMD_SECT_CACHEABLE | \
252 PMD_SECT_AP_WRITE | \
253 PMD_SECT_AP_READ
254 .long PMD_TYPE_SECT | \
255 PMD_SECT_AP_WRITE | \
256 PMD_SECT_AP_READ
257 initfn __sa1100_setup, __\name\()_proc_info
258 .long cpu_arch_name
259 .long cpu_elf_name
260 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
261 .long \cpu_name
262 .long sa1100_processor_functions
263 .long v4wb_tlb_fns
264 .long v4_mc_user_fns
265 .long v4wb_cache_fns
266 .size __\name\()_proc_info, . - __\name\()_proc_info
267.endm
268
269 sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
270 sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name