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1/*
2 * linux/arch/arm/mm/nommu.c
3 *
4 * ARM uCLinux supporting functions.
5 */
6#include <linux/module.h>
7#include <linux/mm.h>
8#include <linux/pagemap.h>
9#include <linux/io.h>
10#include <linux/memblock.h>
11
12#include <asm/cacheflush.h>
13#include <asm/sections.h>
14#include <asm/page.h>
15#include <asm/setup.h>
16#include <asm/mach/arch.h>
17
18#include "mm.h"
19
20void __init arm_mm_memblock_reserve(void)
21{
22 /*
23 * Register the exception vector page.
24 * some architectures which the DRAM is the exception vector to trap,
25 * alloc_page breaks with error, although it is not NULL, but "0."
26 */
27 memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
28}
29
30void __init sanity_check_meminfo(void)
31{
32}
33
34/*
35 * paging_init() sets up the page tables, initialises the zone memory
36 * maps, and sets up the zero page, bad page and bad page tables.
37 */
38void __init paging_init(struct machine_desc *mdesc)
39{
40 bootmem_init();
41}
42
43/*
44 * We don't need to do anything here for nommu machines.
45 */
46void setup_mm_for_reboot(char mode)
47{
48}
49
50void flush_dcache_page(struct page *page)
51{
52 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
53}
54EXPORT_SYMBOL(flush_dcache_page);
55
56void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
57 unsigned long uaddr, void *dst, const void *src,
58 unsigned long len)
59{
60 memcpy(dst, src, len);
61 if (vma->vm_flags & VM_EXEC)
62 __cpuc_coherent_user_range(uaddr, uaddr + len);
63}
64
65void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
66 size_t size, unsigned int mtype)
67{
68 if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
69 return NULL;
70 return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
71}
72EXPORT_SYMBOL(__arm_ioremap_pfn);
73
74void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
75 size_t size, unsigned int mtype, void *caller)
76{
77 return __arm_ioremap_pfn(pfn, offset, size, mtype);
78}
79
80void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
81 unsigned int mtype)
82{
83 return (void __iomem *)phys_addr;
84}
85EXPORT_SYMBOL(__arm_ioremap);
86
87void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
88 unsigned int mtype, void *caller)
89{
90 return __arm_ioremap(phys_addr, size, mtype);
91}
92
93void __iounmap(volatile void __iomem *addr)
94{
95}
96EXPORT_SYMBOL(__iounmap);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mm/nommu.c
4 *
5 * ARM uCLinux supporting functions.
6 */
7#include <linux/module.h>
8#include <linux/mm.h>
9#include <linux/pagemap.h>
10#include <linux/io.h>
11#include <linux/memblock.h>
12#include <linux/kernel.h>
13
14#include <asm/cacheflush.h>
15#include <asm/cp15.h>
16#include <asm/sections.h>
17#include <asm/page.h>
18#include <asm/setup.h>
19#include <asm/traps.h>
20#include <asm/mach/arch.h>
21#include <asm/cputype.h>
22#include <asm/mpu.h>
23#include <asm/procinfo.h>
24
25#include "mm.h"
26
27unsigned long vectors_base;
28
29/*
30 * empty_zero_page is a special page that is used for
31 * zero-initialized data and COW.
32 */
33struct page *empty_zero_page;
34EXPORT_SYMBOL(empty_zero_page);
35
36#ifdef CONFIG_ARM_MPU
37struct mpu_rgn_info mpu_rgn_info;
38#endif
39
40#ifdef CONFIG_CPU_CP15
41#ifdef CONFIG_CPU_HIGH_VECTOR
42unsigned long setup_vectors_base(void)
43{
44 unsigned long reg = get_cr();
45
46 set_cr(reg | CR_V);
47 return 0xffff0000;
48}
49#else /* CONFIG_CPU_HIGH_VECTOR */
50/* Write exception base address to VBAR */
51static inline void set_vbar(unsigned long val)
52{
53 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc");
54}
55
56/*
57 * Security extensions, bits[7:4], permitted values,
58 * 0b0000 - not implemented, 0b0001/0b0010 - implemented
59 */
60static inline bool security_extensions_enabled(void)
61{
62 /* Check CPUID Identification Scheme before ID_PFR1 read */
63 if ((read_cpuid_id() & 0x000f0000) == 0x000f0000)
64 return cpuid_feature_extract(CPUID_EXT_PFR1, 4) ||
65 cpuid_feature_extract(CPUID_EXT_PFR1, 20);
66 return 0;
67}
68
69unsigned long setup_vectors_base(void)
70{
71 unsigned long base = 0, reg = get_cr();
72
73 set_cr(reg & ~CR_V);
74 if (security_extensions_enabled()) {
75 if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM))
76 base = CONFIG_DRAM_BASE;
77 set_vbar(base);
78 } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) {
79 if (CONFIG_DRAM_BASE != 0)
80 pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n");
81 }
82
83 return base;
84}
85#endif /* CONFIG_CPU_HIGH_VECTOR */
86#endif /* CONFIG_CPU_CP15 */
87
88void __init arm_mm_memblock_reserve(void)
89{
90#ifndef CONFIG_CPU_V7M
91 vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0;
92 /*
93 * Register the exception vector page.
94 * some architectures which the DRAM is the exception vector to trap,
95 * alloc_page breaks with error, although it is not NULL, but "0."
96 */
97 memblock_reserve(vectors_base, 2 * PAGE_SIZE);
98#else /* ifndef CONFIG_CPU_V7M */
99 /*
100 * There is no dedicated vector page on V7-M. So nothing needs to be
101 * reserved here.
102 */
103#endif
104 /*
105 * In any case, always ensure address 0 is never used as many things
106 * get very confused if 0 is returned as a legitimate address.
107 */
108 memblock_reserve(0, 1);
109}
110
111static void __init adjust_lowmem_bounds_mpu(void)
112{
113 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
114
115 switch (pmsa) {
116 case MMFR0_PMSAv7:
117 pmsav7_adjust_lowmem_bounds();
118 break;
119 case MMFR0_PMSAv8:
120 pmsav8_adjust_lowmem_bounds();
121 break;
122 default:
123 break;
124 }
125}
126
127static void __init mpu_setup(void)
128{
129 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
130
131 switch (pmsa) {
132 case MMFR0_PMSAv7:
133 pmsav7_setup();
134 break;
135 case MMFR0_PMSAv8:
136 pmsav8_setup();
137 break;
138 default:
139 break;
140 }
141}
142
143void __init adjust_lowmem_bounds(void)
144{
145 phys_addr_t end;
146 adjust_lowmem_bounds_mpu();
147 end = memblock_end_of_DRAM();
148 high_memory = __va(end - 1) + 1;
149 memblock_set_current_limit(end);
150}
151
152/*
153 * paging_init() sets up the page tables, initialises the zone memory
154 * maps, and sets up the zero page, bad page and bad page tables.
155 */
156void __init paging_init(const struct machine_desc *mdesc)
157{
158 void *zero_page;
159
160 early_trap_init((void *)vectors_base);
161 mpu_setup();
162
163 /* allocate the zero page. */
164 zero_page = (void *)memblock_alloc(PAGE_SIZE, PAGE_SIZE);
165 if (!zero_page)
166 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
167 __func__, PAGE_SIZE, PAGE_SIZE);
168
169 bootmem_init();
170
171 empty_zero_page = virt_to_page(zero_page);
172 flush_dcache_page(empty_zero_page);
173}
174
175/*
176 * We don't need to do anything here for nommu machines.
177 */
178void setup_mm_for_reboot(void)
179{
180}
181
182void flush_dcache_page(struct page *page)
183{
184 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
185}
186EXPORT_SYMBOL(flush_dcache_page);
187
188void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
189 unsigned long uaddr, void *dst, const void *src,
190 unsigned long len)
191{
192 memcpy(dst, src, len);
193 if (vma->vm_flags & VM_EXEC)
194 __cpuc_coherent_user_range(uaddr, uaddr + len);
195}
196
197void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
198 size_t size, unsigned int mtype)
199{
200 if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
201 return NULL;
202 return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
203}
204EXPORT_SYMBOL(__arm_ioremap_pfn);
205
206void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
207 unsigned int mtype, void *caller)
208{
209 return (void __iomem *)phys_addr;
210}
211
212void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
213
214void __iomem *ioremap(resource_size_t res_cookie, size_t size)
215{
216 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
217 __builtin_return_address(0));
218}
219EXPORT_SYMBOL(ioremap);
220
221void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
222{
223 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
224 __builtin_return_address(0));
225}
226EXPORT_SYMBOL(ioremap_cache);
227
228void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
229{
230 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
231 __builtin_return_address(0));
232}
233EXPORT_SYMBOL(ioremap_wc);
234
235#ifdef CONFIG_PCI
236
237#include <asm/mach/map.h>
238
239void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)
240{
241 return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,
242 __builtin_return_address(0));
243}
244EXPORT_SYMBOL_GPL(pci_remap_cfgspace);
245#endif
246
247void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)
248{
249 return (void *)phys_addr;
250}
251
252void iounmap(volatile void __iomem *io_addr)
253{
254}
255EXPORT_SYMBOL(iounmap);