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1/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18
19#include <asm/cputype.h>
20#include <asm/sections.h>
21#include <asm/cachetype.h>
22#include <asm/setup.h>
23#include <asm/sizes.h>
24#include <asm/smp_plat.h>
25#include <asm/tlb.h>
26#include <asm/highmem.h>
27#include <asm/traps.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31
32#include "mm.h"
33
34/*
35 * empty_zero_page is a special page that is used for
36 * zero-initialized data and COW.
37 */
38struct page *empty_zero_page;
39EXPORT_SYMBOL(empty_zero_page);
40
41/*
42 * The pmd table for the upper-most set of pages.
43 */
44pmd_t *top_pmd;
45
46#define CPOLICY_UNCACHED 0
47#define CPOLICY_BUFFERED 1
48#define CPOLICY_WRITETHROUGH 2
49#define CPOLICY_WRITEBACK 3
50#define CPOLICY_WRITEALLOC 4
51
52static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
53static unsigned int ecc_mask __initdata = 0;
54pgprot_t pgprot_user;
55pgprot_t pgprot_kernel;
56
57EXPORT_SYMBOL(pgprot_user);
58EXPORT_SYMBOL(pgprot_kernel);
59
60struct cachepolicy {
61 const char policy[16];
62 unsigned int cr_mask;
63 unsigned int pmd;
64 pteval_t pte;
65};
66
67static struct cachepolicy cache_policies[] __initdata = {
68 {
69 .policy = "uncached",
70 .cr_mask = CR_W|CR_C,
71 .pmd = PMD_SECT_UNCACHED,
72 .pte = L_PTE_MT_UNCACHED,
73 }, {
74 .policy = "buffered",
75 .cr_mask = CR_C,
76 .pmd = PMD_SECT_BUFFERED,
77 .pte = L_PTE_MT_BUFFERABLE,
78 }, {
79 .policy = "writethrough",
80 .cr_mask = 0,
81 .pmd = PMD_SECT_WT,
82 .pte = L_PTE_MT_WRITETHROUGH,
83 }, {
84 .policy = "writeback",
85 .cr_mask = 0,
86 .pmd = PMD_SECT_WB,
87 .pte = L_PTE_MT_WRITEBACK,
88 }, {
89 .policy = "writealloc",
90 .cr_mask = 0,
91 .pmd = PMD_SECT_WBWA,
92 .pte = L_PTE_MT_WRITEALLOC,
93 }
94};
95
96/*
97 * These are useful for identifying cache coherency
98 * problems by allowing the cache or the cache and
99 * writebuffer to be turned off. (Note: the write
100 * buffer should not be on and the cache off).
101 */
102static int __init early_cachepolicy(char *p)
103{
104 int i;
105
106 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
107 int len = strlen(cache_policies[i].policy);
108
109 if (memcmp(p, cache_policies[i].policy, len) == 0) {
110 cachepolicy = i;
111 cr_alignment &= ~cache_policies[i].cr_mask;
112 cr_no_alignment &= ~cache_policies[i].cr_mask;
113 break;
114 }
115 }
116 if (i == ARRAY_SIZE(cache_policies))
117 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
118 /*
119 * This restriction is partly to do with the way we boot; it is
120 * unpredictable to have memory mapped using two different sets of
121 * memory attributes (shared, type, and cache attribs). We can not
122 * change these attributes once the initial assembly has setup the
123 * page tables.
124 */
125 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
126 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
127 cachepolicy = CPOLICY_WRITEBACK;
128 }
129 flush_cache_all();
130 set_cr(cr_alignment);
131 return 0;
132}
133early_param("cachepolicy", early_cachepolicy);
134
135static int __init early_nocache(char *__unused)
136{
137 char *p = "buffered";
138 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
139 early_cachepolicy(p);
140 return 0;
141}
142early_param("nocache", early_nocache);
143
144static int __init early_nowrite(char *__unused)
145{
146 char *p = "uncached";
147 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
148 early_cachepolicy(p);
149 return 0;
150}
151early_param("nowb", early_nowrite);
152
153static int __init early_ecc(char *p)
154{
155 if (memcmp(p, "on", 2) == 0)
156 ecc_mask = PMD_PROTECTION;
157 else if (memcmp(p, "off", 3) == 0)
158 ecc_mask = 0;
159 return 0;
160}
161early_param("ecc", early_ecc);
162
163static int __init noalign_setup(char *__unused)
164{
165 cr_alignment &= ~CR_A;
166 cr_no_alignment &= ~CR_A;
167 set_cr(cr_alignment);
168 return 1;
169}
170__setup("noalign", noalign_setup);
171
172#ifndef CONFIG_SMP
173void adjust_cr(unsigned long mask, unsigned long set)
174{
175 unsigned long flags;
176
177 mask &= ~CR_A;
178
179 set &= mask;
180
181 local_irq_save(flags);
182
183 cr_no_alignment = (cr_no_alignment & ~mask) | set;
184 cr_alignment = (cr_alignment & ~mask) | set;
185
186 set_cr((get_cr() & ~mask) | set);
187
188 local_irq_restore(flags);
189}
190#endif
191
192#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
193#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
194
195static struct mem_type mem_types[] = {
196 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
197 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
198 L_PTE_SHARED,
199 .prot_l1 = PMD_TYPE_TABLE,
200 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
201 .domain = DOMAIN_IO,
202 },
203 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
204 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
205 .prot_l1 = PMD_TYPE_TABLE,
206 .prot_sect = PROT_SECT_DEVICE,
207 .domain = DOMAIN_IO,
208 },
209 [MT_DEVICE_CACHED] = { /* ioremap_cached */
210 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
211 .prot_l1 = PMD_TYPE_TABLE,
212 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
213 .domain = DOMAIN_IO,
214 },
215 [MT_DEVICE_WC] = { /* ioremap_wc */
216 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
217 .prot_l1 = PMD_TYPE_TABLE,
218 .prot_sect = PROT_SECT_DEVICE,
219 .domain = DOMAIN_IO,
220 },
221 [MT_UNCACHED] = {
222 .prot_pte = PROT_PTE_DEVICE,
223 .prot_l1 = PMD_TYPE_TABLE,
224 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
225 .domain = DOMAIN_IO,
226 },
227 [MT_CACHECLEAN] = {
228 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
229 .domain = DOMAIN_KERNEL,
230 },
231 [MT_MINICLEAN] = {
232 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
233 .domain = DOMAIN_KERNEL,
234 },
235 [MT_LOW_VECTORS] = {
236 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
237 L_PTE_RDONLY,
238 .prot_l1 = PMD_TYPE_TABLE,
239 .domain = DOMAIN_USER,
240 },
241 [MT_HIGH_VECTORS] = {
242 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
243 L_PTE_USER | L_PTE_RDONLY,
244 .prot_l1 = PMD_TYPE_TABLE,
245 .domain = DOMAIN_USER,
246 },
247 [MT_MEMORY] = {
248 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
249 .prot_l1 = PMD_TYPE_TABLE,
250 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
251 .domain = DOMAIN_KERNEL,
252 },
253 [MT_ROM] = {
254 .prot_sect = PMD_TYPE_SECT,
255 .domain = DOMAIN_KERNEL,
256 },
257 [MT_MEMORY_NONCACHED] = {
258 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
259 L_PTE_MT_BUFFERABLE,
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
262 .domain = DOMAIN_KERNEL,
263 },
264 [MT_MEMORY_DTCM] = {
265 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
266 L_PTE_XN,
267 .prot_l1 = PMD_TYPE_TABLE,
268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
269 .domain = DOMAIN_KERNEL,
270 },
271 [MT_MEMORY_ITCM] = {
272 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
273 .prot_l1 = PMD_TYPE_TABLE,
274 .domain = DOMAIN_KERNEL,
275 },
276};
277
278const struct mem_type *get_mem_type(unsigned int type)
279{
280 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
281}
282EXPORT_SYMBOL(get_mem_type);
283
284/*
285 * Adjust the PMD section entries according to the CPU in use.
286 */
287static void __init build_mem_type_table(void)
288{
289 struct cachepolicy *cp;
290 unsigned int cr = get_cr();
291 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
292 int cpu_arch = cpu_architecture();
293 int i;
294
295 if (cpu_arch < CPU_ARCH_ARMv6) {
296#if defined(CONFIG_CPU_DCACHE_DISABLE)
297 if (cachepolicy > CPOLICY_BUFFERED)
298 cachepolicy = CPOLICY_BUFFERED;
299#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
300 if (cachepolicy > CPOLICY_WRITETHROUGH)
301 cachepolicy = CPOLICY_WRITETHROUGH;
302#endif
303 }
304 if (cpu_arch < CPU_ARCH_ARMv5) {
305 if (cachepolicy >= CPOLICY_WRITEALLOC)
306 cachepolicy = CPOLICY_WRITEBACK;
307 ecc_mask = 0;
308 }
309 if (is_smp())
310 cachepolicy = CPOLICY_WRITEALLOC;
311
312 /*
313 * Strip out features not present on earlier architectures.
314 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
315 * without extended page tables don't have the 'Shared' bit.
316 */
317 if (cpu_arch < CPU_ARCH_ARMv5)
318 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
319 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
320 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
321 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
322 mem_types[i].prot_sect &= ~PMD_SECT_S;
323
324 /*
325 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
326 * "update-able on write" bit on ARM610). However, Xscale and
327 * Xscale3 require this bit to be cleared.
328 */
329 if (cpu_is_xscale() || cpu_is_xsc3()) {
330 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
331 mem_types[i].prot_sect &= ~PMD_BIT4;
332 mem_types[i].prot_l1 &= ~PMD_BIT4;
333 }
334 } else if (cpu_arch < CPU_ARCH_ARMv6) {
335 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
336 if (mem_types[i].prot_l1)
337 mem_types[i].prot_l1 |= PMD_BIT4;
338 if (mem_types[i].prot_sect)
339 mem_types[i].prot_sect |= PMD_BIT4;
340 }
341 }
342
343 /*
344 * Mark the device areas according to the CPU/architecture.
345 */
346 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
347 if (!cpu_is_xsc3()) {
348 /*
349 * Mark device regions on ARMv6+ as execute-never
350 * to prevent speculative instruction fetches.
351 */
352 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
353 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
354 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
355 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
356 }
357 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
358 /*
359 * For ARMv7 with TEX remapping,
360 * - shared device is SXCB=1100
361 * - nonshared device is SXCB=0100
362 * - write combine device mem is SXCB=0001
363 * (Uncached Normal memory)
364 */
365 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
366 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
367 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
368 } else if (cpu_is_xsc3()) {
369 /*
370 * For Xscale3,
371 * - shared device is TEXCB=00101
372 * - nonshared device is TEXCB=01000
373 * - write combine device mem is TEXCB=00100
374 * (Inner/Outer Uncacheable in xsc3 parlance)
375 */
376 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
377 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
378 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
379 } else {
380 /*
381 * For ARMv6 and ARMv7 without TEX remapping,
382 * - shared device is TEXCB=00001
383 * - nonshared device is TEXCB=01000
384 * - write combine device mem is TEXCB=00100
385 * (Uncached Normal in ARMv6 parlance).
386 */
387 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
388 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
389 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
390 }
391 } else {
392 /*
393 * On others, write combining is "Uncached/Buffered"
394 */
395 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
396 }
397
398 /*
399 * Now deal with the memory-type mappings
400 */
401 cp = &cache_policies[cachepolicy];
402 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
403
404 /*
405 * Only use write-through for non-SMP systems
406 */
407 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
408 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
409
410 /*
411 * Enable CPU-specific coherency if supported.
412 * (Only available on XSC3 at the moment.)
413 */
414 if (arch_is_coherent() && cpu_is_xsc3()) {
415 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
416 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
417 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
418 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
419 }
420 /*
421 * ARMv6 and above have extended page tables.
422 */
423 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
424 /*
425 * Mark cache clean areas and XIP ROM read only
426 * from SVC mode and no access from userspace.
427 */
428 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
429 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
430 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
431
432 if (is_smp()) {
433 /*
434 * Mark memory with the "shared" attribute
435 * for SMP systems
436 */
437 user_pgprot |= L_PTE_SHARED;
438 kern_pgprot |= L_PTE_SHARED;
439 vecs_pgprot |= L_PTE_SHARED;
440 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
441 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
442 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
443 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
444 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
445 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
446 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
447 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
448 }
449 }
450
451 /*
452 * Non-cacheable Normal - intended for memory areas that must
453 * not cause dirty cache line writebacks when used
454 */
455 if (cpu_arch >= CPU_ARCH_ARMv6) {
456 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
457 /* Non-cacheable Normal is XCB = 001 */
458 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
459 PMD_SECT_BUFFERED;
460 } else {
461 /* For both ARMv6 and non-TEX-remapping ARMv7 */
462 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
463 PMD_SECT_TEX(1);
464 }
465 } else {
466 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
467 }
468
469 for (i = 0; i < 16; i++) {
470 unsigned long v = pgprot_val(protection_map[i]);
471 protection_map[i] = __pgprot(v | user_pgprot);
472 }
473
474 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
475 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
476
477 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
478 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
479 L_PTE_DIRTY | kern_pgprot);
480
481 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
482 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
483 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
484 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
485 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
486 mem_types[MT_ROM].prot_sect |= cp->pmd;
487
488 switch (cp->pmd) {
489 case PMD_SECT_WT:
490 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
491 break;
492 case PMD_SECT_WB:
493 case PMD_SECT_WBWA:
494 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
495 break;
496 }
497 printk("Memory policy: ECC %sabled, Data cache %s\n",
498 ecc_mask ? "en" : "dis", cp->policy);
499
500 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
501 struct mem_type *t = &mem_types[i];
502 if (t->prot_l1)
503 t->prot_l1 |= PMD_DOMAIN(t->domain);
504 if (t->prot_sect)
505 t->prot_sect |= PMD_DOMAIN(t->domain);
506 }
507}
508
509#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
510pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
511 unsigned long size, pgprot_t vma_prot)
512{
513 if (!pfn_valid(pfn))
514 return pgprot_noncached(vma_prot);
515 else if (file->f_flags & O_SYNC)
516 return pgprot_writecombine(vma_prot);
517 return vma_prot;
518}
519EXPORT_SYMBOL(phys_mem_access_prot);
520#endif
521
522#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
523
524static void __init *early_alloc(unsigned long sz)
525{
526 void *ptr = __va(memblock_alloc(sz, sz));
527 memset(ptr, 0, sz);
528 return ptr;
529}
530
531static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
532{
533 if (pmd_none(*pmd)) {
534 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
535 __pmd_populate(pmd, __pa(pte), prot);
536 }
537 BUG_ON(pmd_bad(*pmd));
538 return pte_offset_kernel(pmd, addr);
539}
540
541static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
542 unsigned long end, unsigned long pfn,
543 const struct mem_type *type)
544{
545 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
546 do {
547 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
548 pfn++;
549 } while (pte++, addr += PAGE_SIZE, addr != end);
550}
551
552static void __init alloc_init_section(pud_t *pud, unsigned long addr,
553 unsigned long end, phys_addr_t phys,
554 const struct mem_type *type)
555{
556 pmd_t *pmd = pmd_offset(pud, addr);
557
558 /*
559 * Try a section mapping - end, addr and phys must all be aligned
560 * to a section boundary. Note that PMDs refer to the individual
561 * L1 entries, whereas PGDs refer to a group of L1 entries making
562 * up one logical pointer to an L2 table.
563 */
564 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
565 pmd_t *p = pmd;
566
567 if (addr & SECTION_SIZE)
568 pmd++;
569
570 do {
571 *pmd = __pmd(phys | type->prot_sect);
572 phys += SECTION_SIZE;
573 } while (pmd++, addr += SECTION_SIZE, addr != end);
574
575 flush_pmd_entry(p);
576 } else {
577 /*
578 * No need to loop; pte's aren't interested in the
579 * individual L1 entries.
580 */
581 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
582 }
583}
584
585static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
586 unsigned long phys, const struct mem_type *type)
587{
588 pud_t *pud = pud_offset(pgd, addr);
589 unsigned long next;
590
591 do {
592 next = pud_addr_end(addr, end);
593 alloc_init_section(pud, addr, next, phys, type);
594 phys += next - addr;
595 } while (pud++, addr = next, addr != end);
596}
597
598static void __init create_36bit_mapping(struct map_desc *md,
599 const struct mem_type *type)
600{
601 unsigned long addr, length, end;
602 phys_addr_t phys;
603 pgd_t *pgd;
604
605 addr = md->virtual;
606 phys = __pfn_to_phys(md->pfn);
607 length = PAGE_ALIGN(md->length);
608
609 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
610 printk(KERN_ERR "MM: CPU does not support supersection "
611 "mapping for 0x%08llx at 0x%08lx\n",
612 (long long)__pfn_to_phys((u64)md->pfn), addr);
613 return;
614 }
615
616 /* N.B. ARMv6 supersections are only defined to work with domain 0.
617 * Since domain assignments can in fact be arbitrary, the
618 * 'domain == 0' check below is required to insure that ARMv6
619 * supersections are only allocated for domain 0 regardless
620 * of the actual domain assignments in use.
621 */
622 if (type->domain) {
623 printk(KERN_ERR "MM: invalid domain in supersection "
624 "mapping for 0x%08llx at 0x%08lx\n",
625 (long long)__pfn_to_phys((u64)md->pfn), addr);
626 return;
627 }
628
629 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
630 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
631 " at 0x%08lx invalid alignment\n",
632 (long long)__pfn_to_phys((u64)md->pfn), addr);
633 return;
634 }
635
636 /*
637 * Shift bits [35:32] of address into bits [23:20] of PMD
638 * (See ARMv6 spec).
639 */
640 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
641
642 pgd = pgd_offset_k(addr);
643 end = addr + length;
644 do {
645 pud_t *pud = pud_offset(pgd, addr);
646 pmd_t *pmd = pmd_offset(pud, addr);
647 int i;
648
649 for (i = 0; i < 16; i++)
650 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
651
652 addr += SUPERSECTION_SIZE;
653 phys += SUPERSECTION_SIZE;
654 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
655 } while (addr != end);
656}
657
658/*
659 * Create the page directory entries and any necessary
660 * page tables for the mapping specified by `md'. We
661 * are able to cope here with varying sizes and address
662 * offsets, and we take full advantage of sections and
663 * supersections.
664 */
665static void __init create_mapping(struct map_desc *md)
666{
667 unsigned long addr, length, end;
668 phys_addr_t phys;
669 const struct mem_type *type;
670 pgd_t *pgd;
671
672 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
673 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
674 " at 0x%08lx in user region\n",
675 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
676 return;
677 }
678
679 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
680 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
681 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
682 " at 0x%08lx overlaps vmalloc space\n",
683 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
684 }
685
686 type = &mem_types[md->type];
687
688 /*
689 * Catch 36-bit addresses
690 */
691 if (md->pfn >= 0x100000) {
692 create_36bit_mapping(md, type);
693 return;
694 }
695
696 addr = md->virtual & PAGE_MASK;
697 phys = __pfn_to_phys(md->pfn);
698 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
699
700 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
701 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
702 "be mapped using pages, ignoring.\n",
703 (long long)__pfn_to_phys(md->pfn), addr);
704 return;
705 }
706
707 pgd = pgd_offset_k(addr);
708 end = addr + length;
709 do {
710 unsigned long next = pgd_addr_end(addr, end);
711
712 alloc_init_pud(pgd, addr, next, phys, type);
713
714 phys += next - addr;
715 addr = next;
716 } while (pgd++, addr != end);
717}
718
719/*
720 * Create the architecture specific mappings
721 */
722void __init iotable_init(struct map_desc *io_desc, int nr)
723{
724 int i;
725
726 for (i = 0; i < nr; i++)
727 create_mapping(io_desc + i);
728}
729
730static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
731
732/*
733 * vmalloc=size forces the vmalloc area to be exactly 'size'
734 * bytes. This can be used to increase (or decrease) the vmalloc
735 * area - the default is 128m.
736 */
737static int __init early_vmalloc(char *arg)
738{
739 unsigned long vmalloc_reserve = memparse(arg, NULL);
740
741 if (vmalloc_reserve < SZ_16M) {
742 vmalloc_reserve = SZ_16M;
743 printk(KERN_WARNING
744 "vmalloc area too small, limiting to %luMB\n",
745 vmalloc_reserve >> 20);
746 }
747
748 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
749 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
750 printk(KERN_WARNING
751 "vmalloc area is too big, limiting to %luMB\n",
752 vmalloc_reserve >> 20);
753 }
754
755 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
756 return 0;
757}
758early_param("vmalloc", early_vmalloc);
759
760static phys_addr_t lowmem_limit __initdata = 0;
761
762void __init sanity_check_meminfo(void)
763{
764 int i, j, highmem = 0;
765
766 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
767 struct membank *bank = &meminfo.bank[j];
768 *bank = meminfo.bank[i];
769
770#ifdef CONFIG_HIGHMEM
771 if (__va(bank->start) >= vmalloc_min ||
772 __va(bank->start) < (void *)PAGE_OFFSET)
773 highmem = 1;
774
775 bank->highmem = highmem;
776
777 /*
778 * Split those memory banks which are partially overlapping
779 * the vmalloc area greatly simplifying things later.
780 */
781 if (__va(bank->start) < vmalloc_min &&
782 bank->size > vmalloc_min - __va(bank->start)) {
783 if (meminfo.nr_banks >= NR_BANKS) {
784 printk(KERN_CRIT "NR_BANKS too low, "
785 "ignoring high memory\n");
786 } else {
787 memmove(bank + 1, bank,
788 (meminfo.nr_banks - i) * sizeof(*bank));
789 meminfo.nr_banks++;
790 i++;
791 bank[1].size -= vmalloc_min - __va(bank->start);
792 bank[1].start = __pa(vmalloc_min - 1) + 1;
793 bank[1].highmem = highmem = 1;
794 j++;
795 }
796 bank->size = vmalloc_min - __va(bank->start);
797 }
798#else
799 bank->highmem = highmem;
800
801 /*
802 * Check whether this memory bank would entirely overlap
803 * the vmalloc area.
804 */
805 if (__va(bank->start) >= vmalloc_min ||
806 __va(bank->start) < (void *)PAGE_OFFSET) {
807 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
808 "(vmalloc region overlap).\n",
809 (unsigned long long)bank->start,
810 (unsigned long long)bank->start + bank->size - 1);
811 continue;
812 }
813
814 /*
815 * Check whether this memory bank would partially overlap
816 * the vmalloc area.
817 */
818 if (__va(bank->start + bank->size) > vmalloc_min ||
819 __va(bank->start + bank->size) < __va(bank->start)) {
820 unsigned long newsize = vmalloc_min - __va(bank->start);
821 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
822 "to -%.8llx (vmalloc region overlap).\n",
823 (unsigned long long)bank->start,
824 (unsigned long long)bank->start + bank->size - 1,
825 (unsigned long long)bank->start + newsize - 1);
826 bank->size = newsize;
827 }
828#endif
829 if (!bank->highmem && bank->start + bank->size > lowmem_limit)
830 lowmem_limit = bank->start + bank->size;
831
832 j++;
833 }
834#ifdef CONFIG_HIGHMEM
835 if (highmem) {
836 const char *reason = NULL;
837
838 if (cache_is_vipt_aliasing()) {
839 /*
840 * Interactions between kmap and other mappings
841 * make highmem support with aliasing VIPT caches
842 * rather difficult.
843 */
844 reason = "with VIPT aliasing cache";
845 }
846 if (reason) {
847 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
848 reason);
849 while (j > 0 && meminfo.bank[j - 1].highmem)
850 j--;
851 }
852 }
853#endif
854 meminfo.nr_banks = j;
855 memblock_set_current_limit(lowmem_limit);
856}
857
858static inline void prepare_page_table(void)
859{
860 unsigned long addr;
861 phys_addr_t end;
862
863 /*
864 * Clear out all the mappings below the kernel image.
865 */
866 for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
867 pmd_clear(pmd_off_k(addr));
868
869#ifdef CONFIG_XIP_KERNEL
870 /* The XIP kernel is mapped in the module area -- skip over it */
871 addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
872#endif
873 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
874 pmd_clear(pmd_off_k(addr));
875
876 /*
877 * Find the end of the first block of lowmem.
878 */
879 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
880 if (end >= lowmem_limit)
881 end = lowmem_limit;
882
883 /*
884 * Clear out all the kernel space mappings, except for the first
885 * memory bank, up to the end of the vmalloc region.
886 */
887 for (addr = __phys_to_virt(end);
888 addr < VMALLOC_END; addr += PGDIR_SIZE)
889 pmd_clear(pmd_off_k(addr));
890}
891
892/*
893 * Reserve the special regions of memory
894 */
895void __init arm_mm_memblock_reserve(void)
896{
897 /*
898 * Reserve the page tables. These are already in use,
899 * and can only be in node 0.
900 */
901 memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
902
903#ifdef CONFIG_SA1111
904 /*
905 * Because of the SA1111 DMA bug, we want to preserve our
906 * precious DMA-able memory...
907 */
908 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
909#endif
910}
911
912/*
913 * Set up device the mappings. Since we clear out the page tables for all
914 * mappings above VMALLOC_END, we will remove any debug device mappings.
915 * This means you have to be careful how you debug this function, or any
916 * called function. This means you can't use any function or debugging
917 * method which may touch any device, otherwise the kernel _will_ crash.
918 */
919static void __init devicemaps_init(struct machine_desc *mdesc)
920{
921 struct map_desc map;
922 unsigned long addr;
923
924 /*
925 * Allocate the vector page early.
926 */
927 vectors_page = early_alloc(PAGE_SIZE);
928
929 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
930 pmd_clear(pmd_off_k(addr));
931
932 /*
933 * Map the kernel if it is XIP.
934 * It is always first in the modulearea.
935 */
936#ifdef CONFIG_XIP_KERNEL
937 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
938 map.virtual = MODULES_VADDR;
939 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
940 map.type = MT_ROM;
941 create_mapping(&map);
942#endif
943
944 /*
945 * Map the cache flushing regions.
946 */
947#ifdef FLUSH_BASE
948 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
949 map.virtual = FLUSH_BASE;
950 map.length = SZ_1M;
951 map.type = MT_CACHECLEAN;
952 create_mapping(&map);
953#endif
954#ifdef FLUSH_BASE_MINICACHE
955 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
956 map.virtual = FLUSH_BASE_MINICACHE;
957 map.length = SZ_1M;
958 map.type = MT_MINICLEAN;
959 create_mapping(&map);
960#endif
961
962 /*
963 * Create a mapping for the machine vectors at the high-vectors
964 * location (0xffff0000). If we aren't using high-vectors, also
965 * create a mapping at the low-vectors virtual address.
966 */
967 map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
968 map.virtual = 0xffff0000;
969 map.length = PAGE_SIZE;
970 map.type = MT_HIGH_VECTORS;
971 create_mapping(&map);
972
973 if (!vectors_high()) {
974 map.virtual = 0;
975 map.type = MT_LOW_VECTORS;
976 create_mapping(&map);
977 }
978
979 /*
980 * Ask the machine support to map in the statically mapped devices.
981 */
982 if (mdesc->map_io)
983 mdesc->map_io();
984
985 /*
986 * Finally flush the caches and tlb to ensure that we're in a
987 * consistent state wrt the writebuffer. This also ensures that
988 * any write-allocated cache lines in the vector page are written
989 * back. After this point, we can start to touch devices again.
990 */
991 local_flush_tlb_all();
992 flush_cache_all();
993}
994
995static void __init kmap_init(void)
996{
997#ifdef CONFIG_HIGHMEM
998 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
999 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1000#endif
1001}
1002
1003static void __init map_lowmem(void)
1004{
1005 struct memblock_region *reg;
1006
1007 /* Map all the lowmem memory banks. */
1008 for_each_memblock(memory, reg) {
1009 phys_addr_t start = reg->base;
1010 phys_addr_t end = start + reg->size;
1011 struct map_desc map;
1012
1013 if (end > lowmem_limit)
1014 end = lowmem_limit;
1015 if (start >= end)
1016 break;
1017
1018 map.pfn = __phys_to_pfn(start);
1019 map.virtual = __phys_to_virt(start);
1020 map.length = end - start;
1021 map.type = MT_MEMORY;
1022
1023 create_mapping(&map);
1024 }
1025}
1026
1027/*
1028 * paging_init() sets up the page tables, initialises the zone memory
1029 * maps, and sets up the zero page, bad page and bad page tables.
1030 */
1031void __init paging_init(struct machine_desc *mdesc)
1032{
1033 void *zero_page;
1034
1035 memblock_set_current_limit(lowmem_limit);
1036
1037 build_mem_type_table();
1038 prepare_page_table();
1039 map_lowmem();
1040 devicemaps_init(mdesc);
1041 kmap_init();
1042
1043 top_pmd = pmd_off_k(0xffff0000);
1044
1045 /* allocate the zero page. */
1046 zero_page = early_alloc(PAGE_SIZE);
1047
1048 bootmem_init();
1049
1050 empty_zero_page = virt_to_page(zero_page);
1051 __flush_dcache_page(NULL, empty_zero_page);
1052}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mm/mmu.c
4 *
5 * Copyright (C) 1995-2005 Russell King
6 */
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/init.h>
11#include <linux/mman.h>
12#include <linux/nodemask.h>
13#include <linux/memblock.h>
14#include <linux/fs.h>
15#include <linux/vmalloc.h>
16#include <linux/sizes.h>
17
18#include <asm/cp15.h>
19#include <asm/cputype.h>
20#include <asm/cachetype.h>
21#include <asm/sections.h>
22#include <asm/setup.h>
23#include <asm/smp_plat.h>
24#include <asm/tlb.h>
25#include <asm/highmem.h>
26#include <asm/system_info.h>
27#include <asm/traps.h>
28#include <asm/procinfo.h>
29#include <asm/memory.h>
30#include <asm/pgalloc.h>
31#include <asm/kasan_def.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/pci.h>
36#include <asm/fixmap.h>
37
38#include "fault.h"
39#include "mm.h"
40#include "tcm.h"
41
42extern unsigned long __atags_pointer;
43
44/*
45 * empty_zero_page is a special page that is used for
46 * zero-initialized data and COW.
47 */
48struct page *empty_zero_page;
49EXPORT_SYMBOL(empty_zero_page);
50
51/*
52 * The pmd table for the upper-most set of pages.
53 */
54pmd_t *top_pmd;
55
56pmdval_t user_pmd_table = _PAGE_USER_TABLE;
57
58#define CPOLICY_UNCACHED 0
59#define CPOLICY_BUFFERED 1
60#define CPOLICY_WRITETHROUGH 2
61#define CPOLICY_WRITEBACK 3
62#define CPOLICY_WRITEALLOC 4
63
64static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
65static unsigned int ecc_mask __initdata = 0;
66pgprot_t pgprot_user;
67pgprot_t pgprot_kernel;
68
69EXPORT_SYMBOL(pgprot_user);
70EXPORT_SYMBOL(pgprot_kernel);
71
72struct cachepolicy {
73 const char policy[16];
74 unsigned int cr_mask;
75 pmdval_t pmd;
76 pteval_t pte;
77};
78
79static struct cachepolicy cache_policies[] __initdata = {
80 {
81 .policy = "uncached",
82 .cr_mask = CR_W|CR_C,
83 .pmd = PMD_SECT_UNCACHED,
84 .pte = L_PTE_MT_UNCACHED,
85 }, {
86 .policy = "buffered",
87 .cr_mask = CR_C,
88 .pmd = PMD_SECT_BUFFERED,
89 .pte = L_PTE_MT_BUFFERABLE,
90 }, {
91 .policy = "writethrough",
92 .cr_mask = 0,
93 .pmd = PMD_SECT_WT,
94 .pte = L_PTE_MT_WRITETHROUGH,
95 }, {
96 .policy = "writeback",
97 .cr_mask = 0,
98 .pmd = PMD_SECT_WB,
99 .pte = L_PTE_MT_WRITEBACK,
100 }, {
101 .policy = "writealloc",
102 .cr_mask = 0,
103 .pmd = PMD_SECT_WBWA,
104 .pte = L_PTE_MT_WRITEALLOC,
105 }
106};
107
108#ifdef CONFIG_CPU_CP15
109static unsigned long initial_pmd_value __initdata = 0;
110
111/*
112 * Initialise the cache_policy variable with the initial state specified
113 * via the "pmd" value. This is used to ensure that on ARMv6 and later,
114 * the C code sets the page tables up with the same policy as the head
115 * assembly code, which avoids an illegal state where the TLBs can get
116 * confused. See comments in early_cachepolicy() for more information.
117 */
118void __init init_default_cache_policy(unsigned long pmd)
119{
120 int i;
121
122 initial_pmd_value = pmd;
123
124 pmd &= PMD_SECT_CACHE_MASK;
125
126 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
127 if (cache_policies[i].pmd == pmd) {
128 cachepolicy = i;
129 break;
130 }
131
132 if (i == ARRAY_SIZE(cache_policies))
133 pr_err("ERROR: could not find cache policy\n");
134}
135
136/*
137 * These are useful for identifying cache coherency problems by allowing
138 * the cache or the cache and writebuffer to be turned off. (Note: the
139 * write buffer should not be on and the cache off).
140 */
141static int __init early_cachepolicy(char *p)
142{
143 int i, selected = -1;
144
145 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
146 int len = strlen(cache_policies[i].policy);
147
148 if (memcmp(p, cache_policies[i].policy, len) == 0) {
149 selected = i;
150 break;
151 }
152 }
153
154 if (selected == -1)
155 pr_err("ERROR: unknown or unsupported cache policy\n");
156
157 /*
158 * This restriction is partly to do with the way we boot; it is
159 * unpredictable to have memory mapped using two different sets of
160 * memory attributes (shared, type, and cache attribs). We can not
161 * change these attributes once the initial assembly has setup the
162 * page tables.
163 */
164 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
165 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
166 cache_policies[cachepolicy].policy);
167 return 0;
168 }
169
170 if (selected != cachepolicy) {
171 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
172 cachepolicy = selected;
173 flush_cache_all();
174 set_cr(cr);
175 }
176 return 0;
177}
178early_param("cachepolicy", early_cachepolicy);
179
180static int __init early_nocache(char *__unused)
181{
182 char *p = "buffered";
183 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
184 early_cachepolicy(p);
185 return 0;
186}
187early_param("nocache", early_nocache);
188
189static int __init early_nowrite(char *__unused)
190{
191 char *p = "uncached";
192 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
193 early_cachepolicy(p);
194 return 0;
195}
196early_param("nowb", early_nowrite);
197
198#ifndef CONFIG_ARM_LPAE
199static int __init early_ecc(char *p)
200{
201 if (memcmp(p, "on", 2) == 0)
202 ecc_mask = PMD_PROTECTION;
203 else if (memcmp(p, "off", 3) == 0)
204 ecc_mask = 0;
205 return 0;
206}
207early_param("ecc", early_ecc);
208#endif
209
210#else /* ifdef CONFIG_CPU_CP15 */
211
212static int __init early_cachepolicy(char *p)
213{
214 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
215 return 0;
216}
217early_param("cachepolicy", early_cachepolicy);
218
219static int __init noalign_setup(char *__unused)
220{
221 pr_warn("noalign kernel parameter not supported without cp15\n");
222 return 1;
223}
224__setup("noalign", noalign_setup);
225
226#endif /* ifdef CONFIG_CPU_CP15 / else */
227
228#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
229#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
230#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
231
232static struct mem_type mem_types[] __ro_after_init = {
233 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
234 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
235 L_PTE_SHARED,
236 .prot_l1 = PMD_TYPE_TABLE,
237 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
238 .domain = DOMAIN_IO,
239 },
240 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
241 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
242 .prot_l1 = PMD_TYPE_TABLE,
243 .prot_sect = PROT_SECT_DEVICE,
244 .domain = DOMAIN_IO,
245 },
246 [MT_DEVICE_CACHED] = { /* ioremap_cache */
247 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
248 .prot_l1 = PMD_TYPE_TABLE,
249 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
250 .domain = DOMAIN_IO,
251 },
252 [MT_DEVICE_WC] = { /* ioremap_wc */
253 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
254 .prot_l1 = PMD_TYPE_TABLE,
255 .prot_sect = PROT_SECT_DEVICE,
256 .domain = DOMAIN_IO,
257 },
258 [MT_UNCACHED] = {
259 .prot_pte = PROT_PTE_DEVICE,
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
262 .domain = DOMAIN_IO,
263 },
264 [MT_CACHECLEAN] = {
265 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
266 .domain = DOMAIN_KERNEL,
267 },
268#ifndef CONFIG_ARM_LPAE
269 [MT_MINICLEAN] = {
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
271 .domain = DOMAIN_KERNEL,
272 },
273#endif
274 [MT_LOW_VECTORS] = {
275 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
276 L_PTE_RDONLY,
277 .prot_l1 = PMD_TYPE_TABLE,
278 .domain = DOMAIN_VECTORS,
279 },
280 [MT_HIGH_VECTORS] = {
281 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
282 L_PTE_USER | L_PTE_RDONLY,
283 .prot_l1 = PMD_TYPE_TABLE,
284 .domain = DOMAIN_VECTORS,
285 },
286 [MT_MEMORY_RWX] = {
287 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
288 .prot_l1 = PMD_TYPE_TABLE,
289 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
290 .domain = DOMAIN_KERNEL,
291 },
292 [MT_MEMORY_RW] = {
293 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
294 L_PTE_XN,
295 .prot_l1 = PMD_TYPE_TABLE,
296 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
297 .domain = DOMAIN_KERNEL,
298 },
299 [MT_MEMORY_RO] = {
300 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
301 L_PTE_XN | L_PTE_RDONLY,
302 .prot_l1 = PMD_TYPE_TABLE,
303#ifdef CONFIG_ARM_LPAE
304 .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2,
305#else
306 .prot_sect = PMD_TYPE_SECT,
307#endif
308 .domain = DOMAIN_KERNEL,
309 },
310 [MT_ROM] = {
311 .prot_sect = PMD_TYPE_SECT,
312 .domain = DOMAIN_KERNEL,
313 },
314 [MT_MEMORY_RWX_NONCACHED] = {
315 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
316 L_PTE_MT_BUFFERABLE,
317 .prot_l1 = PMD_TYPE_TABLE,
318 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
319 .domain = DOMAIN_KERNEL,
320 },
321 [MT_MEMORY_RW_DTCM] = {
322 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
323 L_PTE_XN,
324 .prot_l1 = PMD_TYPE_TABLE,
325 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
326 .domain = DOMAIN_KERNEL,
327 },
328 [MT_MEMORY_RWX_ITCM] = {
329 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
330 .prot_l1 = PMD_TYPE_TABLE,
331 .domain = DOMAIN_KERNEL,
332 },
333 [MT_MEMORY_RW_SO] = {
334 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
335 L_PTE_MT_UNCACHED | L_PTE_XN,
336 .prot_l1 = PMD_TYPE_TABLE,
337 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
338 PMD_SECT_UNCACHED | PMD_SECT_XN,
339 .domain = DOMAIN_KERNEL,
340 },
341 [MT_MEMORY_DMA_READY] = {
342 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
343 L_PTE_XN,
344 .prot_l1 = PMD_TYPE_TABLE,
345 .domain = DOMAIN_KERNEL,
346 },
347};
348
349const struct mem_type *get_mem_type(unsigned int type)
350{
351 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
352}
353EXPORT_SYMBOL(get_mem_type);
354
355static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
356
357static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
358 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
359
360static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
361{
362 return &bm_pte[pte_index(addr)];
363}
364
365static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
366{
367 return pte_offset_kernel(dir, addr);
368}
369
370static inline pmd_t * __init fixmap_pmd(unsigned long addr)
371{
372 return pmd_off_k(addr);
373}
374
375void __init early_fixmap_init(void)
376{
377 pmd_t *pmd;
378
379 /*
380 * The early fixmap range spans multiple pmds, for which
381 * we are not prepared:
382 */
383 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
384 != FIXADDR_TOP >> PMD_SHIFT);
385
386 pmd = fixmap_pmd(FIXADDR_TOP);
387 pmd_populate_kernel(&init_mm, pmd, bm_pte);
388
389 pte_offset_fixmap = pte_offset_early_fixmap;
390}
391
392/*
393 * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
394 * As a result, this can only be called with preemption disabled, as under
395 * stop_machine().
396 */
397void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
398{
399 unsigned long vaddr = __fix_to_virt(idx);
400 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
401
402 /* Make sure fixmap region does not exceed available allocation. */
403 BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) < FIXADDR_START);
404 BUG_ON(idx >= __end_of_fixed_addresses);
405
406 /* We support only device mappings before pgprot_kernel is set. */
407 if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
408 pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
409 return;
410
411 if (pgprot_val(prot))
412 set_pte_at(NULL, vaddr, pte,
413 pfn_pte(phys >> PAGE_SHIFT, prot));
414 else
415 pte_clear(NULL, vaddr, pte);
416 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
417}
418
419static pgprot_t protection_map[16] __ro_after_init = {
420 [VM_NONE] = __PAGE_NONE,
421 [VM_READ] = __PAGE_READONLY,
422 [VM_WRITE] = __PAGE_COPY,
423 [VM_WRITE | VM_READ] = __PAGE_COPY,
424 [VM_EXEC] = __PAGE_READONLY_EXEC,
425 [VM_EXEC | VM_READ] = __PAGE_READONLY_EXEC,
426 [VM_EXEC | VM_WRITE] = __PAGE_COPY_EXEC,
427 [VM_EXEC | VM_WRITE | VM_READ] = __PAGE_COPY_EXEC,
428 [VM_SHARED] = __PAGE_NONE,
429 [VM_SHARED | VM_READ] = __PAGE_READONLY,
430 [VM_SHARED | VM_WRITE] = __PAGE_SHARED,
431 [VM_SHARED | VM_WRITE | VM_READ] = __PAGE_SHARED,
432 [VM_SHARED | VM_EXEC] = __PAGE_READONLY_EXEC,
433 [VM_SHARED | VM_EXEC | VM_READ] = __PAGE_READONLY_EXEC,
434 [VM_SHARED | VM_EXEC | VM_WRITE] = __PAGE_SHARED_EXEC,
435 [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = __PAGE_SHARED_EXEC
436};
437DECLARE_VM_GET_PAGE_PROT
438
439/*
440 * Adjust the PMD section entries according to the CPU in use.
441 */
442static void __init build_mem_type_table(void)
443{
444 struct cachepolicy *cp;
445 unsigned int cr = get_cr();
446 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
447 int cpu_arch = cpu_architecture();
448 int i;
449
450 if (cpu_arch < CPU_ARCH_ARMv6) {
451#if defined(CONFIG_CPU_DCACHE_DISABLE)
452 if (cachepolicy > CPOLICY_BUFFERED)
453 cachepolicy = CPOLICY_BUFFERED;
454#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
455 if (cachepolicy > CPOLICY_WRITETHROUGH)
456 cachepolicy = CPOLICY_WRITETHROUGH;
457#endif
458 }
459 if (cpu_arch < CPU_ARCH_ARMv5) {
460 if (cachepolicy >= CPOLICY_WRITEALLOC)
461 cachepolicy = CPOLICY_WRITEBACK;
462 ecc_mask = 0;
463 }
464
465 if (is_smp()) {
466 if (cachepolicy != CPOLICY_WRITEALLOC) {
467 pr_warn("Forcing write-allocate cache policy for SMP\n");
468 cachepolicy = CPOLICY_WRITEALLOC;
469 }
470 if (!(initial_pmd_value & PMD_SECT_S)) {
471 pr_warn("Forcing shared mappings for SMP\n");
472 initial_pmd_value |= PMD_SECT_S;
473 }
474 }
475
476 /*
477 * Strip out features not present on earlier architectures.
478 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
479 * without extended page tables don't have the 'Shared' bit.
480 */
481 if (cpu_arch < CPU_ARCH_ARMv5)
482 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
483 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
484 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
485 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
486 mem_types[i].prot_sect &= ~PMD_SECT_S;
487
488 /*
489 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
490 * "update-able on write" bit on ARM610). However, Xscale and
491 * Xscale3 require this bit to be cleared.
492 */
493 if (cpu_is_xscale_family()) {
494 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
495 mem_types[i].prot_sect &= ~PMD_BIT4;
496 mem_types[i].prot_l1 &= ~PMD_BIT4;
497 }
498 } else if (cpu_arch < CPU_ARCH_ARMv6) {
499 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
500 if (mem_types[i].prot_l1)
501 mem_types[i].prot_l1 |= PMD_BIT4;
502 if (mem_types[i].prot_sect)
503 mem_types[i].prot_sect |= PMD_BIT4;
504 }
505 }
506
507 /*
508 * Mark the device areas according to the CPU/architecture.
509 */
510 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
511 if (!cpu_is_xsc3()) {
512 /*
513 * Mark device regions on ARMv6+ as execute-never
514 * to prevent speculative instruction fetches.
515 */
516 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
517 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
518 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
519 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
520
521 /* Also setup NX memory mapping */
522 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
523 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_XN;
524 }
525 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
526 /*
527 * For ARMv7 with TEX remapping,
528 * - shared device is SXCB=1100
529 * - nonshared device is SXCB=0100
530 * - write combine device mem is SXCB=0001
531 * (Uncached Normal memory)
532 */
533 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
534 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
535 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
536 } else if (cpu_is_xsc3()) {
537 /*
538 * For Xscale3,
539 * - shared device is TEXCB=00101
540 * - nonshared device is TEXCB=01000
541 * - write combine device mem is TEXCB=00100
542 * (Inner/Outer Uncacheable in xsc3 parlance)
543 */
544 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
545 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
546 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
547 } else {
548 /*
549 * For ARMv6 and ARMv7 without TEX remapping,
550 * - shared device is TEXCB=00001
551 * - nonshared device is TEXCB=01000
552 * - write combine device mem is TEXCB=00100
553 * (Uncached Normal in ARMv6 parlance).
554 */
555 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
556 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
557 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
558 }
559 } else {
560 /*
561 * On others, write combining is "Uncached/Buffered"
562 */
563 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
564 }
565
566 /*
567 * Now deal with the memory-type mappings
568 */
569 cp = &cache_policies[cachepolicy];
570 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
571
572#ifndef CONFIG_ARM_LPAE
573 /*
574 * We don't use domains on ARMv6 (since this causes problems with
575 * v6/v7 kernels), so we must use a separate memory type for user
576 * r/o, kernel r/w to map the vectors page.
577 */
578 if (cpu_arch == CPU_ARCH_ARMv6)
579 vecs_pgprot |= L_PTE_MT_VECTORS;
580
581 /*
582 * Check is it with support for the PXN bit
583 * in the Short-descriptor translation table format descriptors.
584 */
585 if (cpu_arch == CPU_ARCH_ARMv7 &&
586 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
587 user_pmd_table |= PMD_PXNTABLE;
588 }
589#endif
590
591 /*
592 * ARMv6 and above have extended page tables.
593 */
594 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
595#ifndef CONFIG_ARM_LPAE
596 /*
597 * Mark cache clean areas and XIP ROM read only
598 * from SVC mode and no access from userspace.
599 */
600 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
601 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
602 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
603 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
604#endif
605
606 /*
607 * If the initial page tables were created with the S bit
608 * set, then we need to do the same here for the same
609 * reasons given in early_cachepolicy().
610 */
611 if (initial_pmd_value & PMD_SECT_S) {
612 user_pgprot |= L_PTE_SHARED;
613 kern_pgprot |= L_PTE_SHARED;
614 vecs_pgprot |= L_PTE_SHARED;
615 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
616 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
617 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
618 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
619 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
620 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
621 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
622 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
623 mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_S;
624 mem_types[MT_MEMORY_RO].prot_pte |= L_PTE_SHARED;
625 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
626 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
627 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
628 }
629 }
630
631 /*
632 * Non-cacheable Normal - intended for memory areas that must
633 * not cause dirty cache line writebacks when used
634 */
635 if (cpu_arch >= CPU_ARCH_ARMv6) {
636 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
637 /* Non-cacheable Normal is XCB = 001 */
638 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
639 PMD_SECT_BUFFERED;
640 } else {
641 /* For both ARMv6 and non-TEX-remapping ARMv7 */
642 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
643 PMD_SECT_TEX(1);
644 }
645 } else {
646 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
647 }
648
649#ifdef CONFIG_ARM_LPAE
650 /*
651 * Do not generate access flag faults for the kernel mappings.
652 */
653 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
654 mem_types[i].prot_pte |= PTE_EXT_AF;
655 if (mem_types[i].prot_sect)
656 mem_types[i].prot_sect |= PMD_SECT_AF;
657 }
658 kern_pgprot |= PTE_EXT_AF;
659 vecs_pgprot |= PTE_EXT_AF;
660
661 /*
662 * Set PXN for user mappings
663 */
664 user_pgprot |= PTE_EXT_PXN;
665#endif
666
667 for (i = 0; i < 16; i++) {
668 pteval_t v = pgprot_val(protection_map[i]);
669 protection_map[i] = __pgprot(v | user_pgprot);
670 }
671
672 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
673 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
674
675 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
676 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
677 L_PTE_DIRTY | kern_pgprot);
678
679 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
680 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
681 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
682 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
683 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
684 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
685 mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd;
686 mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot;
687 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
688 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
689 mem_types[MT_ROM].prot_sect |= cp->pmd;
690
691 switch (cp->pmd) {
692 case PMD_SECT_WT:
693 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
694 break;
695 case PMD_SECT_WB:
696 case PMD_SECT_WBWA:
697 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
698 break;
699 }
700 pr_info("Memory policy: %sData cache %s\n",
701 ecc_mask ? "ECC enabled, " : "", cp->policy);
702
703 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
704 struct mem_type *t = &mem_types[i];
705 if (t->prot_l1)
706 t->prot_l1 |= PMD_DOMAIN(t->domain);
707 if (t->prot_sect)
708 t->prot_sect |= PMD_DOMAIN(t->domain);
709 }
710}
711
712#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
713pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
714 unsigned long size, pgprot_t vma_prot)
715{
716 if (!pfn_valid(pfn))
717 return pgprot_noncached(vma_prot);
718 else if (file->f_flags & O_SYNC)
719 return pgprot_writecombine(vma_prot);
720 return vma_prot;
721}
722EXPORT_SYMBOL(phys_mem_access_prot);
723#endif
724
725#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
726
727static void __init *early_alloc(unsigned long sz)
728{
729 void *ptr = memblock_alloc(sz, sz);
730
731 if (!ptr)
732 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
733 __func__, sz, sz);
734
735 return ptr;
736}
737
738static void *__init late_alloc(unsigned long sz)
739{
740 void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
741
742 if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
743 BUG();
744 return ptr;
745}
746
747static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
748 unsigned long prot,
749 void *(*alloc)(unsigned long sz))
750{
751 if (pmd_none(*pmd)) {
752 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
753 __pmd_populate(pmd, __pa(pte), prot);
754 }
755 BUG_ON(pmd_bad(*pmd));
756 return pte_offset_kernel(pmd, addr);
757}
758
759static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
760 unsigned long prot)
761{
762 return arm_pte_alloc(pmd, addr, prot, early_alloc);
763}
764
765static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
766 unsigned long end, unsigned long pfn,
767 const struct mem_type *type,
768 void *(*alloc)(unsigned long sz),
769 bool ng)
770{
771 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
772 do {
773 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
774 ng ? PTE_EXT_NG : 0);
775 pfn++;
776 } while (pte++, addr += PAGE_SIZE, addr != end);
777}
778
779static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
780 unsigned long end, phys_addr_t phys,
781 const struct mem_type *type, bool ng)
782{
783 pmd_t *p = pmd;
784
785#ifndef CONFIG_ARM_LPAE
786 /*
787 * In classic MMU format, puds and pmds are folded in to
788 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
789 * group of L1 entries making up one logical pointer to
790 * an L2 table (2MB), where as PMDs refer to the individual
791 * L1 entries (1MB). Hence increment to get the correct
792 * offset for odd 1MB sections.
793 * (See arch/arm/include/asm/pgtable-2level.h)
794 */
795 if (addr & SECTION_SIZE)
796 pmd++;
797#endif
798 do {
799 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
800 phys += SECTION_SIZE;
801 } while (pmd++, addr += SECTION_SIZE, addr != end);
802
803 flush_pmd_entry(p);
804}
805
806static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
807 unsigned long end, phys_addr_t phys,
808 const struct mem_type *type,
809 void *(*alloc)(unsigned long sz), bool ng)
810{
811 pmd_t *pmd = pmd_offset(pud, addr);
812 unsigned long next;
813
814 do {
815 /*
816 * With LPAE, we must loop over to map
817 * all the pmds for the given range.
818 */
819 next = pmd_addr_end(addr, end);
820
821 /*
822 * Try a section mapping - addr, next and phys must all be
823 * aligned to a section boundary.
824 */
825 if (type->prot_sect &&
826 ((addr | next | phys) & ~SECTION_MASK) == 0) {
827 __map_init_section(pmd, addr, next, phys, type, ng);
828 } else {
829 alloc_init_pte(pmd, addr, next,
830 __phys_to_pfn(phys), type, alloc, ng);
831 }
832
833 phys += next - addr;
834
835 } while (pmd++, addr = next, addr != end);
836}
837
838static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
839 unsigned long end, phys_addr_t phys,
840 const struct mem_type *type,
841 void *(*alloc)(unsigned long sz), bool ng)
842{
843 pud_t *pud = pud_offset(p4d, addr);
844 unsigned long next;
845
846 do {
847 next = pud_addr_end(addr, end);
848 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
849 phys += next - addr;
850 } while (pud++, addr = next, addr != end);
851}
852
853static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
854 unsigned long end, phys_addr_t phys,
855 const struct mem_type *type,
856 void *(*alloc)(unsigned long sz), bool ng)
857{
858 p4d_t *p4d = p4d_offset(pgd, addr);
859 unsigned long next;
860
861 do {
862 next = p4d_addr_end(addr, end);
863 alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
864 phys += next - addr;
865 } while (p4d++, addr = next, addr != end);
866}
867
868#ifndef CONFIG_ARM_LPAE
869static void __init create_36bit_mapping(struct mm_struct *mm,
870 struct map_desc *md,
871 const struct mem_type *type,
872 bool ng)
873{
874 unsigned long addr, length, end;
875 phys_addr_t phys;
876 pgd_t *pgd;
877
878 addr = md->virtual;
879 phys = __pfn_to_phys(md->pfn);
880 length = PAGE_ALIGN(md->length);
881
882 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
883 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
884 (long long)__pfn_to_phys((u64)md->pfn), addr);
885 return;
886 }
887
888 /* N.B. ARMv6 supersections are only defined to work with domain 0.
889 * Since domain assignments can in fact be arbitrary, the
890 * 'domain == 0' check below is required to insure that ARMv6
891 * supersections are only allocated for domain 0 regardless
892 * of the actual domain assignments in use.
893 */
894 if (type->domain) {
895 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
896 (long long)__pfn_to_phys((u64)md->pfn), addr);
897 return;
898 }
899
900 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
901 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
902 (long long)__pfn_to_phys((u64)md->pfn), addr);
903 return;
904 }
905
906 /*
907 * Shift bits [35:32] of address into bits [23:20] of PMD
908 * (See ARMv6 spec).
909 */
910 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
911
912 pgd = pgd_offset(mm, addr);
913 end = addr + length;
914 do {
915 p4d_t *p4d = p4d_offset(pgd, addr);
916 pud_t *pud = pud_offset(p4d, addr);
917 pmd_t *pmd = pmd_offset(pud, addr);
918 int i;
919
920 for (i = 0; i < 16; i++)
921 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
922 (ng ? PMD_SECT_nG : 0));
923
924 addr += SUPERSECTION_SIZE;
925 phys += SUPERSECTION_SIZE;
926 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
927 } while (addr != end);
928}
929#endif /* !CONFIG_ARM_LPAE */
930
931static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
932 void *(*alloc)(unsigned long sz),
933 bool ng)
934{
935 unsigned long addr, length, end;
936 phys_addr_t phys;
937 const struct mem_type *type;
938 pgd_t *pgd;
939
940 type = &mem_types[md->type];
941
942#ifndef CONFIG_ARM_LPAE
943 /*
944 * Catch 36-bit addresses
945 */
946 if (md->pfn >= 0x100000) {
947 create_36bit_mapping(mm, md, type, ng);
948 return;
949 }
950#endif
951
952 addr = md->virtual & PAGE_MASK;
953 phys = __pfn_to_phys(md->pfn);
954 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
955
956 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
957 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
958 (long long)__pfn_to_phys(md->pfn), addr);
959 return;
960 }
961
962 pgd = pgd_offset(mm, addr);
963 end = addr + length;
964 do {
965 unsigned long next = pgd_addr_end(addr, end);
966
967 alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
968
969 phys += next - addr;
970 addr = next;
971 } while (pgd++, addr != end);
972}
973
974/*
975 * Create the page directory entries and any necessary
976 * page tables for the mapping specified by `md'. We
977 * are able to cope here with varying sizes and address
978 * offsets, and we take full advantage of sections and
979 * supersections.
980 */
981static void __init create_mapping(struct map_desc *md)
982{
983 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
984 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
985 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
986 return;
987 }
988
989 if (md->type == MT_DEVICE &&
990 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
991 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
992 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
993 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
994 }
995
996 __create_mapping(&init_mm, md, early_alloc, false);
997}
998
999void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
1000 bool ng)
1001{
1002#ifdef CONFIG_ARM_LPAE
1003 p4d_t *p4d;
1004 pud_t *pud;
1005
1006 p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
1007 if (WARN_ON(!p4d))
1008 return;
1009 pud = pud_alloc(mm, p4d, md->virtual);
1010 if (WARN_ON(!pud))
1011 return;
1012 pmd_alloc(mm, pud, 0);
1013#endif
1014 __create_mapping(mm, md, late_alloc, ng);
1015}
1016
1017/*
1018 * Create the architecture specific mappings
1019 */
1020void __init iotable_init(struct map_desc *io_desc, int nr)
1021{
1022 struct map_desc *md;
1023 struct vm_struct *vm;
1024 struct static_vm *svm;
1025
1026 if (!nr)
1027 return;
1028
1029 svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
1030 if (!svm)
1031 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1032 __func__, sizeof(*svm) * nr, __alignof__(*svm));
1033
1034 for (md = io_desc; nr; md++, nr--) {
1035 create_mapping(md);
1036
1037 vm = &svm->vm;
1038 vm->addr = (void *)(md->virtual & PAGE_MASK);
1039 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1040 vm->phys_addr = __pfn_to_phys(md->pfn);
1041 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1042 vm->flags |= VM_ARM_MTYPE(md->type);
1043 vm->caller = iotable_init;
1044 add_static_vm_early(svm++);
1045 }
1046}
1047
1048void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1049 void *caller)
1050{
1051 struct vm_struct *vm;
1052 struct static_vm *svm;
1053
1054 svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
1055 if (!svm)
1056 panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
1057 __func__, sizeof(*svm), __alignof__(*svm));
1058
1059 vm = &svm->vm;
1060 vm->addr = (void *)addr;
1061 vm->size = size;
1062 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1063 vm->caller = caller;
1064 add_static_vm_early(svm);
1065}
1066
1067#ifndef CONFIG_ARM_LPAE
1068
1069/*
1070 * The Linux PMD is made of two consecutive section entries covering 2MB
1071 * (see definition in include/asm/pgtable-2level.h). However a call to
1072 * create_mapping() may optimize static mappings by using individual
1073 * 1MB section mappings. This leaves the actual PMD potentially half
1074 * initialized if the top or bottom section entry isn't used, leaving it
1075 * open to problems if a subsequent ioremap() or vmalloc() tries to use
1076 * the virtual space left free by that unused section entry.
1077 *
1078 * Let's avoid the issue by inserting dummy vm entries covering the unused
1079 * PMD halves once the static mappings are in place.
1080 */
1081
1082static void __init pmd_empty_section_gap(unsigned long addr)
1083{
1084 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1085}
1086
1087static void __init fill_pmd_gaps(void)
1088{
1089 struct static_vm *svm;
1090 struct vm_struct *vm;
1091 unsigned long addr, next = 0;
1092 pmd_t *pmd;
1093
1094 list_for_each_entry(svm, &static_vmlist, list) {
1095 vm = &svm->vm;
1096 addr = (unsigned long)vm->addr;
1097 if (addr < next)
1098 continue;
1099
1100 /*
1101 * Check if this vm starts on an odd section boundary.
1102 * If so and the first section entry for this PMD is free
1103 * then we block the corresponding virtual address.
1104 */
1105 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1106 pmd = pmd_off_k(addr);
1107 if (pmd_none(*pmd))
1108 pmd_empty_section_gap(addr & PMD_MASK);
1109 }
1110
1111 /*
1112 * Then check if this vm ends on an odd section boundary.
1113 * If so and the second section entry for this PMD is empty
1114 * then we block the corresponding virtual address.
1115 */
1116 addr += vm->size;
1117 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1118 pmd = pmd_off_k(addr) + 1;
1119 if (pmd_none(*pmd))
1120 pmd_empty_section_gap(addr);
1121 }
1122
1123 /* no need to look at any vm entry until we hit the next PMD */
1124 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1125 }
1126}
1127
1128#else
1129#define fill_pmd_gaps() do { } while (0)
1130#endif
1131
1132#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1133static void __init pci_reserve_io(void)
1134{
1135 struct static_vm *svm;
1136
1137 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1138 if (svm)
1139 return;
1140
1141 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1142}
1143#else
1144#define pci_reserve_io() do { } while (0)
1145#endif
1146
1147#ifdef CONFIG_DEBUG_LL
1148void __init debug_ll_io_init(void)
1149{
1150 struct map_desc map;
1151
1152 debug_ll_addr(&map.pfn, &map.virtual);
1153 if (!map.pfn || !map.virtual)
1154 return;
1155 map.pfn = __phys_to_pfn(map.pfn);
1156 map.virtual &= PAGE_MASK;
1157 map.length = PAGE_SIZE;
1158 map.type = MT_DEVICE;
1159 iotable_init(&map, 1);
1160}
1161#endif
1162
1163static unsigned long __initdata vmalloc_size = 240 * SZ_1M;
1164
1165/*
1166 * vmalloc=size forces the vmalloc area to be exactly 'size'
1167 * bytes. This can be used to increase (or decrease) the vmalloc
1168 * area - the default is 240MiB.
1169 */
1170static int __init early_vmalloc(char *arg)
1171{
1172 unsigned long vmalloc_reserve = memparse(arg, NULL);
1173 unsigned long vmalloc_max;
1174
1175 if (vmalloc_reserve < SZ_16M) {
1176 vmalloc_reserve = SZ_16M;
1177 pr_warn("vmalloc area is too small, limiting to %luMiB\n",
1178 vmalloc_reserve >> 20);
1179 }
1180
1181 vmalloc_max = VMALLOC_END - (PAGE_OFFSET + SZ_32M + VMALLOC_OFFSET);
1182 if (vmalloc_reserve > vmalloc_max) {
1183 vmalloc_reserve = vmalloc_max;
1184 pr_warn("vmalloc area is too big, limiting to %luMiB\n",
1185 vmalloc_reserve >> 20);
1186 }
1187
1188 vmalloc_size = vmalloc_reserve;
1189 return 0;
1190}
1191early_param("vmalloc", early_vmalloc);
1192
1193phys_addr_t arm_lowmem_limit __initdata = 0;
1194
1195void __init adjust_lowmem_bounds(void)
1196{
1197 phys_addr_t block_start, block_end, memblock_limit = 0;
1198 u64 vmalloc_limit, i;
1199 phys_addr_t lowmem_limit = 0;
1200
1201 /*
1202 * Let's use our own (unoptimized) equivalent of __pa() that is
1203 * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
1204 * The result is used as the upper bound on physical memory address
1205 * and may itself be outside the valid range for which phys_addr_t
1206 * and therefore __pa() is defined.
1207 */
1208 vmalloc_limit = (u64)VMALLOC_END - vmalloc_size - VMALLOC_OFFSET -
1209 PAGE_OFFSET + PHYS_OFFSET;
1210
1211 /*
1212 * The first usable region must be PMD aligned. Mark its start
1213 * as MEMBLOCK_NOMAP if it isn't
1214 */
1215 for_each_mem_range(i, &block_start, &block_end) {
1216 if (!IS_ALIGNED(block_start, PMD_SIZE)) {
1217 phys_addr_t len;
1218
1219 len = round_up(block_start, PMD_SIZE) - block_start;
1220 memblock_mark_nomap(block_start, len);
1221 }
1222 break;
1223 }
1224
1225 for_each_mem_range(i, &block_start, &block_end) {
1226 if (block_start < vmalloc_limit) {
1227 if (block_end > lowmem_limit)
1228 /*
1229 * Compare as u64 to ensure vmalloc_limit does
1230 * not get truncated. block_end should always
1231 * fit in phys_addr_t so there should be no
1232 * issue with assignment.
1233 */
1234 lowmem_limit = min_t(u64,
1235 vmalloc_limit,
1236 block_end);
1237
1238 /*
1239 * Find the first non-pmd-aligned page, and point
1240 * memblock_limit at it. This relies on rounding the
1241 * limit down to be pmd-aligned, which happens at the
1242 * end of this function.
1243 *
1244 * With this algorithm, the start or end of almost any
1245 * bank can be non-pmd-aligned. The only exception is
1246 * that the start of the bank 0 must be section-
1247 * aligned, since otherwise memory would need to be
1248 * allocated when mapping the start of bank 0, which
1249 * occurs before any free memory is mapped.
1250 */
1251 if (!memblock_limit) {
1252 if (!IS_ALIGNED(block_start, PMD_SIZE))
1253 memblock_limit = block_start;
1254 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1255 memblock_limit = lowmem_limit;
1256 }
1257
1258 }
1259 }
1260
1261 arm_lowmem_limit = lowmem_limit;
1262
1263 high_memory = __va(arm_lowmem_limit - 1) + 1;
1264
1265 if (!memblock_limit)
1266 memblock_limit = arm_lowmem_limit;
1267
1268 /*
1269 * Round the memblock limit down to a pmd size. This
1270 * helps to ensure that we will allocate memory from the
1271 * last full pmd, which should be mapped.
1272 */
1273 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1274
1275 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1276 if (memblock_end_of_DRAM() > arm_lowmem_limit) {
1277 phys_addr_t end = memblock_end_of_DRAM();
1278
1279 pr_notice("Ignoring RAM at %pa-%pa\n",
1280 &memblock_limit, &end);
1281 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1282
1283 memblock_remove(memblock_limit, end - memblock_limit);
1284 }
1285 }
1286
1287 memblock_set_current_limit(memblock_limit);
1288}
1289
1290static __init void prepare_page_table(void)
1291{
1292 unsigned long addr;
1293 phys_addr_t end;
1294
1295 /*
1296 * Clear out all the mappings below the kernel image.
1297 */
1298#ifdef CONFIG_KASAN
1299 /*
1300 * KASan's shadow memory inserts itself between the TASK_SIZE
1301 * and MODULES_VADDR. Do not clear the KASan shadow memory mappings.
1302 */
1303 for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE)
1304 pmd_clear(pmd_off_k(addr));
1305 /*
1306 * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes
1307 * equal to MODULES_VADDR and then we exit the pmd clearing. If we
1308 * are using a thumb-compiled kernel, there there will be 8MB more
1309 * to clear as KASan always offset to 16 MB below MODULES_VADDR.
1310 */
1311 for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE)
1312 pmd_clear(pmd_off_k(addr));
1313#else
1314 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1315 pmd_clear(pmd_off_k(addr));
1316#endif
1317
1318#ifdef CONFIG_XIP_KERNEL
1319 /* The XIP kernel is mapped in the module area -- skip over it */
1320 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1321#endif
1322 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1323 pmd_clear(pmd_off_k(addr));
1324
1325 /*
1326 * Find the end of the first block of lowmem.
1327 */
1328 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1329 if (end >= arm_lowmem_limit)
1330 end = arm_lowmem_limit;
1331
1332 /*
1333 * Clear out all the kernel space mappings, except for the first
1334 * memory bank, up to the vmalloc region.
1335 */
1336 for (addr = __phys_to_virt(end);
1337 addr < VMALLOC_START; addr += PMD_SIZE)
1338 pmd_clear(pmd_off_k(addr));
1339}
1340
1341#ifdef CONFIG_ARM_LPAE
1342/* the first page is reserved for pgd */
1343#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1344 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1345#else
1346#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1347#endif
1348
1349/*
1350 * Reserve the special regions of memory
1351 */
1352void __init arm_mm_memblock_reserve(void)
1353{
1354 /*
1355 * Reserve the page tables. These are already in use,
1356 * and can only be in node 0.
1357 */
1358 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1359
1360#ifdef CONFIG_SA1111
1361 /*
1362 * Because of the SA1111 DMA bug, we want to preserve our
1363 * precious DMA-able memory...
1364 */
1365 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1366#endif
1367}
1368
1369/*
1370 * Set up the device mappings. Since we clear out the page tables for all
1371 * mappings above VMALLOC_START, except early fixmap, we might remove debug
1372 * device mappings. This means earlycon can be used to debug this function
1373 * Any other function or debugging method which may touch any device _will_
1374 * crash the kernel.
1375 */
1376static void __init devicemaps_init(const struct machine_desc *mdesc)
1377{
1378 struct map_desc map;
1379 unsigned long addr;
1380 void *vectors;
1381
1382 /*
1383 * Allocate the vector page early.
1384 */
1385 vectors = early_alloc(PAGE_SIZE * 2);
1386
1387 early_trap_init(vectors);
1388
1389 /*
1390 * Clear page table except top pmd used by early fixmaps
1391 */
1392 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1393 pmd_clear(pmd_off_k(addr));
1394
1395 if (__atags_pointer) {
1396 /* create a read-only mapping of the device tree */
1397 map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK);
1398 map.virtual = FDT_FIXED_BASE;
1399 map.length = FDT_FIXED_SIZE;
1400 map.type = MT_MEMORY_RO;
1401 create_mapping(&map);
1402 }
1403
1404 /*
1405 * Map the kernel if it is XIP.
1406 * It is always first in the modulearea.
1407 */
1408#ifdef CONFIG_XIP_KERNEL
1409 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1410 map.virtual = MODULES_VADDR;
1411 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1412 map.type = MT_ROM;
1413 create_mapping(&map);
1414#endif
1415
1416 /*
1417 * Map the cache flushing regions.
1418 */
1419#ifdef FLUSH_BASE
1420 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1421 map.virtual = FLUSH_BASE;
1422 map.length = SZ_1M;
1423 map.type = MT_CACHECLEAN;
1424 create_mapping(&map);
1425#endif
1426#ifdef FLUSH_BASE_MINICACHE
1427 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1428 map.virtual = FLUSH_BASE_MINICACHE;
1429 map.length = SZ_1M;
1430 map.type = MT_MINICLEAN;
1431 create_mapping(&map);
1432#endif
1433
1434 /*
1435 * Create a mapping for the machine vectors at the high-vectors
1436 * location (0xffff0000). If we aren't using high-vectors, also
1437 * create a mapping at the low-vectors virtual address.
1438 */
1439 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1440 map.virtual = 0xffff0000;
1441 map.length = PAGE_SIZE;
1442#ifdef CONFIG_KUSER_HELPERS
1443 map.type = MT_HIGH_VECTORS;
1444#else
1445 map.type = MT_LOW_VECTORS;
1446#endif
1447 create_mapping(&map);
1448
1449 if (!vectors_high()) {
1450 map.virtual = 0;
1451 map.length = PAGE_SIZE * 2;
1452 map.type = MT_LOW_VECTORS;
1453 create_mapping(&map);
1454 }
1455
1456 /* Now create a kernel read-only mapping */
1457 map.pfn += 1;
1458 map.virtual = 0xffff0000 + PAGE_SIZE;
1459 map.length = PAGE_SIZE;
1460 map.type = MT_LOW_VECTORS;
1461 create_mapping(&map);
1462
1463 /*
1464 * Ask the machine support to map in the statically mapped devices.
1465 */
1466 if (mdesc->map_io)
1467 mdesc->map_io();
1468 else
1469 debug_ll_io_init();
1470 fill_pmd_gaps();
1471
1472 /* Reserve fixed i/o space in VMALLOC region */
1473 pci_reserve_io();
1474
1475 /*
1476 * Finally flush the caches and tlb to ensure that we're in a
1477 * consistent state wrt the writebuffer. This also ensures that
1478 * any write-allocated cache lines in the vector page are written
1479 * back. After this point, we can start to touch devices again.
1480 */
1481 local_flush_tlb_all();
1482 flush_cache_all();
1483
1484 /* Enable asynchronous aborts */
1485 early_abt_enable();
1486}
1487
1488static void __init kmap_init(void)
1489{
1490#ifdef CONFIG_HIGHMEM
1491 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1492 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1493#endif
1494
1495 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1496 _PAGE_KERNEL_TABLE);
1497}
1498
1499static void __init map_lowmem(void)
1500{
1501 phys_addr_t start, end;
1502 u64 i;
1503
1504 /* Map all the lowmem memory banks. */
1505 for_each_mem_range(i, &start, &end) {
1506 struct map_desc map;
1507
1508 pr_debug("map lowmem start: 0x%08llx, end: 0x%08llx\n",
1509 (long long)start, (long long)end);
1510 if (end > arm_lowmem_limit)
1511 end = arm_lowmem_limit;
1512 if (start >= end)
1513 break;
1514
1515 /*
1516 * If our kernel image is in the VMALLOC area we need to remove
1517 * the kernel physical memory from lowmem since the kernel will
1518 * be mapped separately.
1519 *
1520 * The kernel will typically be at the very start of lowmem,
1521 * but any placement relative to memory ranges is possible.
1522 *
1523 * If the memblock contains the kernel, we have to chisel out
1524 * the kernel memory from it and map each part separately. We
1525 * get 6 different theoretical cases:
1526 *
1527 * +--------+ +--------+
1528 * +-- start --+ +--------+ | Kernel | | Kernel |
1529 * | | | Kernel | | case 2 | | case 5 |
1530 * | | | case 1 | +--------+ | | +--------+
1531 * | Memory | +--------+ | | | Kernel |
1532 * | range | +--------+ | | | case 6 |
1533 * | | | Kernel | +--------+ | | +--------+
1534 * | | | case 3 | | Kernel | | |
1535 * +-- end ----+ +--------+ | case 4 | | |
1536 * +--------+ +--------+
1537 */
1538
1539 /* Case 5: kernel covers range, don't map anything, should be rare */
1540 if ((start > kernel_sec_start) && (end < kernel_sec_end))
1541 break;
1542
1543 /* Cases where the kernel is starting inside the range */
1544 if ((kernel_sec_start >= start) && (kernel_sec_start <= end)) {
1545 /* Case 6: kernel is embedded in the range, we need two mappings */
1546 if ((start < kernel_sec_start) && (end > kernel_sec_end)) {
1547 /* Map memory below the kernel */
1548 map.pfn = __phys_to_pfn(start);
1549 map.virtual = __phys_to_virt(start);
1550 map.length = kernel_sec_start - start;
1551 map.type = MT_MEMORY_RW;
1552 create_mapping(&map);
1553 /* Map memory above the kernel */
1554 map.pfn = __phys_to_pfn(kernel_sec_end);
1555 map.virtual = __phys_to_virt(kernel_sec_end);
1556 map.length = end - kernel_sec_end;
1557 map.type = MT_MEMORY_RW;
1558 create_mapping(&map);
1559 break;
1560 }
1561 /* Case 1: kernel and range start at the same address, should be common */
1562 if (kernel_sec_start == start)
1563 start = kernel_sec_end;
1564 /* Case 3: kernel and range end at the same address, should be rare */
1565 if (kernel_sec_end == end)
1566 end = kernel_sec_start;
1567 } else if ((kernel_sec_start < start) && (kernel_sec_end > start) && (kernel_sec_end < end)) {
1568 /* Case 2: kernel ends inside range, starts below it */
1569 start = kernel_sec_end;
1570 } else if ((kernel_sec_start > start) && (kernel_sec_start < end) && (kernel_sec_end > end)) {
1571 /* Case 4: kernel starts inside range, ends above it */
1572 end = kernel_sec_start;
1573 }
1574 map.pfn = __phys_to_pfn(start);
1575 map.virtual = __phys_to_virt(start);
1576 map.length = end - start;
1577 map.type = MT_MEMORY_RW;
1578 create_mapping(&map);
1579 }
1580}
1581
1582static void __init map_kernel(void)
1583{
1584 /*
1585 * We use the well known kernel section start and end and split the area in the
1586 * middle like this:
1587 * . .
1588 * | RW memory |
1589 * +----------------+ kernel_x_start
1590 * | Executable |
1591 * | kernel memory |
1592 * +----------------+ kernel_x_end / kernel_nx_start
1593 * | Non-executable |
1594 * | kernel memory |
1595 * +----------------+ kernel_nx_end
1596 * | RW memory |
1597 * . .
1598 *
1599 * Notice that we are dealing with section sized mappings here so all of this
1600 * will be bumped to the closest section boundary. This means that some of the
1601 * non-executable part of the kernel memory is actually mapped as executable.
1602 * This will only persist until we turn on proper memory management later on
1603 * and we remap the whole kernel with page granularity.
1604 */
1605 phys_addr_t kernel_x_start = kernel_sec_start;
1606 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1607 phys_addr_t kernel_nx_start = kernel_x_end;
1608 phys_addr_t kernel_nx_end = kernel_sec_end;
1609 struct map_desc map;
1610
1611 map.pfn = __phys_to_pfn(kernel_x_start);
1612 map.virtual = __phys_to_virt(kernel_x_start);
1613 map.length = kernel_x_end - kernel_x_start;
1614 map.type = MT_MEMORY_RWX;
1615 create_mapping(&map);
1616
1617 /* If the nx part is small it may end up covered by the tail of the RWX section */
1618 if (kernel_x_end == kernel_nx_end)
1619 return;
1620
1621 map.pfn = __phys_to_pfn(kernel_nx_start);
1622 map.virtual = __phys_to_virt(kernel_nx_start);
1623 map.length = kernel_nx_end - kernel_nx_start;
1624 map.type = MT_MEMORY_RW;
1625 create_mapping(&map);
1626}
1627
1628#ifdef CONFIG_ARM_PV_FIXUP
1629typedef void pgtables_remap(long long offset, unsigned long pgd);
1630pgtables_remap lpae_pgtables_remap_asm;
1631
1632/*
1633 * early_paging_init() recreates boot time page table setup, allowing machines
1634 * to switch over to a high (>4G) address space on LPAE systems
1635 */
1636static void __init early_paging_init(const struct machine_desc *mdesc)
1637{
1638 pgtables_remap *lpae_pgtables_remap;
1639 unsigned long pa_pgd;
1640 unsigned int cr, ttbcr;
1641 long long offset;
1642
1643 if (!mdesc->pv_fixup)
1644 return;
1645
1646 offset = mdesc->pv_fixup();
1647 if (offset == 0)
1648 return;
1649
1650 /*
1651 * Offset the kernel section physical offsets so that the kernel
1652 * mapping will work out later on.
1653 */
1654 kernel_sec_start += offset;
1655 kernel_sec_end += offset;
1656
1657 /*
1658 * Get the address of the remap function in the 1:1 identity
1659 * mapping setup by the early page table assembly code. We
1660 * must get this prior to the pv update. The following barrier
1661 * ensures that this is complete before we fixup any P:V offsets.
1662 */
1663 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1664 pa_pgd = __pa(swapper_pg_dir);
1665 barrier();
1666
1667 pr_info("Switching physical address space to 0x%08llx\n",
1668 (u64)PHYS_OFFSET + offset);
1669
1670 /* Re-set the phys pfn offset, and the pv offset */
1671 __pv_offset += offset;
1672 __pv_phys_pfn_offset += PFN_DOWN(offset);
1673
1674 /* Run the patch stub to update the constants */
1675 fixup_pv_table(&__pv_table_begin,
1676 (&__pv_table_end - &__pv_table_begin) << 2);
1677
1678 /*
1679 * We changing not only the virtual to physical mapping, but also
1680 * the physical addresses used to access memory. We need to flush
1681 * all levels of cache in the system with caching disabled to
1682 * ensure that all data is written back, and nothing is prefetched
1683 * into the caches. We also need to prevent the TLB walkers
1684 * allocating into the caches too. Note that this is ARMv7 LPAE
1685 * specific.
1686 */
1687 cr = get_cr();
1688 set_cr(cr & ~(CR_I | CR_C));
1689 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1690 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1691 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1692 flush_cache_all();
1693
1694 /*
1695 * Fixup the page tables - this must be in the idmap region as
1696 * we need to disable the MMU to do this safely, and hence it
1697 * needs to be assembly. It's fairly simple, as we're using the
1698 * temporary tables setup by the initial assembly code.
1699 */
1700 lpae_pgtables_remap(offset, pa_pgd);
1701
1702 /* Re-enable the caches and cacheable TLB walks */
1703 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1704 set_cr(cr);
1705}
1706
1707#else
1708
1709static void __init early_paging_init(const struct machine_desc *mdesc)
1710{
1711 long long offset;
1712
1713 if (!mdesc->pv_fixup)
1714 return;
1715
1716 offset = mdesc->pv_fixup();
1717 if (offset == 0)
1718 return;
1719
1720 pr_crit("Physical address space modification is only to support Keystone2.\n");
1721 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1722 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1723 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1724}
1725
1726#endif
1727
1728static void __init early_fixmap_shutdown(void)
1729{
1730 int i;
1731 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1732
1733 pte_offset_fixmap = pte_offset_late_fixmap;
1734 pmd_clear(fixmap_pmd(va));
1735 local_flush_tlb_kernel_page(va);
1736
1737 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1738 pte_t *pte;
1739 struct map_desc map;
1740
1741 map.virtual = fix_to_virt(i);
1742 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1743
1744 /* Only i/o device mappings are supported ATM */
1745 if (pte_none(*pte) ||
1746 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1747 continue;
1748
1749 map.pfn = pte_pfn(*pte);
1750 map.type = MT_DEVICE;
1751 map.length = PAGE_SIZE;
1752
1753 create_mapping(&map);
1754 }
1755}
1756
1757/*
1758 * paging_init() sets up the page tables, initialises the zone memory
1759 * maps, and sets up the zero page, bad page and bad page tables.
1760 */
1761void __init paging_init(const struct machine_desc *mdesc)
1762{
1763 void *zero_page;
1764
1765 pr_debug("physical kernel sections: 0x%08llx-0x%08llx\n",
1766 kernel_sec_start, kernel_sec_end);
1767
1768 prepare_page_table();
1769 map_lowmem();
1770 memblock_set_current_limit(arm_lowmem_limit);
1771 pr_debug("lowmem limit is %08llx\n", (long long)arm_lowmem_limit);
1772 /*
1773 * After this point early_alloc(), i.e. the memblock allocator, can
1774 * be used
1775 */
1776 map_kernel();
1777 dma_contiguous_remap();
1778 early_fixmap_shutdown();
1779 devicemaps_init(mdesc);
1780 kmap_init();
1781 tcm_init();
1782
1783 top_pmd = pmd_off_k(0xffff0000);
1784
1785 /* allocate the zero page. */
1786 zero_page = early_alloc(PAGE_SIZE);
1787
1788 bootmem_init();
1789
1790 empty_zero_page = virt_to_page(zero_page);
1791 __flush_dcache_page(NULL, empty_zero_page);
1792}
1793
1794void __init early_mm_init(const struct machine_desc *mdesc)
1795{
1796 build_mem_type_table();
1797 early_paging_init(mdesc);
1798}
1799
1800void set_pte_at(struct mm_struct *mm, unsigned long addr,
1801 pte_t *ptep, pte_t pteval)
1802{
1803 unsigned long ext = 0;
1804
1805 if (addr < TASK_SIZE && pte_valid_user(pteval)) {
1806 if (!pte_special(pteval))
1807 __sync_icache_dcache(pteval);
1808 ext |= PTE_EXT_NG;
1809 }
1810
1811 set_pte_ext(ptep, pteval, ext);
1812}