1#ifndef __ASMARM_SMP_TWD_H
 2#define __ASMARM_SMP_TWD_H
 3
 4#define TWD_TIMER_LOAD			0x00
 5#define TWD_TIMER_COUNTER		0x04
 6#define TWD_TIMER_CONTROL		0x08
 7#define TWD_TIMER_INTSTAT		0x0C
 8
 9#define TWD_WDOG_LOAD			0x20
10#define TWD_WDOG_COUNTER		0x24
11#define TWD_WDOG_CONTROL		0x28
12#define TWD_WDOG_INTSTAT		0x2C
13#define TWD_WDOG_RESETSTAT		0x30
14#define TWD_WDOG_DISABLE		0x34
15
16#define TWD_TIMER_CONTROL_ENABLE	(1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
20
21struct clock_event_device;
22
23extern void __iomem *twd_base;
24
25int twd_timer_ack(void);
26void twd_timer_setup(struct clock_event_device *);
27
28#endif

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __ASMARM_SMP_TWD_H
 3#define __ASMARM_SMP_TWD_H
 4
 5#define TWD_TIMER_LOAD			0x00
 6#define TWD_TIMER_COUNTER		0x04
 7#define TWD_TIMER_CONTROL		0x08
 8#define TWD_TIMER_INTSTAT		0x0C
 9
10#define TWD_WDOG_LOAD			0x20
11#define TWD_WDOG_COUNTER		0x24
12#define TWD_WDOG_CONTROL		0x28
13#define TWD_WDOG_INTSTAT		0x2C
14#define TWD_WDOG_RESETSTAT		0x30
15#define TWD_WDOG_DISABLE		0x34
16
17#define TWD_TIMER_CONTROL_ENABLE	(1 << 0)
18#define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)
19#define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
20#define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
 
 
 
 
 
 
 
21
22#endif