Loading...
1/*
2 * Freescale SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 * Copyright 2010 Freescale Semiconductor, Inc.
8 *
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/interrupt.h>
22#include <linux/delay.h>
23#include <linux/irq.h>
24#include <linux/spi/spi.h>
25#include <linux/spi/spi_bitbang.h>
26#include <linux/platform_device.h>
27#include <linux/fsl_devices.h>
28#include <linux/dma-mapping.h>
29#include <linux/mm.h>
30#include <linux/mutex.h>
31#include <linux/of.h>
32#include <linux/of_platform.h>
33#include <linux/gpio.h>
34#include <linux/of_gpio.h>
35
36#include <sysdev/fsl_soc.h>
37#include <asm/cpm.h>
38#include <asm/qe.h>
39
40#include "spi-fsl-lib.h"
41
42/* CPM1 and CPM2 are mutually exclusive. */
43#ifdef CONFIG_CPM1
44#include <asm/cpm1.h>
45#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
46#else
47#include <asm/cpm2.h>
48#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
49#endif
50
51/* SPI Controller registers */
52struct fsl_spi_reg {
53 u8 res1[0x20];
54 __be32 mode;
55 __be32 event;
56 __be32 mask;
57 __be32 command;
58 __be32 transmit;
59 __be32 receive;
60};
61
62/* SPI Controller mode register definitions */
63#define SPMODE_LOOP (1 << 30)
64#define SPMODE_CI_INACTIVEHIGH (1 << 29)
65#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
66#define SPMODE_DIV16 (1 << 27)
67#define SPMODE_REV (1 << 26)
68#define SPMODE_MS (1 << 25)
69#define SPMODE_ENABLE (1 << 24)
70#define SPMODE_LEN(x) ((x) << 20)
71#define SPMODE_PM(x) ((x) << 16)
72#define SPMODE_OP (1 << 14)
73#define SPMODE_CG(x) ((x) << 7)
74
75/*
76 * Default for SPI Mode:
77 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
78 */
79#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
80 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
81
82/* SPIE register values */
83#define SPIE_NE 0x00000200 /* Not empty */
84#define SPIE_NF 0x00000100 /* Not full */
85
86/* SPIM register values */
87#define SPIM_NE 0x00000200 /* Not empty */
88#define SPIM_NF 0x00000100 /* Not full */
89
90#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
91#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
92
93/* SPCOM register values */
94#define SPCOM_STR (1 << 23) /* Start transmit */
95
96#define SPI_PRAM_SIZE 0x100
97#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
98
99static void *fsl_dummy_rx;
100static DEFINE_MUTEX(fsl_dummy_rx_lock);
101static int fsl_dummy_rx_refcnt;
102
103static void fsl_spi_change_mode(struct spi_device *spi)
104{
105 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
106 struct spi_mpc8xxx_cs *cs = spi->controller_state;
107 struct fsl_spi_reg *reg_base = mspi->reg_base;
108 __be32 __iomem *mode = ®_base->mode;
109 unsigned long flags;
110
111 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
112 return;
113
114 /* Turn off IRQs locally to minimize time that SPI is disabled. */
115 local_irq_save(flags);
116
117 /* Turn off SPI unit prior changing mode */
118 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
119
120 /* When in CPM mode, we need to reinit tx and rx. */
121 if (mspi->flags & SPI_CPM_MODE) {
122 if (mspi->flags & SPI_QE) {
123 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
124 QE_CR_PROTOCOL_UNSPECIFIED, 0);
125 } else {
126 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
127 if (mspi->flags & SPI_CPM1) {
128 out_be16(&mspi->pram->rbptr,
129 in_be16(&mspi->pram->rbase));
130 out_be16(&mspi->pram->tbptr,
131 in_be16(&mspi->pram->tbase));
132 }
133 }
134 }
135 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
136 local_irq_restore(flags);
137}
138
139static void fsl_spi_chipselect(struct spi_device *spi, int value)
140{
141 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
142 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
143 bool pol = spi->mode & SPI_CS_HIGH;
144 struct spi_mpc8xxx_cs *cs = spi->controller_state;
145
146 if (value == BITBANG_CS_INACTIVE) {
147 if (pdata->cs_control)
148 pdata->cs_control(spi, !pol);
149 }
150
151 if (value == BITBANG_CS_ACTIVE) {
152 mpc8xxx_spi->rx_shift = cs->rx_shift;
153 mpc8xxx_spi->tx_shift = cs->tx_shift;
154 mpc8xxx_spi->get_rx = cs->get_rx;
155 mpc8xxx_spi->get_tx = cs->get_tx;
156
157 fsl_spi_change_mode(spi);
158
159 if (pdata->cs_control)
160 pdata->cs_control(spi, pol);
161 }
162}
163
164static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
165 struct spi_device *spi,
166 struct mpc8xxx_spi *mpc8xxx_spi,
167 int bits_per_word)
168{
169 cs->rx_shift = 0;
170 cs->tx_shift = 0;
171 if (bits_per_word <= 8) {
172 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
173 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
174 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
175 cs->rx_shift = 16;
176 cs->tx_shift = 24;
177 }
178 } else if (bits_per_word <= 16) {
179 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
180 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
181 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
182 cs->rx_shift = 16;
183 cs->tx_shift = 16;
184 }
185 } else if (bits_per_word <= 32) {
186 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
187 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
188 } else
189 return -EINVAL;
190
191 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
192 spi->mode & SPI_LSB_FIRST) {
193 cs->tx_shift = 0;
194 if (bits_per_word <= 8)
195 cs->rx_shift = 8;
196 else
197 cs->rx_shift = 0;
198 }
199 mpc8xxx_spi->rx_shift = cs->rx_shift;
200 mpc8xxx_spi->tx_shift = cs->tx_shift;
201 mpc8xxx_spi->get_rx = cs->get_rx;
202 mpc8xxx_spi->get_tx = cs->get_tx;
203
204 return bits_per_word;
205}
206
207static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
208 struct spi_device *spi,
209 int bits_per_word)
210{
211 /* QE uses Little Endian for words > 8
212 * so transform all words > 8 into 8 bits
213 * Unfortnatly that doesn't work for LSB so
214 * reject these for now */
215 /* Note: 32 bits word, LSB works iff
216 * tfcr/rfcr is set to CPMFCR_GBL */
217 if (spi->mode & SPI_LSB_FIRST &&
218 bits_per_word > 8)
219 return -EINVAL;
220 if (bits_per_word > 8)
221 return 8; /* pretend its 8 bits */
222 return bits_per_word;
223}
224
225static int fsl_spi_setup_transfer(struct spi_device *spi,
226 struct spi_transfer *t)
227{
228 struct mpc8xxx_spi *mpc8xxx_spi;
229 int bits_per_word = 0;
230 u8 pm;
231 u32 hz = 0;
232 struct spi_mpc8xxx_cs *cs = spi->controller_state;
233
234 mpc8xxx_spi = spi_master_get_devdata(spi->master);
235
236 if (t) {
237 bits_per_word = t->bits_per_word;
238 hz = t->speed_hz;
239 }
240
241 /* spi_transfer level calls that work per-word */
242 if (!bits_per_word)
243 bits_per_word = spi->bits_per_word;
244
245 /* Make sure its a bit width we support [4..16, 32] */
246 if ((bits_per_word < 4)
247 || ((bits_per_word > 16) && (bits_per_word != 32)))
248 return -EINVAL;
249
250 if (!hz)
251 hz = spi->max_speed_hz;
252
253 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
254 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
255 mpc8xxx_spi,
256 bits_per_word);
257 else if (mpc8xxx_spi->flags & SPI_QE)
258 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
259 bits_per_word);
260
261 if (bits_per_word < 0)
262 return bits_per_word;
263
264 if (bits_per_word == 32)
265 bits_per_word = 0;
266 else
267 bits_per_word = bits_per_word - 1;
268
269 /* mask out bits we are going to set */
270 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
271 | SPMODE_PM(0xF));
272
273 cs->hw_mode |= SPMODE_LEN(bits_per_word);
274
275 if ((mpc8xxx_spi->spibrg / hz) > 64) {
276 cs->hw_mode |= SPMODE_DIV16;
277 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
278
279 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
280 "Will use %d Hz instead.\n", dev_name(&spi->dev),
281 hz, mpc8xxx_spi->spibrg / 1024);
282 if (pm > 16)
283 pm = 16;
284 } else {
285 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
286 }
287 if (pm)
288 pm--;
289
290 cs->hw_mode |= SPMODE_PM(pm);
291
292 fsl_spi_change_mode(spi);
293 return 0;
294}
295
296static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
297{
298 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
299 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
300 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
301 unsigned int xfer_ofs;
302 struct fsl_spi_reg *reg_base = mspi->reg_base;
303
304 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
305
306 if (mspi->rx_dma == mspi->dma_dummy_rx)
307 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma);
308 else
309 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
310 out_be16(&rx_bd->cbd_datlen, 0);
311 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
312
313 if (mspi->tx_dma == mspi->dma_dummy_tx)
314 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma);
315 else
316 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
317 out_be16(&tx_bd->cbd_datlen, xfer_len);
318 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
319 BD_SC_LAST);
320
321 /* start transfer */
322 mpc8xxx_spi_write_reg(®_base->command, SPCOM_STR);
323}
324
325static int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
326 struct spi_transfer *t, bool is_dma_mapped)
327{
328 struct device *dev = mspi->dev;
329 struct fsl_spi_reg *reg_base = mspi->reg_base;
330
331 if (is_dma_mapped) {
332 mspi->map_tx_dma = 0;
333 mspi->map_rx_dma = 0;
334 } else {
335 mspi->map_tx_dma = 1;
336 mspi->map_rx_dma = 1;
337 }
338
339 if (!t->tx_buf) {
340 mspi->tx_dma = mspi->dma_dummy_tx;
341 mspi->map_tx_dma = 0;
342 }
343
344 if (!t->rx_buf) {
345 mspi->rx_dma = mspi->dma_dummy_rx;
346 mspi->map_rx_dma = 0;
347 }
348
349 if (mspi->map_tx_dma) {
350 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
351
352 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
353 DMA_TO_DEVICE);
354 if (dma_mapping_error(dev, mspi->tx_dma)) {
355 dev_err(dev, "unable to map tx dma\n");
356 return -ENOMEM;
357 }
358 } else if (t->tx_buf) {
359 mspi->tx_dma = t->tx_dma;
360 }
361
362 if (mspi->map_rx_dma) {
363 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
364 DMA_FROM_DEVICE);
365 if (dma_mapping_error(dev, mspi->rx_dma)) {
366 dev_err(dev, "unable to map rx dma\n");
367 goto err_rx_dma;
368 }
369 } else if (t->rx_buf) {
370 mspi->rx_dma = t->rx_dma;
371 }
372
373 /* enable rx ints */
374 mpc8xxx_spi_write_reg(®_base->mask, SPIE_RXB);
375
376 mspi->xfer_in_progress = t;
377 mspi->count = t->len;
378
379 /* start CPM transfers */
380 fsl_spi_cpm_bufs_start(mspi);
381
382 return 0;
383
384err_rx_dma:
385 if (mspi->map_tx_dma)
386 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
387 return -ENOMEM;
388}
389
390static void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
391{
392 struct device *dev = mspi->dev;
393 struct spi_transfer *t = mspi->xfer_in_progress;
394
395 if (mspi->map_tx_dma)
396 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
397 if (mspi->map_rx_dma)
398 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
399 mspi->xfer_in_progress = NULL;
400}
401
402static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
403 struct spi_transfer *t, unsigned int len)
404{
405 u32 word;
406 struct fsl_spi_reg *reg_base = mspi->reg_base;
407
408 mspi->count = len;
409
410 /* enable rx ints */
411 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
412
413 /* transmit word */
414 word = mspi->get_tx(mspi);
415 mpc8xxx_spi_write_reg(®_base->transmit, word);
416
417 return 0;
418}
419
420static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
421 bool is_dma_mapped)
422{
423 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
424 struct fsl_spi_reg *reg_base;
425 unsigned int len = t->len;
426 u8 bits_per_word;
427 int ret;
428
429 reg_base = mpc8xxx_spi->reg_base;
430 bits_per_word = spi->bits_per_word;
431 if (t->bits_per_word)
432 bits_per_word = t->bits_per_word;
433
434 if (bits_per_word > 8) {
435 /* invalid length? */
436 if (len & 1)
437 return -EINVAL;
438 len /= 2;
439 }
440 if (bits_per_word > 16) {
441 /* invalid length? */
442 if (len & 1)
443 return -EINVAL;
444 len /= 2;
445 }
446
447 mpc8xxx_spi->tx = t->tx_buf;
448 mpc8xxx_spi->rx = t->rx_buf;
449
450 INIT_COMPLETION(mpc8xxx_spi->done);
451
452 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
453 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
454 else
455 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
456 if (ret)
457 return ret;
458
459 wait_for_completion(&mpc8xxx_spi->done);
460
461 /* disable rx ints */
462 mpc8xxx_spi_write_reg(®_base->mask, 0);
463
464 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
465 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
466
467 return mpc8xxx_spi->count;
468}
469
470static void fsl_spi_do_one_msg(struct spi_message *m)
471{
472 struct spi_device *spi = m->spi;
473 struct spi_transfer *t;
474 unsigned int cs_change;
475 const int nsecs = 50;
476 int status;
477
478 cs_change = 1;
479 status = 0;
480 list_for_each_entry(t, &m->transfers, transfer_list) {
481 if (t->bits_per_word || t->speed_hz) {
482 /* Don't allow changes if CS is active */
483 status = -EINVAL;
484
485 if (cs_change)
486 status = fsl_spi_setup_transfer(spi, t);
487 if (status < 0)
488 break;
489 }
490
491 if (cs_change) {
492 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
493 ndelay(nsecs);
494 }
495 cs_change = t->cs_change;
496 if (t->len)
497 status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
498 if (status) {
499 status = -EMSGSIZE;
500 break;
501 }
502 m->actual_length += t->len;
503
504 if (t->delay_usecs)
505 udelay(t->delay_usecs);
506
507 if (cs_change) {
508 ndelay(nsecs);
509 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
510 ndelay(nsecs);
511 }
512 }
513
514 m->status = status;
515 m->complete(m->context);
516
517 if (status || !cs_change) {
518 ndelay(nsecs);
519 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
520 }
521
522 fsl_spi_setup_transfer(spi, NULL);
523}
524
525static int fsl_spi_setup(struct spi_device *spi)
526{
527 struct mpc8xxx_spi *mpc8xxx_spi;
528 struct fsl_spi_reg *reg_base;
529 int retval;
530 u32 hw_mode;
531 struct spi_mpc8xxx_cs *cs = spi->controller_state;
532
533 if (!spi->max_speed_hz)
534 return -EINVAL;
535
536 if (!cs) {
537 cs = kzalloc(sizeof *cs, GFP_KERNEL);
538 if (!cs)
539 return -ENOMEM;
540 spi->controller_state = cs;
541 }
542 mpc8xxx_spi = spi_master_get_devdata(spi->master);
543
544 reg_base = mpc8xxx_spi->reg_base;
545
546 hw_mode = cs->hw_mode; /* Save original settings */
547 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
548 /* mask out bits we are going to set */
549 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
550 | SPMODE_REV | SPMODE_LOOP);
551
552 if (spi->mode & SPI_CPHA)
553 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
554 if (spi->mode & SPI_CPOL)
555 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
556 if (!(spi->mode & SPI_LSB_FIRST))
557 cs->hw_mode |= SPMODE_REV;
558 if (spi->mode & SPI_LOOP)
559 cs->hw_mode |= SPMODE_LOOP;
560
561 retval = fsl_spi_setup_transfer(spi, NULL);
562 if (retval < 0) {
563 cs->hw_mode = hw_mode; /* Restore settings */
564 return retval;
565 }
566 return 0;
567}
568
569static void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
570{
571 u16 len;
572 struct fsl_spi_reg *reg_base = mspi->reg_base;
573
574 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
575 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
576
577 len = in_be16(&mspi->rx_bd->cbd_datlen);
578 if (len > mspi->count) {
579 WARN_ON(1);
580 len = mspi->count;
581 }
582
583 /* Clear the events */
584 mpc8xxx_spi_write_reg(®_base->event, events);
585
586 mspi->count -= len;
587 if (mspi->count)
588 fsl_spi_cpm_bufs_start(mspi);
589 else
590 complete(&mspi->done);
591}
592
593static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
594{
595 struct fsl_spi_reg *reg_base = mspi->reg_base;
596
597 /* We need handle RX first */
598 if (events & SPIE_NE) {
599 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
600
601 if (mspi->rx)
602 mspi->get_rx(rx_data, mspi);
603 }
604
605 if ((events & SPIE_NF) == 0)
606 /* spin until TX is done */
607 while (((events =
608 mpc8xxx_spi_read_reg(®_base->event)) &
609 SPIE_NF) == 0)
610 cpu_relax();
611
612 /* Clear the events */
613 mpc8xxx_spi_write_reg(®_base->event, events);
614
615 mspi->count -= 1;
616 if (mspi->count) {
617 u32 word = mspi->get_tx(mspi);
618
619 mpc8xxx_spi_write_reg(®_base->transmit, word);
620 } else {
621 complete(&mspi->done);
622 }
623}
624
625static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
626{
627 struct mpc8xxx_spi *mspi = context_data;
628 irqreturn_t ret = IRQ_NONE;
629 u32 events;
630 struct fsl_spi_reg *reg_base = mspi->reg_base;
631
632 /* Get interrupt events(tx/rx) */
633 events = mpc8xxx_spi_read_reg(®_base->event);
634 if (events)
635 ret = IRQ_HANDLED;
636
637 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
638
639 if (mspi->flags & SPI_CPM_MODE)
640 fsl_spi_cpm_irq(mspi, events);
641 else
642 fsl_spi_cpu_irq(mspi, events);
643
644 return ret;
645}
646
647static void *fsl_spi_alloc_dummy_rx(void)
648{
649 mutex_lock(&fsl_dummy_rx_lock);
650
651 if (!fsl_dummy_rx)
652 fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
653 if (fsl_dummy_rx)
654 fsl_dummy_rx_refcnt++;
655
656 mutex_unlock(&fsl_dummy_rx_lock);
657
658 return fsl_dummy_rx;
659}
660
661static void fsl_spi_free_dummy_rx(void)
662{
663 mutex_lock(&fsl_dummy_rx_lock);
664
665 switch (fsl_dummy_rx_refcnt) {
666 case 0:
667 WARN_ON(1);
668 break;
669 case 1:
670 kfree(fsl_dummy_rx);
671 fsl_dummy_rx = NULL;
672 /* fall through */
673 default:
674 fsl_dummy_rx_refcnt--;
675 break;
676 }
677
678 mutex_unlock(&fsl_dummy_rx_lock);
679}
680
681static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
682{
683 struct device *dev = mspi->dev;
684 struct device_node *np = dev->of_node;
685 const u32 *iprop;
686 int size;
687 void __iomem *spi_base;
688 unsigned long pram_ofs = -ENOMEM;
689
690 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
691 iprop = of_get_property(np, "reg", &size);
692
693 /* QE with a fixed pram location? */
694 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
695 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
696
697 /* QE but with a dynamic pram location? */
698 if (mspi->flags & SPI_QE) {
699 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
700 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
701 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
702 return pram_ofs;
703 }
704
705 spi_base = of_iomap(np, 1);
706 if (spi_base == NULL)
707 return -EINVAL;
708
709 if (mspi->flags & SPI_CPM2) {
710 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
711 out_be16(spi_base, pram_ofs);
712 } else {
713 struct spi_pram __iomem *pram = spi_base;
714 u16 rpbase = in_be16(&pram->rpbase);
715
716 /* Microcode relocation patch applied? */
717 if (rpbase)
718 pram_ofs = rpbase;
719 else {
720 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
721 out_be16(spi_base, pram_ofs);
722 }
723 }
724
725 iounmap(spi_base);
726 return pram_ofs;
727}
728
729static int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
730{
731 struct device *dev = mspi->dev;
732 struct device_node *np = dev->of_node;
733 const u32 *iprop;
734 int size;
735 unsigned long pram_ofs;
736 unsigned long bds_ofs;
737
738 if (!(mspi->flags & SPI_CPM_MODE))
739 return 0;
740
741 if (!fsl_spi_alloc_dummy_rx())
742 return -ENOMEM;
743
744 if (mspi->flags & SPI_QE) {
745 iprop = of_get_property(np, "cell-index", &size);
746 if (iprop && size == sizeof(*iprop))
747 mspi->subblock = *iprop;
748
749 switch (mspi->subblock) {
750 default:
751 dev_warn(dev, "cell-index unspecified, assuming SPI1");
752 /* fall through */
753 case 0:
754 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
755 break;
756 case 1:
757 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
758 break;
759 }
760 }
761
762 pram_ofs = fsl_spi_cpm_get_pram(mspi);
763 if (IS_ERR_VALUE(pram_ofs)) {
764 dev_err(dev, "can't allocate spi parameter ram\n");
765 goto err_pram;
766 }
767
768 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
769 sizeof(*mspi->rx_bd), 8);
770 if (IS_ERR_VALUE(bds_ofs)) {
771 dev_err(dev, "can't allocate bds\n");
772 goto err_bds;
773 }
774
775 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
776 DMA_TO_DEVICE);
777 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
778 dev_err(dev, "unable to map dummy tx buffer\n");
779 goto err_dummy_tx;
780 }
781
782 mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR,
783 DMA_FROM_DEVICE);
784 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
785 dev_err(dev, "unable to map dummy rx buffer\n");
786 goto err_dummy_rx;
787 }
788
789 mspi->pram = cpm_muram_addr(pram_ofs);
790
791 mspi->tx_bd = cpm_muram_addr(bds_ofs);
792 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
793
794 /* Initialize parameter ram. */
795 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
796 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
797 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
798 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
799 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
800 out_be32(&mspi->pram->rstate, 0);
801 out_be32(&mspi->pram->rdp, 0);
802 out_be16(&mspi->pram->rbptr, 0);
803 out_be16(&mspi->pram->rbc, 0);
804 out_be32(&mspi->pram->rxtmp, 0);
805 out_be32(&mspi->pram->tstate, 0);
806 out_be32(&mspi->pram->tdp, 0);
807 out_be16(&mspi->pram->tbptr, 0);
808 out_be16(&mspi->pram->tbc, 0);
809 out_be32(&mspi->pram->txtmp, 0);
810
811 return 0;
812
813err_dummy_rx:
814 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
815err_dummy_tx:
816 cpm_muram_free(bds_ofs);
817err_bds:
818 cpm_muram_free(pram_ofs);
819err_pram:
820 fsl_spi_free_dummy_rx();
821 return -ENOMEM;
822}
823
824static void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
825{
826 struct device *dev = mspi->dev;
827
828 if (!(mspi->flags & SPI_CPM_MODE))
829 return;
830
831 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
832 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
833 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
834 cpm_muram_free(cpm_muram_offset(mspi->pram));
835 fsl_spi_free_dummy_rx();
836}
837
838static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
839{
840 iounmap(mspi->reg_base);
841 fsl_spi_cpm_free(mspi);
842}
843
844static struct spi_master * __devinit fsl_spi_probe(struct device *dev,
845 struct resource *mem, unsigned int irq)
846{
847 struct fsl_spi_platform_data *pdata = dev->platform_data;
848 struct spi_master *master;
849 struct mpc8xxx_spi *mpc8xxx_spi;
850 struct fsl_spi_reg *reg_base;
851 u32 regval;
852 int ret = 0;
853
854 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
855 if (master == NULL) {
856 ret = -ENOMEM;
857 goto err;
858 }
859
860 dev_set_drvdata(dev, master);
861
862 ret = mpc8xxx_spi_probe(dev, mem, irq);
863 if (ret)
864 goto err_probe;
865
866 master->setup = fsl_spi_setup;
867
868 mpc8xxx_spi = spi_master_get_devdata(master);
869 mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
870 mpc8xxx_spi->spi_remove = fsl_spi_remove;
871
872
873 ret = fsl_spi_cpm_init(mpc8xxx_spi);
874 if (ret)
875 goto err_cpm_init;
876
877 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
878 mpc8xxx_spi->rx_shift = 16;
879 mpc8xxx_spi->tx_shift = 24;
880 }
881
882 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
883 if (mpc8xxx_spi->reg_base == NULL) {
884 ret = -ENOMEM;
885 goto err_ioremap;
886 }
887
888 /* Register for SPI Interrupt */
889 ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
890 0, "fsl_spi", mpc8xxx_spi);
891
892 if (ret != 0)
893 goto free_irq;
894
895 reg_base = mpc8xxx_spi->reg_base;
896
897 /* SPI controller initializations */
898 mpc8xxx_spi_write_reg(®_base->mode, 0);
899 mpc8xxx_spi_write_reg(®_base->mask, 0);
900 mpc8xxx_spi_write_reg(®_base->command, 0);
901 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
902
903 /* Enable SPI interface */
904 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
905 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
906 regval |= SPMODE_OP;
907
908 mpc8xxx_spi_write_reg(®_base->mode, regval);
909
910 ret = spi_register_master(master);
911 if (ret < 0)
912 goto unreg_master;
913
914 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
915 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
916
917 return master;
918
919unreg_master:
920 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
921free_irq:
922 iounmap(mpc8xxx_spi->reg_base);
923err_ioremap:
924 fsl_spi_cpm_free(mpc8xxx_spi);
925err_cpm_init:
926err_probe:
927 spi_master_put(master);
928err:
929 return ERR_PTR(ret);
930}
931
932static void fsl_spi_cs_control(struct spi_device *spi, bool on)
933{
934 struct device *dev = spi->dev.parent;
935 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
936 u16 cs = spi->chip_select;
937 int gpio = pinfo->gpios[cs];
938 bool alow = pinfo->alow_flags[cs];
939
940 gpio_set_value(gpio, on ^ alow);
941}
942
943static int of_fsl_spi_get_chipselects(struct device *dev)
944{
945 struct device_node *np = dev->of_node;
946 struct fsl_spi_platform_data *pdata = dev->platform_data;
947 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
948 unsigned int ngpios;
949 int i = 0;
950 int ret;
951
952 ngpios = of_gpio_count(np);
953 if (!ngpios) {
954 /*
955 * SPI w/o chip-select line. One SPI device is still permitted
956 * though.
957 */
958 pdata->max_chipselect = 1;
959 return 0;
960 }
961
962 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
963 if (!pinfo->gpios)
964 return -ENOMEM;
965 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
966
967 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
968 GFP_KERNEL);
969 if (!pinfo->alow_flags) {
970 ret = -ENOMEM;
971 goto err_alloc_flags;
972 }
973
974 for (; i < ngpios; i++) {
975 int gpio;
976 enum of_gpio_flags flags;
977
978 gpio = of_get_gpio_flags(np, i, &flags);
979 if (!gpio_is_valid(gpio)) {
980 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
981 ret = gpio;
982 goto err_loop;
983 }
984
985 ret = gpio_request(gpio, dev_name(dev));
986 if (ret) {
987 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
988 goto err_loop;
989 }
990
991 pinfo->gpios[i] = gpio;
992 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
993
994 ret = gpio_direction_output(pinfo->gpios[i],
995 pinfo->alow_flags[i]);
996 if (ret) {
997 dev_err(dev, "can't set output direction for gpio "
998 "#%d: %d\n", i, ret);
999 goto err_loop;
1000 }
1001 }
1002
1003 pdata->max_chipselect = ngpios;
1004 pdata->cs_control = fsl_spi_cs_control;
1005
1006 return 0;
1007
1008err_loop:
1009 while (i >= 0) {
1010 if (gpio_is_valid(pinfo->gpios[i]))
1011 gpio_free(pinfo->gpios[i]);
1012 i--;
1013 }
1014
1015 kfree(pinfo->alow_flags);
1016 pinfo->alow_flags = NULL;
1017err_alloc_flags:
1018 kfree(pinfo->gpios);
1019 pinfo->gpios = NULL;
1020 return ret;
1021}
1022
1023static int of_fsl_spi_free_chipselects(struct device *dev)
1024{
1025 struct fsl_spi_platform_data *pdata = dev->platform_data;
1026 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1027 int i;
1028
1029 if (!pinfo->gpios)
1030 return 0;
1031
1032 for (i = 0; i < pdata->max_chipselect; i++) {
1033 if (gpio_is_valid(pinfo->gpios[i]))
1034 gpio_free(pinfo->gpios[i]);
1035 }
1036
1037 kfree(pinfo->gpios);
1038 kfree(pinfo->alow_flags);
1039 return 0;
1040}
1041
1042static int __devinit of_fsl_spi_probe(struct platform_device *ofdev)
1043{
1044 struct device *dev = &ofdev->dev;
1045 struct device_node *np = ofdev->dev.of_node;
1046 struct spi_master *master;
1047 struct resource mem;
1048 struct resource irq;
1049 int ret = -ENOMEM;
1050
1051 ret = of_mpc8xxx_spi_probe(ofdev);
1052 if (ret)
1053 return ret;
1054
1055 ret = of_fsl_spi_get_chipselects(dev);
1056 if (ret)
1057 goto err;
1058
1059 ret = of_address_to_resource(np, 0, &mem);
1060 if (ret)
1061 goto err;
1062
1063 ret = of_irq_to_resource(np, 0, &irq);
1064 if (!ret) {
1065 ret = -EINVAL;
1066 goto err;
1067 }
1068
1069 master = fsl_spi_probe(dev, &mem, irq.start);
1070 if (IS_ERR(master)) {
1071 ret = PTR_ERR(master);
1072 goto err;
1073 }
1074
1075 return 0;
1076
1077err:
1078 of_fsl_spi_free_chipselects(dev);
1079 return ret;
1080}
1081
1082static int __devexit of_fsl_spi_remove(struct platform_device *ofdev)
1083{
1084 int ret;
1085
1086 ret = mpc8xxx_spi_remove(&ofdev->dev);
1087 if (ret)
1088 return ret;
1089 of_fsl_spi_free_chipselects(&ofdev->dev);
1090 return 0;
1091}
1092
1093static const struct of_device_id of_fsl_spi_match[] = {
1094 { .compatible = "fsl,spi" },
1095 {}
1096};
1097MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
1098
1099static struct platform_driver of_fsl_spi_driver = {
1100 .driver = {
1101 .name = "fsl_spi",
1102 .owner = THIS_MODULE,
1103 .of_match_table = of_fsl_spi_match,
1104 },
1105 .probe = of_fsl_spi_probe,
1106 .remove = __devexit_p(of_fsl_spi_remove),
1107};
1108
1109#ifdef CONFIG_MPC832x_RDB
1110/*
1111 * XXX XXX XXX
1112 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1113 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1114 * tree can work with OpenFirmware driver. But for now we support old trees
1115 * as well.
1116 */
1117static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1118{
1119 struct resource *mem;
1120 int irq;
1121 struct spi_master *master;
1122
1123 if (!pdev->dev.platform_data)
1124 return -EINVAL;
1125
1126 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1127 if (!mem)
1128 return -EINVAL;
1129
1130 irq = platform_get_irq(pdev, 0);
1131 if (irq <= 0)
1132 return -EINVAL;
1133
1134 master = fsl_spi_probe(&pdev->dev, mem, irq);
1135 if (IS_ERR(master))
1136 return PTR_ERR(master);
1137 return 0;
1138}
1139
1140static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1141{
1142 return mpc8xxx_spi_remove(&pdev->dev);
1143}
1144
1145MODULE_ALIAS("platform:mpc8xxx_spi");
1146static struct platform_driver mpc8xxx_spi_driver = {
1147 .probe = plat_mpc8xxx_spi_probe,
1148 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
1149 .driver = {
1150 .name = "mpc8xxx_spi",
1151 .owner = THIS_MODULE,
1152 },
1153};
1154
1155static bool legacy_driver_failed;
1156
1157static void __init legacy_driver_register(void)
1158{
1159 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1160}
1161
1162static void __exit legacy_driver_unregister(void)
1163{
1164 if (legacy_driver_failed)
1165 return;
1166 platform_driver_unregister(&mpc8xxx_spi_driver);
1167}
1168#else
1169static void __init legacy_driver_register(void) {}
1170static void __exit legacy_driver_unregister(void) {}
1171#endif /* CONFIG_MPC832x_RDB */
1172
1173static int __init fsl_spi_init(void)
1174{
1175 legacy_driver_register();
1176 return platform_driver_register(&of_fsl_spi_driver);
1177}
1178module_init(fsl_spi_init);
1179
1180static void __exit fsl_spi_exit(void)
1181{
1182 platform_driver_unregister(&of_fsl_spi_driver);
1183 legacy_driver_unregister();
1184}
1185module_exit(fsl_spi_exit);
1186
1187MODULE_AUTHOR("Kumar Gala");
1188MODULE_DESCRIPTION("Simple Freescale SPI Driver");
1189MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale SPI controller driver.
4 *
5 * Maintainer: Kumar Gala
6 *
7 * Copyright (C) 2006 Polycom, Inc.
8 * Copyright 2010 Freescale Semiconductor, Inc.
9 *
10 * CPM SPI and QE buffer descriptors mode support:
11 * Copyright (c) 2009 MontaVista Software, Inc.
12 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
13 *
14 * GRLIB support:
15 * Copyright (c) 2012 Aeroflex Gaisler AB.
16 * Author: Andreas Larsson <andreas@gaisler.com>
17 */
18#include <linux/delay.h>
19#include <linux/dma-mapping.h>
20#include <linux/fsl_devices.h>
21#include <linux/gpio/consumer.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/kernel.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/mutex.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/of_platform.h>
32#include <linux/platform_device.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
35#include <linux/types.h>
36
37#ifdef CONFIG_FSL_SOC
38#include <sysdev/fsl_soc.h>
39#endif
40
41/* Specific to the MPC8306/MPC8309 */
42#define IMMR_SPI_CS_OFFSET 0x14c
43#define SPI_BOOT_SEL_BIT 0x80000000
44
45#include "spi-fsl-lib.h"
46#include "spi-fsl-cpm.h"
47#include "spi-fsl-spi.h"
48
49#define TYPE_FSL 0
50#define TYPE_GRLIB 1
51
52struct fsl_spi_match_data {
53 int type;
54};
55
56static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
57 .type = TYPE_FSL,
58};
59
60static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
61 .type = TYPE_GRLIB,
62};
63
64static const struct of_device_id of_fsl_spi_match[] = {
65 {
66 .compatible = "fsl,spi",
67 .data = &of_fsl_spi_fsl_config,
68 },
69 {
70 .compatible = "aeroflexgaisler,spictrl",
71 .data = &of_fsl_spi_grlib_config,
72 },
73 {}
74};
75MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
76
77static int fsl_spi_get_type(struct device *dev)
78{
79 const struct of_device_id *match;
80
81 if (dev->of_node) {
82 match = of_match_node(of_fsl_spi_match, dev->of_node);
83 if (match && match->data)
84 return ((struct fsl_spi_match_data *)match->data)->type;
85 }
86 return TYPE_FSL;
87}
88
89static void fsl_spi_change_mode(struct spi_device *spi)
90{
91 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
92 struct spi_mpc8xxx_cs *cs = spi->controller_state;
93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
94 __be32 __iomem *mode = ®_base->mode;
95 unsigned long flags;
96
97 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
98 return;
99
100 /* Turn off IRQs locally to minimize time that SPI is disabled. */
101 local_irq_save(flags);
102
103 /* Turn off SPI unit prior changing mode */
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
105
106 /* When in CPM mode, we need to reinit tx and rx. */
107 if (mspi->flags & SPI_CPM_MODE) {
108 fsl_spi_cpm_reinit_txrx(mspi);
109 }
110 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
111 local_irq_restore(flags);
112}
113
114static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
115 int bits_per_word, int msb_first)
116{
117 *rx_shift = 0;
118 *tx_shift = 0;
119 if (msb_first) {
120 if (bits_per_word <= 8) {
121 *rx_shift = 16;
122 *tx_shift = 24;
123 } else if (bits_per_word <= 16) {
124 *rx_shift = 16;
125 *tx_shift = 16;
126 }
127 } else {
128 if (bits_per_word <= 8)
129 *rx_shift = 8;
130 }
131}
132
133static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
134 int bits_per_word, int msb_first)
135{
136 *rx_shift = 0;
137 *tx_shift = 0;
138 if (bits_per_word <= 16) {
139 if (msb_first) {
140 *rx_shift = 16; /* LSB in bit 16 */
141 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
142 } else {
143 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
144 }
145 }
146}
147
148static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
149 struct spi_device *spi,
150 struct mpc8xxx_spi *mpc8xxx_spi,
151 int bits_per_word)
152{
153 cs->rx_shift = 0;
154 cs->tx_shift = 0;
155 if (bits_per_word <= 8) {
156 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
157 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
158 } else if (bits_per_word <= 16) {
159 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
160 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
161 } else if (bits_per_word <= 32) {
162 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
163 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
164 } else
165 return -EINVAL;
166
167 if (mpc8xxx_spi->set_shifts)
168 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
169 bits_per_word,
170 !(spi->mode & SPI_LSB_FIRST));
171
172 mpc8xxx_spi->rx_shift = cs->rx_shift;
173 mpc8xxx_spi->tx_shift = cs->tx_shift;
174 mpc8xxx_spi->get_rx = cs->get_rx;
175 mpc8xxx_spi->get_tx = cs->get_tx;
176
177 return bits_per_word;
178}
179
180static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
181 struct spi_device *spi,
182 int bits_per_word)
183{
184 /* QE uses Little Endian for words > 8
185 * so transform all words > 8 into 8 bits
186 * Unfortnatly that doesn't work for LSB so
187 * reject these for now */
188 /* Note: 32 bits word, LSB works iff
189 * tfcr/rfcr is set to CPMFCR_GBL */
190 if (spi->mode & SPI_LSB_FIRST &&
191 bits_per_word > 8)
192 return -EINVAL;
193 if (bits_per_word > 8)
194 return 8; /* pretend its 8 bits */
195 return bits_per_word;
196}
197
198static int fsl_spi_setup_transfer(struct spi_device *spi,
199 struct spi_transfer *t)
200{
201 struct mpc8xxx_spi *mpc8xxx_spi;
202 int bits_per_word = 0;
203 u8 pm;
204 u32 hz = 0;
205 struct spi_mpc8xxx_cs *cs = spi->controller_state;
206
207 mpc8xxx_spi = spi_master_get_devdata(spi->master);
208
209 if (t) {
210 bits_per_word = t->bits_per_word;
211 hz = t->speed_hz;
212 }
213
214 /* spi_transfer level calls that work per-word */
215 if (!bits_per_word)
216 bits_per_word = spi->bits_per_word;
217
218 if (!hz)
219 hz = spi->max_speed_hz;
220
221 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
222 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
223 mpc8xxx_spi,
224 bits_per_word);
225 else if (mpc8xxx_spi->flags & SPI_QE)
226 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
227 bits_per_word);
228
229 if (bits_per_word < 0)
230 return bits_per_word;
231
232 if (bits_per_word == 32)
233 bits_per_word = 0;
234 else
235 bits_per_word = bits_per_word - 1;
236
237 /* mask out bits we are going to set */
238 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
239 | SPMODE_PM(0xF));
240
241 cs->hw_mode |= SPMODE_LEN(bits_per_word);
242
243 if ((mpc8xxx_spi->spibrg / hz) > 64) {
244 cs->hw_mode |= SPMODE_DIV16;
245 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
246 WARN_ONCE(pm > 16,
247 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
248 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
249 if (pm > 16)
250 pm = 16;
251 } else {
252 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
253 }
254 if (pm)
255 pm--;
256
257 cs->hw_mode |= SPMODE_PM(pm);
258
259 fsl_spi_change_mode(spi);
260 return 0;
261}
262
263static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
264 struct spi_transfer *t, unsigned int len)
265{
266 u32 word;
267 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
268
269 mspi->count = len;
270
271 /* enable rx ints */
272 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
273
274 /* transmit word */
275 word = mspi->get_tx(mspi);
276 mpc8xxx_spi_write_reg(®_base->transmit, word);
277
278 return 0;
279}
280
281static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
282 bool is_dma_mapped)
283{
284 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
285 struct fsl_spi_reg __iomem *reg_base;
286 unsigned int len = t->len;
287 u8 bits_per_word;
288 int ret;
289
290 reg_base = mpc8xxx_spi->reg_base;
291 bits_per_word = spi->bits_per_word;
292 if (t->bits_per_word)
293 bits_per_word = t->bits_per_word;
294
295 if (bits_per_word > 8) {
296 /* invalid length? */
297 if (len & 1)
298 return -EINVAL;
299 len /= 2;
300 }
301 if (bits_per_word > 16) {
302 /* invalid length? */
303 if (len & 1)
304 return -EINVAL;
305 len /= 2;
306 }
307
308 mpc8xxx_spi->tx = t->tx_buf;
309 mpc8xxx_spi->rx = t->rx_buf;
310
311 reinit_completion(&mpc8xxx_spi->done);
312
313 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
314 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
315 else
316 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
317 if (ret)
318 return ret;
319
320 wait_for_completion(&mpc8xxx_spi->done);
321
322 /* disable rx ints */
323 mpc8xxx_spi_write_reg(®_base->mask, 0);
324
325 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
326 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
327
328 return mpc8xxx_spi->count;
329}
330
331static int fsl_spi_prepare_message(struct spi_controller *ctlr,
332 struct spi_message *m)
333{
334 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
335 struct spi_transfer *t;
336 struct spi_transfer *first;
337
338 first = list_first_entry(&m->transfers, struct spi_transfer,
339 transfer_list);
340
341 /*
342 * In CPU mode, optimize large byte transfers to use larger
343 * bits_per_word values to reduce number of interrupts taken.
344 *
345 * Some glitches can appear on the SPI clock when the mode changes.
346 * Check that there is no speed change during the transfer and set it up
347 * now to change the mode without having a chip-select asserted.
348 */
349 list_for_each_entry(t, &m->transfers, transfer_list) {
350 if (t->speed_hz != first->speed_hz) {
351 dev_err(&m->spi->dev,
352 "speed_hz cannot change during message.\n");
353 return -EINVAL;
354 }
355 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
356 if (t->len < 256 || t->bits_per_word != 8)
357 continue;
358 if ((t->len & 3) == 0)
359 t->bits_per_word = 32;
360 else if ((t->len & 1) == 0)
361 t->bits_per_word = 16;
362 }
363 }
364 return fsl_spi_setup_transfer(m->spi, first);
365}
366
367static int fsl_spi_transfer_one(struct spi_controller *controller,
368 struct spi_device *spi,
369 struct spi_transfer *t)
370{
371 int status;
372
373 status = fsl_spi_setup_transfer(spi, t);
374 if (status < 0)
375 return status;
376 if (t->len)
377 status = fsl_spi_bufs(spi, t, !!t->tx_dma || !!t->rx_dma);
378 if (status > 0)
379 return -EMSGSIZE;
380
381 return status;
382}
383
384static int fsl_spi_unprepare_message(struct spi_controller *controller,
385 struct spi_message *msg)
386{
387 return fsl_spi_setup_transfer(msg->spi, NULL);
388}
389
390static int fsl_spi_setup(struct spi_device *spi)
391{
392 struct mpc8xxx_spi *mpc8xxx_spi;
393 struct fsl_spi_reg __iomem *reg_base;
394 bool initial_setup = false;
395 int retval;
396 u32 hw_mode;
397 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
398
399 if (!spi->max_speed_hz)
400 return -EINVAL;
401
402 if (!cs) {
403 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
404 if (!cs)
405 return -ENOMEM;
406 spi_set_ctldata(spi, cs);
407 initial_setup = true;
408 }
409 mpc8xxx_spi = spi_master_get_devdata(spi->master);
410
411 reg_base = mpc8xxx_spi->reg_base;
412
413 hw_mode = cs->hw_mode; /* Save original settings */
414 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
415 /* mask out bits we are going to set */
416 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
417 | SPMODE_REV | SPMODE_LOOP);
418
419 if (spi->mode & SPI_CPHA)
420 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
421 if (spi->mode & SPI_CPOL)
422 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
423 if (!(spi->mode & SPI_LSB_FIRST))
424 cs->hw_mode |= SPMODE_REV;
425 if (spi->mode & SPI_LOOP)
426 cs->hw_mode |= SPMODE_LOOP;
427
428 retval = fsl_spi_setup_transfer(spi, NULL);
429 if (retval < 0) {
430 cs->hw_mode = hw_mode; /* Restore settings */
431 if (initial_setup)
432 kfree(cs);
433 return retval;
434 }
435
436 return 0;
437}
438
439static void fsl_spi_cleanup(struct spi_device *spi)
440{
441 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
442
443 kfree(cs);
444 spi_set_ctldata(spi, NULL);
445}
446
447static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
448{
449 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
450
451 /* We need handle RX first */
452 if (events & SPIE_NE) {
453 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
454
455 if (mspi->rx)
456 mspi->get_rx(rx_data, mspi);
457 }
458
459 if ((events & SPIE_NF) == 0)
460 /* spin until TX is done */
461 while (((events =
462 mpc8xxx_spi_read_reg(®_base->event)) &
463 SPIE_NF) == 0)
464 cpu_relax();
465
466 /* Clear the events */
467 mpc8xxx_spi_write_reg(®_base->event, events);
468
469 mspi->count -= 1;
470 if (mspi->count) {
471 u32 word = mspi->get_tx(mspi);
472
473 mpc8xxx_spi_write_reg(®_base->transmit, word);
474 } else {
475 complete(&mspi->done);
476 }
477}
478
479static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
480{
481 struct mpc8xxx_spi *mspi = context_data;
482 irqreturn_t ret = IRQ_NONE;
483 u32 events;
484 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
485
486 /* Get interrupt events(tx/rx) */
487 events = mpc8xxx_spi_read_reg(®_base->event);
488 if (events)
489 ret = IRQ_HANDLED;
490
491 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
492
493 if (mspi->flags & SPI_CPM_MODE)
494 fsl_spi_cpm_irq(mspi, events);
495 else
496 fsl_spi_cpu_irq(mspi, events);
497
498 return ret;
499}
500
501static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
502{
503 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
504 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
505 u32 slvsel;
506 u16 cs = spi->chip_select;
507
508 if (cs < mpc8xxx_spi->native_chipselects) {
509 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
510 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
511 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
512 }
513}
514
515static void fsl_spi_grlib_probe(struct device *dev)
516{
517 struct spi_master *master = dev_get_drvdata(dev);
518 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
519 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
520 int mbits;
521 u32 capabilities;
522
523 capabilities = mpc8xxx_spi_read_reg(®_base->cap);
524
525 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
526 mbits = SPCAP_MAXWLEN(capabilities);
527 if (mbits)
528 mpc8xxx_spi->max_bits_per_word = mbits + 1;
529
530 mpc8xxx_spi->native_chipselects = 0;
531 if (SPCAP_SSEN(capabilities)) {
532 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
533 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
534 }
535 master->num_chipselect = mpc8xxx_spi->native_chipselects;
536 master->set_cs = fsl_spi_grlib_cs_control;
537}
538
539static void fsl_spi_cs_control(struct spi_device *spi, bool on)
540{
541 struct device *dev = spi->dev.parent->parent;
542 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
543 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
544
545 if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
546 return;
547 iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
548}
549
550static struct spi_master *fsl_spi_probe(struct device *dev,
551 struct resource *mem, unsigned int irq)
552{
553 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
554 struct spi_master *master;
555 struct mpc8xxx_spi *mpc8xxx_spi;
556 struct fsl_spi_reg __iomem *reg_base;
557 u32 regval;
558 int ret = 0;
559
560 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
561 if (master == NULL) {
562 ret = -ENOMEM;
563 goto err;
564 }
565
566 dev_set_drvdata(dev, master);
567
568 mpc8xxx_spi_probe(dev, mem, irq);
569
570 master->setup = fsl_spi_setup;
571 master->cleanup = fsl_spi_cleanup;
572 master->prepare_message = fsl_spi_prepare_message;
573 master->transfer_one = fsl_spi_transfer_one;
574 master->unprepare_message = fsl_spi_unprepare_message;
575 master->use_gpio_descriptors = true;
576 master->set_cs = fsl_spi_cs_control;
577
578 mpc8xxx_spi = spi_master_get_devdata(master);
579 mpc8xxx_spi->max_bits_per_word = 32;
580 mpc8xxx_spi->type = fsl_spi_get_type(dev);
581
582 ret = fsl_spi_cpm_init(mpc8xxx_spi);
583 if (ret)
584 goto err_cpm_init;
585
586 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
587 if (IS_ERR(mpc8xxx_spi->reg_base)) {
588 ret = PTR_ERR(mpc8xxx_spi->reg_base);
589 goto err_probe;
590 }
591
592 if (mpc8xxx_spi->type == TYPE_GRLIB)
593 fsl_spi_grlib_probe(dev);
594
595 master->bits_per_word_mask =
596 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
597 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
598
599 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
600 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
601
602 if (mpc8xxx_spi->set_shifts)
603 /* 8 bits per word and MSB first */
604 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
605 &mpc8xxx_spi->tx_shift, 8, 1);
606
607 /* Register for SPI Interrupt */
608 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
609 0, "fsl_spi", mpc8xxx_spi);
610
611 if (ret != 0)
612 goto err_probe;
613
614 reg_base = mpc8xxx_spi->reg_base;
615
616 /* SPI controller initializations */
617 mpc8xxx_spi_write_reg(®_base->mode, 0);
618 mpc8xxx_spi_write_reg(®_base->mask, 0);
619 mpc8xxx_spi_write_reg(®_base->command, 0);
620 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
621
622 /* Enable SPI interface */
623 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
624 if (mpc8xxx_spi->max_bits_per_word < 8) {
625 regval &= ~SPMODE_LEN(0xF);
626 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
627 }
628 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
629 regval |= SPMODE_OP;
630
631 mpc8xxx_spi_write_reg(®_base->mode, regval);
632
633 ret = devm_spi_register_master(dev, master);
634 if (ret < 0)
635 goto err_probe;
636
637 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
638 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
639
640 return master;
641
642err_probe:
643 fsl_spi_cpm_free(mpc8xxx_spi);
644err_cpm_init:
645 spi_master_put(master);
646err:
647 return ERR_PTR(ret);
648}
649
650static int of_fsl_spi_probe(struct platform_device *ofdev)
651{
652 struct device *dev = &ofdev->dev;
653 struct device_node *np = ofdev->dev.of_node;
654 struct spi_master *master;
655 struct resource mem;
656 int irq, type;
657 int ret;
658 bool spisel_boot = false;
659#if IS_ENABLED(CONFIG_FSL_SOC)
660 struct mpc8xxx_spi_probe_info *pinfo = NULL;
661#endif
662
663
664 ret = of_mpc8xxx_spi_probe(ofdev);
665 if (ret)
666 return ret;
667
668 type = fsl_spi_get_type(&ofdev->dev);
669 if (type == TYPE_FSL) {
670 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
671#if IS_ENABLED(CONFIG_FSL_SOC)
672 pinfo = to_of_pinfo(pdata);
673
674 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
675 if (spisel_boot) {
676 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
677 if (!pinfo->immr_spi_cs)
678 return -ENOMEM;
679 }
680#endif
681 /*
682 * Handle the case where we have one hardwired (always selected)
683 * device on the first "chipselect". Else we let the core code
684 * handle any GPIOs or native chip selects and assign the
685 * appropriate callback for dealing with the CS lines. This isn't
686 * supported on the GRLIB variant.
687 */
688 ret = gpiod_count(dev, "cs");
689 if (ret < 0)
690 ret = 0;
691 if (ret == 0 && !spisel_boot)
692 pdata->max_chipselect = 1;
693 else
694 pdata->max_chipselect = ret + spisel_boot;
695 }
696
697 ret = of_address_to_resource(np, 0, &mem);
698 if (ret)
699 goto unmap_out;
700
701 irq = platform_get_irq(ofdev, 0);
702 if (irq < 0) {
703 ret = irq;
704 goto unmap_out;
705 }
706
707 master = fsl_spi_probe(dev, &mem, irq);
708
709 return PTR_ERR_OR_ZERO(master);
710
711unmap_out:
712#if IS_ENABLED(CONFIG_FSL_SOC)
713 if (spisel_boot)
714 iounmap(pinfo->immr_spi_cs);
715#endif
716 return ret;
717}
718
719static int of_fsl_spi_remove(struct platform_device *ofdev)
720{
721 struct spi_master *master = platform_get_drvdata(ofdev);
722 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
723
724 fsl_spi_cpm_free(mpc8xxx_spi);
725 return 0;
726}
727
728static struct platform_driver of_fsl_spi_driver = {
729 .driver = {
730 .name = "fsl_spi",
731 .of_match_table = of_fsl_spi_match,
732 },
733 .probe = of_fsl_spi_probe,
734 .remove = of_fsl_spi_remove,
735};
736
737#ifdef CONFIG_MPC832x_RDB
738/*
739 * XXX XXX XXX
740 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
741 * only. The driver should go away soon, since newer MPC8323E-RDB's device
742 * tree can work with OpenFirmware driver. But for now we support old trees
743 * as well.
744 */
745static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
746{
747 struct resource *mem;
748 int irq;
749 struct spi_master *master;
750
751 if (!dev_get_platdata(&pdev->dev))
752 return -EINVAL;
753
754 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755 if (!mem)
756 return -EINVAL;
757
758 irq = platform_get_irq(pdev, 0);
759 if (irq <= 0)
760 return -EINVAL;
761
762 master = fsl_spi_probe(&pdev->dev, mem, irq);
763 return PTR_ERR_OR_ZERO(master);
764}
765
766static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
767{
768 struct spi_master *master = platform_get_drvdata(pdev);
769 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
770
771 fsl_spi_cpm_free(mpc8xxx_spi);
772
773 return 0;
774}
775
776MODULE_ALIAS("platform:mpc8xxx_spi");
777static struct platform_driver mpc8xxx_spi_driver = {
778 .probe = plat_mpc8xxx_spi_probe,
779 .remove = plat_mpc8xxx_spi_remove,
780 .driver = {
781 .name = "mpc8xxx_spi",
782 },
783};
784
785static bool legacy_driver_failed;
786
787static void __init legacy_driver_register(void)
788{
789 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
790}
791
792static void __exit legacy_driver_unregister(void)
793{
794 if (legacy_driver_failed)
795 return;
796 platform_driver_unregister(&mpc8xxx_spi_driver);
797}
798#else
799static void __init legacy_driver_register(void) {}
800static void __exit legacy_driver_unregister(void) {}
801#endif /* CONFIG_MPC832x_RDB */
802
803static int __init fsl_spi_init(void)
804{
805 legacy_driver_register();
806 return platform_driver_register(&of_fsl_spi_driver);
807}
808module_init(fsl_spi_init);
809
810static void __exit fsl_spi_exit(void)
811{
812 platform_driver_unregister(&of_fsl_spi_driver);
813 legacy_driver_unregister();
814}
815module_exit(fsl_spi_exit);
816
817MODULE_AUTHOR("Kumar Gala");
818MODULE_DESCRIPTION("Simple Freescale SPI Driver");
819MODULE_LICENSE("GPL");