1// SPDX-License-Identifier: GPL-2.0
   2/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
   3 * sungem.c: Sun GEM ethernet driver.
   4 *
   5 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
   6 *
   7 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
   8 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
   9 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
  10 *
  11 * NAPI and NETPOLL support
  12 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
  13 *
  14 */
  15
  16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17
  18#include <linux/module.h>
  19#include <linux/kernel.h>
  20#include <linux/types.h>
  21#include <linux/fcntl.h>
  22#include <linux/interrupt.h>
  23#include <linux/ioport.h>
  24#include <linux/in.h>
  25#include <linux/sched.h>
  26#include <linux/string.h>
  27#include <linux/delay.h>
  28#include <linux/errno.h>
  29#include <linux/pci.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/netdevice.h>
  32#include <linux/etherdevice.h>
  33#include <linux/skbuff.h>
  34#include <linux/mii.h>
  35#include <linux/ethtool.h>
  36#include <linux/crc32.h>
  37#include <linux/random.h>
  38#include <linux/workqueue.h>
  39#include <linux/if_vlan.h>
  40#include <linux/bitops.h>
  41#include <linux/mm.h>
  42#include <linux/gfp.h>
  43
  44#include <asm/io.h>
  45#include <asm/byteorder.h>
  46#include <linux/uaccess.h>
  47#include <asm/irq.h>
  48
  49#ifdef CONFIG_SPARC
  50#include <asm/idprom.h>
  51#include <asm/prom.h>
  52#endif
  53
  54#ifdef CONFIG_PPC_PMAC
  55#include <asm/machdep.h>
  56#include <asm/pmac_feature.h>
  57#endif
  58
  59#include <linux/sungem_phy.h>
  60#include "sungem.h"
  61
  62#define STRIP_FCS
  63
  64#define DEFAULT_MSG	(NETIF_MSG_DRV		| \
  65			 NETIF_MSG_PROBE	| \
  66			 NETIF_MSG_LINK)
  67
  68#define ADVERTISE_MASK	(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
  69			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
  70			 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
  71			 SUPPORTED_Pause | SUPPORTED_Autoneg)
  72
  73#define DRV_NAME	"sungem"
  74#define DRV_VERSION	"1.0"
  75#define DRV_AUTHOR	"David S. Miller <davem@redhat.com>"
  76
  77static char version[] =
  78        DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
  79
  80MODULE_AUTHOR(DRV_AUTHOR);
  81MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
  82MODULE_LICENSE("GPL");
  83
  84#define GEM_MODULE_NAME	"gem"
  85
  86static const struct pci_device_id gem_pci_tbl[] = {
  87	{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
  88	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  89
  90	/* These models only differ from the original GEM in
  91	 * that their tx/rx fifos are of a different size and
  92	 * they only support 10/100 speeds. -DaveM
  93	 *
  94	 * Apple's GMAC does support gigabit on machines with
  95	 * the BCM54xx PHYs. -BenH
  96	 */
  97	{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
  98	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  99	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
 100	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 101	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
 102	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 103	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
 104	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 105	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
 106	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 107	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
 108	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 109	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
 110	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 111	{0, }
 112};
 113
 114MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
 115
 116static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
 117{
 118	u32 cmd;
 119	int limit = 10000;
 120
 121	cmd  = (1 << 30);
 122	cmd |= (2 << 28);
 123	cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 124	cmd |= (reg << 18) & MIF_FRAME_REGAD;
 125	cmd |= (MIF_FRAME_TAMSB);
 126	writel(cmd, gp->regs + MIF_FRAME);
 127
 128	while (--limit) {
 129		cmd = readl(gp->regs + MIF_FRAME);
 130		if (cmd & MIF_FRAME_TALSB)
 131			break;
 132
 133		udelay(10);
 134	}
 135
 136	if (!limit)
 137		cmd = 0xffff;
 138
 139	return cmd & MIF_FRAME_DATA;
 140}
 141
 142static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
 143{
 144	struct gem *gp = netdev_priv(dev);
 145	return __sungem_phy_read(gp, mii_id, reg);
 146}
 147
 148static inline u16 sungem_phy_read(struct gem *gp, int reg)
 149{
 150	return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
 151}
 152
 153static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
 154{
 155	u32 cmd;
 156	int limit = 10000;
 157
 158	cmd  = (1 << 30);
 159	cmd |= (1 << 28);
 160	cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 161	cmd |= (reg << 18) & MIF_FRAME_REGAD;
 162	cmd |= (MIF_FRAME_TAMSB);
 163	cmd |= (val & MIF_FRAME_DATA);
 164	writel(cmd, gp->regs + MIF_FRAME);
 165
 166	while (limit--) {
 167		cmd = readl(gp->regs + MIF_FRAME);
 168		if (cmd & MIF_FRAME_TALSB)
 169			break;
 170
 171		udelay(10);
 172	}
 173}
 174
 175static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
 176{
 177	struct gem *gp = netdev_priv(dev);
 178	__sungem_phy_write(gp, mii_id, reg, val & 0xffff);
 179}
 180
 181static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
 182{
 183	__sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
 184}
 185
 186static inline void gem_enable_ints(struct gem *gp)
 187{
 188	/* Enable all interrupts but TXDONE */
 189	writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 190}
 191
 192static inline void gem_disable_ints(struct gem *gp)
 193{
 194	/* Disable all interrupts, including TXDONE */
 195	writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 196	(void)readl(gp->regs + GREG_IMASK); /* write posting */
 197}
 198
 199static void gem_get_cell(struct gem *gp)
 200{
 201	BUG_ON(gp->cell_enabled < 0);
 202	gp->cell_enabled++;
 203#ifdef CONFIG_PPC_PMAC
 204	if (gp->cell_enabled == 1) {
 205		mb();
 206		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
 207		udelay(10);
 208	}
 209#endif /* CONFIG_PPC_PMAC */
 210}
 211
 212/* Turn off the chip's clock */
 213static void gem_put_cell(struct gem *gp)
 214{
 215	BUG_ON(gp->cell_enabled <= 0);
 216	gp->cell_enabled--;
 217#ifdef CONFIG_PPC_PMAC
 218	if (gp->cell_enabled == 0) {
 219		mb();
 220		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
 221		udelay(10);
 222	}
 223#endif /* CONFIG_PPC_PMAC */
 224}
 225
 226static inline void gem_netif_stop(struct gem *gp)
 227{
 228	netif_trans_update(gp->dev);	/* prevent tx timeout */
 229	napi_disable(&gp->napi);
 230	netif_tx_disable(gp->dev);
 231}
 232
 233static inline void gem_netif_start(struct gem *gp)
 234{
 235	/* NOTE: unconditional netif_wake_queue is only
 236	 * appropriate so long as all callers are assured to
 237	 * have free tx slots.
 238	 */
 239	netif_wake_queue(gp->dev);
 240	napi_enable(&gp->napi);
 241}
 242
 243static void gem_schedule_reset(struct gem *gp)
 244{
 245	gp->reset_task_pending = 1;
 246	schedule_work(&gp->reset_task);
 247}
 248
 249static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
 250{
 251	if (netif_msg_intr(gp))
 252		printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
 253}
 254
 255static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 256{
 257	u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
 258	u32 pcs_miistat;
 259
 260	if (netif_msg_intr(gp))
 261		printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
 262			gp->dev->name, pcs_istat);
 263
 264	if (!(pcs_istat & PCS_ISTAT_LSC)) {
 265		netdev_err(dev, "PCS irq but no link status change???\n");
 266		return 0;
 267	}
 268
 269	/* The link status bit latches on zero, so you must
 270	 * read it twice in such a case to see a transition
 271	 * to the link being up.
 272	 */
 273	pcs_miistat = readl(gp->regs + PCS_MIISTAT);
 274	if (!(pcs_miistat & PCS_MIISTAT_LS))
 275		pcs_miistat |=
 276			(readl(gp->regs + PCS_MIISTAT) &
 277			 PCS_MIISTAT_LS);
 278
 279	if (pcs_miistat & PCS_MIISTAT_ANC) {
 280		/* The remote-fault indication is only valid
 281		 * when autoneg has completed.
 282		 */
 283		if (pcs_miistat & PCS_MIISTAT_RF)
 284			netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
 285		else
 286			netdev_info(dev, "PCS AutoNEG complete\n");
 287	}
 288
 289	if (pcs_miistat & PCS_MIISTAT_LS) {
 290		netdev_info(dev, "PCS link is now up\n");
 291		netif_carrier_on(gp->dev);
 292	} else {
 293		netdev_info(dev, "PCS link is now down\n");
 294		netif_carrier_off(gp->dev);
 295		/* If this happens and the link timer is not running,
 296		 * reset so we re-negotiate.
 297		 */
 298		if (!timer_pending(&gp->link_timer))
 299			return 1;
 300	}
 301
 302	return 0;
 303}
 304
 305static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 306{
 307	u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
 308
 309	if (netif_msg_intr(gp))
 310		printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
 311			gp->dev->name, txmac_stat);
 312
 313	/* Defer timer expiration is quite normal,
 314	 * don't even log the event.
 315	 */
 316	if ((txmac_stat & MAC_TXSTAT_DTE) &&
 317	    !(txmac_stat & ~MAC_TXSTAT_DTE))
 318		return 0;
 319
 320	if (txmac_stat & MAC_TXSTAT_URUN) {
 321		netdev_err(dev, "TX MAC xmit underrun\n");
 322		dev->stats.tx_fifo_errors++;
 323	}
 324
 325	if (txmac_stat & MAC_TXSTAT_MPE) {
 326		netdev_err(dev, "TX MAC max packet size error\n");
 327		dev->stats.tx_errors++;
 328	}
 329
 330	/* The rest are all cases of one of the 16-bit TX
 331	 * counters expiring.
 332	 */
 333	if (txmac_stat & MAC_TXSTAT_NCE)
 334		dev->stats.collisions += 0x10000;
 335
 336	if (txmac_stat & MAC_TXSTAT_ECE) {
 337		dev->stats.tx_aborted_errors += 0x10000;
 338		dev->stats.collisions += 0x10000;
 339	}
 340
 341	if (txmac_stat & MAC_TXSTAT_LCE) {
 342		dev->stats.tx_aborted_errors += 0x10000;
 343		dev->stats.collisions += 0x10000;
 344	}
 345
 346	/* We do not keep track of MAC_TXSTAT_FCE and
 347	 * MAC_TXSTAT_PCE events.
 348	 */
 349	return 0;
 350}
 351
 352/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
 353 * so we do the following.
 354 *
 355 * If any part of the reset goes wrong, we return 1 and that causes the
 356 * whole chip to be reset.
 357 */
 358static int gem_rxmac_reset(struct gem *gp)
 359{
 360	struct net_device *dev = gp->dev;
 361	int limit, i;
 362	u64 desc_dma;
 363	u32 val;
 364
 365	/* First, reset & disable MAC RX. */
 366	writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
 367	for (limit = 0; limit < 5000; limit++) {
 368		if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
 369			break;
 370		udelay(10);
 371	}
 372	if (limit == 5000) {
 373		netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
 374		return 1;
 375	}
 376
 377	writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
 378	       gp->regs + MAC_RXCFG);
 379	for (limit = 0; limit < 5000; limit++) {
 380		if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
 381			break;
 382		udelay(10);
 383	}
 384	if (limit == 5000) {
 385		netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
 386		return 1;
 387	}
 388
 389	/* Second, disable RX DMA. */
 390	writel(0, gp->regs + RXDMA_CFG);
 391	for (limit = 0; limit < 5000; limit++) {
 392		if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
 393			break;
 394		udelay(10);
 395	}
 396	if (limit == 5000) {
 397		netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
 398		return 1;
 399	}
 400
 401	mdelay(5);
 402
 403	/* Execute RX reset command. */
 404	writel(gp->swrst_base | GREG_SWRST_RXRST,
 405	       gp->regs + GREG_SWRST);
 406	for (limit = 0; limit < 5000; limit++) {
 407		if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
 408			break;
 409		udelay(10);
 410	}
 411	if (limit == 5000) {
 412		netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
 413		return 1;
 414	}
 415
 416	/* Refresh the RX ring. */
 417	for (i = 0; i < RX_RING_SIZE; i++) {
 418		struct gem_rxd *rxd = &gp->init_block->rxd[i];
 419
 420		if (gp->rx_skbs[i] == NULL) {
 421			netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
 422			return 1;
 423		}
 424
 425		rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 426	}
 427	gp->rx_new = gp->rx_old = 0;
 428
 429	/* Now we must reprogram the rest of RX unit. */
 430	desc_dma = (u64) gp->gblock_dvma;
 431	desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
 432	writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
 433	writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
 434	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
 435	val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
 436	       (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
 437	writel(val, gp->regs + RXDMA_CFG);
 438	if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
 439		writel(((5 & RXDMA_BLANK_IPKTS) |
 440			((8 << 12) & RXDMA_BLANK_ITIME)),
 441		       gp->regs + RXDMA_BLANK);
 442	else
 443		writel(((5 & RXDMA_BLANK_IPKTS) |
 444			((4 << 12) & RXDMA_BLANK_ITIME)),
 445		       gp->regs + RXDMA_BLANK);
 446	val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
 447	val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
 448	writel(val, gp->regs + RXDMA_PTHRESH);
 449	val = readl(gp->regs + RXDMA_CFG);
 450	writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
 451	writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
 452	val = readl(gp->regs + MAC_RXCFG);
 453	writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
 454
 455	return 0;
 456}
 457
 458static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 459{
 460	u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
 461	int ret = 0;
 462
 463	if (netif_msg_intr(gp))
 464		printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
 465			gp->dev->name, rxmac_stat);
 466
 467	if (rxmac_stat & MAC_RXSTAT_OFLW) {
 468		u32 smac = readl(gp->regs + MAC_SMACHINE);
 469
 470		netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
 471		dev->stats.rx_over_errors++;
 472		dev->stats.rx_fifo_errors++;
 473
 474		ret = gem_rxmac_reset(gp);
 475	}
 476
 477	if (rxmac_stat & MAC_RXSTAT_ACE)
 478		dev->stats.rx_frame_errors += 0x10000;
 479
 480	if (rxmac_stat & MAC_RXSTAT_CCE)
 481		dev->stats.rx_crc_errors += 0x10000;
 482
 483	if (rxmac_stat & MAC_RXSTAT_LCE)
 484		dev->stats.rx_length_errors += 0x10000;
 485
 486	/* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
 487	 * events.
 488	 */
 489	return ret;
 490}
 491
 492static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 493{
 494	u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
 495
 496	if (netif_msg_intr(gp))
 497		printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
 498			gp->dev->name, mac_cstat);
 499
 500	/* This interrupt is just for pause frame and pause
 501	 * tracking.  It is useful for diagnostics and debug
 502	 * but probably by default we will mask these events.
 503	 */
 504	if (mac_cstat & MAC_CSTAT_PS)
 505		gp->pause_entered++;
 506
 507	if (mac_cstat & MAC_CSTAT_PRCV)
 508		gp->pause_last_time_recvd = (mac_cstat >> 16);
 509
 510	return 0;
 511}
 512
 513static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 514{
 515	u32 mif_status = readl(gp->regs + MIF_STATUS);
 516	u32 reg_val, changed_bits;
 517
 518	reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
 519	changed_bits = (mif_status & MIF_STATUS_STAT);
 520
 521	gem_handle_mif_event(gp, reg_val, changed_bits);
 522
 523	return 0;
 524}
 525
 526static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 527{
 528	u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
 529
 530	if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
 531	    gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
 532		netdev_err(dev, "PCI error [%04x]", pci_estat);
 533
 534		if (pci_estat & GREG_PCIESTAT_BADACK)
 535			pr_cont(" <No ACK64# during ABS64 cycle>");
 536		if (pci_estat & GREG_PCIESTAT_DTRTO)
 537			pr_cont(" <Delayed transaction timeout>");
 538		if (pci_estat & GREG_PCIESTAT_OTHER)
 539			pr_cont(" <other>");
 540		pr_cont("\n");
 541	} else {
 542		pci_estat |= GREG_PCIESTAT_OTHER;
 543		netdev_err(dev, "PCI error\n");
 544	}
 545
 546	if (pci_estat & GREG_PCIESTAT_OTHER) {
 547		int pci_errs;
 548
 549		/* Interrogate PCI config space for the
 550		 * true cause.
 551		 */
 552		pci_errs = pci_status_get_and_clear_errors(gp->pdev);
 553		netdev_err(dev, "PCI status errors[%04x]\n", pci_errs);
 554		if (pci_errs & PCI_STATUS_PARITY)
 555			netdev_err(dev, "PCI parity error detected\n");
 556		if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT)
 557			netdev_err(dev, "PCI target abort\n");
 558		if (pci_errs & PCI_STATUS_REC_TARGET_ABORT)
 559			netdev_err(dev, "PCI master acks target abort\n");
 560		if (pci_errs & PCI_STATUS_REC_MASTER_ABORT)
 561			netdev_err(dev, "PCI master abort\n");
 562		if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR)
 563			netdev_err(dev, "PCI system error SERR#\n");
 564		if (pci_errs & PCI_STATUS_DETECTED_PARITY)
 565			netdev_err(dev, "PCI parity error\n");
 566	}
 567
 568	/* For all PCI errors, we should reset the chip. */
 569	return 1;
 570}
 571
 572/* All non-normal interrupt conditions get serviced here.
 573 * Returns non-zero if we should just exit the interrupt
 574 * handler right now (ie. if we reset the card which invalidates
 575 * all of the other original irq status bits).
 576 */
 577static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
 578{
 579	if (gem_status & GREG_STAT_RXNOBUF) {
 580		/* Frame arrived, no free RX buffers available. */
 581		if (netif_msg_rx_err(gp))
 582			printk(KERN_DEBUG "%s: no buffer for rx frame\n",
 583				gp->dev->name);
 584		dev->stats.rx_dropped++;
 585	}
 586
 587	if (gem_status & GREG_STAT_RXTAGERR) {
 588		/* corrupt RX tag framing */
 589		if (netif_msg_rx_err(gp))
 590			printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
 591				gp->dev->name);
 592		dev->stats.rx_errors++;
 593
 594		return 1;
 595	}
 596
 597	if (gem_status & GREG_STAT_PCS) {
 598		if (gem_pcs_interrupt(dev, gp, gem_status))
 599			return 1;
 600	}
 601
 602	if (gem_status & GREG_STAT_TXMAC) {
 603		if (gem_txmac_interrupt(dev, gp, gem_status))
 604			return 1;
 605	}
 606
 607	if (gem_status & GREG_STAT_RXMAC) {
 608		if (gem_rxmac_interrupt(dev, gp, gem_status))
 609			return 1;
 610	}
 611
 612	if (gem_status & GREG_STAT_MAC) {
 613		if (gem_mac_interrupt(dev, gp, gem_status))
 614			return 1;
 615	}
 616
 617	if (gem_status & GREG_STAT_MIF) {
 618		if (gem_mif_interrupt(dev, gp, gem_status))
 619			return 1;
 620	}
 621
 622	if (gem_status & GREG_STAT_PCIERR) {
 623		if (gem_pci_interrupt(dev, gp, gem_status))
 624			return 1;
 625	}
 626
 627	return 0;
 628}
 629
 630static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
 631{
 632	int entry, limit;
 633
 634	entry = gp->tx_old;
 635	limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
 636	while (entry != limit) {
 637		struct sk_buff *skb;
 638		struct gem_txd *txd;
 639		dma_addr_t dma_addr;
 640		u32 dma_len;
 641		int frag;
 642
 643		if (netif_msg_tx_done(gp))
 644			printk(KERN_DEBUG "%s: tx done, slot %d\n",
 645				gp->dev->name, entry);
 646		skb = gp->tx_skbs[entry];
 647		if (skb_shinfo(skb)->nr_frags) {
 648			int last = entry + skb_shinfo(skb)->nr_frags;
 649			int walk = entry;
 650			int incomplete = 0;
 651
 652			last &= (TX_RING_SIZE - 1);
 653			for (;;) {
 654				walk = NEXT_TX(walk);
 655				if (walk == limit)
 656					incomplete = 1;
 657				if (walk == last)
 658					break;
 659			}
 660			if (incomplete)
 661				break;
 662		}
 663		gp->tx_skbs[entry] = NULL;
 664		dev->stats.tx_bytes += skb->len;
 665
 666		for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
 667			txd = &gp->init_block->txd[entry];
 668
 669			dma_addr = le64_to_cpu(txd->buffer);
 670			dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
 671
 672			dma_unmap_page(&gp->pdev->dev, dma_addr, dma_len,
 673				       DMA_TO_DEVICE);
 674			entry = NEXT_TX(entry);
 675		}
 676
 677		dev->stats.tx_packets++;
 678		dev_consume_skb_any(skb);
 679	}
 680	gp->tx_old = entry;
 681
 682	/* Need to make the tx_old update visible to gem_start_xmit()
 683	 * before checking for netif_queue_stopped().  Without the
 684	 * memory barrier, there is a small possibility that gem_start_xmit()
 685	 * will miss it and cause the queue to be stopped forever.
 686	 */
 687	smp_mb();
 688
 689	if (unlikely(netif_queue_stopped(dev) &&
 690		     TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
 691		struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 692
 693		__netif_tx_lock(txq, smp_processor_id());
 694		if (netif_queue_stopped(dev) &&
 695		    TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
 696			netif_wake_queue(dev);
 697		__netif_tx_unlock(txq);
 698	}
 699}
 700
 701static __inline__ void gem_post_rxds(struct gem *gp, int limit)
 702{
 703	int cluster_start, curr, count, kick;
 704
 705	cluster_start = curr = (gp->rx_new & ~(4 - 1));
 706	count = 0;
 707	kick = -1;
 708	dma_wmb();
 709	while (curr != limit) {
 710		curr = NEXT_RX(curr);
 711		if (++count == 4) {
 712			struct gem_rxd *rxd =
 713				&gp->init_block->rxd[cluster_start];
 714			for (;;) {
 715				rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 716				rxd++;
 717				cluster_start = NEXT_RX(cluster_start);
 718				if (cluster_start == curr)
 719					break;
 720			}
 721			kick = curr;
 722			count = 0;
 723		}
 724	}
 725	if (kick >= 0) {
 726		mb();
 727		writel(kick, gp->regs + RXDMA_KICK);
 728	}
 729}
 730
 731#define ALIGNED_RX_SKB_ADDR(addr) \
 732        ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
 733static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
 734						gfp_t gfp_flags)
 735{
 736	struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
 737
 738	if (likely(skb)) {
 739		unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
 740		skb_reserve(skb, offset);
 741	}
 742	return skb;
 743}
 744
 745static int gem_rx(struct gem *gp, int work_to_do)
 746{
 747	struct net_device *dev = gp->dev;
 748	int entry, drops, work_done = 0;
 749	u32 done;
 750
 751	if (netif_msg_rx_status(gp))
 752		printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
 753			gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
 754
 755	entry = gp->rx_new;
 756	drops = 0;
 757	done = readl(gp->regs + RXDMA_DONE);
 758	for (;;) {
 759		struct gem_rxd *rxd = &gp->init_block->rxd[entry];
 760		struct sk_buff *skb;
 761		u64 status = le64_to_cpu(rxd->status_word);
 762		dma_addr_t dma_addr;
 763		int len;
 764
 765		if ((status & RXDCTRL_OWN) != 0)
 766			break;
 767
 768		if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
 769			break;
 770
 771		/* When writing back RX descriptor, GEM writes status
 772		 * then buffer address, possibly in separate transactions.
 773		 * If we don't wait for the chip to write both, we could
 774		 * post a new buffer to this descriptor then have GEM spam
 775		 * on the buffer address.  We sync on the RX completion
 776		 * register to prevent this from happening.
 777		 */
 778		if (entry == done) {
 779			done = readl(gp->regs + RXDMA_DONE);
 780			if (entry == done)
 781				break;
 782		}
 783
 784		/* We can now account for the work we're about to do */
 785		work_done++;
 786
 787		skb = gp->rx_skbs[entry];
 788
 789		len = (status & RXDCTRL_BUFSZ) >> 16;
 790		if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
 791			dev->stats.rx_errors++;
 792			if (len < ETH_ZLEN)
 793				dev->stats.rx_length_errors++;
 794			if (len & RXDCTRL_BAD)
 795				dev->stats.rx_crc_errors++;
 796
 797			/* We'll just return it to GEM. */
 798		drop_it:
 799			dev->stats.rx_dropped++;
 800			goto next;
 801		}
 802
 803		dma_addr = le64_to_cpu(rxd->buffer);
 804		if (len > RX_COPY_THRESHOLD) {
 805			struct sk_buff *new_skb;
 806
 807			new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
 808			if (new_skb == NULL) {
 809				drops++;
 810				goto drop_it;
 811			}
 812			dma_unmap_page(&gp->pdev->dev, dma_addr,
 813				       RX_BUF_ALLOC_SIZE(gp), DMA_FROM_DEVICE);
 814			gp->rx_skbs[entry] = new_skb;
 815			skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
 816			rxd->buffer = cpu_to_le64(dma_map_page(&gp->pdev->dev,
 817							       virt_to_page(new_skb->data),
 818							       offset_in_page(new_skb->data),
 819							       RX_BUF_ALLOC_SIZE(gp),
 820							       DMA_FROM_DEVICE));
 821			skb_reserve(new_skb, RX_OFFSET);
 822
 823			/* Trim the original skb for the netif. */
 824			skb_trim(skb, len);
 825		} else {
 826			struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
 827
 828			if (copy_skb == NULL) {
 829				drops++;
 830				goto drop_it;
 831			}
 832
 833			skb_reserve(copy_skb, 2);
 834			skb_put(copy_skb, len);
 835			dma_sync_single_for_cpu(&gp->pdev->dev, dma_addr, len,
 836						DMA_FROM_DEVICE);
 837			skb_copy_from_linear_data(skb, copy_skb->data, len);
 838			dma_sync_single_for_device(&gp->pdev->dev, dma_addr,
 839						   len, DMA_FROM_DEVICE);
 840
 841			/* We'll reuse the original ring buffer. */
 842			skb = copy_skb;
 843		}
 844
 845		if (likely(dev->features & NETIF_F_RXCSUM)) {
 846			__sum16 csum;
 847
 848			csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
 849			skb->csum = csum_unfold(csum);
 850			skb->ip_summed = CHECKSUM_COMPLETE;
 851		}
 852		skb->protocol = eth_type_trans(skb, gp->dev);
 853
 854		napi_gro_receive(&gp->napi, skb);
 855
 856		dev->stats.rx_packets++;
 857		dev->stats.rx_bytes += len;
 858
 859	next:
 860		entry = NEXT_RX(entry);
 861	}
 862
 863	gem_post_rxds(gp, entry);
 864
 865	gp->rx_new = entry;
 866
 867	if (drops)
 868		netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
 869
 870	return work_done;
 871}
 872
 873static int gem_poll(struct napi_struct *napi, int budget)
 874{
 875	struct gem *gp = container_of(napi, struct gem, napi);
 876	struct net_device *dev = gp->dev;
 877	int work_done;
 878
 879	work_done = 0;
 880	do {
 881		/* Handle anomalies */
 882		if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
 883			struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 884			int reset;
 885
 886			/* We run the abnormal interrupt handling code with
 887			 * the Tx lock. It only resets the Rx portion of the
 888			 * chip, but we need to guard it against DMA being
 889			 * restarted by the link poll timer
 890			 */
 891			__netif_tx_lock(txq, smp_processor_id());
 892			reset = gem_abnormal_irq(dev, gp, gp->status);
 893			__netif_tx_unlock(txq);
 894			if (reset) {
 895				gem_schedule_reset(gp);
 896				napi_complete(napi);
 897				return work_done;
 898			}
 899		}
 900
 901		/* Run TX completion thread */
 902		gem_tx(dev, gp, gp->status);
 903
 904		/* Run RX thread. We don't use any locking here,
 905		 * code willing to do bad things - like cleaning the
 906		 * rx ring - must call napi_disable(), which
 907		 * schedule_timeout()'s if polling is already disabled.
 908		 */
 909		work_done += gem_rx(gp, budget - work_done);
 910
 911		if (work_done >= budget)
 912			return work_done;
 913
 914		gp->status = readl(gp->regs + GREG_STAT);
 915	} while (gp->status & GREG_STAT_NAPI);
 916
 917	napi_complete_done(napi, work_done);
 918	gem_enable_ints(gp);
 919
 920	return work_done;
 921}
 922
 923static irqreturn_t gem_interrupt(int irq, void *dev_id)
 924{
 925	struct net_device *dev = dev_id;
 926	struct gem *gp = netdev_priv(dev);
 927
 928	if (napi_schedule_prep(&gp->napi)) {
 929		u32 gem_status = readl(gp->regs + GREG_STAT);
 930
 931		if (unlikely(gem_status == 0)) {
 932			napi_enable(&gp->napi);
 933			return IRQ_NONE;
 934		}
 935		if (netif_msg_intr(gp))
 936			printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
 937			       gp->dev->name, gem_status);
 938
 939		gp->status = gem_status;
 940		gem_disable_ints(gp);
 941		__napi_schedule(&gp->napi);
 942	}
 943
 944	/* If polling was disabled at the time we received that
 945	 * interrupt, we may return IRQ_HANDLED here while we
 946	 * should return IRQ_NONE. No big deal...
 947	 */
 948	return IRQ_HANDLED;
 949}
 950
 951#ifdef CONFIG_NET_POLL_CONTROLLER
 952static void gem_poll_controller(struct net_device *dev)
 953{
 954	struct gem *gp = netdev_priv(dev);
 955
 956	disable_irq(gp->pdev->irq);
 957	gem_interrupt(gp->pdev->irq, dev);
 958	enable_irq(gp->pdev->irq);
 959}
 960#endif
 961
 962static void gem_tx_timeout(struct net_device *dev, unsigned int txqueue)
 963{
 964	struct gem *gp = netdev_priv(dev);
 965
 966	netdev_err(dev, "transmit timed out, resetting\n");
 967
 968	netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
 969		   readl(gp->regs + TXDMA_CFG),
 970		   readl(gp->regs + MAC_TXSTAT),
 971		   readl(gp->regs + MAC_TXCFG));
 972	netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
 973		   readl(gp->regs + RXDMA_CFG),
 974		   readl(gp->regs + MAC_RXSTAT),
 975		   readl(gp->regs + MAC_RXCFG));
 976
 977	gem_schedule_reset(gp);
 978}
 979
 980static __inline__ int gem_intme(int entry)
 981{
 982	/* Algorithm: IRQ every 1/2 of descriptors. */
 983	if (!(entry & ((TX_RING_SIZE>>1)-1)))
 984		return 1;
 985
 986	return 0;
 987}
 988
 989static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
 990				  struct net_device *dev)
 991{
 992	struct gem *gp = netdev_priv(dev);
 993	int entry;
 994	u64 ctrl;
 995
 996	ctrl = 0;
 997	if (skb->ip_summed == CHECKSUM_PARTIAL) {
 998		const u64 csum_start_off = skb_checksum_start_offset(skb);
 999		const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1000
1001		ctrl = (TXDCTRL_CENAB |
1002			(csum_start_off << 15) |
1003			(csum_stuff_off << 21));
1004	}
1005
1006	if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1007		/* This is a hard error, log it. */
1008		if (!netif_queue_stopped(dev)) {
1009			netif_stop_queue(dev);
1010			netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1011		}
1012		return NETDEV_TX_BUSY;
1013	}
1014
1015	entry = gp->tx_new;
1016	gp->tx_skbs[entry] = skb;
1017
1018	if (skb_shinfo(skb)->nr_frags == 0) {
1019		struct gem_txd *txd = &gp->init_block->txd[entry];
1020		dma_addr_t mapping;
1021		u32 len;
1022
1023		len = skb->len;
1024		mapping = dma_map_page(&gp->pdev->dev,
1025				       virt_to_page(skb->data),
1026				       offset_in_page(skb->data),
1027				       len, DMA_TO_DEVICE);
1028		ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1029		if (gem_intme(entry))
1030			ctrl |= TXDCTRL_INTME;
1031		txd->buffer = cpu_to_le64(mapping);
1032		dma_wmb();
1033		txd->control_word = cpu_to_le64(ctrl);
1034		entry = NEXT_TX(entry);
1035	} else {
1036		struct gem_txd *txd;
1037		u32 first_len;
1038		u64 intme;
1039		dma_addr_t first_mapping;
1040		int frag, first_entry = entry;
1041
1042		intme = 0;
1043		if (gem_intme(entry))
1044			intme |= TXDCTRL_INTME;
1045
1046		/* We must give this initial chunk to the device last.
1047		 * Otherwise we could race with the device.
1048		 */
1049		first_len = skb_headlen(skb);
1050		first_mapping = dma_map_page(&gp->pdev->dev,
1051					     virt_to_page(skb->data),
1052					     offset_in_page(skb->data),
1053					     first_len, DMA_TO_DEVICE);
1054		entry = NEXT_TX(entry);
1055
1056		for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1057			const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1058			u32 len;
1059			dma_addr_t mapping;
1060			u64 this_ctrl;
1061
1062			len = skb_frag_size(this_frag);
1063			mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1064						   0, len, DMA_TO_DEVICE);
1065			this_ctrl = ctrl;
1066			if (frag == skb_shinfo(skb)->nr_frags - 1)
1067				this_ctrl |= TXDCTRL_EOF;
1068
1069			txd = &gp->init_block->txd[entry];
1070			txd->buffer = cpu_to_le64(mapping);
1071			dma_wmb();
1072			txd->control_word = cpu_to_le64(this_ctrl | len);
1073
1074			if (gem_intme(entry))
1075				intme |= TXDCTRL_INTME;
1076
1077			entry = NEXT_TX(entry);
1078		}
1079		txd = &gp->init_block->txd[first_entry];
1080		txd->buffer = cpu_to_le64(first_mapping);
1081		dma_wmb();
1082		txd->control_word =
1083			cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1084	}
1085
1086	gp->tx_new = entry;
1087	if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1088		netif_stop_queue(dev);
1089
1090		/* netif_stop_queue() must be done before checking
1091		 * tx index in TX_BUFFS_AVAIL() below, because
1092		 * in gem_tx(), we update tx_old before checking for
1093		 * netif_queue_stopped().
1094		 */
1095		smp_mb();
1096		if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1097			netif_wake_queue(dev);
1098	}
1099	if (netif_msg_tx_queued(gp))
1100		printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1101		       dev->name, entry, skb->len);
1102	mb();
1103	writel(gp->tx_new, gp->regs + TXDMA_KICK);
1104
1105	return NETDEV_TX_OK;
1106}
1107
1108static void gem_pcs_reset(struct gem *gp)
1109{
1110	int limit;
1111	u32 val;
1112
1113	/* Reset PCS unit. */
1114	val = readl(gp->regs + PCS_MIICTRL);
1115	val |= PCS_MIICTRL_RST;
1116	writel(val, gp->regs + PCS_MIICTRL);
1117
1118	limit = 32;
1119	while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1120		udelay(100);
1121		if (limit-- <= 0)
1122			break;
1123	}
1124	if (limit < 0)
1125		netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1126}
1127
1128static void gem_pcs_reinit_adv(struct gem *gp)
1129{
1130	u32 val;
1131
1132	/* Make sure PCS is disabled while changing advertisement
1133	 * configuration.
1134	 */
1135	val = readl(gp->regs + PCS_CFG);
1136	val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1137	writel(val, gp->regs + PCS_CFG);
1138
1139	/* Advertise all capabilities except asymmetric
1140	 * pause.
1141	 */
1142	val = readl(gp->regs + PCS_MIIADV);
1143	val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1144		PCS_MIIADV_SP | PCS_MIIADV_AP);
1145	writel(val, gp->regs + PCS_MIIADV);
1146
1147	/* Enable and restart auto-negotiation, disable wrapback/loopback,
1148	 * and re-enable PCS.
1149	 */
1150	val = readl(gp->regs + PCS_MIICTRL);
1151	val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1152	val &= ~PCS_MIICTRL_WB;
1153	writel(val, gp->regs + PCS_MIICTRL);
1154
1155	val = readl(gp->regs + PCS_CFG);
1156	val |= PCS_CFG_ENABLE;
1157	writel(val, gp->regs + PCS_CFG);
1158
1159	/* Make sure serialink loopback is off.  The meaning
1160	 * of this bit is logically inverted based upon whether
1161	 * you are in Serialink or SERDES mode.
1162	 */
1163	val = readl(gp->regs + PCS_SCTRL);
1164	if (gp->phy_type == phy_serialink)
1165		val &= ~PCS_SCTRL_LOOP;
1166	else
1167		val |= PCS_SCTRL_LOOP;
1168	writel(val, gp->regs + PCS_SCTRL);
1169}
1170
1171#define STOP_TRIES 32
1172
1173static void gem_reset(struct gem *gp)
1174{
1175	int limit;
1176	u32 val;
1177
1178	/* Make sure we won't get any more interrupts */
1179	writel(0xffffffff, gp->regs + GREG_IMASK);
1180
1181	/* Reset the chip */
1182	writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1183	       gp->regs + GREG_SWRST);
1184
1185	limit = STOP_TRIES;
1186
1187	do {
1188		udelay(20);
1189		val = readl(gp->regs + GREG_SWRST);
1190		if (limit-- <= 0)
1191			break;
1192	} while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1193
1194	if (limit < 0)
1195		netdev_err(gp->dev, "SW reset is ghetto\n");
1196
1197	if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1198		gem_pcs_reinit_adv(gp);
1199}
1200
1201static void gem_start_dma(struct gem *gp)
1202{
1203	u32 val;
1204
1205	/* We are ready to rock, turn everything on. */
1206	val = readl(gp->regs + TXDMA_CFG);
1207	writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1208	val = readl(gp->regs + RXDMA_CFG);
1209	writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1210	val = readl(gp->regs + MAC_TXCFG);
1211	writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1212	val = readl(gp->regs + MAC_RXCFG);
1213	writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1214
1215	(void) readl(gp->regs + MAC_RXCFG);
1216	udelay(100);
1217
1218	gem_enable_ints(gp);
1219
1220	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1221}
1222
1223/* DMA won't be actually stopped before about 4ms tho ...
1224 */
1225static void gem_stop_dma(struct gem *gp)
1226{
1227	u32 val;
1228
1229	/* We are done rocking, turn everything off. */
1230	val = readl(gp->regs + TXDMA_CFG);
1231	writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1232	val = readl(gp->regs + RXDMA_CFG);
1233	writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1234	val = readl(gp->regs + MAC_TXCFG);
1235	writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1236	val = readl(gp->regs + MAC_RXCFG);
1237	writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1238
1239	(void) readl(gp->regs + MAC_RXCFG);
1240
1241	/* Need to wait a bit ... done by the caller */
1242}
1243
1244
1245// XXX dbl check what that function should do when called on PCS PHY
1246static void gem_begin_auto_negotiation(struct gem *gp,
1247				       const struct ethtool_link_ksettings *ep)
1248{
1249	u32 advertise, features;
1250	int autoneg;
1251	int speed;
1252	int duplex;
1253	u32 advertising;
1254
1255	if (ep)
1256		ethtool_convert_link_mode_to_legacy_u32(
1257			&advertising, ep->link_modes.advertising);
1258
1259	if (gp->phy_type != phy_mii_mdio0 &&
1260	    gp->phy_type != phy_mii_mdio1)
1261		goto non_mii;
1262
1263	/* Setup advertise */
1264	if (found_mii_phy(gp))
1265		features = gp->phy_mii.def->features;
1266	else
1267		features = 0;
1268
1269	advertise = features & ADVERTISE_MASK;
1270	if (gp->phy_mii.advertising != 0)
1271		advertise &= gp->phy_mii.advertising;
1272
1273	autoneg = gp->want_autoneg;
1274	speed = gp->phy_mii.speed;
1275	duplex = gp->phy_mii.duplex;
1276
1277	/* Setup link parameters */
1278	if (!ep)
1279		goto start_aneg;
1280	if (ep->base.autoneg == AUTONEG_ENABLE) {
1281		advertise = advertising;
1282		autoneg = 1;
1283	} else {
1284		autoneg = 0;
1285		speed = ep->base.speed;
1286		duplex = ep->base.duplex;
1287	}
1288
1289start_aneg:
1290	/* Sanitize settings based on PHY capabilities */
1291	if ((features & SUPPORTED_Autoneg) == 0)
1292		autoneg = 0;
1293	if (speed == SPEED_1000 &&
1294	    !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1295		speed = SPEED_100;
1296	if (speed == SPEED_100 &&
1297	    !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1298		speed = SPEED_10;
1299	if (duplex == DUPLEX_FULL &&
1300	    !(features & (SUPPORTED_1000baseT_Full |
1301	    		  SUPPORTED_100baseT_Full |
1302	    		  SUPPORTED_10baseT_Full)))
1303	    	duplex = DUPLEX_HALF;
1304	if (speed == 0)
1305		speed = SPEED_10;
1306
1307	/* If we are asleep, we don't try to actually setup the PHY, we
1308	 * just store the settings
1309	 */
1310	if (!netif_device_present(gp->dev)) {
1311		gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1312		gp->phy_mii.speed = speed;
1313		gp->phy_mii.duplex = duplex;
1314		return;
1315	}
1316
1317	/* Configure PHY & start aneg */
1318	gp->want_autoneg = autoneg;
1319	if (autoneg) {
1320		if (found_mii_phy(gp))
1321			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1322		gp->lstate = link_aneg;
1323	} else {
1324		if (found_mii_phy(gp))
1325			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1326		gp->lstate = link_force_ok;
1327	}
1328
1329non_mii:
1330	gp->timer_ticks = 0;
1331	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1332}
1333
1334/* A link-up condition has occurred, initialize and enable the
1335 * rest of the chip.
1336 */
1337static int gem_set_link_modes(struct gem *gp)
1338{
1339	struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1340	int full_duplex, speed, pause;
1341	u32 val;
1342
1343	full_duplex = 0;
1344	speed = SPEED_10;
1345	pause = 0;
1346
1347	if (found_mii_phy(gp)) {
1348	    	if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1349	    		return 1;
1350		full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1351		speed = gp->phy_mii.speed;
1352		pause = gp->phy_mii.pause;
1353	} else if (gp->phy_type == phy_serialink ||
1354	    	   gp->phy_type == phy_serdes) {
1355		u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1356
1357		if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1358			full_duplex = 1;
1359		speed = SPEED_1000;
1360	}
1361
1362	netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1363		   speed, (full_duplex ? "full" : "half"));
1364
1365
1366	/* We take the tx queue lock to avoid collisions between
1367	 * this code, the tx path and the NAPI-driven error path
1368	 */
1369	__netif_tx_lock(txq, smp_processor_id());
1370
1371	val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1372	if (full_duplex) {
1373		val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1374	} else {
1375		/* MAC_TXCFG_NBO must be zero. */
1376	}
1377	writel(val, gp->regs + MAC_TXCFG);
1378
1379	val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1380	if (!full_duplex &&
1381	    (gp->phy_type == phy_mii_mdio0 ||
1382	     gp->phy_type == phy_mii_mdio1)) {
1383		val |= MAC_XIFCFG_DISE;
1384	} else if (full_duplex) {
1385		val |= MAC_XIFCFG_FLED;
1386	}
1387
1388	if (speed == SPEED_1000)
1389		val |= (MAC_XIFCFG_GMII);
1390
1391	writel(val, gp->regs + MAC_XIFCFG);
1392
1393	/* If gigabit and half-duplex, enable carrier extension
1394	 * mode.  Else, disable it.
1395	 */
1396	if (speed == SPEED_1000 && !full_duplex) {
1397		val = readl(gp->regs + MAC_TXCFG);
1398		writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1399
1400		val = readl(gp->regs + MAC_RXCFG);
1401		writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1402	} else {
1403		val = readl(gp->regs + MAC_TXCFG);
1404		writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1405
1406		val = readl(gp->regs + MAC_RXCFG);
1407		writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1408	}
1409
1410	if (gp->phy_type == phy_serialink ||
1411	    gp->phy_type == phy_serdes) {
1412		u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1413
1414		if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1415			pause = 1;
1416	}
1417
1418	if (!full_duplex)
1419		writel(512, gp->regs + MAC_STIME);
1420	else
1421		writel(64, gp->regs + MAC_STIME);
1422	val = readl(gp->regs + MAC_MCCFG);
1423	if (pause)
1424		val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1425	else
1426		val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1427	writel(val, gp->regs + MAC_MCCFG);
1428
1429	gem_start_dma(gp);
1430
1431	__netif_tx_unlock(txq);
1432
1433	if (netif_msg_link(gp)) {
1434		if (pause) {
1435			netdev_info(gp->dev,
1436				    "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1437				    gp->rx_fifo_sz,
1438				    gp->rx_pause_off,
1439				    gp->rx_pause_on);
1440		} else {
1441			netdev_info(gp->dev, "Pause is disabled\n");
1442		}
1443	}
1444
1445	return 0;
1446}
1447
1448static int gem_mdio_link_not_up(struct gem *gp)
1449{
1450	switch (gp->lstate) {
1451	case link_force_ret:
1452		netif_info(gp, link, gp->dev,
1453			   "Autoneg failed again, keeping forced mode\n");
1454		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1455			gp->last_forced_speed, DUPLEX_HALF);
1456		gp->timer_ticks = 5;
1457		gp->lstate = link_force_ok;
1458		return 0;
1459	case link_aneg:
1460		/* We try forced modes after a failed aneg only on PHYs that don't
1461		 * have "magic_aneg" bit set, which means they internally do the
1462		 * while forced-mode thingy. On these, we just restart aneg
1463		 */
1464		if (gp->phy_mii.def->magic_aneg)
1465			return 1;
1466		netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1467		/* Try forced modes. */
1468		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1469			DUPLEX_HALF);
1470		gp->timer_ticks = 5;
1471		gp->lstate = link_force_try;
1472		return 0;
1473	case link_force_try:
1474		/* Downgrade from 100 to 10 Mbps if necessary.
1475		 * If already at 10Mbps, warn user about the
1476		 * situation every 10 ticks.
1477		 */
1478		if (gp->phy_mii.speed == SPEED_100) {
1479			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1480				DUPLEX_HALF);
1481			gp->timer_ticks = 5;
1482			netif_info(gp, link, gp->dev,
1483				   "switching to forced 10bt\n");
1484			return 0;
1485		} else
1486			return 1;
1487	default:
1488		return 0;
1489	}
1490}
1491
1492static void gem_link_timer(struct timer_list *t)
1493{
1494	struct gem *gp = from_timer(gp, t, link_timer);
1495	struct net_device *dev = gp->dev;
1496	int restart_aneg = 0;
1497
1498	/* There's no point doing anything if we're going to be reset */
1499	if (gp->reset_task_pending)
1500		return;
1501
1502	if (gp->phy_type == phy_serialink ||
1503	    gp->phy_type == phy_serdes) {
1504		u32 val = readl(gp->regs + PCS_MIISTAT);
1505
1506		if (!(val & PCS_MIISTAT_LS))
1507			val = readl(gp->regs + PCS_MIISTAT);
1508
1509		if ((val & PCS_MIISTAT_LS) != 0) {
1510			if (gp->lstate == link_up)
1511				goto restart;
1512
1513			gp->lstate = link_up;
1514			netif_carrier_on(dev);
1515			(void)gem_set_link_modes(gp);
1516		}
1517		goto restart;
1518	}
1519	if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1520		/* Ok, here we got a link. If we had it due to a forced
1521		 * fallback, and we were configured for autoneg, we do
1522		 * retry a short autoneg pass. If you know your hub is
1523		 * broken, use ethtool ;)
1524		 */
1525		if (gp->lstate == link_force_try && gp->want_autoneg) {
1526			gp->lstate = link_force_ret;
1527			gp->last_forced_speed = gp->phy_mii.speed;
1528			gp->timer_ticks = 5;
1529			if (netif_msg_link(gp))
1530				netdev_info(dev,
1531					    "Got link after fallback, retrying autoneg once...\n");
1532			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1533		} else if (gp->lstate != link_up) {
1534			gp->lstate = link_up;
1535			netif_carrier_on(dev);
1536			if (gem_set_link_modes(gp))
1537				restart_aneg = 1;
1538		}
1539	} else {
1540		/* If the link was previously up, we restart the
1541		 * whole process
1542		 */
1543		if (gp->lstate == link_up) {
1544			gp->lstate = link_down;
1545			netif_info(gp, link, dev, "Link down\n");
1546			netif_carrier_off(dev);
1547			gem_schedule_reset(gp);
1548			/* The reset task will restart the timer */
1549			return;
1550		} else if (++gp->timer_ticks > 10) {
1551			if (found_mii_phy(gp))
1552				restart_aneg = gem_mdio_link_not_up(gp);
1553			else
1554				restart_aneg = 1;
1555		}
1556	}
1557	if (restart_aneg) {
1558		gem_begin_auto_negotiation(gp, NULL);
1559		return;
1560	}
1561restart:
1562	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1563}
1564
1565static void gem_clean_rings(struct gem *gp)
1566{
1567	struct gem_init_block *gb = gp->init_block;
1568	struct sk_buff *skb;
1569	int i;
1570	dma_addr_t dma_addr;
1571
1572	for (i = 0; i < RX_RING_SIZE; i++) {
1573		struct gem_rxd *rxd;
1574
1575		rxd = &gb->rxd[i];
1576		if (gp->rx_skbs[i] != NULL) {
1577			skb = gp->rx_skbs[i];
1578			dma_addr = le64_to_cpu(rxd->buffer);
1579			dma_unmap_page(&gp->pdev->dev, dma_addr,
1580				       RX_BUF_ALLOC_SIZE(gp),
1581				       DMA_FROM_DEVICE);
1582			dev_kfree_skb_any(skb);
1583			gp->rx_skbs[i] = NULL;
1584		}
1585		rxd->status_word = 0;
1586		dma_wmb();
1587		rxd->buffer = 0;
1588	}
1589
1590	for (i = 0; i < TX_RING_SIZE; i++) {
1591		if (gp->tx_skbs[i] != NULL) {
1592			struct gem_txd *txd;
1593			int frag;
1594
1595			skb = gp->tx_skbs[i];
1596			gp->tx_skbs[i] = NULL;
1597
1598			for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1599				int ent = i & (TX_RING_SIZE - 1);
1600
1601				txd = &gb->txd[ent];
1602				dma_addr = le64_to_cpu(txd->buffer);
1603				dma_unmap_page(&gp->pdev->dev, dma_addr,
1604					       le64_to_cpu(txd->control_word) &
1605					       TXDCTRL_BUFSZ, DMA_TO_DEVICE);
1606
1607				if (frag != skb_shinfo(skb)->nr_frags)
1608					i++;
1609			}
1610			dev_kfree_skb_any(skb);
1611		}
1612	}
1613}
1614
1615static void gem_init_rings(struct gem *gp)
1616{
1617	struct gem_init_block *gb = gp->init_block;
1618	struct net_device *dev = gp->dev;
1619	int i;
1620	dma_addr_t dma_addr;
1621
1622	gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1623
1624	gem_clean_rings(gp);
1625
1626	gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1627			    (unsigned)VLAN_ETH_FRAME_LEN);
1628
1629	for (i = 0; i < RX_RING_SIZE; i++) {
1630		struct sk_buff *skb;
1631		struct gem_rxd *rxd = &gb->rxd[i];
1632
1633		skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1634		if (!skb) {
1635			rxd->buffer = 0;
1636			rxd->status_word = 0;
1637			continue;
1638		}
1639
1640		gp->rx_skbs[i] = skb;
1641		skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1642		dma_addr = dma_map_page(&gp->pdev->dev,
1643					virt_to_page(skb->data),
1644					offset_in_page(skb->data),
1645					RX_BUF_ALLOC_SIZE(gp),
1646					DMA_FROM_DEVICE);
1647		rxd->buffer = cpu_to_le64(dma_addr);
1648		dma_wmb();
1649		rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1650		skb_reserve(skb, RX_OFFSET);
1651	}
1652
1653	for (i = 0; i < TX_RING_SIZE; i++) {
1654		struct gem_txd *txd = &gb->txd[i];
1655
1656		txd->control_word = 0;
1657		dma_wmb();
1658		txd->buffer = 0;
1659	}
1660	wmb();
1661}
1662
1663/* Init PHY interface and start link poll state machine */
1664static void gem_init_phy(struct gem *gp)
1665{
1666	u32 mifcfg;
1667
1668	/* Revert MIF CFG setting done on stop_phy */
1669	mifcfg = readl(gp->regs + MIF_CFG);
1670	mifcfg &= ~MIF_CFG_BBMODE;
1671	writel(mifcfg, gp->regs + MIF_CFG);
1672
1673	if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1674		int i;
1675
1676		/* Those delays sucks, the HW seems to love them though, I'll
1677		 * seriously consider breaking some locks here to be able
1678		 * to schedule instead
1679		 */
1680		for (i = 0; i < 3; i++) {
1681#ifdef CONFIG_PPC_PMAC
1682			pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1683			msleep(20);
1684#endif
1685			/* Some PHYs used by apple have problem getting back to us,
1686			 * we do an additional reset here
1687			 */
1688			sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1689			msleep(20);
1690			if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1691				break;
1692			if (i == 2)
1693				netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1694		}
1695	}
1696
1697	if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1698	    gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1699		u32 val;
1700
1701		/* Init datapath mode register. */
1702		if (gp->phy_type == phy_mii_mdio0 ||
1703		    gp->phy_type == phy_mii_mdio1) {
1704			val = PCS_DMODE_MGM;
1705		} else if (gp->phy_type == phy_serialink) {
1706			val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1707		} else {
1708			val = PCS_DMODE_ESM;
1709		}
1710
1711		writel(val, gp->regs + PCS_DMODE);
1712	}
1713
1714	if (gp->phy_type == phy_mii_mdio0 ||
1715	    gp->phy_type == phy_mii_mdio1) {
1716		/* Reset and detect MII PHY */
1717		sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1718
1719		/* Init PHY */
1720		if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1721			gp->phy_mii.def->ops->init(&gp->phy_mii);
1722	} else {
1723		gem_pcs_reset(gp);
1724		gem_pcs_reinit_adv(gp);
1725	}
1726
1727	/* Default aneg parameters */
1728	gp->timer_ticks = 0;
1729	gp->lstate = link_down;
1730	netif_carrier_off(gp->dev);
1731
1732	/* Print things out */
1733	if (gp->phy_type == phy_mii_mdio0 ||
1734	    gp->phy_type == phy_mii_mdio1)
1735		netdev_info(gp->dev, "Found %s PHY\n",
1736			    gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1737
1738	gem_begin_auto_negotiation(gp, NULL);
1739}
1740
1741static void gem_init_dma(struct gem *gp)
1742{
1743	u64 desc_dma = (u64) gp->gblock_dvma;
1744	u32 val;
1745
1746	val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1747	writel(val, gp->regs + TXDMA_CFG);
1748
1749	writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1750	writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1751	desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1752
1753	writel(0, gp->regs + TXDMA_KICK);
1754
1755	val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1756	       (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
1757	writel(val, gp->regs + RXDMA_CFG);
1758
1759	writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1760	writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1761
1762	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1763
1764	val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1765	val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1766	writel(val, gp->regs + RXDMA_PTHRESH);
1767
1768	if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1769		writel(((5 & RXDMA_BLANK_IPKTS) |
1770			((8 << 12) & RXDMA_BLANK_ITIME)),
1771		       gp->regs + RXDMA_BLANK);
1772	else
1773		writel(((5 & RXDMA_BLANK_IPKTS) |
1774			((4 << 12) & RXDMA_BLANK_ITIME)),
1775		       gp->regs + RXDMA_BLANK);
1776}
1777
1778static u32 gem_setup_multicast(struct gem *gp)
1779{
1780	u32 rxcfg = 0;
1781	int i;
1782
1783	if ((gp->dev->flags & IFF_ALLMULTI) ||
1784	    (netdev_mc_count(gp->dev) > 256)) {
1785	    	for (i=0; i<16; i++)
1786			writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1787		rxcfg |= MAC_RXCFG_HFE;
1788	} else if (gp->dev->flags & IFF_PROMISC) {
1789		rxcfg |= MAC_RXCFG_PROM;
1790	} else {
1791		u16 hash_table[16];
1792		u32 crc;
1793		struct netdev_hw_addr *ha;
1794		int i;
1795
1796		memset(hash_table, 0, sizeof(hash_table));
1797		netdev_for_each_mc_addr(ha, gp->dev) {
1798			crc = ether_crc_le(6, ha->addr);
1799			crc >>= 24;
1800			hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1801		}
1802	    	for (i=0; i<16; i++)
1803			writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1804		rxcfg |= MAC_RXCFG_HFE;
1805	}
1806
1807	return rxcfg;
1808}
1809
1810static void gem_init_mac(struct gem *gp)
1811{
1812	const unsigned char *e = &gp->dev->dev_addr[0];
1813
1814	writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1815
1816	writel(0x00, gp->regs + MAC_IPG0);
1817	writel(0x08, gp->regs + MAC_IPG1);
1818	writel(0x04, gp->regs + MAC_IPG2);
1819	writel(0x40, gp->regs + MAC_STIME);
1820	writel(0x40, gp->regs + MAC_MINFSZ);
1821
1822	/* Ethernet payload + header + FCS + optional VLAN tag. */
1823	writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1824
1825	writel(0x07, gp->regs + MAC_PASIZE);
1826	writel(0x04, gp->regs + MAC_JAMSIZE);
1827	writel(0x10, gp->regs + MAC_ATTLIM);
1828	writel(0x8808, gp->regs + MAC_MCTYPE);
1829
1830	writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1831
1832	writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1833	writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1834	writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1835
1836	writel(0, gp->regs + MAC_ADDR3);
1837	writel(0, gp->regs + MAC_ADDR4);
1838	writel(0, gp->regs + MAC_ADDR5);
1839
1840	writel(0x0001, gp->regs + MAC_ADDR6);
1841	writel(0xc200, gp->regs + MAC_ADDR7);
1842	writel(0x0180, gp->regs + MAC_ADDR8);
1843
1844	writel(0, gp->regs + MAC_AFILT0);
1845	writel(0, gp->regs + MAC_AFILT1);
1846	writel(0, gp->regs + MAC_AFILT2);
1847	writel(0, gp->regs + MAC_AF21MSK);
1848	writel(0, gp->regs + MAC_AF0MSK);
1849
1850	gp->mac_rx_cfg = gem_setup_multicast(gp);
1851#ifdef STRIP_FCS
1852	gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1853#endif
1854	writel(0, gp->regs + MAC_NCOLL);
1855	writel(0, gp->regs + MAC_FASUCC);
1856	writel(0, gp->regs + MAC_ECOLL);
1857	writel(0, gp->regs + MAC_LCOLL);
1858	writel(0, gp->regs + MAC_DTIMER);
1859	writel(0, gp->regs + MAC_PATMPS);
1860	writel(0, gp->regs + MAC_RFCTR);
1861	writel(0, gp->regs + MAC_LERR);
1862	writel(0, gp->regs + MAC_AERR);
1863	writel(0, gp->regs + MAC_FCSERR);
1864	writel(0, gp->regs + MAC_RXCVERR);
1865
1866	/* Clear RX/TX/MAC/XIF config, we will set these up and enable
1867	 * them once a link is established.
1868	 */
1869	writel(0, gp->regs + MAC_TXCFG);
1870	writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1871	writel(0, gp->regs + MAC_MCCFG);
1872	writel(0, gp->regs + MAC_XIFCFG);
1873
1874	/* Setup MAC interrupts.  We want to get all of the interesting
1875	 * counter expiration events, but we do not want to hear about
1876	 * normal rx/tx as the DMA engine tells us that.
1877	 */
1878	writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1879	writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1880
1881	/* Don't enable even the PAUSE interrupts for now, we
1882	 * make no use of those events other than to record them.
1883	 */
1884	writel(0xffffffff, gp->regs + MAC_MCMASK);
1885
1886	/* Don't enable GEM's WOL in normal operations
1887	 */
1888	if (gp->has_wol)
1889		writel(0, gp->regs + WOL_WAKECSR);
1890}
1891
1892static void gem_init_pause_thresholds(struct gem *gp)
1893{
1894	u32 cfg;
1895
1896	/* Calculate pause thresholds.  Setting the OFF threshold to the
1897	 * full RX fifo size effectively disables PAUSE generation which
1898	 * is what we do for 10/100 only GEMs which have FIFOs too small
1899	 * to make real gains from PAUSE.
1900	 */
1901	if (gp->rx_fifo_sz <= (2 * 1024)) {
1902		gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1903	} else {
1904		int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1905		int off = (gp->rx_fifo_sz - (max_frame * 2));
1906		int on = off - max_frame;
1907
1908		gp->rx_pause_off = off;
1909		gp->rx_pause_on = on;
1910	}
1911
1912
1913	/* Configure the chip "burst" DMA mode & enable some
1914	 * HW bug fixes on Apple version
1915	 */
1916	cfg  = 0;
1917	if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1918		cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1919#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1920	cfg |= GREG_CFG_IBURST;
1921#endif
1922	cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1923	cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1924	writel(cfg, gp->regs + GREG_CFG);
1925
1926	/* If Infinite Burst didn't stick, then use different
1927	 * thresholds (and Apple bug fixes don't exist)
1928	 */
1929	if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1930		cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1931		cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1932		writel(cfg, gp->regs + GREG_CFG);
1933	}
1934}
1935
1936static int gem_check_invariants(struct gem *gp)
1937{
1938	struct pci_dev *pdev = gp->pdev;
1939	u32 mif_cfg;
1940
1941	/* On Apple's sungem, we can't rely on registers as the chip
1942	 * was been powered down by the firmware. The PHY is looked
1943	 * up later on.
1944	 */
1945	if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1946		gp->phy_type = phy_mii_mdio0;
1947		gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1948		gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1949		gp->swrst_base = 0;
1950
1951		mif_cfg = readl(gp->regs + MIF_CFG);
1952		mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1953		mif_cfg |= MIF_CFG_MDI0;
1954		writel(mif_cfg, gp->regs + MIF_CFG);
1955		writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1956		writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1957
1958		/* We hard-code the PHY address so we can properly bring it out of
1959		 * reset later on, we can't really probe it at this point, though
1960		 * that isn't an issue.
1961		 */
1962		if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1963			gp->mii_phy_addr = 1;
1964		else
1965			gp->mii_phy_addr = 0;
1966
1967		return 0;
1968	}
1969
1970	mif_cfg = readl(gp->regs + MIF_CFG);
1971
1972	if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1973	    pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1974		/* One of the MII PHYs _must_ be present
1975		 * as this chip has no gigabit PHY.
1976		 */
1977		if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1978			pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1979			       mif_cfg);
1980			return -1;
1981		}
1982	}
1983
1984	/* Determine initial PHY interface type guess.  MDIO1 is the
1985	 * external PHY and thus takes precedence over MDIO0.
1986	 */
1987
1988	if (mif_cfg & MIF_CFG_MDI1) {
1989		gp->phy_type = phy_mii_mdio1;
1990		mif_cfg |= MIF_CFG_PSELECT;
1991		writel(mif_cfg, gp->regs + MIF_CFG);
1992	} else if (mif_cfg & MIF_CFG_MDI0) {
1993		gp->phy_type = phy_mii_mdio0;
1994		mif_cfg &= ~MIF_CFG_PSELECT;
1995		writel(mif_cfg, gp->regs + MIF_CFG);
1996	} else {
1997#ifdef CONFIG_SPARC
1998		const char *p;
1999
2000		p = of_get_property(gp->of_node, "shared-pins", NULL);
2001		if (p && !strcmp(p, "serdes"))
2002			gp->phy_type = phy_serdes;
2003		else
2004#endif
2005			gp->phy_type = phy_serialink;
2006	}
2007	if (gp->phy_type == phy_mii_mdio1 ||
2008	    gp->phy_type == phy_mii_mdio0) {
2009		int i;
2010
2011		for (i = 0; i < 32; i++) {
2012			gp->mii_phy_addr = i;
2013			if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2014				break;
2015		}
2016		if (i == 32) {
2017			if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2018				pr_err("RIO MII phy will not respond\n");
2019				return -1;
2020			}
2021			gp->phy_type = phy_serdes;
2022		}
2023	}
2024
2025	/* Fetch the FIFO configurations now too. */
2026	gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2027	gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2028
2029	if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2030		if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2031			if (gp->tx_fifo_sz != (9 * 1024) ||
2032			    gp->rx_fifo_sz != (20 * 1024)) {
2033				pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2034				       gp->tx_fifo_sz, gp->rx_fifo_sz);
2035				return -1;
2036			}
2037			gp->swrst_base = 0;
2038		} else {
2039			if (gp->tx_fifo_sz != (2 * 1024) ||
2040			    gp->rx_fifo_sz != (2 * 1024)) {
2041				pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2042				       gp->tx_fifo_sz, gp->rx_fifo_sz);
2043				return -1;
2044			}
2045			gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2046		}
2047	}
2048
2049	return 0;
2050}
2051
2052static void gem_reinit_chip(struct gem *gp)
2053{
2054	/* Reset the chip */
2055	gem_reset(gp);
2056
2057	/* Make sure ints are disabled */
2058	gem_disable_ints(gp);
2059
2060	/* Allocate & setup ring buffers */
2061	gem_init_rings(gp);
2062
2063	/* Configure pause thresholds */
2064	gem_init_pause_thresholds(gp);
2065
2066	/* Init DMA & MAC engines */
2067	gem_init_dma(gp);
2068	gem_init_mac(gp);
2069}
2070
2071
2072static void gem_stop_phy(struct gem *gp, int wol)
2073{
2074	u32 mifcfg;
2075
2076	/* Let the chip settle down a bit, it seems that helps
2077	 * for sleep mode on some models
2078	 */
2079	msleep(10);
2080
2081	/* Make sure we aren't polling PHY status change. We
2082	 * don't currently use that feature though
2083	 */
2084	mifcfg = readl(gp->regs + MIF_CFG);
2085	mifcfg &= ~MIF_CFG_POLL;
2086	writel(mifcfg, gp->regs + MIF_CFG);
2087
2088	if (wol && gp->has_wol) {
2089		const unsigned char *e = &gp->dev->dev_addr[0];
2090		u32 csr;
2091
2092		/* Setup wake-on-lan for MAGIC packet */
2093		writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2094		       gp->regs + MAC_RXCFG);
2095		writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2096		writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2097		writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2098
2099		writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2100		csr = WOL_WAKECSR_ENABLE;
2101		if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2102			csr |= WOL_WAKECSR_MII;
2103		writel(csr, gp->regs + WOL_WAKECSR);
2104	} else {
2105		writel(0, gp->regs + MAC_RXCFG);
2106		(void)readl(gp->regs + MAC_RXCFG);
2107		/* Machine sleep will die in strange ways if we
2108		 * dont wait a bit here, looks like the chip takes
2109		 * some time to really shut down
2110		 */
2111		msleep(10);
2112	}
2113
2114	writel(0, gp->regs + MAC_TXCFG);
2115	writel(0, gp->regs + MAC_XIFCFG);
2116	writel(0, gp->regs + TXDMA_CFG);
2117	writel(0, gp->regs + RXDMA_CFG);
2118
2119	if (!wol) {
2120		gem_reset(gp);
2121		writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2122		writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2123
2124		if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2125			gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2126
2127		/* According to Apple, we must set the MDIO pins to this begnign
2128		 * state or we may 1) eat more current, 2) damage some PHYs
2129		 */
2130		writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2131		writel(0, gp->regs + MIF_BBCLK);
2132		writel(0, gp->regs + MIF_BBDATA);
2133		writel(0, gp->regs + MIF_BBOENAB);
2134		writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2135		(void) readl(gp->regs + MAC_XIFCFG);
2136	}
2137}
2138
2139static int gem_do_start(struct net_device *dev)
2140{
2141	struct gem *gp = netdev_priv(dev);
2142	int rc;
2143
2144	pci_set_master(gp->pdev);
2145
2146	/* Init & setup chip hardware */
2147	gem_reinit_chip(gp);
2148
2149	/* An interrupt might come in handy */
2150	rc = request_irq(gp->pdev->irq, gem_interrupt,
2151			 IRQF_SHARED, dev->name, (void *)dev);
2152	if (rc) {
2153		netdev_err(dev, "failed to request irq !\n");
2154
2155		gem_reset(gp);
2156		gem_clean_rings(gp);
2157		gem_put_cell(gp);
2158		return rc;
2159	}
2160
2161	/* Mark us as attached again if we come from resume(), this has
2162	 * no effect if we weren't detached and needs to be done now.
2163	 */
2164	netif_device_attach(dev);
2165
2166	/* Restart NAPI & queues */
2167	gem_netif_start(gp);
2168
2169	/* Detect & init PHY, start autoneg etc... this will
2170	 * eventually result in starting DMA operations when
2171	 * the link is up
2172	 */
2173	gem_init_phy(gp);
2174
2175	return 0;
2176}
2177
2178static void gem_do_stop(struct net_device *dev, int wol)
2179{
2180	struct gem *gp = netdev_priv(dev);
2181
2182	/* Stop NAPI and stop tx queue */
2183	gem_netif_stop(gp);
2184
2185	/* Make sure ints are disabled. We don't care about
2186	 * synchronizing as NAPI is disabled, thus a stray
2187	 * interrupt will do nothing bad (our irq handler
2188	 * just schedules NAPI)
2189	 */
2190	gem_disable_ints(gp);
2191
2192	/* Stop the link timer */
2193	del_timer_sync(&gp->link_timer);
2194
2195	/* We cannot cancel the reset task while holding the
2196	 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2197	 * if we did. This is not an issue however as the reset
2198	 * task is synchronized vs. us (rtnl_lock) and will do
2199	 * nothing if the device is down or suspended. We do
2200	 * still clear reset_task_pending to avoid a spurrious
2201	 * reset later on in case we do resume before it gets
2202	 * scheduled.
2203	 */
2204	gp->reset_task_pending = 0;
2205
2206	/* If we are going to sleep with WOL */
2207	gem_stop_dma(gp);
2208	msleep(10);
2209	if (!wol)
2210		gem_reset(gp);
2211	msleep(10);
2212
2213	/* Get rid of rings */
2214	gem_clean_rings(gp);
2215
2216	/* No irq needed anymore */
2217	free_irq(gp->pdev->irq, (void *) dev);
2218
2219	/* Shut the PHY down eventually and setup WOL */
2220	gem_stop_phy(gp, wol);
2221}
2222
2223static void gem_reset_task(struct work_struct *work)
2224{
2225	struct gem *gp = container_of(work, struct gem, reset_task);
2226
2227	/* Lock out the network stack (essentially shield ourselves
2228	 * against a racing open, close, control call, or suspend
2229	 */
2230	rtnl_lock();
2231
2232	/* Skip the reset task if suspended or closed, or if it's
2233	 * been cancelled by gem_do_stop (see comment there)
2234	 */
2235	if (!netif_device_present(gp->dev) ||
2236	    !netif_running(gp->dev) ||
2237	    !gp->reset_task_pending) {
2238		rtnl_unlock();
2239		return;
2240	}
2241
2242	/* Stop the link timer */
2243	del_timer_sync(&gp->link_timer);
2244
2245	/* Stop NAPI and tx */
2246	gem_netif_stop(gp);
2247
2248	/* Reset the chip & rings */
2249	gem_reinit_chip(gp);
2250	if (gp->lstate == link_up)
2251		gem_set_link_modes(gp);
2252
2253	/* Restart NAPI and Tx */
2254	gem_netif_start(gp);
2255
2256	/* We are back ! */
2257	gp->reset_task_pending = 0;
2258
2259	/* If the link is not up, restart autoneg, else restart the
2260	 * polling timer
2261	 */
2262	if (gp->lstate != link_up)
2263		gem_begin_auto_negotiation(gp, NULL);
2264	else
2265		mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2266
2267	rtnl_unlock();
2268}
2269
2270static int gem_open(struct net_device *dev)
2271{
2272	struct gem *gp = netdev_priv(dev);
2273	int rc;
2274
2275	/* We allow open while suspended, we just do nothing,
2276	 * the chip will be initialized in resume()
2277	 */
2278	if (netif_device_present(dev)) {
2279		/* Enable the cell */
2280		gem_get_cell(gp);
2281
2282		/* Make sure PCI access and bus master are enabled */
2283		rc = pci_enable_device(gp->pdev);
2284		if (rc) {
2285			netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2286
2287			/* Put cell and forget it for now, it will be considered
2288			 *as still asleep, a new sleep cycle may bring it back
2289			 */
2290			gem_put_cell(gp);
2291			return -ENXIO;
2292		}
2293		return gem_do_start(dev);
2294	}
2295
2296	return 0;
2297}
2298
2299static int gem_close(struct net_device *dev)
2300{
2301	struct gem *gp = netdev_priv(dev);
2302
2303	if (netif_device_present(dev)) {
2304		gem_do_stop(dev, 0);
2305
2306		/* Make sure bus master is disabled */
2307		pci_disable_device(gp->pdev);
2308
2309		/* Cell not needed neither if no WOL */
2310		if (!gp->asleep_wol)
2311			gem_put_cell(gp);
2312	}
2313	return 0;
2314}
2315
2316static int __maybe_unused gem_suspend(struct device *dev_d)
2317{
2318	struct net_device *dev = dev_get_drvdata(dev_d);
2319	struct gem *gp = netdev_priv(dev);
2320
2321	/* Lock the network stack first to avoid racing with open/close,
2322	 * reset task and setting calls
2323	 */
2324	rtnl_lock();
2325
2326	/* Not running, mark ourselves non-present, no need for
2327	 * a lock here
2328	 */
2329	if (!netif_running(dev)) {
2330		netif_device_detach(dev);
2331		rtnl_unlock();
2332		return 0;
2333	}
2334	netdev_info(dev, "suspending, WakeOnLan %s\n",
2335		    (gp->wake_on_lan && netif_running(dev)) ?
2336		    "enabled" : "disabled");
2337
2338	/* Tell the network stack we're gone. gem_do_stop() below will
2339	 * synchronize with TX, stop NAPI etc...
2340	 */
2341	netif_device_detach(dev);
2342
2343	/* Switch off chip, remember WOL setting */
2344	gp->asleep_wol = !!gp->wake_on_lan;
2345	gem_do_stop(dev, gp->asleep_wol);
2346
2347	/* Cell not needed neither if no WOL */
2348	if (!gp->asleep_wol)
2349		gem_put_cell(gp);
2350
2351	/* Unlock the network stack */
2352	rtnl_unlock();
2353
2354	return 0;
2355}
2356
2357static int __maybe_unused gem_resume(struct device *dev_d)
2358{
2359	struct net_device *dev = dev_get_drvdata(dev_d);
2360	struct gem *gp = netdev_priv(dev);
2361
2362	/* See locking comment in gem_suspend */
2363	rtnl_lock();
2364
2365	/* Not running, mark ourselves present, no need for
2366	 * a lock here
2367	 */
2368	if (!netif_running(dev)) {
2369		netif_device_attach(dev);
2370		rtnl_unlock();
2371		return 0;
2372	}
2373
2374	/* Enable the cell */
2375	gem_get_cell(gp);
2376
2377	/* Restart chip. If that fails there isn't much we can do, we
2378	 * leave things stopped.
2379	 */
2380	gem_do_start(dev);
2381
2382	/* If we had WOL enabled, the cell clock was never turned off during
2383	 * sleep, so we end up beeing unbalanced. Fix that here
2384	 */
2385	if (gp->asleep_wol)
2386		gem_put_cell(gp);
2387
2388	/* Unlock the network stack */
2389	rtnl_unlock();
2390
2391	return 0;
2392}
2393
2394static struct net_device_stats *gem_get_stats(struct net_device *dev)
2395{
2396	struct gem *gp = netdev_priv(dev);
2397
2398	/* I have seen this being called while the PM was in progress,
2399	 * so we shield against this. Let's also not poke at registers
2400	 * while the reset task is going on.
2401	 *
2402	 * TODO: Move stats collection elsewhere (link timer ?) and
2403	 * make this a nop to avoid all those synchro issues
2404	 */
2405	if (!netif_device_present(dev) || !netif_running(dev))
2406		goto bail;
2407
2408	/* Better safe than sorry... */
2409	if (WARN_ON(!gp->cell_enabled))
2410		goto bail;
2411
2412	dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2413	writel(0, gp->regs + MAC_FCSERR);
2414
2415	dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2416	writel(0, gp->regs + MAC_AERR);
2417
2418	dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2419	writel(0, gp->regs + MAC_LERR);
2420
2421	dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2422	dev->stats.collisions +=
2423		(readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2424	writel(0, gp->regs + MAC_ECOLL);
2425	writel(0, gp->regs + MAC_LCOLL);
2426 bail:
2427	return &dev->stats;
2428}
2429
2430static int gem_set_mac_address(struct net_device *dev, void *addr)
2431{
2432	struct sockaddr *macaddr = (struct sockaddr *) addr;
2433	const unsigned char *e = &dev->dev_addr[0];
2434	struct gem *gp = netdev_priv(dev);
2435
2436	if (!is_valid_ether_addr(macaddr->sa_data))
2437		return -EADDRNOTAVAIL;
2438
2439	eth_hw_addr_set(dev, macaddr->sa_data);
2440
2441	/* We'll just catch it later when the device is up'd or resumed */
2442	if (!netif_running(dev) || !netif_device_present(dev))
2443		return 0;
2444
2445	/* Better safe than sorry... */
2446	if (WARN_ON(!gp->cell_enabled))
2447		return 0;
2448
2449	writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2450	writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2451	writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2452
2453	return 0;
2454}
2455
2456static void gem_set_multicast(struct net_device *dev)
2457{
2458	struct gem *gp = netdev_priv(dev);
2459	u32 rxcfg, rxcfg_new;
2460	int limit = 10000;
2461
2462	if (!netif_running(dev) || !netif_device_present(dev))
2463		return;
2464
2465	/* Better safe than sorry... */
2466	if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2467		return;
2468
2469	rxcfg = readl(gp->regs + MAC_RXCFG);
2470	rxcfg_new = gem_setup_multicast(gp);
2471#ifdef STRIP_FCS
2472	rxcfg_new |= MAC_RXCFG_SFCS;
2473#endif
2474	gp->mac_rx_cfg = rxcfg_new;
2475
2476	writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2477	while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2478		if (!limit--)
2479			break;
2480		udelay(10);
2481	}
2482
2483	rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2484	rxcfg |= rxcfg_new;
2485
2486	writel(rxcfg, gp->regs + MAC_RXCFG);
2487}
2488
2489/* Jumbo-grams don't seem to work :-( */
2490#define GEM_MIN_MTU	ETH_MIN_MTU
2491#if 1
2492#define GEM_MAX_MTU	ETH_DATA_LEN
2493#else
2494#define GEM_MAX_MTU	9000
2495#endif
2496
2497static int gem_change_mtu(struct net_device *dev, int new_mtu)
2498{
2499	struct gem *gp = netdev_priv(dev);
2500
2501	dev->mtu = new_mtu;
2502
2503	/* We'll just catch it later when the device is up'd or resumed */
2504	if (!netif_running(dev) || !netif_device_present(dev))
2505		return 0;
2506
2507	/* Better safe than sorry... */
2508	if (WARN_ON(!gp->cell_enabled))
2509		return 0;
2510
2511	gem_netif_stop(gp);
2512	gem_reinit_chip(gp);
2513	if (gp->lstate == link_up)
2514		gem_set_link_modes(gp);
2515	gem_netif_start(gp);
2516
2517	return 0;
2518}
2519
2520static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2521{
2522	struct gem *gp = netdev_priv(dev);
2523
2524	strscpy(info->driver, DRV_NAME, sizeof(info->driver));
2525	strscpy(info->version, DRV_VERSION, sizeof(info->version));
2526	strscpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2527}
2528
2529static int gem_get_link_ksettings(struct net_device *dev,
2530				  struct ethtool_link_ksettings *cmd)
2531{
2532	struct gem *gp = netdev_priv(dev);
2533	u32 supported, advertising;
2534
2535	if (gp->phy_type == phy_mii_mdio0 ||
2536	    gp->phy_type == phy_mii_mdio1) {
2537		if (gp->phy_mii.def)
2538			supported = gp->phy_mii.def->features;
2539		else
2540			supported = (SUPPORTED_10baseT_Half |
2541					  SUPPORTED_10baseT_Full);
2542
2543		/* XXX hardcoded stuff for now */
2544		cmd->base.port = PORT_MII;
2545		cmd->base.phy_address = 0; /* XXX fixed PHYAD */
2546
2547		/* Return current PHY settings */
2548		cmd->base.autoneg = gp->want_autoneg;
2549		cmd->base.speed = gp->phy_mii.speed;
2550		cmd->base.duplex = gp->phy_mii.duplex;
2551		advertising = gp->phy_mii.advertising;
2552
2553		/* If we started with a forced mode, we don't have a default
2554		 * advertise set, we need to return something sensible so
2555		 * userland can re-enable autoneg properly.
2556		 */
2557		if (advertising == 0)
2558			advertising = supported;
2559	} else { // XXX PCS ?
2560		supported =
2561			(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2562			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2563			 SUPPORTED_Autoneg);
2564		advertising = supported;
2565		cmd->base.speed = 0;
2566		cmd->base.duplex = 0;
2567		cmd->base.port = 0;
2568		cmd->base.phy_address = 0;
2569		cmd->base.autoneg = 0;
2570
2571		/* serdes means usually a Fibre connector, with most fixed */
2572		if (gp->phy_type == phy_serdes) {
2573			cmd->base.port = PORT_FIBRE;
2574			supported = (SUPPORTED_1000baseT_Half |
2575				SUPPORTED_1000baseT_Full |
2576				SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2577				SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2578			advertising = supported;
2579			if (gp->lstate == link_up)
2580				cmd->base.speed = SPEED_1000;
2581			cmd->base.duplex = DUPLEX_FULL;
2582			cmd->base.autoneg = 1;
2583		}
2584	}
2585
2586	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2587						supported);
2588	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2589						advertising);
2590
2591	return 0;
2592}
2593
2594static int gem_set_link_ksettings(struct net_device *dev,
2595				  const struct ethtool_link_ksettings *cmd)
2596{
2597	struct gem *gp = netdev_priv(dev);
2598	u32 speed = cmd->base.speed;
2599	u32 advertising;
2600
2601	ethtool_convert_link_mode_to_legacy_u32(&advertising,
2602						cmd->link_modes.advertising);
2603
2604	/* Verify the settings we care about. */
2605	if (cmd->base.autoneg != AUTONEG_ENABLE &&
2606	    cmd->base.autoneg != AUTONEG_DISABLE)
2607		return -EINVAL;
2608
2609	if (cmd->base.autoneg == AUTONEG_ENABLE &&
2610	    advertising == 0)
2611		return -EINVAL;
2612
2613	if (cmd->base.autoneg == AUTONEG_DISABLE &&
2614	    ((speed != SPEED_1000 &&
2615	      speed != SPEED_100 &&
2616	      speed != SPEED_10) ||
2617	     (cmd->base.duplex != DUPLEX_HALF &&
2618	      cmd->base.duplex != DUPLEX_FULL)))
2619		return -EINVAL;
2620
2621	/* Apply settings and restart link process. */
2622	if (netif_device_present(gp->dev)) {
2623		del_timer_sync(&gp->link_timer);
2624		gem_begin_auto_negotiation(gp, cmd);
2625	}
2626
2627	return 0;
2628}
2629
2630static int gem_nway_reset(struct net_device *dev)
2631{
2632	struct gem *gp = netdev_priv(dev);
2633
2634	if (!gp->want_autoneg)
2635		return -EINVAL;
2636
2637	/* Restart link process  */
2638	if (netif_device_present(gp->dev)) {
2639		del_timer_sync(&gp->link_timer);
2640		gem_begin_auto_negotiation(gp, NULL);
2641	}
2642
2643	return 0;
2644}
2645
2646static u32 gem_get_msglevel(struct net_device *dev)
2647{
2648	struct gem *gp = netdev_priv(dev);
2649	return gp->msg_enable;
2650}
2651
2652static void gem_set_msglevel(struct net_device *dev, u32 value)
2653{
2654	struct gem *gp = netdev_priv(dev);
2655	gp->msg_enable = value;
2656}
2657
2658
2659/* Add more when I understand how to program the chip */
2660/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2661
2662#define WOL_SUPPORTED_MASK	(WAKE_MAGIC)
2663
2664static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2665{
2666	struct gem *gp = netdev_priv(dev);
2667
2668	/* Add more when I understand how to program the chip */
2669	if (gp->has_wol) {
2670		wol->supported = WOL_SUPPORTED_MASK;
2671		wol->wolopts = gp->wake_on_lan;
2672	} else {
2673		wol->supported = 0;
2674		wol->wolopts = 0;
2675	}
2676}
2677
2678static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2679{
2680	struct gem *gp = netdev_priv(dev);
2681
2682	if (!gp->has_wol)
2683		return -EOPNOTSUPP;
2684	gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2685	return 0;
2686}
2687
2688static const struct ethtool_ops gem_ethtool_ops = {
2689	.get_drvinfo		= gem_get_drvinfo,
2690	.get_link		= ethtool_op_get_link,
2691	.nway_reset		= gem_nway_reset,
2692	.get_msglevel		= gem_get_msglevel,
2693	.set_msglevel		= gem_set_msglevel,
2694	.get_wol		= gem_get_wol,
2695	.set_wol		= gem_set_wol,
2696	.get_link_ksettings	= gem_get_link_ksettings,
2697	.set_link_ksettings	= gem_set_link_ksettings,
2698};
2699
2700static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2701{
2702	struct gem *gp = netdev_priv(dev);
2703	struct mii_ioctl_data *data = if_mii(ifr);
2704	int rc = -EOPNOTSUPP;
2705
2706	/* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2707	 * netif_device_present() is true and holds rtnl_lock for us
2708	 * so we have nothing to worry about
2709	 */
2710
2711	switch (cmd) {
2712	case SIOCGMIIPHY:		/* Get address of MII PHY in use. */
2713		data->phy_id = gp->mii_phy_addr;
2714		fallthrough;
2715
2716	case SIOCGMIIREG:		/* Read MII PHY register. */
2717		data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2718					   data->reg_num & 0x1f);
2719		rc = 0;
2720		break;
2721
2722	case SIOCSMIIREG:		/* Write MII PHY register. */
2723		__sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2724			    data->val_in);
2725		rc = 0;
2726		break;
2727	}
2728	return rc;
2729}
2730
2731#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2732/* Fetch MAC address from vital product data of PCI ROM. */
2733static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2734{
2735	int this_offset;
2736
2737	for (this_offset = 0x20; this_offset < len; this_offset++) {
2738		void __iomem *p = rom_base + this_offset;
2739		int i;
2740
2741		if (readb(p + 0) != 0x90 ||
2742		    readb(p + 1) != 0x00 ||
2743		    readb(p + 2) != 0x09 ||
2744		    readb(p + 3) != 0x4e ||
2745		    readb(p + 4) != 0x41 ||
2746		    readb(p + 5) != 0x06)
2747			continue;
2748
2749		this_offset += 6;
2750		p += 6;
2751
2752		for (i = 0; i < 6; i++)
2753			dev_addr[i] = readb(p + i);
2754		return 1;
2755	}
2756	return 0;
2757}
2758
2759static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2760{
2761	size_t size;
2762	void __iomem *p = pci_map_rom(pdev, &size);
2763
2764	if (p) {
2765		int found;
2766
2767		found = readb(p) == 0x55 &&
2768			readb(p + 1) == 0xaa &&
2769			find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2770		pci_unmap_rom(pdev, p);
2771		if (found)
2772			return;
2773	}
2774
2775	/* Sun MAC prefix then 3 random bytes. */
2776	dev_addr[0] = 0x08;
2777	dev_addr[1] = 0x00;
2778	dev_addr[2] = 0x20;
2779	get_random_bytes(dev_addr + 3, 3);
2780}
2781#endif /* not Sparc and not PPC */
2782
2783static int gem_get_device_address(struct gem *gp)
2784{
2785#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2786	struct net_device *dev = gp->dev;
2787	const unsigned char *addr;
2788
2789	addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2790	if (addr == NULL) {
2791#ifdef CONFIG_SPARC
2792		addr = idprom->id_ethaddr;
2793#else
2794		printk("\n");
2795		pr_err("%s: can't get mac-address\n", dev->name);
2796		return -1;
2797#endif
2798	}
2799	eth_hw_addr_set(dev, addr);
2800#else
2801	u8 addr[ETH_ALEN];
2802
2803	get_gem_mac_nonobp(gp->pdev, addr);
2804	eth_hw_addr_set(gp->dev, addr);
2805#endif
2806	return 0;
2807}
2808
2809static void gem_remove_one(struct pci_dev *pdev)
2810{
2811	struct net_device *dev = pci_get_drvdata(pdev);
2812
2813	if (dev) {
2814		struct gem *gp = netdev_priv(dev);
2815
2816		unregister_netdev(dev);
2817
2818		/* Ensure reset task is truly gone */
2819		cancel_work_sync(&gp->reset_task);
2820
2821		/* Free resources */
2822		dma_free_coherent(&pdev->dev, sizeof(struct gem_init_block),
2823				  gp->init_block, gp->gblock_dvma);
2824		iounmap(gp->regs);
2825		pci_release_regions(pdev);
2826		free_netdev(dev);
2827	}
2828}
2829
2830static const struct net_device_ops gem_netdev_ops = {
2831	.ndo_open		= gem_open,
2832	.ndo_stop		= gem_close,
2833	.ndo_start_xmit		= gem_start_xmit,
2834	.ndo_get_stats		= gem_get_stats,
2835	.ndo_set_rx_mode	= gem_set_multicast,
2836	.ndo_eth_ioctl		= gem_ioctl,
2837	.ndo_tx_timeout		= gem_tx_timeout,
2838	.ndo_change_mtu		= gem_change_mtu,
2839	.ndo_validate_addr	= eth_validate_addr,
2840	.ndo_set_mac_address    = gem_set_mac_address,
2841#ifdef CONFIG_NET_POLL_CONTROLLER
2842	.ndo_poll_controller    = gem_poll_controller,
2843#endif
2844};
2845
2846static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2847{
2848	unsigned long gemreg_base, gemreg_len;
2849	struct net_device *dev;
2850	struct gem *gp;
2851	int err, pci_using_dac;
2852
2853	printk_once(KERN_INFO "%s", version);
2854
2855	/* Apple gmac note: during probe, the chip is powered up by
2856	 * the arch code to allow the code below to work (and to let
2857	 * the chip be probed on the config space. It won't stay powered
2858	 * up until the interface is brought up however, so we can't rely
2859	 * on register configuration done at this point.
2860	 */
2861	err = pci_enable_device(pdev);
2862	if (err) {
2863		pr_err("Cannot enable MMIO operation, aborting\n");
2864		return err;
2865	}
2866	pci_set_master(pdev);
2867
2868	/* Configure DMA attributes. */
2869
2870	/* All of the GEM documentation states that 64-bit DMA addressing
2871	 * is fully supported and should work just fine.  However the
2872	 * front end for RIO based GEMs is different and only supports
2873	 * 32-bit addressing.
2874	 *
2875	 * For now we assume the various PPC GEMs are 32-bit only as well.
2876	 */
2877	if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2878	    pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2879	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2880		pci_using_dac = 1;
2881	} else {
2882		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2883		if (err) {
2884			pr_err("No usable DMA configuration, aborting\n");
2885			goto err_disable_device;
2886		}
2887		pci_using_dac = 0;
2888	}
2889
2890	gemreg_base = pci_resource_start(pdev, 0);
2891	gemreg_len = pci_resource_len(pdev, 0);
2892
2893	if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2894		pr_err("Cannot find proper PCI device base address, aborting\n");
2895		err = -ENODEV;
2896		goto err_disable_device;
2897	}
2898
2899	dev = alloc_etherdev(sizeof(*gp));
2900	if (!dev) {
2901		err = -ENOMEM;
2902		goto err_disable_device;
2903	}
2904	SET_NETDEV_DEV(dev, &pdev->dev);
2905
2906	gp = netdev_priv(dev);
2907
2908	err = pci_request_regions(pdev, DRV_NAME);
2909	if (err) {
2910		pr_err("Cannot obtain PCI resources, aborting\n");
2911		goto err_out_free_netdev;
2912	}
2913
2914	gp->pdev = pdev;
2915	gp->dev = dev;
2916
2917	gp->msg_enable = DEFAULT_MSG;
2918
2919	timer_setup(&gp->link_timer, gem_link_timer, 0);
2920
2921	INIT_WORK(&gp->reset_task, gem_reset_task);
2922
2923	gp->lstate = link_down;
2924	gp->timer_ticks = 0;
2925	netif_carrier_off(dev);
2926
2927	gp->regs = ioremap(gemreg_base, gemreg_len);
2928	if (!gp->regs) {
2929		pr_err("Cannot map device registers, aborting\n");
2930		err = -EIO;
2931		goto err_out_free_res;
2932	}
2933
2934	/* On Apple, we want a reference to the Open Firmware device-tree
2935	 * node. We use it for clock control.
2936	 */
2937#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2938	gp->of_node = pci_device_to_OF_node(pdev);
2939#endif
2940
2941	/* Only Apple version supports WOL afaik */
2942	if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2943		gp->has_wol = 1;
2944
2945	/* Make sure cell is enabled */
2946	gem_get_cell(gp);
2947
2948	/* Make sure everything is stopped and in init state */
2949	gem_reset(gp);
2950
2951	/* Fill up the mii_phy structure (even if we won't use it) */
2952	gp->phy_mii.dev = dev;
2953	gp->phy_mii.mdio_read = _sungem_phy_read;
2954	gp->phy_mii.mdio_write = _sungem_phy_write;
2955#ifdef CONFIG_PPC_PMAC
2956	gp->phy_mii.platform_data = gp->of_node;
2957#endif
2958	/* By default, we start with autoneg */
2959	gp->want_autoneg = 1;
2960
2961	/* Check fifo sizes, PHY type, etc... */
2962	if (gem_check_invariants(gp)) {
2963		err = -ENODEV;
2964		goto err_out_iounmap;
2965	}
2966
2967	/* It is guaranteed that the returned buffer will be at least
2968	 * PAGE_SIZE aligned.
2969	 */
2970	gp->init_block = dma_alloc_coherent(&pdev->dev, sizeof(struct gem_init_block),
2971					    &gp->gblock_dvma, GFP_KERNEL);
2972	if (!gp->init_block) {
2973		pr_err("Cannot allocate init block, aborting\n");
2974		err = -ENOMEM;
2975		goto err_out_iounmap;
2976	}
2977
2978	err = gem_get_device_address(gp);
2979	if (err)
2980		goto err_out_free_consistent;
2981
2982	dev->netdev_ops = &gem_netdev_ops;
2983	netif_napi_add(dev, &gp->napi, gem_poll);
2984	dev->ethtool_ops = &gem_ethtool_ops;
2985	dev->watchdog_timeo = 5 * HZ;
2986	dev->dma = 0;
2987
2988	/* Set that now, in case PM kicks in now */
2989	pci_set_drvdata(pdev, dev);
2990
2991	/* We can do scatter/gather and HW checksum */
2992	dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2993	dev->features = dev->hw_features;
2994	if (pci_using_dac)
2995		dev->features |= NETIF_F_HIGHDMA;
2996
2997	/* MTU range: 68 - 1500 (Jumbo mode is broken) */
2998	dev->min_mtu = GEM_MIN_MTU;
2999	dev->max_mtu = GEM_MAX_MTU;
3000
3001	/* Register with kernel */
3002	if (register_netdev(dev)) {
3003		pr_err("Cannot register net device, aborting\n");
3004		err = -ENOMEM;
3005		goto err_out_free_consistent;
3006	}
3007
3008	/* Undo the get_cell with appropriate locking (we could use
3009	 * ndo_init/uninit but that would be even more clumsy imho)
3010	 */
3011	rtnl_lock();
3012	gem_put_cell(gp);
3013	rtnl_unlock();
3014
3015	netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3016		    dev->dev_addr);
3017	return 0;
3018
3019err_out_free_consistent:
3020	gem_remove_one(pdev);
3021err_out_iounmap:
3022	gem_put_cell(gp);
3023	iounmap(gp->regs);
3024
3025err_out_free_res:
3026	pci_release_regions(pdev);
3027
3028err_out_free_netdev:
3029	free_netdev(dev);
3030err_disable_device:
3031	pci_disable_device(pdev);
3032	return err;
3033
3034}
3035
3036static SIMPLE_DEV_PM_OPS(gem_pm_ops, gem_suspend, gem_resume);
3037
3038static struct pci_driver gem_driver = {
3039	.name		= GEM_MODULE_NAME,
3040	.id_table	= gem_pci_tbl,
3041	.probe		= gem_init_one,
3042	.remove		= gem_remove_one,
3043	.driver.pm	= &gem_pm_ops,
3044};
3045
3046module_pci_driver(gem_driver);