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1// SPDX-License-Identifier: GPL-2.0
2/* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
3 *
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
6 *
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
8 * integrated PHYs for the user facing ports, and an extension interface which
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
10 * RGMII. The switch is configured via the Realtek Simple Management Interface
11 * (SMI), which uses the MDIO/MDC lines.
12 *
13 * Below is a simplified block diagram of the chip and its relevant interfaces.
14 *
15 * .-----------------------------------.
16 * | |
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC |
21 * | |
22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension |
23 * | interface 1 GMAC 1 |
24 * | |
25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ |
26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ |
27 * | ~RTL8365MB ~~~ |
28 * | ~GXXXC TAIWAN~ |
29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ |
30 * | |
31 * Interrupt <----------> Link UP/DOWN events |
32 * controller | |
33 * '-----------------------------------'
34 *
35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the
36 * kernel. Netdevices are created for the user ports, as are PHY devices for
37 * their integrated PHYs. The device tree firmware should also specify the link
38 * partner of the extension port - either via a fixed-link or other phy-handle.
39 * See the device tree bindings for more detailed information. Note that the
40 * driver has only been tested with a fixed-link, but in principle it should not
41 * matter.
42 *
43 * NOTE: Currently, only the RGMII interface is implemented in this driver.
44 *
45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a
46 * custom irqchip to handle this interrupt and demultiplex the events by reading
47 * the status registers via SMI. Interrupts are then propagated to the relevant
48 * PHY device.
49 *
50 * The EEPROM contains initial register values which the chip will read over I2C
51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases,
52 * the driver will manually reprogram some registers using jam tables to reach
53 * an initial state defined by the vendor driver.
54 *
55 * This Linux driver is written based on an OS-agnostic vendor driver from
56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt
57 * source tree under the name rtl8367c. The vendor driver claims to support a
58 * number of similar switch controllers from Realtek, but the only hardware we
59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under
60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of
61 * common hardware revision, there exist examples of chips with the suffix -VC
62 * which are explicitly not supported by the rtl8367c driver and which instead
63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has
64 * been modestly named rtl8365mb. Future implementors may wish to rename things
65 * accordingly.
66 *
67 * In the same family of chips, some carry up to 8 user ports and up to 2
68 * extension ports. Where possible this driver tries to make things generic, but
69 * more work must be done to support these configurations. According to
70 * documentation from Realtek, the family should include the following chips:
71 *
72 * - RTL8363NB
73 * - RTL8363NB-VB
74 * - RTL8363SC
75 * - RTL8363SC-VB
76 * - RTL8364NB
77 * - RTL8364NB-VB
78 * - RTL8365MB-VC
79 * - RTL8366SC
80 * - RTL8367RB-VB
81 * - RTL8367SB
82 * - RTL8367S
83 * - RTL8370MB
84 * - RTL8310SR
85 *
86 * Some of the register logic for these additional chips has been skipped over
87 * while implementing this driver. It is therefore not possible to assume that
88 * things will work out-of-the-box for other chips, and a careful review of the
89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be
90 * one of the simpler chips.
91 */
92
93#include <linux/bitfield.h>
94#include <linux/bitops.h>
95#include <linux/interrupt.h>
96#include <linux/irqdomain.h>
97#include <linux/mutex.h>
98#include <linux/of_irq.h>
99#include <linux/regmap.h>
100#include <linux/if_bridge.h>
101
102#include "realtek.h"
103
104/* Family-specific data and limits */
105#define RTL8365MB_PHYADDRMAX 7
106#define RTL8365MB_NUM_PHYREGS 32
107#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)
108#define RTL8365MB_MAX_NUM_PORTS 11
109#define RTL8365MB_MAX_NUM_EXTINTS 3
110#define RTL8365MB_LEARN_LIMIT_MAX 2112
111
112/* Chip identification registers */
113#define RTL8365MB_CHIP_ID_REG 0x1300
114
115#define RTL8365MB_CHIP_VER_REG 0x1301
116
117#define RTL8365MB_MAGIC_REG 0x13C2
118#define RTL8365MB_MAGIC_VALUE 0x0249
119
120/* Chip reset register */
121#define RTL8365MB_CHIP_RESET_REG 0x1322
122#define RTL8365MB_CHIP_RESET_SW_MASK 0x0002
123#define RTL8365MB_CHIP_RESET_HW_MASK 0x0001
124
125/* Interrupt polarity register */
126#define RTL8365MB_INTR_POLARITY_REG 0x1100
127#define RTL8365MB_INTR_POLARITY_MASK 0x0001
128#define RTL8365MB_INTR_POLARITY_HIGH 0
129#define RTL8365MB_INTR_POLARITY_LOW 1
130
131/* Interrupt control/status register - enable/check specific interrupt types */
132#define RTL8365MB_INTR_CTRL_REG 0x1101
133#define RTL8365MB_INTR_STATUS_REG 0x1102
134#define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000
135#define RTL8365MB_INTR_SLIENT_START_MASK 0x0800
136#define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200
137#define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100
138#define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080
139#define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040
140#define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020
141#define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010
142#define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008
143#define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004
144#define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002
145#define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001
146#define RTL8365MB_INTR_ALL_MASK \
147 (RTL8365MB_INTR_SLIENT_START_2_MASK | \
148 RTL8365MB_INTR_SLIENT_START_MASK | \
149 RTL8365MB_INTR_ACL_ACTION_MASK | \
150 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \
151 RTL8365MB_INTR_INTERRUPT_8051_MASK | \
152 RTL8365MB_INTR_LOOP_DETECTION_MASK | \
153 RTL8365MB_INTR_GREEN_TIMER_MASK | \
154 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \
155 RTL8365MB_INTR_SPEED_CHANGE_MASK | \
156 RTL8365MB_INTR_LEARN_OVER_MASK | \
157 RTL8365MB_INTR_METER_EXCEEDED_MASK | \
158 RTL8365MB_INTR_LINK_CHANGE_MASK)
159
160/* Per-port interrupt type status registers */
161#define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106
162#define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF
163
164#define RTL8365MB_PORT_LINKUP_IND_REG 0x1107
165#define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF
166
167/* PHY indirect access registers */
168#define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00
169#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002
170#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0
171#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1
172#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001
173#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1
174#define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01
175#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02
176#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0)
177#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5)
178#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8)
179#define RTL8365MB_PHY_BASE 0x2000
180#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03
181#define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04
182
183/* PHY OCP address prefix register */
184#define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15
185#define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0
186#define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00
187
188/* The PHY OCP addresses of PHY registers 0~31 start here */
189#define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400
190
191/* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */
192#define RTL8365MB_EXT_PORT_MODE_DISABLE 0
193#define RTL8365MB_EXT_PORT_MODE_RGMII 1
194#define RTL8365MB_EXT_PORT_MODE_MII_MAC 2
195#define RTL8365MB_EXT_PORT_MODE_MII_PHY 3
196#define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4
197#define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5
198#define RTL8365MB_EXT_PORT_MODE_GMII 6
199#define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7
200#define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8
201#define RTL8365MB_EXT_PORT_MODE_SGMII 9
202#define RTL8365MB_EXT_PORT_MODE_HSGMII 10
203#define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11
204#define RTL8365MB_EXT_PORT_MODE_1000X 12
205#define RTL8365MB_EXT_PORT_MODE_100FX 13
206
207/* External interface mode configuration registers 0~1 */
208#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT1 */
209#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */
210#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \
211 ((_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \
212 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \
213 0x0)
214#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \
215 (0xF << (((_extint) % 2)))
216#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \
217 (((_extint) % 2) * 4)
218
219/* External interface RGMII TX/RX delay configuration registers 0~2 */
220#define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */
221#define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */
222#define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */
223#define RTL8365MB_EXT_RGMXF_REG(_extint) \
224 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \
225 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \
226 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \
227 0x0)
228#define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007
229#define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008
230
231/* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */
232#define RTL8365MB_PORT_SPEED_10M 0
233#define RTL8365MB_PORT_SPEED_100M 1
234#define RTL8365MB_PORT_SPEED_1000M 2
235
236/* External interface force configuration registers 0~2 */
237#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */
238#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */
239#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */
240#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \
241 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \
242 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \
243 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \
244 0x0)
245#define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000
246#define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080
247#define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040
248#define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020
249#define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010
250#define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004
251#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003
252
253/* CPU port mask register - controls which ports are treated as CPU ports */
254#define RTL8365MB_CPU_PORT_MASK_REG 0x1219
255#define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF
256
257/* CPU control register */
258#define RTL8365MB_CPU_CTRL_REG 0x121A
259#define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400
260#define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200
261#define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080
262#define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040
263#define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038
264#define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006
265#define RTL8365MB_CPU_CTRL_EN_MASK 0x0001
266
267/* Maximum packet length register */
268#define RTL8365MB_CFG0_MAX_LEN_REG 0x088C
269#define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF
270
271/* Port learning limit registers */
272#define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20
273#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \
274 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport))
275
276/* Port isolation (forwarding mask) registers */
277#define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2
278#define RTL8365MB_PORT_ISOLATION_REG(_physport) \
279 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))
280#define RTL8365MB_PORT_ISOLATION_MASK 0x07FF
281
282/* MSTP port state registers - indexed by tree instance */
283#define RTL8365MB_MSTI_CTRL_BASE 0x0A00
284#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \
285 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3))
286#define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1)
287#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \
288 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))
289
290/* MIB counter value registers */
291#define RTL8365MB_MIB_COUNTER_BASE 0x1000
292#define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x))
293
294/* MIB counter address register */
295#define RTL8365MB_MIB_ADDRESS_REG 0x1004
296#define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C
297#define RTL8365MB_MIB_ADDRESS(_p, _x) \
298 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2)
299
300#define RTL8365MB_MIB_CTRL0_REG 0x1005
301#define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002
302#define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001
303
304/* The DSA callback .get_stats64 runs in atomic context, so we are not allowed
305 * to block. On the other hand, accessing MIB counters absolutely requires us to
306 * block. The solution is thus to schedule work which polls the MIB counters
307 * asynchronously and updates some private data, which the callback can then
308 * fetch atomically. Three seconds should be a good enough polling interval.
309 */
310#define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ)
311
312enum rtl8365mb_mib_counter_index {
313 RTL8365MB_MIB_ifInOctets,
314 RTL8365MB_MIB_dot3StatsFCSErrors,
315 RTL8365MB_MIB_dot3StatsSymbolErrors,
316 RTL8365MB_MIB_dot3InPauseFrames,
317 RTL8365MB_MIB_dot3ControlInUnknownOpcodes,
318 RTL8365MB_MIB_etherStatsFragments,
319 RTL8365MB_MIB_etherStatsJabbers,
320 RTL8365MB_MIB_ifInUcastPkts,
321 RTL8365MB_MIB_etherStatsDropEvents,
322 RTL8365MB_MIB_ifInMulticastPkts,
323 RTL8365MB_MIB_ifInBroadcastPkts,
324 RTL8365MB_MIB_inMldChecksumError,
325 RTL8365MB_MIB_inIgmpChecksumError,
326 RTL8365MB_MIB_inMldSpecificQuery,
327 RTL8365MB_MIB_inMldGeneralQuery,
328 RTL8365MB_MIB_inIgmpSpecificQuery,
329 RTL8365MB_MIB_inIgmpGeneralQuery,
330 RTL8365MB_MIB_inMldLeaves,
331 RTL8365MB_MIB_inIgmpLeaves,
332 RTL8365MB_MIB_etherStatsOctets,
333 RTL8365MB_MIB_etherStatsUnderSizePkts,
334 RTL8365MB_MIB_etherOversizeStats,
335 RTL8365MB_MIB_etherStatsPkts64Octets,
336 RTL8365MB_MIB_etherStatsPkts65to127Octets,
337 RTL8365MB_MIB_etherStatsPkts128to255Octets,
338 RTL8365MB_MIB_etherStatsPkts256to511Octets,
339 RTL8365MB_MIB_etherStatsPkts512to1023Octets,
340 RTL8365MB_MIB_etherStatsPkts1024to1518Octets,
341 RTL8365MB_MIB_ifOutOctets,
342 RTL8365MB_MIB_dot3StatsSingleCollisionFrames,
343 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames,
344 RTL8365MB_MIB_dot3StatsDeferredTransmissions,
345 RTL8365MB_MIB_dot3StatsLateCollisions,
346 RTL8365MB_MIB_etherStatsCollisions,
347 RTL8365MB_MIB_dot3StatsExcessiveCollisions,
348 RTL8365MB_MIB_dot3OutPauseFrames,
349 RTL8365MB_MIB_ifOutDiscards,
350 RTL8365MB_MIB_dot1dTpPortInDiscards,
351 RTL8365MB_MIB_ifOutUcastPkts,
352 RTL8365MB_MIB_ifOutMulticastPkts,
353 RTL8365MB_MIB_ifOutBroadcastPkts,
354 RTL8365MB_MIB_outOampduPkts,
355 RTL8365MB_MIB_inOampduPkts,
356 RTL8365MB_MIB_inIgmpJoinsSuccess,
357 RTL8365MB_MIB_inIgmpJoinsFail,
358 RTL8365MB_MIB_inMldJoinsSuccess,
359 RTL8365MB_MIB_inMldJoinsFail,
360 RTL8365MB_MIB_inReportSuppressionDrop,
361 RTL8365MB_MIB_inLeaveSuppressionDrop,
362 RTL8365MB_MIB_outIgmpReports,
363 RTL8365MB_MIB_outIgmpLeaves,
364 RTL8365MB_MIB_outIgmpGeneralQuery,
365 RTL8365MB_MIB_outIgmpSpecificQuery,
366 RTL8365MB_MIB_outMldReports,
367 RTL8365MB_MIB_outMldLeaves,
368 RTL8365MB_MIB_outMldGeneralQuery,
369 RTL8365MB_MIB_outMldSpecificQuery,
370 RTL8365MB_MIB_inKnownMulticastPkts,
371 RTL8365MB_MIB_END,
372};
373
374struct rtl8365mb_mib_counter {
375 u32 offset;
376 u32 length;
377 const char *name;
378};
379
380#define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \
381 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name }
382
383static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = {
384 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets),
385 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors),
386 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors),
387 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames),
388 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes),
389 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments),
390 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers),
391 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts),
392 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents),
393 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts),
394 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts),
395 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError),
396 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError),
397 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery),
398 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery),
399 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery),
400 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery),
401 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves),
402 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves),
403 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets),
404 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts),
405 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats),
406 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets),
407 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets),
408 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets),
409 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets),
410 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets),
411 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets),
412 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets),
413 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames),
414 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames),
415 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions),
416 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions),
417 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions),
418 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions),
419 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames),
420 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards),
421 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards),
422 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts),
423 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts),
424 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts),
425 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts),
426 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts),
427 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess),
428 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail),
429 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess),
430 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail),
431 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop),
432 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop),
433 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports),
434 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves),
435 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery),
436 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery),
437 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports),
438 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves),
439 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery),
440 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery),
441 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts),
442};
443
444static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END);
445
446struct rtl8365mb_jam_tbl_entry {
447 u16 reg;
448 u16 val;
449};
450
451/* Lifted from the vendor driver sources */
452static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = {
453 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 },
454 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA },
455 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 },
456 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F },
457 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 },
458 { 0x13F0, 0x0000 },
459};
460
461static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = {
462 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 },
463 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E },
464 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 },
465 { 0x1D32, 0x0002 },
466};
467
468enum rtl8365mb_phy_interface_mode {
469 RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0,
470 RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0),
471 RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1),
472 RTL8365MB_PHY_INTERFACE_MODE_TMII = BIT(2),
473 RTL8365MB_PHY_INTERFACE_MODE_RMII = BIT(3),
474 RTL8365MB_PHY_INTERFACE_MODE_RGMII = BIT(4),
475 RTL8365MB_PHY_INTERFACE_MODE_SGMII = BIT(5),
476 RTL8365MB_PHY_INTERFACE_MODE_HSGMII = BIT(6),
477};
478
479/**
480 * struct rtl8365mb_extint - external interface info
481 * @port: the port with an external interface
482 * @id: the external interface ID, which is either 0, 1, or 2
483 * @supported_interfaces: a bitmask of supported PHY interface modes
484 *
485 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded
486 * in &struct rtl8365mb_chip_info for every port with an external interface.
487 */
488struct rtl8365mb_extint {
489 int port;
490 int id;
491 unsigned int supported_interfaces;
492};
493
494/**
495 * struct rtl8365mb_chip_info - static chip-specific info
496 * @name: human-readable chip name
497 * @chip_id: chip identifier
498 * @chip_ver: chip silicon revision
499 * @extints: available external interfaces
500 * @jam_table: chip-specific initialization jam table
501 * @jam_size: size of the chip's jam table
502 *
503 * These data are specific to a given chip in the family of switches supported
504 * by this driver. When adding support for another chip in the family, a new
505 * chip info should be added to the rtl8365mb_chip_infos array.
506 */
507struct rtl8365mb_chip_info {
508 const char *name;
509 u32 chip_id;
510 u32 chip_ver;
511 const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS];
512 const struct rtl8365mb_jam_tbl_entry *jam_table;
513 size_t jam_size;
514};
515
516/* Chip info for each supported switch in the family */
517#define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode)
518static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {
519 {
520 .name = "RTL8365MB-VC",
521 .chip_id = 0x6367,
522 .chip_ver = 0x0040,
523 .extints = {
524 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
525 PHY_INTF(RMII) | PHY_INTF(RGMII) },
526 },
527 .jam_table = rtl8365mb_init_jam_8365mb_vc,
528 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
529 },
530 {
531 .name = "RTL8367S",
532 .chip_id = 0x6367,
533 .chip_ver = 0x00A0,
534 .extints = {
535 { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) },
536 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |
537 PHY_INTF(RMII) | PHY_INTF(RGMII) },
538 },
539 .jam_table = rtl8365mb_init_jam_8365mb_vc,
540 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
541 },
542 {
543 .name = "RTL8367RB-VB",
544 .chip_id = 0x6367,
545 .chip_ver = 0x0020,
546 .extints = {
547 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |
548 PHY_INTF(RMII) | PHY_INTF(RGMII) },
549 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |
550 PHY_INTF(RMII) | PHY_INTF(RGMII) },
551 },
552 .jam_table = rtl8365mb_init_jam_8365mb_vc,
553 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),
554 },
555};
556
557enum rtl8365mb_stp_state {
558 RTL8365MB_STP_STATE_DISABLED = 0,
559 RTL8365MB_STP_STATE_BLOCKING = 1,
560 RTL8365MB_STP_STATE_LEARNING = 2,
561 RTL8365MB_STP_STATE_FORWARDING = 3,
562};
563
564enum rtl8365mb_cpu_insert {
565 RTL8365MB_CPU_INSERT_TO_ALL = 0,
566 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1,
567 RTL8365MB_CPU_INSERT_TO_NONE = 2,
568};
569
570enum rtl8365mb_cpu_position {
571 RTL8365MB_CPU_POS_AFTER_SA = 0,
572 RTL8365MB_CPU_POS_BEFORE_CRC = 1,
573};
574
575enum rtl8365mb_cpu_format {
576 RTL8365MB_CPU_FORMAT_8BYTES = 0,
577 RTL8365MB_CPU_FORMAT_4BYTES = 1,
578};
579
580enum rtl8365mb_cpu_rxlen {
581 RTL8365MB_CPU_RXLEN_72BYTES = 0,
582 RTL8365MB_CPU_RXLEN_64BYTES = 1,
583};
584
585/**
586 * struct rtl8365mb_cpu - CPU port configuration
587 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames
588 * @mask: port mask of ports that parse should parse CPU tags
589 * @trap_port: forward trapped frames to this port
590 * @insert: CPU tag insertion mode in switch->CPU frames
591 * @position: position of CPU tag in frame
592 * @rx_length: minimum CPU RX length
593 * @format: CPU tag format
594 *
595 * Represents the CPU tagging and CPU port configuration of the switch. These
596 * settings are configurable at runtime.
597 */
598struct rtl8365mb_cpu {
599 bool enable;
600 u32 mask;
601 u32 trap_port;
602 enum rtl8365mb_cpu_insert insert;
603 enum rtl8365mb_cpu_position position;
604 enum rtl8365mb_cpu_rxlen rx_length;
605 enum rtl8365mb_cpu_format format;
606};
607
608/**
609 * struct rtl8365mb_port - private per-port data
610 * @priv: pointer to parent realtek_priv data
611 * @index: DSA port index, same as dsa_port::index
612 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic
613 * access via rtl8365mb_get_stats64
614 * @stats_lock: protect the stats structure during read/update
615 * @mib_work: delayed work for polling MIB counters
616 */
617struct rtl8365mb_port {
618 struct realtek_priv *priv;
619 unsigned int index;
620 struct rtnl_link_stats64 stats;
621 spinlock_t stats_lock;
622 struct delayed_work mib_work;
623};
624
625/**
626 * struct rtl8365mb - driver private data
627 * @priv: pointer to parent realtek_priv data
628 * @irq: registered IRQ or zero
629 * @chip_info: chip-specific info about the attached switch
630 * @cpu: CPU tagging and CPU port configuration for this chip
631 * @mib_lock: prevent concurrent reads of MIB counters
632 * @ports: per-port data
633 *
634 * Private data for this driver.
635 */
636struct rtl8365mb {
637 struct realtek_priv *priv;
638 int irq;
639 const struct rtl8365mb_chip_info *chip_info;
640 struct rtl8365mb_cpu cpu;
641 struct mutex mib_lock;
642 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];
643};
644
645static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)
646{
647 u32 val;
648
649 return regmap_read_poll_timeout(priv->map_nolock,
650 RTL8365MB_INDIRECT_ACCESS_STATUS_REG,
651 val, !val, 10, 100);
652}
653
654static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,
655 u32 ocp_addr)
656{
657 u32 val;
658 int ret;
659
660 /* Set OCP prefix */
661 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);
662 ret = regmap_update_bits(
663 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG,
664 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,
665 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));
666 if (ret)
667 return ret;
668
669 /* Set PHY register address */
670 val = RTL8365MB_PHY_BASE;
671 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy);
672 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK,
673 ocp_addr >> 1);
674 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,
675 ocp_addr >> 6);
676 ret = regmap_write(priv->map_nolock,
677 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val);
678 if (ret)
679 return ret;
680
681 return 0;
682}
683
684static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,
685 u32 ocp_addr, u16 *data)
686{
687 u32 val;
688 int ret;
689
690 mutex_lock(&priv->map_lock);
691
692 ret = rtl8365mb_phy_poll_busy(priv);
693 if (ret)
694 goto out;
695
696 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
697 if (ret)
698 goto out;
699
700 /* Execute read operation */
701 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
702 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
703 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
704 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ);
705 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
706 val);
707 if (ret)
708 goto out;
709
710 ret = rtl8365mb_phy_poll_busy(priv);
711 if (ret)
712 goto out;
713
714 /* Get PHY register data */
715 ret = regmap_read(priv->map_nolock,
716 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val);
717 if (ret)
718 goto out;
719
720 *data = val & 0xFFFF;
721
722out:
723 mutex_unlock(&priv->map_lock);
724
725 return ret;
726}
727
728static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,
729 u32 ocp_addr, u16 data)
730{
731 u32 val;
732 int ret;
733
734 mutex_lock(&priv->map_lock);
735
736 ret = rtl8365mb_phy_poll_busy(priv);
737 if (ret)
738 goto out;
739
740 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);
741 if (ret)
742 goto out;
743
744 /* Set PHY register data */
745 ret = regmap_write(priv->map_nolock,
746 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data);
747 if (ret)
748 goto out;
749
750 /* Execute write operation */
751 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,
752 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |
753 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,
754 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE);
755 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,
756 val);
757 if (ret)
758 goto out;
759
760 ret = rtl8365mb_phy_poll_busy(priv);
761 if (ret)
762 goto out;
763
764out:
765 mutex_unlock(&priv->map_lock);
766
767 return 0;
768}
769
770static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum)
771{
772 u32 ocp_addr;
773 u16 val;
774 int ret;
775
776 if (phy > RTL8365MB_PHYADDRMAX)
777 return -EINVAL;
778
779 if (regnum > RTL8365MB_PHYREGMAX)
780 return -EINVAL;
781
782 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
783
784 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val);
785 if (ret) {
786 dev_err(priv->dev,
787 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy,
788 regnum, ocp_addr, ret);
789 return ret;
790 }
791
792 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",
793 phy, regnum, ocp_addr, val);
794
795 return val;
796}
797
798static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum,
799 u16 val)
800{
801 u32 ocp_addr;
802 int ret;
803
804 if (phy > RTL8365MB_PHYADDRMAX)
805 return -EINVAL;
806
807 if (regnum > RTL8365MB_PHYREGMAX)
808 return -EINVAL;
809
810 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;
811
812 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val);
813 if (ret) {
814 dev_err(priv->dev,
815 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy,
816 regnum, ocp_addr, ret);
817 return ret;
818 }
819
820 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",
821 phy, regnum, ocp_addr, val);
822
823 return 0;
824}
825
826static int rtl8365mb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum)
827{
828 return rtl8365mb_phy_read(ds->priv, phy, regnum);
829}
830
831static int rtl8365mb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum,
832 u16 val)
833{
834 return rtl8365mb_phy_write(ds->priv, phy, regnum, val);
835}
836
837static const struct rtl8365mb_extint *
838rtl8365mb_get_port_extint(struct realtek_priv *priv, int port)
839{
840 struct rtl8365mb *mb = priv->chip_data;
841 int i;
842
843 for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) {
844 const struct rtl8365mb_extint *extint =
845 &mb->chip_info->extints[i];
846
847 if (!extint->supported_interfaces)
848 continue;
849
850 if (extint->port == port)
851 return extint;
852 }
853
854 return NULL;
855}
856
857static enum dsa_tag_protocol
858rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port,
859 enum dsa_tag_protocol mp)
860{
861 struct realtek_priv *priv = ds->priv;
862 struct rtl8365mb_cpu *cpu;
863 struct rtl8365mb *mb;
864
865 mb = priv->chip_data;
866 cpu = &mb->cpu;
867
868 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC)
869 return DSA_TAG_PROTO_RTL8_4T;
870
871 return DSA_TAG_PROTO_RTL8_4;
872}
873
874static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,
875 phy_interface_t interface)
876{
877 const struct rtl8365mb_extint *extint =
878 rtl8365mb_get_port_extint(priv, port);
879 struct device_node *dn;
880 struct dsa_port *dp;
881 int tx_delay = 0;
882 int rx_delay = 0;
883 u32 val;
884 int ret;
885
886 if (!extint)
887 return -ENODEV;
888
889 dp = dsa_to_port(priv->ds, port);
890 dn = dp->dn;
891
892 /* Set the RGMII TX/RX delay
893 *
894 * The Realtek vendor driver indicates the following possible
895 * configuration settings:
896 *
897 * TX delay:
898 * 0 = no delay, 1 = 2 ns delay
899 * RX delay:
900 * 0 = no delay, 7 = maximum delay
901 * Each step is approximately 0.3 ns, so the maximum delay is about
902 * 2.1 ns.
903 *
904 * The vendor driver also states that this must be configured *before*
905 * forcing the external interface into a particular mode, which is done
906 * in the rtl8365mb_phylink_mac_link_{up,down} functions.
907 *
908 * Only configure an RGMII TX (resp. RX) delay if the
909 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is
910 * specified. We ignore the detail of the RGMII interface mode
911 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only
912 * property.
913 */
914 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) {
915 val = val / 1000; /* convert to ns */
916
917 if (val == 0 || val == 2)
918 tx_delay = val / 2;
919 else
920 dev_warn(priv->dev,
921 "RGMII TX delay must be 0 or 2 ns\n");
922 }
923
924 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) {
925 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */
926
927 if (val <= 7)
928 rx_delay = val;
929 else
930 dev_warn(priv->dev,
931 "RGMII RX delay must be 0 to 2.1 ns\n");
932 }
933
934 ret = regmap_update_bits(
935 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id),
936 RTL8365MB_EXT_RGMXF_TXDELAY_MASK |
937 RTL8365MB_EXT_RGMXF_RXDELAY_MASK,
938 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) |
939 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay));
940 if (ret)
941 return ret;
942
943 ret = regmap_update_bits(
944 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id),
945 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id),
946 RTL8365MB_EXT_PORT_MODE_RGMII
947 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(
948 extint->id));
949 if (ret)
950 return ret;
951
952 return 0;
953}
954
955static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,
956 bool link, int speed, int duplex,
957 bool tx_pause, bool rx_pause)
958{
959 const struct rtl8365mb_extint *extint =
960 rtl8365mb_get_port_extint(priv, port);
961 u32 r_tx_pause;
962 u32 r_rx_pause;
963 u32 r_duplex;
964 u32 r_speed;
965 u32 r_link;
966 int val;
967 int ret;
968
969 if (!extint)
970 return -ENODEV;
971
972 if (link) {
973 /* Force the link up with the desired configuration */
974 r_link = 1;
975 r_rx_pause = rx_pause ? 1 : 0;
976 r_tx_pause = tx_pause ? 1 : 0;
977
978 if (speed == SPEED_1000) {
979 r_speed = RTL8365MB_PORT_SPEED_1000M;
980 } else if (speed == SPEED_100) {
981 r_speed = RTL8365MB_PORT_SPEED_100M;
982 } else if (speed == SPEED_10) {
983 r_speed = RTL8365MB_PORT_SPEED_10M;
984 } else {
985 dev_err(priv->dev, "unsupported port speed %s\n",
986 phy_speed_to_str(speed));
987 return -EINVAL;
988 }
989
990 if (duplex == DUPLEX_FULL) {
991 r_duplex = 1;
992 } else if (duplex == DUPLEX_HALF) {
993 r_duplex = 0;
994 } else {
995 dev_err(priv->dev, "unsupported duplex %s\n",
996 phy_duplex_to_str(duplex));
997 return -EINVAL;
998 }
999 } else {
1000 /* Force the link down and reset any programmed configuration */
1001 r_link = 0;
1002 r_tx_pause = 0;
1003 r_rx_pause = 0;
1004 r_speed = 0;
1005 r_duplex = 0;
1006 }
1007
1008 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) |
1009 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK,
1010 r_tx_pause) |
1011 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK,
1012 r_rx_pause) |
1013 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) |
1014 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK,
1015 r_duplex) |
1016 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed);
1017 ret = regmap_write(priv->map,
1018 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id),
1019 val);
1020 if (ret)
1021 return ret;
1022
1023 return 0;
1024}
1025
1026static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port,
1027 struct phylink_config *config)
1028{
1029 const struct rtl8365mb_extint *extint =
1030 rtl8365mb_get_port_extint(ds->priv, port);
1031
1032 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
1033 MAC_10 | MAC_100 | MAC_1000FD;
1034
1035 if (!extint) {
1036 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1037 config->supported_interfaces);
1038
1039 /* GMII is the default interface mode for phylib, so
1040 * we have to support it for ports with integrated PHY.
1041 */
1042 __set_bit(PHY_INTERFACE_MODE_GMII,
1043 config->supported_interfaces);
1044 return;
1045 }
1046
1047 /* Populate according to the modes supported by _this driver_,
1048 * not necessarily the modes supported by the hardware, some of
1049 * which remain unimplemented.
1050 */
1051
1052 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII)
1053 phy_interface_set_rgmii(config->supported_interfaces);
1054}
1055
1056static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port,
1057 unsigned int mode,
1058 const struct phylink_link_state *state)
1059{
1060 struct realtek_priv *priv = ds->priv;
1061 int ret;
1062
1063 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) {
1064 dev_err(priv->dev,
1065 "port %d supports only conventional PHY or fixed-link\n",
1066 port);
1067 return;
1068 }
1069
1070 if (phy_interface_mode_is_rgmii(state->interface)) {
1071 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface);
1072 if (ret)
1073 dev_err(priv->dev,
1074 "failed to configure RGMII mode on port %d: %d\n",
1075 port, ret);
1076 return;
1077 }
1078
1079 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also
1080 * supports
1081 */
1082}
1083
1084static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port,
1085 unsigned int mode,
1086 phy_interface_t interface)
1087{
1088 struct realtek_priv *priv = ds->priv;
1089 struct rtl8365mb_port *p;
1090 struct rtl8365mb *mb;
1091 int ret;
1092
1093 mb = priv->chip_data;
1094 p = &mb->ports[port];
1095 cancel_delayed_work_sync(&p->mib_work);
1096
1097 if (phy_interface_mode_is_rgmii(interface)) {
1098 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0,
1099 false, false);
1100 if (ret)
1101 dev_err(priv->dev,
1102 "failed to reset forced mode on port %d: %d\n",
1103 port, ret);
1104
1105 return;
1106 }
1107}
1108
1109static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port,
1110 unsigned int mode,
1111 phy_interface_t interface,
1112 struct phy_device *phydev, int speed,
1113 int duplex, bool tx_pause,
1114 bool rx_pause)
1115{
1116 struct realtek_priv *priv = ds->priv;
1117 struct rtl8365mb_port *p;
1118 struct rtl8365mb *mb;
1119 int ret;
1120
1121 mb = priv->chip_data;
1122 p = &mb->ports[port];
1123 schedule_delayed_work(&p->mib_work, 0);
1124
1125 if (phy_interface_mode_is_rgmii(interface)) {
1126 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed,
1127 duplex, tx_pause,
1128 rx_pause);
1129 if (ret)
1130 dev_err(priv->dev,
1131 "failed to force mode on port %d: %d\n", port,
1132 ret);
1133
1134 return;
1135 }
1136}
1137
1138static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port,
1139 u8 state)
1140{
1141 struct realtek_priv *priv = ds->priv;
1142 enum rtl8365mb_stp_state val;
1143 int msti = 0;
1144
1145 switch (state) {
1146 case BR_STATE_DISABLED:
1147 val = RTL8365MB_STP_STATE_DISABLED;
1148 break;
1149 case BR_STATE_BLOCKING:
1150 case BR_STATE_LISTENING:
1151 val = RTL8365MB_STP_STATE_BLOCKING;
1152 break;
1153 case BR_STATE_LEARNING:
1154 val = RTL8365MB_STP_STATE_LEARNING;
1155 break;
1156 case BR_STATE_FORWARDING:
1157 val = RTL8365MB_STP_STATE_FORWARDING;
1158 break;
1159 default:
1160 dev_err(priv->dev, "invalid STP state: %u\n", state);
1161 return;
1162 }
1163
1164 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port),
1165 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port),
1166 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port));
1167}
1168
1169static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,
1170 bool enable)
1171{
1172 /* Enable/disable learning by limiting the number of L2 addresses the
1173 * port can learn. Realtek documentation states that a limit of zero
1174 * disables learning. When enabling learning, set it to the chip's
1175 * maximum.
1176 */
1177 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),
1178 enable ? RTL8365MB_LEARN_LIMIT_MAX : 0);
1179}
1180
1181static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port,
1182 u32 mask)
1183{
1184 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);
1185}
1186
1187static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port,
1188 u32 offset, u32 length, u64 *mibvalue)
1189{
1190 u64 tmpvalue = 0;
1191 u32 val;
1192 int ret;
1193 int i;
1194
1195 /* The MIB address is an SRAM address. We request a particular address
1196 * and then poll the control register before reading the value from some
1197 * counter registers.
1198 */
1199 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG,
1200 RTL8365MB_MIB_ADDRESS(port, offset));
1201 if (ret)
1202 return ret;
1203
1204 /* Poll for completion */
1205 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val,
1206 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK),
1207 10, 100);
1208 if (ret)
1209 return ret;
1210
1211 /* Presumably this indicates a MIB counter read failure */
1212 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK)
1213 return -EIO;
1214
1215 /* There are four MIB counter registers each holding a 16 bit word of a
1216 * MIB counter. Depending on the offset, we should read from the upper
1217 * two or lower two registers. In case the MIB counter is 4 words, we
1218 * read from all four registers.
1219 */
1220 if (length == 4)
1221 offset = 3;
1222 else
1223 offset = (offset + 1) % 4;
1224
1225 /* Read the MIB counter 16 bits at a time */
1226 for (i = 0; i < length; i++) {
1227 ret = regmap_read(priv->map,
1228 RTL8365MB_MIB_COUNTER_REG(offset - i), &val);
1229 if (ret)
1230 return ret;
1231
1232 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF);
1233 }
1234
1235 /* Only commit the result if no error occurred */
1236 *mibvalue = tmpvalue;
1237
1238 return 0;
1239}
1240
1241static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
1242{
1243 struct realtek_priv *priv = ds->priv;
1244 struct rtl8365mb *mb;
1245 int ret;
1246 int i;
1247
1248 mb = priv->chip_data;
1249
1250 mutex_lock(&mb->mib_lock);
1251 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1252 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1253
1254 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1255 mib->length, &data[i]);
1256 if (ret) {
1257 dev_err(priv->dev,
1258 "failed to read port %d counters: %d\n", port,
1259 ret);
1260 break;
1261 }
1262 }
1263 mutex_unlock(&mb->mib_lock);
1264}
1265
1266static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data)
1267{
1268 int i;
1269
1270 if (stringset != ETH_SS_STATS)
1271 return;
1272
1273 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1274 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1275
1276 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN);
1277 }
1278}
1279
1280static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset)
1281{
1282 if (sset != ETH_SS_STATS)
1283 return -EOPNOTSUPP;
1284
1285 return RTL8365MB_MIB_END;
1286}
1287
1288static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port,
1289 struct ethtool_eth_phy_stats *phy_stats)
1290{
1291 struct realtek_priv *priv = ds->priv;
1292 struct rtl8365mb_mib_counter *mib;
1293 struct rtl8365mb *mb;
1294
1295 mb = priv->chip_data;
1296 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors];
1297
1298 mutex_lock(&mb->mib_lock);
1299 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1300 &phy_stats->SymbolErrorDuringCarrier);
1301 mutex_unlock(&mb->mib_lock);
1302}
1303
1304static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port,
1305 struct ethtool_eth_mac_stats *mac_stats)
1306{
1307 u64 cnt[RTL8365MB_MIB_END] = {
1308 [RTL8365MB_MIB_ifOutOctets] = 1,
1309 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1310 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1311 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1312 [RTL8365MB_MIB_dot3OutPauseFrames] = 1,
1313 [RTL8365MB_MIB_ifOutDiscards] = 1,
1314 [RTL8365MB_MIB_ifInOctets] = 1,
1315 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1316 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1317 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1318 [RTL8365MB_MIB_dot3InPauseFrames] = 1,
1319 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1,
1320 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1,
1321 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1322 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1,
1323 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1324 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1,
1325
1326 };
1327 struct realtek_priv *priv = ds->priv;
1328 struct rtl8365mb *mb;
1329 int ret;
1330 int i;
1331
1332 mb = priv->chip_data;
1333
1334 mutex_lock(&mb->mib_lock);
1335 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1336 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];
1337
1338 /* Only fetch required MIB counters (marked = 1 above) */
1339 if (!cnt[i])
1340 continue;
1341
1342 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,
1343 mib->length, &cnt[i]);
1344 if (ret)
1345 break;
1346 }
1347 mutex_unlock(&mb->mib_lock);
1348
1349 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into
1350 * IEEE 802.3 Managed Objects. This is not always completely faithful,
1351 * but we try out best. See RFC 3635 for a detailed treatment of the
1352 * subject.
1353 */
1354
1355 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1356 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1357 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] +
1358 cnt[RTL8365MB_MIB_dot3OutPauseFrames] -
1359 cnt[RTL8365MB_MIB_ifOutDiscards];
1360 mac_stats->SingleCollisionFrames =
1361 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames];
1362 mac_stats->MultipleCollisionFrames =
1363 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames];
1364 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1365 cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1366 cnt[RTL8365MB_MIB_ifInBroadcastPkts] +
1367 cnt[RTL8365MB_MIB_dot3InPauseFrames];
1368 mac_stats->FrameCheckSequenceErrors =
1369 cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1370 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] -
1371 18 * mac_stats->FramesTransmittedOK;
1372 mac_stats->FramesWithDeferredXmissions =
1373 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions];
1374 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1375 mac_stats->FramesAbortedDueToXSColls =
1376 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions];
1377 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] -
1378 18 * mac_stats->FramesReceivedOK;
1379 mac_stats->MulticastFramesXmittedOK =
1380 cnt[RTL8365MB_MIB_ifOutMulticastPkts];
1381 mac_stats->BroadcastFramesXmittedOK =
1382 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1383 mac_stats->MulticastFramesReceivedOK =
1384 cnt[RTL8365MB_MIB_ifInMulticastPkts];
1385 mac_stats->BroadcastFramesReceivedOK =
1386 cnt[RTL8365MB_MIB_ifInBroadcastPkts];
1387}
1388
1389static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port,
1390 struct ethtool_eth_ctrl_stats *ctrl_stats)
1391{
1392 struct realtek_priv *priv = ds->priv;
1393 struct rtl8365mb_mib_counter *mib;
1394 struct rtl8365mb *mb;
1395
1396 mb = priv->chip_data;
1397 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes];
1398
1399 mutex_lock(&mb->mib_lock);
1400 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,
1401 &ctrl_stats->UnsupportedOpcodesReceived);
1402 mutex_unlock(&mb->mib_lock);
1403}
1404
1405static void rtl8365mb_stats_update(struct realtek_priv *priv, int port)
1406{
1407 u64 cnt[RTL8365MB_MIB_END] = {
1408 [RTL8365MB_MIB_ifOutOctets] = 1,
1409 [RTL8365MB_MIB_ifOutUcastPkts] = 1,
1410 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,
1411 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,
1412 [RTL8365MB_MIB_ifOutDiscards] = 1,
1413 [RTL8365MB_MIB_ifInOctets] = 1,
1414 [RTL8365MB_MIB_ifInUcastPkts] = 1,
1415 [RTL8365MB_MIB_ifInMulticastPkts] = 1,
1416 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,
1417 [RTL8365MB_MIB_etherStatsDropEvents] = 1,
1418 [RTL8365MB_MIB_etherStatsCollisions] = 1,
1419 [RTL8365MB_MIB_etherStatsFragments] = 1,
1420 [RTL8365MB_MIB_etherStatsJabbers] = 1,
1421 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,
1422 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,
1423 };
1424 struct rtl8365mb *mb = priv->chip_data;
1425 struct rtnl_link_stats64 *stats;
1426 int ret;
1427 int i;
1428
1429 stats = &mb->ports[port].stats;
1430
1431 mutex_lock(&mb->mib_lock);
1432 for (i = 0; i < RTL8365MB_MIB_END; i++) {
1433 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i];
1434
1435 /* Only fetch required MIB counters (marked = 1 above) */
1436 if (!cnt[i])
1437 continue;
1438
1439 ret = rtl8365mb_mib_counter_read(priv, port, c->offset,
1440 c->length, &cnt[i]);
1441 if (ret)
1442 break;
1443 }
1444 mutex_unlock(&mb->mib_lock);
1445
1446 /* Don't update statistics if there was an error reading the counters */
1447 if (ret)
1448 return;
1449
1450 spin_lock(&mb->ports[port].stats_lock);
1451
1452 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] +
1453 cnt[RTL8365MB_MIB_ifInMulticastPkts] +
1454 cnt[RTL8365MB_MIB_ifInBroadcastPkts] -
1455 cnt[RTL8365MB_MIB_ifOutDiscards];
1456
1457 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] +
1458 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +
1459 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];
1460
1461 /* if{In,Out}Octets includes FCS - remove it */
1462 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets;
1463 stats->tx_bytes =
1464 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets;
1465
1466 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents];
1467 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards];
1468
1469 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts];
1470 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions];
1471
1472 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] +
1473 cnt[RTL8365MB_MIB_etherStatsJabbers];
1474 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors];
1475 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors;
1476
1477 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards];
1478 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];
1479 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors;
1480
1481 spin_unlock(&mb->ports[port].stats_lock);
1482}
1483
1484static void rtl8365mb_stats_poll(struct work_struct *work)
1485{
1486 struct rtl8365mb_port *p = container_of(to_delayed_work(work),
1487 struct rtl8365mb_port,
1488 mib_work);
1489 struct realtek_priv *priv = p->priv;
1490
1491 rtl8365mb_stats_update(priv, p->index);
1492
1493 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES);
1494}
1495
1496static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port,
1497 struct rtnl_link_stats64 *s)
1498{
1499 struct realtek_priv *priv = ds->priv;
1500 struct rtl8365mb_port *p;
1501 struct rtl8365mb *mb;
1502
1503 mb = priv->chip_data;
1504 p = &mb->ports[port];
1505
1506 spin_lock(&p->stats_lock);
1507 memcpy(s, &p->stats, sizeof(*s));
1508 spin_unlock(&p->stats_lock);
1509}
1510
1511static void rtl8365mb_stats_setup(struct realtek_priv *priv)
1512{
1513 struct rtl8365mb *mb = priv->chip_data;
1514 int i;
1515
1516 /* Per-chip global mutex to protect MIB counter access, since doing
1517 * so requires accessing a series of registers in a particular order.
1518 */
1519 mutex_init(&mb->mib_lock);
1520
1521 for (i = 0; i < priv->num_ports; i++) {
1522 struct rtl8365mb_port *p = &mb->ports[i];
1523
1524 if (dsa_is_unused_port(priv->ds, i))
1525 continue;
1526
1527 /* Per-port spinlock to protect the stats64 data */
1528 spin_lock_init(&p->stats_lock);
1529
1530 /* This work polls the MIB counters and keeps the stats64 data
1531 * up-to-date.
1532 */
1533 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll);
1534 }
1535}
1536
1537static void rtl8365mb_stats_teardown(struct realtek_priv *priv)
1538{
1539 struct rtl8365mb *mb = priv->chip_data;
1540 int i;
1541
1542 for (i = 0; i < priv->num_ports; i++) {
1543 struct rtl8365mb_port *p = &mb->ports[i];
1544
1545 if (dsa_is_unused_port(priv->ds, i))
1546 continue;
1547
1548 cancel_delayed_work_sync(&p->mib_work);
1549 }
1550}
1551
1552static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg,
1553 u32 *val)
1554{
1555 int ret;
1556
1557 ret = regmap_read(priv->map, reg, val);
1558 if (ret)
1559 return ret;
1560
1561 return regmap_write(priv->map, reg, *val);
1562}
1563
1564static irqreturn_t rtl8365mb_irq(int irq, void *data)
1565{
1566 struct realtek_priv *priv = data;
1567 unsigned long line_changes = 0;
1568 u32 stat;
1569 int line;
1570 int ret;
1571
1572 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG,
1573 &stat);
1574 if (ret)
1575 goto out_error;
1576
1577 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) {
1578 u32 linkdown_ind;
1579 u32 linkup_ind;
1580 u32 val;
1581
1582 ret = rtl8365mb_get_and_clear_status_reg(
1583 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val);
1584 if (ret)
1585 goto out_error;
1586
1587 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val);
1588
1589 ret = rtl8365mb_get_and_clear_status_reg(
1590 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val);
1591 if (ret)
1592 goto out_error;
1593
1594 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val);
1595
1596 line_changes = linkup_ind | linkdown_ind;
1597 }
1598
1599 if (!line_changes)
1600 goto out_none;
1601
1602 for_each_set_bit(line, &line_changes, priv->num_ports) {
1603 int child_irq = irq_find_mapping(priv->irqdomain, line);
1604
1605 handle_nested_irq(child_irq);
1606 }
1607
1608 return IRQ_HANDLED;
1609
1610out_error:
1611 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret);
1612
1613out_none:
1614 return IRQ_NONE;
1615}
1616
1617static struct irq_chip rtl8365mb_irq_chip = {
1618 .name = "rtl8365mb",
1619 /* The hardware doesn't support masking IRQs on a per-port basis */
1620};
1621
1622static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq,
1623 irq_hw_number_t hwirq)
1624{
1625 irq_set_chip_data(irq, domain->host_data);
1626 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq);
1627 irq_set_nested_thread(irq, 1);
1628 irq_set_noprobe(irq);
1629
1630 return 0;
1631}
1632
1633static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq)
1634{
1635 irq_set_nested_thread(irq, 0);
1636 irq_set_chip_and_handler(irq, NULL, NULL);
1637 irq_set_chip_data(irq, NULL);
1638}
1639
1640static const struct irq_domain_ops rtl8365mb_irqdomain_ops = {
1641 .map = rtl8365mb_irq_map,
1642 .unmap = rtl8365mb_irq_unmap,
1643 .xlate = irq_domain_xlate_onecell,
1644};
1645
1646static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable)
1647{
1648 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG,
1649 RTL8365MB_INTR_LINK_CHANGE_MASK,
1650 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK,
1651 enable ? 1 : 0));
1652}
1653
1654static int rtl8365mb_irq_enable(struct realtek_priv *priv)
1655{
1656 return rtl8365mb_set_irq_enable(priv, true);
1657}
1658
1659static int rtl8365mb_irq_disable(struct realtek_priv *priv)
1660{
1661 return rtl8365mb_set_irq_enable(priv, false);
1662}
1663
1664static int rtl8365mb_irq_setup(struct realtek_priv *priv)
1665{
1666 struct rtl8365mb *mb = priv->chip_data;
1667 struct device_node *intc;
1668 u32 irq_trig;
1669 int virq;
1670 int irq;
1671 u32 val;
1672 int ret;
1673 int i;
1674
1675 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
1676 if (!intc) {
1677 dev_err(priv->dev, "missing child interrupt-controller node\n");
1678 return -EINVAL;
1679 }
1680
1681 /* rtl8365mb IRQs cascade off this one */
1682 irq = of_irq_get(intc, 0);
1683 if (irq <= 0) {
1684 if (irq != -EPROBE_DEFER)
1685 dev_err(priv->dev, "failed to get parent irq: %d\n",
1686 irq);
1687 ret = irq ? irq : -EINVAL;
1688 goto out_put_node;
1689 }
1690
1691 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports,
1692 &rtl8365mb_irqdomain_ops, priv);
1693 if (!priv->irqdomain) {
1694 dev_err(priv->dev, "failed to add irq domain\n");
1695 ret = -ENOMEM;
1696 goto out_put_node;
1697 }
1698
1699 for (i = 0; i < priv->num_ports; i++) {
1700 virq = irq_create_mapping(priv->irqdomain, i);
1701 if (!virq) {
1702 dev_err(priv->dev,
1703 "failed to create irq domain mapping\n");
1704 ret = -EINVAL;
1705 goto out_remove_irqdomain;
1706 }
1707
1708 irq_set_parent(virq, irq);
1709 }
1710
1711 /* Configure chip interrupt signal polarity */
1712 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1713 switch (irq_trig) {
1714 case IRQF_TRIGGER_RISING:
1715 case IRQF_TRIGGER_HIGH:
1716 val = RTL8365MB_INTR_POLARITY_HIGH;
1717 break;
1718 case IRQF_TRIGGER_FALLING:
1719 case IRQF_TRIGGER_LOW:
1720 val = RTL8365MB_INTR_POLARITY_LOW;
1721 break;
1722 default:
1723 dev_err(priv->dev, "unsupported irq trigger type %u\n",
1724 irq_trig);
1725 ret = -EINVAL;
1726 goto out_remove_irqdomain;
1727 }
1728
1729 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG,
1730 RTL8365MB_INTR_POLARITY_MASK,
1731 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val));
1732 if (ret)
1733 goto out_remove_irqdomain;
1734
1735 /* Disable the interrupt in case the chip has it enabled on reset */
1736 ret = rtl8365mb_irq_disable(priv);
1737 if (ret)
1738 goto out_remove_irqdomain;
1739
1740 /* Clear the interrupt status register */
1741 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG,
1742 RTL8365MB_INTR_ALL_MASK);
1743 if (ret)
1744 goto out_remove_irqdomain;
1745
1746 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT,
1747 "rtl8365mb", priv);
1748 if (ret) {
1749 dev_err(priv->dev, "failed to request irq: %d\n", ret);
1750 goto out_remove_irqdomain;
1751 }
1752
1753 /* Store the irq so that we know to free it during teardown */
1754 mb->irq = irq;
1755
1756 ret = rtl8365mb_irq_enable(priv);
1757 if (ret)
1758 goto out_free_irq;
1759
1760 of_node_put(intc);
1761
1762 return 0;
1763
1764out_free_irq:
1765 free_irq(mb->irq, priv);
1766 mb->irq = 0;
1767
1768out_remove_irqdomain:
1769 for (i = 0; i < priv->num_ports; i++) {
1770 virq = irq_find_mapping(priv->irqdomain, i);
1771 irq_dispose_mapping(virq);
1772 }
1773
1774 irq_domain_remove(priv->irqdomain);
1775 priv->irqdomain = NULL;
1776
1777out_put_node:
1778 of_node_put(intc);
1779
1780 return ret;
1781}
1782
1783static void rtl8365mb_irq_teardown(struct realtek_priv *priv)
1784{
1785 struct rtl8365mb *mb = priv->chip_data;
1786 int virq;
1787 int i;
1788
1789 if (mb->irq) {
1790 free_irq(mb->irq, priv);
1791 mb->irq = 0;
1792 }
1793
1794 if (priv->irqdomain) {
1795 for (i = 0; i < priv->num_ports; i++) {
1796 virq = irq_find_mapping(priv->irqdomain, i);
1797 irq_dispose_mapping(virq);
1798 }
1799
1800 irq_domain_remove(priv->irqdomain);
1801 priv->irqdomain = NULL;
1802 }
1803}
1804
1805static int rtl8365mb_cpu_config(struct realtek_priv *priv)
1806{
1807 struct rtl8365mb *mb = priv->chip_data;
1808 struct rtl8365mb_cpu *cpu = &mb->cpu;
1809 u32 val;
1810 int ret;
1811
1812 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG,
1813 RTL8365MB_CPU_PORT_MASK_MASK,
1814 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK,
1815 cpu->mask));
1816 if (ret)
1817 return ret;
1818
1819 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |
1820 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) |
1821 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) |
1822 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) |
1823 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) |
1824 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) |
1825 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK,
1826 cpu->trap_port >> 3 & 0x1);
1827 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val);
1828 if (ret)
1829 return ret;
1830
1831 return 0;
1832}
1833
1834static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds,
1835 enum dsa_tag_protocol proto)
1836{
1837 struct realtek_priv *priv = ds->priv;
1838 struct rtl8365mb_cpu *cpu;
1839 struct rtl8365mb *mb;
1840
1841 mb = priv->chip_data;
1842 cpu = &mb->cpu;
1843
1844 switch (proto) {
1845 case DSA_TAG_PROTO_RTL8_4:
1846 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1847 cpu->position = RTL8365MB_CPU_POS_AFTER_SA;
1848 break;
1849 case DSA_TAG_PROTO_RTL8_4T:
1850 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;
1851 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC;
1852 break;
1853 /* The switch also supports a 4-byte format, similar to rtl4a but with
1854 * the same 0x04 8-bit version and probably 8-bit port source/dest.
1855 * There is no public doc about it. Not supported yet and it will probably
1856 * never be.
1857 */
1858 default:
1859 return -EPROTONOSUPPORT;
1860 }
1861
1862 return rtl8365mb_cpu_config(priv);
1863}
1864
1865static int rtl8365mb_switch_init(struct realtek_priv *priv)
1866{
1867 struct rtl8365mb *mb = priv->chip_data;
1868 const struct rtl8365mb_chip_info *ci;
1869 int ret;
1870 int i;
1871
1872 ci = mb->chip_info;
1873
1874 /* Do any chip-specific init jam before getting to the common stuff */
1875 if (ci->jam_table) {
1876 for (i = 0; i < ci->jam_size; i++) {
1877 ret = regmap_write(priv->map, ci->jam_table[i].reg,
1878 ci->jam_table[i].val);
1879 if (ret)
1880 return ret;
1881 }
1882 }
1883
1884 /* Common init jam */
1885 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) {
1886 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg,
1887 rtl8365mb_init_jam_common[i].val);
1888 if (ret)
1889 return ret;
1890 }
1891
1892 return 0;
1893}
1894
1895static int rtl8365mb_reset_chip(struct realtek_priv *priv)
1896{
1897 u32 val;
1898
1899 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG,
1900 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1));
1901
1902 /* Realtek documentation says the chip needs 1 second to reset. Sleep
1903 * for 100 ms before accessing any registers to prevent ACK timeouts.
1904 */
1905 msleep(100);
1906 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,
1907 !(val & RTL8365MB_CHIP_RESET_HW_MASK),
1908 20000, 1e6);
1909}
1910
1911static int rtl8365mb_setup(struct dsa_switch *ds)
1912{
1913 struct realtek_priv *priv = ds->priv;
1914 struct rtl8365mb_cpu *cpu;
1915 struct dsa_port *cpu_dp;
1916 struct rtl8365mb *mb;
1917 int ret;
1918 int i;
1919
1920 mb = priv->chip_data;
1921 cpu = &mb->cpu;
1922
1923 ret = rtl8365mb_reset_chip(priv);
1924 if (ret) {
1925 dev_err(priv->dev, "failed to reset chip: %d\n", ret);
1926 goto out_error;
1927 }
1928
1929 /* Configure switch to vendor-defined initial state */
1930 ret = rtl8365mb_switch_init(priv);
1931 if (ret) {
1932 dev_err(priv->dev, "failed to initialize switch: %d\n", ret);
1933 goto out_error;
1934 }
1935
1936 /* Set up cascading IRQs */
1937 ret = rtl8365mb_irq_setup(priv);
1938 if (ret == -EPROBE_DEFER)
1939 return ret;
1940 else if (ret)
1941 dev_info(priv->dev, "no interrupt support\n");
1942
1943 /* Configure CPU tagging */
1944 dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) {
1945 cpu->mask |= BIT(cpu_dp->index);
1946
1947 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS)
1948 cpu->trap_port = cpu_dp->index;
1949 }
1950 cpu->enable = cpu->mask > 0;
1951 ret = rtl8365mb_cpu_config(priv);
1952 if (ret)
1953 goto out_teardown_irq;
1954
1955 /* Configure ports */
1956 for (i = 0; i < priv->num_ports; i++) {
1957 struct rtl8365mb_port *p = &mb->ports[i];
1958
1959 if (dsa_is_unused_port(priv->ds, i))
1960 continue;
1961
1962 /* Forward only to the CPU */
1963 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask);
1964 if (ret)
1965 goto out_teardown_irq;
1966
1967 /* Disable learning */
1968 ret = rtl8365mb_port_set_learning(priv, i, false);
1969 if (ret)
1970 goto out_teardown_irq;
1971
1972 /* Set the initial STP state of all ports to DISABLED, otherwise
1973 * ports will still forward frames to the CPU despite being
1974 * administratively down by default.
1975 */
1976 rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED);
1977
1978 /* Set up per-port private data */
1979 p->priv = priv;
1980 p->index = i;
1981 }
1982
1983 /* Set maximum packet length to 1536 bytes */
1984 ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,
1985 RTL8365MB_CFG0_MAX_LEN_MASK,
1986 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536));
1987 if (ret)
1988 goto out_teardown_irq;
1989
1990 if (priv->setup_interface) {
1991 ret = priv->setup_interface(ds);
1992 if (ret) {
1993 dev_err(priv->dev, "could not set up MDIO bus\n");
1994 goto out_teardown_irq;
1995 }
1996 }
1997
1998 /* Start statistics counter polling */
1999 rtl8365mb_stats_setup(priv);
2000
2001 return 0;
2002
2003out_teardown_irq:
2004 rtl8365mb_irq_teardown(priv);
2005
2006out_error:
2007 return ret;
2008}
2009
2010static void rtl8365mb_teardown(struct dsa_switch *ds)
2011{
2012 struct realtek_priv *priv = ds->priv;
2013
2014 rtl8365mb_stats_teardown(priv);
2015 rtl8365mb_irq_teardown(priv);
2016}
2017
2018static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver)
2019{
2020 int ret;
2021
2022 /* For some reason we have to write a magic value to an arbitrary
2023 * register whenever accessing the chip ID/version registers.
2024 */
2025 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE);
2026 if (ret)
2027 return ret;
2028
2029 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id);
2030 if (ret)
2031 return ret;
2032
2033 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver);
2034 if (ret)
2035 return ret;
2036
2037 /* Reset magic register */
2038 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0);
2039 if (ret)
2040 return ret;
2041
2042 return 0;
2043}
2044
2045static int rtl8365mb_detect(struct realtek_priv *priv)
2046{
2047 struct rtl8365mb *mb = priv->chip_data;
2048 u32 chip_id;
2049 u32 chip_ver;
2050 int ret;
2051 int i;
2052
2053 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver);
2054 if (ret) {
2055 dev_err(priv->dev, "failed to read chip id and version: %d\n",
2056 ret);
2057 return ret;
2058 }
2059
2060 for (i = 0; i < ARRAY_SIZE(rtl8365mb_chip_infos); i++) {
2061 const struct rtl8365mb_chip_info *ci = &rtl8365mb_chip_infos[i];
2062
2063 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) {
2064 mb->chip_info = ci;
2065 break;
2066 }
2067 }
2068
2069 if (!mb->chip_info) {
2070 dev_err(priv->dev,
2071 "unrecognized switch (id=0x%04x, ver=0x%04x)", chip_id,
2072 chip_ver);
2073 return -ENODEV;
2074 }
2075
2076 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name);
2077
2078 priv->num_ports = RTL8365MB_MAX_NUM_PORTS;
2079 mb->priv = priv;
2080 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;
2081 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
2082 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
2083 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
2084 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;
2085
2086 return 0;
2087}
2088
2089static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = {
2090 .get_tag_protocol = rtl8365mb_get_tag_protocol,
2091 .change_tag_protocol = rtl8365mb_change_tag_protocol,
2092 .setup = rtl8365mb_setup,
2093 .teardown = rtl8365mb_teardown,
2094 .phylink_get_caps = rtl8365mb_phylink_get_caps,
2095 .phylink_mac_config = rtl8365mb_phylink_mac_config,
2096 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down,
2097 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up,
2098 .port_stp_state_set = rtl8365mb_port_stp_state_set,
2099 .get_strings = rtl8365mb_get_strings,
2100 .get_ethtool_stats = rtl8365mb_get_ethtool_stats,
2101 .get_sset_count = rtl8365mb_get_sset_count,
2102 .get_eth_phy_stats = rtl8365mb_get_phy_stats,
2103 .get_eth_mac_stats = rtl8365mb_get_mac_stats,
2104 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,
2105 .get_stats64 = rtl8365mb_get_stats64,
2106};
2107
2108static const struct dsa_switch_ops rtl8365mb_switch_ops_mdio = {
2109 .get_tag_protocol = rtl8365mb_get_tag_protocol,
2110 .change_tag_protocol = rtl8365mb_change_tag_protocol,
2111 .setup = rtl8365mb_setup,
2112 .teardown = rtl8365mb_teardown,
2113 .phylink_get_caps = rtl8365mb_phylink_get_caps,
2114 .phylink_mac_config = rtl8365mb_phylink_mac_config,
2115 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down,
2116 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up,
2117 .phy_read = rtl8365mb_dsa_phy_read,
2118 .phy_write = rtl8365mb_dsa_phy_write,
2119 .port_stp_state_set = rtl8365mb_port_stp_state_set,
2120 .get_strings = rtl8365mb_get_strings,
2121 .get_ethtool_stats = rtl8365mb_get_ethtool_stats,
2122 .get_sset_count = rtl8365mb_get_sset_count,
2123 .get_eth_phy_stats = rtl8365mb_get_phy_stats,
2124 .get_eth_mac_stats = rtl8365mb_get_mac_stats,
2125 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,
2126 .get_stats64 = rtl8365mb_get_stats64,
2127};
2128
2129static const struct realtek_ops rtl8365mb_ops = {
2130 .detect = rtl8365mb_detect,
2131 .phy_read = rtl8365mb_phy_read,
2132 .phy_write = rtl8365mb_phy_write,
2133};
2134
2135const struct realtek_variant rtl8365mb_variant = {
2136 .ds_ops_smi = &rtl8365mb_switch_ops_smi,
2137 .ds_ops_mdio = &rtl8365mb_switch_ops_mdio,
2138 .ops = &rtl8365mb_ops,
2139 .clk_delay = 10,
2140 .cmd_read = 0xb9,
2141 .cmd_write = 0xb8,
2142 .chip_data_sz = sizeof(struct rtl8365mb),
2143};
2144EXPORT_SYMBOL_GPL(rtl8365mb_variant);
2145
2146MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>");
2147MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch");
2148MODULE_LICENSE("GPL");