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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2014 IBM Corp.
4 */
5
6#include <linux/pci_regs.h>
7#include <linux/pci_ids.h>
8#include <linux/device.h>
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sort.h>
13#include <linux/pci.h>
14#include <linux/of.h>
15#include <linux/delay.h>
16#include <asm/opal.h>
17#include <asm/msi_bitmap.h>
18#include <asm/pnv-pci.h>
19#include <asm/io.h>
20#include <asm/reg.h>
21
22#include "cxl.h"
23#include <misc/cxl.h>
24
25
26#define CXL_PCI_VSEC_ID 0x1280
27#define CXL_VSEC_MIN_SIZE 0x80
28
29#define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
30 { \
31 pci_read_config_word(dev, vsec + 0x6, dest); \
32 *dest >>= 4; \
33 }
34#define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
35 pci_read_config_byte(dev, vsec + 0x8, dest)
36
37#define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
38 pci_read_config_byte(dev, vsec + 0x9, dest)
39#define CXL_STATUS_SECOND_PORT 0x80
40#define CXL_STATUS_MSI_X_FULL 0x40
41#define CXL_STATUS_MSI_X_SINGLE 0x20
42#define CXL_STATUS_FLASH_RW 0x08
43#define CXL_STATUS_FLASH_RO 0x04
44#define CXL_STATUS_LOADABLE_AFU 0x02
45#define CXL_STATUS_LOADABLE_PSL 0x01
46/* If we see these features we won't try to use the card */
47#define CXL_UNSUPPORTED_FEATURES \
48 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
49
50#define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
51 pci_read_config_byte(dev, vsec + 0xa, dest)
52#define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
53 pci_write_config_byte(dev, vsec + 0xa, val)
54#define CXL_VSEC_PROTOCOL_MASK 0xe0
55#define CXL_VSEC_PROTOCOL_1024TB 0x80
56#define CXL_VSEC_PROTOCOL_512TB 0x40
57#define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
58#define CXL_VSEC_PROTOCOL_ENABLE 0x01
59
60#define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
61 pci_read_config_word(dev, vsec + 0xc, dest)
62#define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
63 pci_read_config_byte(dev, vsec + 0xe, dest)
64#define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
65 pci_read_config_byte(dev, vsec + 0xf, dest)
66#define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0x10, dest)
68
69#define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
70 pci_read_config_byte(dev, vsec + 0x13, dest)
71#define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
72 pci_write_config_byte(dev, vsec + 0x13, val)
73#define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
74#define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
75#define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
76
77#define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
78 pci_read_config_dword(dev, vsec + 0x20, dest)
79#define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
80 pci_read_config_dword(dev, vsec + 0x24, dest)
81#define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
82 pci_read_config_dword(dev, vsec + 0x28, dest)
83#define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x2c, dest)
85
86
87/* This works a little different than the p1/p2 register accesses to make it
88 * easier to pull out individual fields */
89#define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
90#define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
91#define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
92#define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
93
94#define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
95#define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
96#define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
97#define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
98#define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
99#define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
100#define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
101#define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
102#define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
103#define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
104#define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
105#define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
106#define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
107#define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
108#define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
109#define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
110#define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
111#define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
112#define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
113#define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
114
115static const struct pci_device_id cxl_pci_tbl[] = {
116 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
117 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
118 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
119 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
120 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
121 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
122 { }
123};
124MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
125
126
127/*
128 * Mostly using these wrappers to avoid confusion:
129 * priv 1 is BAR2, while priv 2 is BAR0
130 */
131static inline resource_size_t p1_base(struct pci_dev *dev)
132{
133 return pci_resource_start(dev, 2);
134}
135
136static inline resource_size_t p1_size(struct pci_dev *dev)
137{
138 return pci_resource_len(dev, 2);
139}
140
141static inline resource_size_t p2_base(struct pci_dev *dev)
142{
143 return pci_resource_start(dev, 0);
144}
145
146static inline resource_size_t p2_size(struct pci_dev *dev)
147{
148 return pci_resource_len(dev, 0);
149}
150
151static int find_cxl_vsec(struct pci_dev *dev)
152{
153 int vsec = 0;
154 u16 val;
155
156 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
157 pci_read_config_word(dev, vsec + 0x4, &val);
158 if (val == CXL_PCI_VSEC_ID)
159 return vsec;
160 }
161 return 0;
162
163}
164
165static void dump_cxl_config_space(struct pci_dev *dev)
166{
167 int vsec;
168 u32 val;
169
170 dev_info(&dev->dev, "dump_cxl_config_space\n");
171
172 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
173 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
174 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
175 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
177 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
179 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
181 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
183 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
184
185 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
186 p1_base(dev), p1_size(dev));
187 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
188 p2_base(dev), p2_size(dev));
189 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
190 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
191
192 if (!(vsec = find_cxl_vsec(dev)))
193 return;
194
195#define show_reg(name, what) \
196 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
197
198 pci_read_config_dword(dev, vsec + 0x0, &val);
199 show_reg("Cap ID", (val >> 0) & 0xffff);
200 show_reg("Cap Ver", (val >> 16) & 0xf);
201 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
202 pci_read_config_dword(dev, vsec + 0x4, &val);
203 show_reg("VSEC ID", (val >> 0) & 0xffff);
204 show_reg("VSEC Rev", (val >> 16) & 0xf);
205 show_reg("VSEC Length", (val >> 20) & 0xfff);
206 pci_read_config_dword(dev, vsec + 0x8, &val);
207 show_reg("Num AFUs", (val >> 0) & 0xff);
208 show_reg("Status", (val >> 8) & 0xff);
209 show_reg("Mode Control", (val >> 16) & 0xff);
210 show_reg("Reserved", (val >> 24) & 0xff);
211 pci_read_config_dword(dev, vsec + 0xc, &val);
212 show_reg("PSL Rev", (val >> 0) & 0xffff);
213 show_reg("CAIA Ver", (val >> 16) & 0xffff);
214 pci_read_config_dword(dev, vsec + 0x10, &val);
215 show_reg("Base Image Rev", (val >> 0) & 0xffff);
216 show_reg("Reserved", (val >> 16) & 0x0fff);
217 show_reg("Image Control", (val >> 28) & 0x3);
218 show_reg("Reserved", (val >> 30) & 0x1);
219 show_reg("Image Loaded", (val >> 31) & 0x1);
220
221 pci_read_config_dword(dev, vsec + 0x14, &val);
222 show_reg("Reserved", val);
223 pci_read_config_dword(dev, vsec + 0x18, &val);
224 show_reg("Reserved", val);
225 pci_read_config_dword(dev, vsec + 0x1c, &val);
226 show_reg("Reserved", val);
227
228 pci_read_config_dword(dev, vsec + 0x20, &val);
229 show_reg("AFU Descriptor Offset", val);
230 pci_read_config_dword(dev, vsec + 0x24, &val);
231 show_reg("AFU Descriptor Size", val);
232 pci_read_config_dword(dev, vsec + 0x28, &val);
233 show_reg("Problem State Offset", val);
234 pci_read_config_dword(dev, vsec + 0x2c, &val);
235 show_reg("Problem State Size", val);
236
237 pci_read_config_dword(dev, vsec + 0x30, &val);
238 show_reg("Reserved", val);
239 pci_read_config_dword(dev, vsec + 0x34, &val);
240 show_reg("Reserved", val);
241 pci_read_config_dword(dev, vsec + 0x38, &val);
242 show_reg("Reserved", val);
243 pci_read_config_dword(dev, vsec + 0x3c, &val);
244 show_reg("Reserved", val);
245
246 pci_read_config_dword(dev, vsec + 0x40, &val);
247 show_reg("PSL Programming Port", val);
248 pci_read_config_dword(dev, vsec + 0x44, &val);
249 show_reg("PSL Programming Control", val);
250
251 pci_read_config_dword(dev, vsec + 0x48, &val);
252 show_reg("Reserved", val);
253 pci_read_config_dword(dev, vsec + 0x4c, &val);
254 show_reg("Reserved", val);
255
256 pci_read_config_dword(dev, vsec + 0x50, &val);
257 show_reg("Flash Address Register", val);
258 pci_read_config_dword(dev, vsec + 0x54, &val);
259 show_reg("Flash Size Register", val);
260 pci_read_config_dword(dev, vsec + 0x58, &val);
261 show_reg("Flash Status/Control Register", val);
262 pci_read_config_dword(dev, vsec + 0x58, &val);
263 show_reg("Flash Data Port", val);
264
265#undef show_reg
266}
267
268static void dump_afu_descriptor(struct cxl_afu *afu)
269{
270 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
271 int i;
272
273#define show_reg(name, what) \
274 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
275
276 val = AFUD_READ_INFO(afu);
277 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
278 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
279 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
280 show_reg("req_prog_mode", val & 0xffffULL);
281 afu_cr_num = AFUD_NUM_CRS(val);
282
283 val = AFUD_READ(afu, 0x8);
284 show_reg("Reserved", val);
285 val = AFUD_READ(afu, 0x10);
286 show_reg("Reserved", val);
287 val = AFUD_READ(afu, 0x18);
288 show_reg("Reserved", val);
289
290 val = AFUD_READ_CR(afu);
291 show_reg("Reserved", (val >> (63-7)) & 0xff);
292 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
293 afu_cr_len = AFUD_CR_LEN(val) * 256;
294
295 val = AFUD_READ_CR_OFF(afu);
296 afu_cr_off = val;
297 show_reg("AFU_CR_offset", val);
298
299 val = AFUD_READ_PPPSA(afu);
300 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
301 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
302
303 val = AFUD_READ_PPPSA_OFF(afu);
304 show_reg("PerProcessPSA_offset", val);
305
306 val = AFUD_READ_EB(afu);
307 show_reg("Reserved", (val >> (63-7)) & 0xff);
308 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
309
310 val = AFUD_READ_EB_OFF(afu);
311 show_reg("AFU_EB_offset", val);
312
313 for (i = 0; i < afu_cr_num; i++) {
314 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
315 show_reg("CR Vendor", val & 0xffff);
316 show_reg("CR Device", (val >> 16) & 0xffff);
317 }
318#undef show_reg
319}
320
321#define P8_CAPP_UNIT0_ID 0xBA
322#define P8_CAPP_UNIT1_ID 0XBE
323#define P9_CAPP_UNIT0_ID 0xC0
324#define P9_CAPP_UNIT1_ID 0xE0
325
326static int get_phb_index(struct device_node *np, u32 *phb_index)
327{
328 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
329 return -ENODEV;
330 return 0;
331}
332
333static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
334{
335 /*
336 * POWER 8:
337 * - For chips other than POWER8NVL, we only have CAPP 0,
338 * irrespective of which PHB is used.
339 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
340 * CAPP 1 is attached to PHB1.
341 */
342 if (cxl_is_power8()) {
343 if (!pvr_version_is(PVR_POWER8NVL))
344 return P8_CAPP_UNIT0_ID;
345
346 if (phb_index == 0)
347 return P8_CAPP_UNIT0_ID;
348
349 if (phb_index == 1)
350 return P8_CAPP_UNIT1_ID;
351 }
352
353 /*
354 * POWER 9:
355 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
356 * PEC1 (PHB1 - PHB2). No capi mode
357 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
358 */
359 if (cxl_is_power9()) {
360 if (phb_index == 0)
361 return P9_CAPP_UNIT0_ID;
362
363 if (phb_index == 3)
364 return P9_CAPP_UNIT1_ID;
365 }
366
367 return 0;
368}
369
370int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
371 u32 *phb_index, u64 *capp_unit_id)
372{
373 int rc;
374 struct device_node *np;
375 const __be32 *prop;
376
377 if (!(np = pnv_pci_get_phb_node(dev)))
378 return -ENODEV;
379
380 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
381 np = of_get_next_parent(np);
382 if (!np)
383 return -ENODEV;
384
385 *chipid = be32_to_cpup(prop);
386
387 rc = get_phb_index(np, phb_index);
388 if (rc) {
389 pr_err("cxl: invalid phb index\n");
390 of_node_put(np);
391 return rc;
392 }
393
394 *capp_unit_id = get_capp_unit_id(np, *phb_index);
395 of_node_put(np);
396 if (!*capp_unit_id) {
397 pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible slot\n",
398 *chipid, *phb_index);
399 return -ENODEV;
400 }
401
402 return 0;
403}
404
405static DEFINE_MUTEX(indications_mutex);
406
407static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
408 u64 *nbwind)
409{
410 static u64 nbw, asn, capi = 0;
411 struct device_node *np;
412 const __be32 *prop;
413
414 mutex_lock(&indications_mutex);
415 if (!capi) {
416 if (!(np = pnv_pci_get_phb_node(dev))) {
417 mutex_unlock(&indications_mutex);
418 return -ENODEV;
419 }
420
421 prop = of_get_property(np, "ibm,phb-indications", NULL);
422 if (!prop) {
423 nbw = 0x0300UL; /* legacy values */
424 asn = 0x0400UL;
425 capi = 0x0200UL;
426 } else {
427 nbw = (u64)be32_to_cpu(prop[2]);
428 asn = (u64)be32_to_cpu(prop[1]);
429 capi = (u64)be32_to_cpu(prop[0]);
430 }
431 of_node_put(np);
432 }
433 *capiind = capi;
434 *asnind = asn;
435 *nbwind = nbw;
436 mutex_unlock(&indications_mutex);
437 return 0;
438}
439
440int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
441{
442 u64 xsl_dsnctl;
443 u64 capiind, asnind, nbwind;
444
445 /*
446 * CAPI Identifier bits [0:7]
447 * bit 61:60 MSI bits --> 0
448 * bit 59 TVT selector --> 0
449 */
450 if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
451 return -ENODEV;
452
453 /*
454 * Tell XSL where to route data to.
455 * The field chipid should match the PHB CAPI_CMPM register
456 */
457 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
458 xsl_dsnctl |= (capp_unit_id << (63-15));
459
460 /* nMMU_ID Defaults to: b’000001001’*/
461 xsl_dsnctl |= ((u64)0x09 << (63-28));
462
463 /*
464 * Used to identify CAPI packets which should be sorted into
465 * the Non-Blocking queues by the PHB. This field should match
466 * the PHB PBL_NBW_CMPM register
467 * nbwind=0x03, bits [57:58], must include capi indicator.
468 * Not supported on P9 DD1.
469 */
470 xsl_dsnctl |= (nbwind << (63-55));
471
472 /*
473 * Upper 16b address bits of ASB_Notify messages sent to the
474 * system. Need to match the PHB’s ASN Compare/Mask Register.
475 * Not supported on P9 DD1.
476 */
477 xsl_dsnctl |= asnind;
478
479 *reg = xsl_dsnctl;
480 return 0;
481}
482
483static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
484 struct pci_dev *dev)
485{
486 u64 xsl_dsnctl, psl_fircntl;
487 u64 chipid;
488 u32 phb_index;
489 u64 capp_unit_id;
490 u64 psl_debug;
491 int rc;
492
493 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
494 if (rc)
495 return rc;
496
497 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
498 if (rc)
499 return rc;
500
501 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
502
503 /* Set fir_cntl to recommended value for production env */
504 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
505 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
506 psl_fircntl |= 0x1ULL; /* ce_thresh */
507 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
508
509 /* Setup the PSL to transmit packets on the PCIe before the
510 * CAPP is enabled. Make sure that CAPP virtual machines are disabled
511 */
512 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
513
514 /*
515 * A response to an ASB_Notify request is returned by the
516 * system as an MMIO write to the address defined in
517 * the PSL_TNR_ADDR register.
518 * keep the Reset Value: 0x00020000E0000000
519 */
520
521 /* Enable XSL rty limit */
522 cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
523
524 /* Change XSL_INV dummy read threshold */
525 cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
526
527 if (phb_index == 3) {
528 /* disable machines 31-47 and 20-27 for DMA */
529 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
530 }
531
532 /* Snoop machines */
533 cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
534
535 /* Enable NORST and DD2 features */
536 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
537
538 /*
539 * Check if PSL has data-cache. We need to flush adapter datacache
540 * when as its about to be removed.
541 */
542 psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
543 if (psl_debug & CXL_PSL_DEBUG_CDC) {
544 dev_dbg(&dev->dev, "No data-cache present\n");
545 adapter->native->no_data_cache = true;
546 }
547
548 return 0;
549}
550
551static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
552{
553 u64 psl_dsnctl, psl_fircntl;
554 u64 chipid;
555 u32 phb_index;
556 u64 capp_unit_id;
557 int rc;
558
559 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
560 if (rc)
561 return rc;
562
563 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
564 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
565 /* Tell PSL where to route data to */
566 psl_dsnctl |= (chipid << (63-5));
567 psl_dsnctl |= (capp_unit_id << (63-13));
568
569 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
570 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
571 /* snoop write mask */
572 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
573 /* set fir_cntl to recommended value for production env */
574 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
575 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
576 psl_fircntl |= 0x1ULL; /* ce_thresh */
577 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
578 /* for debugging with trace arrays */
579 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
580
581 return 0;
582}
583
584/* PSL */
585#define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
586#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
587/* For the PSL this is a multiple for 0 < n <= 7: */
588#define PSL_2048_250MHZ_CYCLES 1
589
590static void write_timebase_ctrl_psl8(struct cxl *adapter)
591{
592 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
593 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
594}
595
596static u64 timebase_read_psl9(struct cxl *adapter)
597{
598 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
599}
600
601static u64 timebase_read_psl8(struct cxl *adapter)
602{
603 return cxl_p1_read(adapter, CXL_PSL_Timebase);
604}
605
606static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
607{
608 struct device_node *np;
609
610 adapter->psl_timebase_synced = false;
611
612 if (!(np = pnv_pci_get_phb_node(dev)))
613 return;
614
615 /* Do not fail when CAPP timebase sync is not supported by OPAL */
616 of_node_get(np);
617 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
618 of_node_put(np);
619 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
620 return;
621 }
622 of_node_put(np);
623
624 /*
625 * Setup PSL Timebase Control and Status register
626 * with the recommended Timebase Sync Count value
627 */
628 if (adapter->native->sl_ops->write_timebase_ctrl)
629 adapter->native->sl_ops->write_timebase_ctrl(adapter);
630
631 /* Enable PSL Timebase */
632 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
633 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
634
635 return;
636}
637
638static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
639{
640 return 0;
641}
642
643static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
644{
645 /* read/write masks for this slice */
646 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
647 /* APC read/write masks for this slice */
648 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
649 /* for debugging with trace arrays */
650 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
651 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
652
653 return 0;
654}
655
656int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
657 unsigned int virq)
658{
659 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
660
661 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
662}
663
664int cxl_update_image_control(struct cxl *adapter)
665{
666 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
667 int rc;
668 int vsec;
669 u8 image_state;
670
671 if (!(vsec = find_cxl_vsec(dev))) {
672 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
673 return -ENODEV;
674 }
675
676 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
677 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
678 return rc;
679 }
680
681 if (adapter->perst_loads_image)
682 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
683 else
684 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
685
686 if (adapter->perst_select_user)
687 image_state |= CXL_VSEC_PERST_SELECT_USER;
688 else
689 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
690
691 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
692 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
693 return rc;
694 }
695
696 return 0;
697}
698
699int cxl_pci_alloc_one_irq(struct cxl *adapter)
700{
701 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
702
703 return pnv_cxl_alloc_hwirqs(dev, 1);
704}
705
706void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
707{
708 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
709
710 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
711}
712
713int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
714 struct cxl *adapter, unsigned int num)
715{
716 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
717
718 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
719}
720
721void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
722 struct cxl *adapter)
723{
724 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
725
726 pnv_cxl_release_hwirq_ranges(irqs, dev);
727}
728
729static int setup_cxl_bars(struct pci_dev *dev)
730{
731 /* Safety check in case we get backported to < 3.17 without M64 */
732 if ((p1_base(dev) < 0x100000000ULL) ||
733 (p2_base(dev) < 0x100000000ULL)) {
734 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
735 return -ENODEV;
736 }
737
738 /*
739 * BAR 4/5 has a special meaning for CXL and must be programmed with a
740 * special value corresponding to the CXL protocol address range.
741 * For POWER 8/9 that means bits 48:49 must be set to 10
742 */
743 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
744 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
745
746 return 0;
747}
748
749/* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
750static int switch_card_to_cxl(struct pci_dev *dev)
751{
752 int vsec;
753 u8 val;
754 int rc;
755
756 dev_info(&dev->dev, "switch card to CXL\n");
757
758 if (!(vsec = find_cxl_vsec(dev))) {
759 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
760 return -ENODEV;
761 }
762
763 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
764 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
765 return rc;
766 }
767 val &= ~CXL_VSEC_PROTOCOL_MASK;
768 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
769 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
770 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
771 return rc;
772 }
773 /*
774 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
775 * we must wait 100ms after this mode switch before touching
776 * PCIe config space.
777 */
778 msleep(100);
779
780 return 0;
781}
782
783static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
784{
785 u64 p1n_base, p2n_base, afu_desc;
786 const u64 p1n_size = 0x100;
787 const u64 p2n_size = 0x1000;
788
789 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
790 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
791 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
792 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
793
794 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
795 goto err;
796 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
797 goto err1;
798 if (afu_desc) {
799 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
800 goto err2;
801 }
802
803 return 0;
804err2:
805 iounmap(afu->p2n_mmio);
806err1:
807 iounmap(afu->native->p1n_mmio);
808err:
809 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
810 return -ENOMEM;
811}
812
813static void pci_unmap_slice_regs(struct cxl_afu *afu)
814{
815 if (afu->p2n_mmio) {
816 iounmap(afu->p2n_mmio);
817 afu->p2n_mmio = NULL;
818 }
819 if (afu->native->p1n_mmio) {
820 iounmap(afu->native->p1n_mmio);
821 afu->native->p1n_mmio = NULL;
822 }
823 if (afu->native->afu_desc_mmio) {
824 iounmap(afu->native->afu_desc_mmio);
825 afu->native->afu_desc_mmio = NULL;
826 }
827}
828
829void cxl_pci_release_afu(struct device *dev)
830{
831 struct cxl_afu *afu = to_cxl_afu(dev);
832
833 pr_devel("%s\n", __func__);
834
835 idr_destroy(&afu->contexts_idr);
836 cxl_release_spa(afu);
837
838 kfree(afu->native);
839 kfree(afu);
840}
841
842/* Expects AFU struct to have recently been zeroed out */
843static int cxl_read_afu_descriptor(struct cxl_afu *afu)
844{
845 u64 val;
846
847 val = AFUD_READ_INFO(afu);
848 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
849 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
850 afu->crs_num = AFUD_NUM_CRS(val);
851
852 if (AFUD_AFU_DIRECTED(val))
853 afu->modes_supported |= CXL_MODE_DIRECTED;
854 if (AFUD_DEDICATED_PROCESS(val))
855 afu->modes_supported |= CXL_MODE_DEDICATED;
856 if (AFUD_TIME_SLICED(val))
857 afu->modes_supported |= CXL_MODE_TIME_SLICED;
858
859 val = AFUD_READ_PPPSA(afu);
860 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
861 afu->psa = AFUD_PPPSA_PSA(val);
862 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
863 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
864
865 val = AFUD_READ_CR(afu);
866 afu->crs_len = AFUD_CR_LEN(val) * 256;
867 afu->crs_offset = AFUD_READ_CR_OFF(afu);
868
869
870 /* eb_len is in multiple of 4K */
871 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
872 afu->eb_offset = AFUD_READ_EB_OFF(afu);
873
874 /* eb_off is 4K aligned so lower 12 bits are always zero */
875 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
876 dev_warn(&afu->dev,
877 "Invalid AFU error buffer offset %Lx\n",
878 afu->eb_offset);
879 dev_info(&afu->dev,
880 "Ignoring AFU error buffer in the descriptor\n");
881 /* indicate that no afu buffer exists */
882 afu->eb_len = 0;
883 }
884
885 return 0;
886}
887
888static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
889{
890 int i, rc;
891 u32 val;
892
893 if (afu->psa && afu->adapter->ps_size <
894 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
895 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
896 return -ENODEV;
897 }
898
899 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
900 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
901
902 for (i = 0; i < afu->crs_num; i++) {
903 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
904 if (rc || val == 0) {
905 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
906 return -EINVAL;
907 }
908 }
909
910 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
911 /*
912 * We could also check this for the dedicated process model
913 * since the architecture indicates it should be set to 1, but
914 * in that case we ignore the value and I'd rather not risk
915 * breaking any existing dedicated process AFUs that left it as
916 * 0 (not that I'm aware of any). It is clearly an error for an
917 * AFU directed AFU to set this to 0, and would have previously
918 * triggered a bug resulting in the maximum not being enforced
919 * at all since idr_alloc treats 0 as no maximum.
920 */
921 dev_err(&afu->dev, "AFU does not support any processes\n");
922 return -EINVAL;
923 }
924
925 return 0;
926}
927
928static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
929{
930 u64 reg;
931
932 /*
933 * Clear out any regs that contain either an IVTE or address or may be
934 * waiting on an acknowledgment to try to be a bit safer as we bring
935 * it online
936 */
937 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
938 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
939 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
940 if (cxl_ops->afu_reset(afu))
941 return -EIO;
942 if (cxl_afu_disable(afu))
943 return -EIO;
944 if (cxl_psl_purge(afu))
945 return -EIO;
946 }
947 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
948 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
949 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
950 if (reg) {
951 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
952 if (reg & CXL_PSL9_DSISR_An_TF)
953 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
954 else
955 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
956 }
957 if (afu->adapter->native->sl_ops->register_serr_irq) {
958 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
959 if (reg) {
960 if (reg & ~0x000000007fffffff)
961 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
962 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
963 }
964 }
965 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
966 if (reg) {
967 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
968 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
969 }
970
971 return 0;
972}
973
974static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
975{
976 u64 reg;
977
978 /*
979 * Clear out any regs that contain either an IVTE or address or may be
980 * waiting on an acknowledgement to try to be a bit safer as we bring
981 * it online
982 */
983 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
984 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
985 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
986 if (cxl_ops->afu_reset(afu))
987 return -EIO;
988 if (cxl_afu_disable(afu))
989 return -EIO;
990 if (cxl_psl_purge(afu))
991 return -EIO;
992 }
993 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
994 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
995 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
996 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
997 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
998 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
999 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1000 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1001 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1002 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1003 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1004 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1005 if (reg) {
1006 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1007 if (reg & CXL_PSL_DSISR_TRANS)
1008 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1009 else
1010 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1011 }
1012 if (afu->adapter->native->sl_ops->register_serr_irq) {
1013 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1014 if (reg) {
1015 if (reg & ~0xffff)
1016 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1017 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1018 }
1019 }
1020 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1021 if (reg) {
1022 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1023 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1024 }
1025
1026 return 0;
1027}
1028
1029#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1030/*
1031 * afu_eb_read:
1032 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1033 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1034 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1035 */
1036ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1037 loff_t off, size_t count)
1038{
1039 loff_t aligned_start, aligned_end;
1040 size_t aligned_length;
1041 void *tbuf;
1042 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1043
1044 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1045 return 0;
1046
1047 /* calculate aligned read window */
1048 count = min((size_t)(afu->eb_len - off), count);
1049 aligned_start = round_down(off, 8);
1050 aligned_end = round_up(off + count, 8);
1051 aligned_length = aligned_end - aligned_start;
1052
1053 /* max we can copy in one read is PAGE_SIZE */
1054 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1055 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1056 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1057 }
1058
1059 /* use bounce buffer for copy */
1060 tbuf = (void *)__get_free_page(GFP_KERNEL);
1061 if (!tbuf)
1062 return -ENOMEM;
1063
1064 /* perform aligned read from the mmio region */
1065 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1066 memcpy(buf, tbuf + (off & 0x7), count);
1067
1068 free_page((unsigned long)tbuf);
1069
1070 return count;
1071}
1072
1073static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1074{
1075 int rc;
1076
1077 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1078 return rc;
1079
1080 if (adapter->native->sl_ops->sanitise_afu_regs) {
1081 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1082 if (rc)
1083 goto err1;
1084 }
1085
1086 /* We need to reset the AFU before we can read the AFU descriptor */
1087 if ((rc = cxl_ops->afu_reset(afu)))
1088 goto err1;
1089
1090 if (cxl_verbose)
1091 dump_afu_descriptor(afu);
1092
1093 if ((rc = cxl_read_afu_descriptor(afu)))
1094 goto err1;
1095
1096 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1097 goto err1;
1098
1099 if (adapter->native->sl_ops->afu_regs_init)
1100 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1101 goto err1;
1102
1103 if (adapter->native->sl_ops->register_serr_irq)
1104 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1105 goto err1;
1106
1107 if ((rc = cxl_native_register_psl_irq(afu)))
1108 goto err2;
1109
1110 atomic_set(&afu->configured_state, 0);
1111 return 0;
1112
1113err2:
1114 if (adapter->native->sl_ops->release_serr_irq)
1115 adapter->native->sl_ops->release_serr_irq(afu);
1116err1:
1117 pci_unmap_slice_regs(afu);
1118 return rc;
1119}
1120
1121static void pci_deconfigure_afu(struct cxl_afu *afu)
1122{
1123 /*
1124 * It's okay to deconfigure when AFU is already locked, otherwise wait
1125 * until there are no readers
1126 */
1127 if (atomic_read(&afu->configured_state) != -1) {
1128 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1129 schedule();
1130 }
1131 cxl_native_release_psl_irq(afu);
1132 if (afu->adapter->native->sl_ops->release_serr_irq)
1133 afu->adapter->native->sl_ops->release_serr_irq(afu);
1134 pci_unmap_slice_regs(afu);
1135}
1136
1137static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1138{
1139 struct cxl_afu *afu;
1140 int rc = -ENOMEM;
1141
1142 afu = cxl_alloc_afu(adapter, slice);
1143 if (!afu)
1144 return -ENOMEM;
1145
1146 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1147 if (!afu->native)
1148 goto err_free_afu;
1149
1150 mutex_init(&afu->native->spa_mutex);
1151
1152 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1153 if (rc)
1154 goto err_free_native;
1155
1156 rc = pci_configure_afu(afu, adapter, dev);
1157 if (rc)
1158 goto err_free_native;
1159
1160 /* Don't care if this fails */
1161 cxl_debugfs_afu_add(afu);
1162
1163 /*
1164 * After we call this function we must not free the afu directly, even
1165 * if it returns an error!
1166 */
1167 if ((rc = cxl_register_afu(afu)))
1168 goto err_put_dev;
1169
1170 if ((rc = cxl_sysfs_afu_add(afu)))
1171 goto err_del_dev;
1172
1173 adapter->afu[afu->slice] = afu;
1174
1175 if ((rc = cxl_pci_vphb_add(afu)))
1176 dev_info(&afu->dev, "Can't register vPHB\n");
1177
1178 return 0;
1179
1180err_del_dev:
1181 device_del(&afu->dev);
1182err_put_dev:
1183 pci_deconfigure_afu(afu);
1184 cxl_debugfs_afu_remove(afu);
1185 put_device(&afu->dev);
1186 return rc;
1187
1188err_free_native:
1189 kfree(afu->native);
1190err_free_afu:
1191 kfree(afu);
1192 return rc;
1193
1194}
1195
1196static void cxl_pci_remove_afu(struct cxl_afu *afu)
1197{
1198 pr_devel("%s\n", __func__);
1199
1200 if (!afu)
1201 return;
1202
1203 cxl_pci_vphb_remove(afu);
1204 cxl_sysfs_afu_remove(afu);
1205 cxl_debugfs_afu_remove(afu);
1206
1207 spin_lock(&afu->adapter->afu_list_lock);
1208 afu->adapter->afu[afu->slice] = NULL;
1209 spin_unlock(&afu->adapter->afu_list_lock);
1210
1211 cxl_context_detach_all(afu);
1212 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1213
1214 pci_deconfigure_afu(afu);
1215 device_unregister(&afu->dev);
1216}
1217
1218int cxl_pci_reset(struct cxl *adapter)
1219{
1220 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1221 int rc;
1222
1223 if (adapter->perst_same_image) {
1224 dev_warn(&dev->dev,
1225 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1226 return -EINVAL;
1227 }
1228
1229 dev_info(&dev->dev, "CXL reset\n");
1230
1231 /*
1232 * The adapter is about to be reset, so ignore errors.
1233 */
1234 cxl_data_cache_flush(adapter);
1235
1236 /* pcie_warm_reset requests a fundamental pci reset which includes a
1237 * PERST assert/deassert. PERST triggers a loading of the image
1238 * if "user" or "factory" is selected in sysfs */
1239 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1240 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1241 return rc;
1242 }
1243
1244 return rc;
1245}
1246
1247static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1248{
1249 if (pci_request_region(dev, 2, "priv 2 regs"))
1250 goto err1;
1251 if (pci_request_region(dev, 0, "priv 1 regs"))
1252 goto err2;
1253
1254 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1255 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1256
1257 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1258 goto err3;
1259
1260 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1261 goto err4;
1262
1263 return 0;
1264
1265err4:
1266 iounmap(adapter->native->p1_mmio);
1267 adapter->native->p1_mmio = NULL;
1268err3:
1269 pci_release_region(dev, 0);
1270err2:
1271 pci_release_region(dev, 2);
1272err1:
1273 return -ENOMEM;
1274}
1275
1276static void cxl_unmap_adapter_regs(struct cxl *adapter)
1277{
1278 if (adapter->native->p1_mmio) {
1279 iounmap(adapter->native->p1_mmio);
1280 adapter->native->p1_mmio = NULL;
1281 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1282 }
1283 if (adapter->native->p2_mmio) {
1284 iounmap(adapter->native->p2_mmio);
1285 adapter->native->p2_mmio = NULL;
1286 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1287 }
1288}
1289
1290static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1291{
1292 int vsec;
1293 u32 afu_desc_off, afu_desc_size;
1294 u32 ps_off, ps_size;
1295 u16 vseclen;
1296 u8 image_state;
1297
1298 if (!(vsec = find_cxl_vsec(dev))) {
1299 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1300 return -ENODEV;
1301 }
1302
1303 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1304 if (vseclen < CXL_VSEC_MIN_SIZE) {
1305 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1306 return -EINVAL;
1307 }
1308
1309 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1310 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1311 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1312 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1313 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1314 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1315 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1316 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1317 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1318
1319 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1320 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1321 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1322 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1323 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1324
1325 /* Convert everything to bytes, because there is NO WAY I'd look at the
1326 * code a month later and forget what units these are in ;-) */
1327 adapter->native->ps_off = ps_off * 64 * 1024;
1328 adapter->ps_size = ps_size * 64 * 1024;
1329 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1330 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1331
1332 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1333 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1334
1335 return 0;
1336}
1337
1338/*
1339 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1340 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1341 * reported. Mask this error in the Uncorrectable Error Mask Register.
1342 *
1343 * The upper nibble of the PSL revision is used to distinguish between
1344 * different cards. The affected ones have it set to 0.
1345 */
1346static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1347{
1348 int aer;
1349 u32 data;
1350
1351 if (adapter->psl_rev & 0xf000)
1352 return;
1353 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1354 return;
1355 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1356 if (data & PCI_ERR_UNC_MALF_TLP)
1357 if (data & PCI_ERR_UNC_INTN)
1358 return;
1359 data |= PCI_ERR_UNC_MALF_TLP;
1360 data |= PCI_ERR_UNC_INTN;
1361 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1362}
1363
1364static bool cxl_compatible_caia_version(struct cxl *adapter)
1365{
1366 if (cxl_is_power8() && (adapter->caia_major == 1))
1367 return true;
1368
1369 if (cxl_is_power9() && (adapter->caia_major == 2))
1370 return true;
1371
1372 return false;
1373}
1374
1375static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1376{
1377 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1378 return -EBUSY;
1379
1380 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1381 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1382 return -EINVAL;
1383 }
1384
1385 if (!cxl_compatible_caia_version(adapter)) {
1386 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1387 adapter->caia_major);
1388 return -ENODEV;
1389 }
1390
1391 if (!adapter->slices) {
1392 /* Once we support dynamic reprogramming we can use the card if
1393 * it supports loadable AFUs */
1394 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1395 return -EINVAL;
1396 }
1397
1398 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1399 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1400 return -EINVAL;
1401 }
1402
1403 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1404 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1405 "available in BAR2: 0x%llx > 0x%llx\n",
1406 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1407 return -EINVAL;
1408 }
1409
1410 return 0;
1411}
1412
1413ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1414{
1415 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1416}
1417
1418static void cxl_release_adapter(struct device *dev)
1419{
1420 struct cxl *adapter = to_cxl_adapter(dev);
1421
1422 pr_devel("cxl_release_adapter\n");
1423
1424 cxl_remove_adapter_nr(adapter);
1425
1426 kfree(adapter->native);
1427 kfree(adapter);
1428}
1429
1430#define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1431
1432static int sanitise_adapter_regs(struct cxl *adapter)
1433{
1434 int rc = 0;
1435
1436 /* Clear PSL tberror bit by writing 1 to it */
1437 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1438
1439 if (adapter->native->sl_ops->invalidate_all) {
1440 /* do not invalidate ERAT entries when not reloading on PERST */
1441 if (cxl_is_power9() && (adapter->perst_loads_image))
1442 return 0;
1443 rc = adapter->native->sl_ops->invalidate_all(adapter);
1444 }
1445
1446 return rc;
1447}
1448
1449/* This should contain *only* operations that can safely be done in
1450 * both creation and recovery.
1451 */
1452static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1453{
1454 int rc;
1455
1456 adapter->dev.parent = &dev->dev;
1457 adapter->dev.release = cxl_release_adapter;
1458 pci_set_drvdata(dev, adapter);
1459
1460 rc = pci_enable_device(dev);
1461 if (rc) {
1462 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1463 return rc;
1464 }
1465
1466 if ((rc = cxl_read_vsec(adapter, dev)))
1467 return rc;
1468
1469 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1470 return rc;
1471
1472 cxl_fixup_malformed_tlp(adapter, dev);
1473
1474 if ((rc = setup_cxl_bars(dev)))
1475 return rc;
1476
1477 if ((rc = switch_card_to_cxl(dev)))
1478 return rc;
1479
1480 if ((rc = cxl_update_image_control(adapter)))
1481 return rc;
1482
1483 if ((rc = cxl_map_adapter_regs(adapter, dev)))
1484 return rc;
1485
1486 if ((rc = sanitise_adapter_regs(adapter)))
1487 goto err;
1488
1489 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1490 goto err;
1491
1492 /* Required for devices using CAPP DMA mode, harmless for others */
1493 pci_set_master(dev);
1494
1495 adapter->tunneled_ops_supported = false;
1496
1497 if (cxl_is_power9()) {
1498 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
1499 dev_info(&dev->dev, "Tunneled operations unsupported\n");
1500 else
1501 adapter->tunneled_ops_supported = true;
1502 }
1503
1504 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1505 goto err;
1506
1507 /* If recovery happened, the last step is to turn on snooping.
1508 * In the non-recovery case this has no effect */
1509 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1510 goto err;
1511
1512 /* Ignore error, adapter init is not dependant on timebase sync */
1513 cxl_setup_psl_timebase(adapter, dev);
1514
1515 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1516 goto err;
1517
1518 return 0;
1519
1520err:
1521 cxl_unmap_adapter_regs(adapter);
1522 return rc;
1523
1524}
1525
1526static void cxl_deconfigure_adapter(struct cxl *adapter)
1527{
1528 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1529
1530 if (cxl_is_power9())
1531 pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
1532
1533 cxl_native_release_psl_err_irq(adapter);
1534 cxl_unmap_adapter_regs(adapter);
1535
1536 pci_disable_device(pdev);
1537}
1538
1539static void cxl_stop_trace_psl9(struct cxl *adapter)
1540{
1541 int traceid;
1542 u64 trace_state, trace_mask;
1543 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1544
1545 /* read each tracearray state and issue mmio to stop them is needed */
1546 for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
1547 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
1548 trace_mask = (0x3ULL << (62 - traceid * 2));
1549 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1550 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1551 traceid, trace_state);
1552
1553 /* issue mmio if the trace array isn't in FIN state */
1554 if (trace_state != CXL_PSL9_TRACESTATE_FIN)
1555 cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
1556 0x8400000000000000ULL | traceid);
1557 }
1558}
1559
1560static void cxl_stop_trace_psl8(struct cxl *adapter)
1561{
1562 int slice;
1563
1564 /* Stop the trace */
1565 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
1566
1567 /* Stop the slice traces */
1568 spin_lock(&adapter->afu_list_lock);
1569 for (slice = 0; slice < adapter->slices; slice++) {
1570 if (adapter->afu[slice])
1571 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1572 0x8000000000000000LL);
1573 }
1574 spin_unlock(&adapter->afu_list_lock);
1575}
1576
1577static const struct cxl_service_layer_ops psl9_ops = {
1578 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1579 .invalidate_all = cxl_invalidate_all_psl9,
1580 .afu_regs_init = init_implementation_afu_regs_psl9,
1581 .sanitise_afu_regs = sanitise_afu_regs_psl9,
1582 .register_serr_irq = cxl_native_register_serr_irq,
1583 .release_serr_irq = cxl_native_release_serr_irq,
1584 .handle_interrupt = cxl_irq_psl9,
1585 .fail_irq = cxl_fail_irq_psl,
1586 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1587 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1588 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1589 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1590 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1591 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1592 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1593 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
1594 .debugfs_stop_trace = cxl_stop_trace_psl9,
1595 .timebase_read = timebase_read_psl9,
1596 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1597 .needs_reset_before_disable = true,
1598};
1599
1600static const struct cxl_service_layer_ops psl8_ops = {
1601 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1602 .invalidate_all = cxl_invalidate_all_psl8,
1603 .afu_regs_init = init_implementation_afu_regs_psl8,
1604 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1605 .register_serr_irq = cxl_native_register_serr_irq,
1606 .release_serr_irq = cxl_native_release_serr_irq,
1607 .handle_interrupt = cxl_irq_psl8,
1608 .fail_irq = cxl_fail_irq_psl,
1609 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1610 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1611 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1612 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1613 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1614 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1615 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1616 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
1617 .debugfs_stop_trace = cxl_stop_trace_psl8,
1618 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1619 .timebase_read = timebase_read_psl8,
1620 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1621 .needs_reset_before_disable = true,
1622};
1623
1624static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1625{
1626 if (cxl_is_power8()) {
1627 dev_info(&dev->dev, "Device uses a PSL8\n");
1628 adapter->native->sl_ops = &psl8_ops;
1629 } else {
1630 dev_info(&dev->dev, "Device uses a PSL9\n");
1631 adapter->native->sl_ops = &psl9_ops;
1632 }
1633}
1634
1635
1636static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1637{
1638 struct cxl *adapter;
1639 int rc;
1640
1641 adapter = cxl_alloc_adapter();
1642 if (!adapter)
1643 return ERR_PTR(-ENOMEM);
1644
1645 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1646 if (!adapter->native) {
1647 rc = -ENOMEM;
1648 goto err_release;
1649 }
1650
1651 set_sl_ops(adapter, dev);
1652
1653 /* Set defaults for parameters which need to persist over
1654 * configure/reconfigure
1655 */
1656 adapter->perst_loads_image = true;
1657 adapter->perst_same_image = false;
1658
1659 rc = cxl_configure_adapter(adapter, dev);
1660 if (rc) {
1661 pci_disable_device(dev);
1662 goto err_release;
1663 }
1664
1665 /* Don't care if this one fails: */
1666 cxl_debugfs_adapter_add(adapter);
1667
1668 /*
1669 * After we call this function we must not free the adapter directly,
1670 * even if it returns an error!
1671 */
1672 if ((rc = cxl_register_adapter(adapter)))
1673 goto err_put_dev;
1674
1675 if ((rc = cxl_sysfs_adapter_add(adapter)))
1676 goto err_del_dev;
1677
1678 /* Release the context lock as adapter is configured */
1679 cxl_adapter_context_unlock(adapter);
1680
1681 return adapter;
1682
1683err_del_dev:
1684 device_del(&adapter->dev);
1685err_put_dev:
1686 /* This should mirror cxl_remove_adapter, except without the
1687 * sysfs parts
1688 */
1689 cxl_debugfs_adapter_remove(adapter);
1690 cxl_deconfigure_adapter(adapter);
1691 put_device(&adapter->dev);
1692 return ERR_PTR(rc);
1693
1694err_release:
1695 cxl_release_adapter(&adapter->dev);
1696 return ERR_PTR(rc);
1697}
1698
1699static void cxl_pci_remove_adapter(struct cxl *adapter)
1700{
1701 pr_devel("cxl_remove_adapter\n");
1702
1703 cxl_sysfs_adapter_remove(adapter);
1704 cxl_debugfs_adapter_remove(adapter);
1705
1706 /*
1707 * Flush adapter datacache as its about to be removed.
1708 */
1709 cxl_data_cache_flush(adapter);
1710
1711 cxl_deconfigure_adapter(adapter);
1712
1713 device_unregister(&adapter->dev);
1714}
1715
1716#define CXL_MAX_PCIEX_PARENT 2
1717
1718int cxl_slot_is_switched(struct pci_dev *dev)
1719{
1720 struct device_node *np;
1721 int depth = 0;
1722
1723 if (!(np = pci_device_to_OF_node(dev))) {
1724 pr_err("cxl: np = NULL\n");
1725 return -ENODEV;
1726 }
1727 of_node_get(np);
1728 while (np) {
1729 np = of_get_next_parent(np);
1730 if (!of_node_is_type(np, "pciex"))
1731 break;
1732 depth++;
1733 }
1734 of_node_put(np);
1735 return (depth > CXL_MAX_PCIEX_PARENT);
1736}
1737
1738static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1739{
1740 struct cxl *adapter;
1741 int slice;
1742 int rc;
1743
1744 if (cxl_pci_is_vphb_device(dev)) {
1745 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1746 return -ENODEV;
1747 }
1748
1749 if (cxl_slot_is_switched(dev)) {
1750 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1751 return -ENODEV;
1752 }
1753
1754 if (cxl_is_power9() && !radix_enabled()) {
1755 dev_info(&dev->dev, "Only Radix mode supported\n");
1756 return -ENODEV;
1757 }
1758
1759 if (cxl_verbose)
1760 dump_cxl_config_space(dev);
1761
1762 adapter = cxl_pci_init_adapter(dev);
1763 if (IS_ERR(adapter)) {
1764 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1765 return PTR_ERR(adapter);
1766 }
1767
1768 for (slice = 0; slice < adapter->slices; slice++) {
1769 if ((rc = pci_init_afu(adapter, slice, dev))) {
1770 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1771 continue;
1772 }
1773
1774 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1775 if (rc)
1776 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
1777 }
1778
1779 return 0;
1780}
1781
1782static void cxl_remove(struct pci_dev *dev)
1783{
1784 struct cxl *adapter = pci_get_drvdata(dev);
1785 struct cxl_afu *afu;
1786 int i;
1787
1788 /*
1789 * Lock to prevent someone grabbing a ref through the adapter list as
1790 * we are removing it
1791 */
1792 for (i = 0; i < adapter->slices; i++) {
1793 afu = adapter->afu[i];
1794 cxl_pci_remove_afu(afu);
1795 }
1796 cxl_pci_remove_adapter(adapter);
1797}
1798
1799static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1800 pci_channel_state_t state)
1801{
1802 struct pci_dev *afu_dev;
1803 struct pci_driver *afu_drv;
1804 const struct pci_error_handlers *err_handler;
1805 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1806 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1807
1808 /* There should only be one entry, but go through the list
1809 * anyway
1810 */
1811 if (afu == NULL || afu->phb == NULL)
1812 return result;
1813
1814 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1815 afu_drv = to_pci_driver(afu_dev->dev.driver);
1816 if (!afu_drv)
1817 continue;
1818
1819 afu_dev->error_state = state;
1820
1821 err_handler = afu_drv->err_handler;
1822 if (err_handler)
1823 afu_result = err_handler->error_detected(afu_dev,
1824 state);
1825 /* Disconnect trumps all, NONE trumps NEED_RESET */
1826 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1827 result = PCI_ERS_RESULT_DISCONNECT;
1828 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1829 (result == PCI_ERS_RESULT_NEED_RESET))
1830 result = PCI_ERS_RESULT_NONE;
1831 }
1832 return result;
1833}
1834
1835static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
1836 pci_channel_state_t state)
1837{
1838 struct cxl *adapter = pci_get_drvdata(pdev);
1839 struct cxl_afu *afu;
1840 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1841 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1842 int i;
1843
1844 /* At this point, we could still have an interrupt pending.
1845 * Let's try to get them out of the way before they do
1846 * anything we don't like.
1847 */
1848 schedule();
1849
1850 /* If we're permanently dead, give up. */
1851 if (state == pci_channel_io_perm_failure) {
1852 spin_lock(&adapter->afu_list_lock);
1853 for (i = 0; i < adapter->slices; i++) {
1854 afu = adapter->afu[i];
1855 /*
1856 * Tell the AFU drivers; but we don't care what they
1857 * say, we're going away.
1858 */
1859 cxl_vphb_error_detected(afu, state);
1860 }
1861 spin_unlock(&adapter->afu_list_lock);
1862 return PCI_ERS_RESULT_DISCONNECT;
1863 }
1864
1865 /* Are we reflashing?
1866 *
1867 * If we reflash, we could come back as something entirely
1868 * different, including a non-CAPI card. As such, by default
1869 * we don't participate in the process. We'll be unbound and
1870 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1871 * us!)
1872 *
1873 * However, this isn't the entire story: for reliablity
1874 * reasons, we usually want to reflash the FPGA on PERST in
1875 * order to get back to a more reliable known-good state.
1876 *
1877 * This causes us a bit of a problem: if we reflash we can't
1878 * trust that we'll come back the same - we could have a new
1879 * image and been PERSTed in order to load that
1880 * image. However, most of the time we actually *will* come
1881 * back the same - for example a regular EEH event.
1882 *
1883 * Therefore, we allow the user to assert that the image is
1884 * indeed the same and that we should continue on into EEH
1885 * anyway.
1886 */
1887 if (adapter->perst_loads_image && !adapter->perst_same_image) {
1888 /* TODO take the PHB out of CXL mode */
1889 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1890 return PCI_ERS_RESULT_NONE;
1891 }
1892
1893 /*
1894 * At this point, we want to try to recover. We'll always
1895 * need a complete slot reset: we don't trust any other reset.
1896 *
1897 * Now, we go through each AFU:
1898 * - We send the driver, if bound, an error_detected callback.
1899 * We expect it to clean up, but it can also tell us to give
1900 * up and permanently detach the card. To simplify things, if
1901 * any bound AFU driver doesn't support EEH, we give up on EEH.
1902 *
1903 * - We detach all contexts associated with the AFU. This
1904 * does not free them, but puts them into a CLOSED state
1905 * which causes any the associated files to return useful
1906 * errors to userland. It also unmaps, but does not free,
1907 * any IRQs.
1908 *
1909 * - We clean up our side: releasing and unmapping resources we hold
1910 * so we can wire them up again when the hardware comes back up.
1911 *
1912 * Driver authors should note:
1913 *
1914 * - Any contexts you create in your kernel driver (except
1915 * those associated with anonymous file descriptors) are
1916 * your responsibility to free and recreate. Likewise with
1917 * any attached resources.
1918 *
1919 * - We will take responsibility for re-initialising the
1920 * device context (the one set up for you in
1921 * cxl_pci_enable_device_hook and accessed through
1922 * cxl_get_context). If you've attached IRQs or other
1923 * resources to it, they remains yours to free.
1924 *
1925 * You can call the same functions to release resources as you
1926 * normally would: we make sure that these functions continue
1927 * to work when the hardware is down.
1928 *
1929 * Two examples:
1930 *
1931 * 1) If you normally free all your resources at the end of
1932 * each request, or if you use anonymous FDs, your
1933 * error_detected callback can simply set a flag to tell
1934 * your driver not to start any new calls. You can then
1935 * clear the flag in the resume callback.
1936 *
1937 * 2) If you normally allocate your resources on startup:
1938 * * Set a flag in error_detected as above.
1939 * * Let CXL detach your contexts.
1940 * * In slot_reset, free the old resources and allocate new ones.
1941 * * In resume, clear the flag to allow things to start.
1942 */
1943
1944 /* Make sure no one else changes the afu list */
1945 spin_lock(&adapter->afu_list_lock);
1946
1947 for (i = 0; i < adapter->slices; i++) {
1948 afu = adapter->afu[i];
1949
1950 if (afu == NULL)
1951 continue;
1952
1953 afu_result = cxl_vphb_error_detected(afu, state);
1954 cxl_context_detach_all(afu);
1955 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1956 pci_deconfigure_afu(afu);
1957
1958 /* Disconnect trumps all, NONE trumps NEED_RESET */
1959 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1960 result = PCI_ERS_RESULT_DISCONNECT;
1961 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1962 (result == PCI_ERS_RESULT_NEED_RESET))
1963 result = PCI_ERS_RESULT_NONE;
1964 }
1965 spin_unlock(&adapter->afu_list_lock);
1966
1967 /* should take the context lock here */
1968 if (cxl_adapter_context_lock(adapter) != 0)
1969 dev_warn(&adapter->dev,
1970 "Couldn't take context lock with %d active-contexts\n",
1971 atomic_read(&adapter->contexts_num));
1972
1973 cxl_deconfigure_adapter(adapter);
1974
1975 return result;
1976}
1977
1978static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
1979{
1980 struct cxl *adapter = pci_get_drvdata(pdev);
1981 struct cxl_afu *afu;
1982 struct cxl_context *ctx;
1983 struct pci_dev *afu_dev;
1984 struct pci_driver *afu_drv;
1985 const struct pci_error_handlers *err_handler;
1986 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
1987 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1988 int i;
1989
1990 if (cxl_configure_adapter(adapter, pdev))
1991 goto err;
1992
1993 /*
1994 * Unlock context activation for the adapter. Ideally this should be
1995 * done in cxl_pci_resume but cxlflash module tries to activate the
1996 * master context as part of slot_reset callback.
1997 */
1998 cxl_adapter_context_unlock(adapter);
1999
2000 spin_lock(&adapter->afu_list_lock);
2001 for (i = 0; i < adapter->slices; i++) {
2002 afu = adapter->afu[i];
2003
2004 if (afu == NULL)
2005 continue;
2006
2007 if (pci_configure_afu(afu, adapter, pdev))
2008 goto err_unlock;
2009
2010 if (cxl_afu_select_best_mode(afu))
2011 goto err_unlock;
2012
2013 if (afu->phb == NULL)
2014 continue;
2015
2016 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2017 /* Reset the device context.
2018 * TODO: make this less disruptive
2019 */
2020 ctx = cxl_get_context(afu_dev);
2021
2022 if (ctx && cxl_release_context(ctx))
2023 goto err_unlock;
2024
2025 ctx = cxl_dev_context_init(afu_dev);
2026 if (IS_ERR(ctx))
2027 goto err_unlock;
2028
2029 afu_dev->dev.archdata.cxl_ctx = ctx;
2030
2031 if (cxl_ops->afu_check_and_enable(afu))
2032 goto err_unlock;
2033
2034 afu_dev->error_state = pci_channel_io_normal;
2035
2036 /* If there's a driver attached, allow it to
2037 * chime in on recovery. Drivers should check
2038 * if everything has come back OK, but
2039 * shouldn't start new work until we call
2040 * their resume function.
2041 */
2042 afu_drv = to_pci_driver(afu_dev->dev.driver);
2043 if (!afu_drv)
2044 continue;
2045
2046 err_handler = afu_drv->err_handler;
2047 if (err_handler && err_handler->slot_reset)
2048 afu_result = err_handler->slot_reset(afu_dev);
2049
2050 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2051 result = PCI_ERS_RESULT_DISCONNECT;
2052 }
2053 }
2054
2055 spin_unlock(&adapter->afu_list_lock);
2056 return result;
2057
2058err_unlock:
2059 spin_unlock(&adapter->afu_list_lock);
2060
2061err:
2062 /* All the bits that happen in both error_detected and cxl_remove
2063 * should be idempotent, so we don't need to worry about leaving a mix
2064 * of unconfigured and reconfigured resources.
2065 */
2066 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2067 return PCI_ERS_RESULT_DISCONNECT;
2068}
2069
2070static void cxl_pci_resume(struct pci_dev *pdev)
2071{
2072 struct cxl *adapter = pci_get_drvdata(pdev);
2073 struct cxl_afu *afu;
2074 struct pci_dev *afu_dev;
2075 struct pci_driver *afu_drv;
2076 const struct pci_error_handlers *err_handler;
2077 int i;
2078
2079 /* Everything is back now. Drivers should restart work now.
2080 * This is not the place to be checking if everything came back up
2081 * properly, because there's no return value: do that in slot_reset.
2082 */
2083 spin_lock(&adapter->afu_list_lock);
2084 for (i = 0; i < adapter->slices; i++) {
2085 afu = adapter->afu[i];
2086
2087 if (afu == NULL || afu->phb == NULL)
2088 continue;
2089
2090 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2091 afu_drv = to_pci_driver(afu_dev->dev.driver);
2092 if (!afu_drv)
2093 continue;
2094
2095 err_handler = afu_drv->err_handler;
2096 if (err_handler && err_handler->resume)
2097 err_handler->resume(afu_dev);
2098 }
2099 }
2100 spin_unlock(&adapter->afu_list_lock);
2101}
2102
2103static const struct pci_error_handlers cxl_err_handler = {
2104 .error_detected = cxl_pci_error_detected,
2105 .slot_reset = cxl_pci_slot_reset,
2106 .resume = cxl_pci_resume,
2107};
2108
2109struct pci_driver cxl_pci_driver = {
2110 .name = "cxl-pci",
2111 .id_table = cxl_pci_tbl,
2112 .probe = cxl_probe,
2113 .remove = cxl_remove,
2114 .shutdown = cxl_remove,
2115 .err_handler = &cxl_err_handler,
2116};