1/*
  2 * Xtensa built-in interrupt controller
  3 *
  4 * Copyright (C) 2002 - 2013 Tensilica, Inc.
  5 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  6 *
  7 * This file is subject to the terms and conditions of the GNU General Public
  8 * License.  See the file "COPYING" in the main directory of this archive
  9 * for more details.
 10 *
 11 * Chris Zankel <chris@zankel.net>
 12 * Kevin Chea
 13 */
 14
 15#include <linux/interrupt.h>
 16#include <linux/irqdomain.h>
 17#include <linux/irq.h>
 18#include <linux/irqchip.h>
 19#include <linux/of.h>
 20
 21unsigned int cached_irq_mask;
 22
 23/*
 24 * Device Tree IRQ specifier translation function which works with one or
 25 * two cell bindings. First cell value maps directly to the hwirq number.
 26 * Second cell if present specifies whether hwirq number is external (1) or
 27 * internal (0).
 28 */
 29static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
 30		struct device_node *ctrlr,
 31		const u32 *intspec, unsigned int intsize,
 32		unsigned long *out_hwirq, unsigned int *out_type)
 33{
 34	return xtensa_irq_domain_xlate(intspec, intsize,
 35			intspec[0], intspec[0],
 36			out_hwirq, out_type);
 37}
 38
 39static const struct irq_domain_ops xtensa_irq_domain_ops = {
 40	.xlate = xtensa_pic_irq_domain_xlate,
 41	.map = xtensa_irq_map,
 42};
 43
 44static void xtensa_irq_mask(struct irq_data *d)
 45{
 46	cached_irq_mask &= ~(1 << d->hwirq);
 47	xtensa_set_sr(cached_irq_mask, intenable);
 48}
 49
 50static void xtensa_irq_unmask(struct irq_data *d)
 51{
 52	cached_irq_mask |= 1 << d->hwirq;
 53	xtensa_set_sr(cached_irq_mask, intenable);
 54}
 55
 56static void xtensa_irq_enable(struct irq_data *d)
 57{
 58	xtensa_irq_unmask(d);
 59}
 60
 61static void xtensa_irq_disable(struct irq_data *d)
 62{
 63	xtensa_irq_mask(d);
 64}
 65
 66static void xtensa_irq_ack(struct irq_data *d)
 67{
 68	xtensa_set_sr(1 << d->hwirq, intclear);
 69}
 70
 71static int xtensa_irq_retrigger(struct irq_data *d)
 72{
 73	unsigned int mask = 1u << d->hwirq;
 74
 75	if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
 76		return 0;
 77	xtensa_set_sr(mask, intset);
 78	return 1;
 79}
 80
 81static struct irq_chip xtensa_irq_chip = {
 82	.name		= "xtensa",
 83	.irq_enable	= xtensa_irq_enable,
 84	.irq_disable	= xtensa_irq_disable,
 85	.irq_mask	= xtensa_irq_mask,
 86	.irq_unmask	= xtensa_irq_unmask,
 87	.irq_ack	= xtensa_irq_ack,
 88	.irq_retrigger	= xtensa_irq_retrigger,
 89};
 90
 91int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
 92{
 93	struct irq_domain *root_domain =
 94		irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
 95				&xtensa_irq_domain_ops, &xtensa_irq_chip);
 96	irq_set_default_host(root_domain);
 97	return 0;
 98}
 99
100static int __init xtensa_pic_init(struct device_node *np,
101		struct device_node *interrupt_parent)
102{
103	struct irq_domain *root_domain =
104		irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
105				&xtensa_irq_chip);
106	irq_set_default_host(root_domain);
107	return 0;
108}
109IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);