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1/*
2 * Support for IDE interfaces on PowerMacs.
3 *
4 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
8 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25#include <linux/types.h>
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36#include <linux/slab.h>
37
38#include <asm/prom.h>
39#include <asm/io.h>
40#include <asm/dbdma.h>
41#include <asm/ide.h>
42#include <asm/pci-bridge.h>
43#include <asm/machdep.h>
44#include <asm/pmac_feature.h>
45#include <asm/sections.h>
46#include <asm/irq.h>
47#include <asm/mediabay.h>
48
49#define DRV_NAME "ide-pmac"
50
51#undef IDE_PMAC_DEBUG
52
53#define DMA_WAIT_TIMEOUT 50
54
55typedef struct pmac_ide_hwif {
56 unsigned long regbase;
57 int irq;
58 int kind;
59 int aapl_bus_id;
60 unsigned broken_dma : 1;
61 unsigned broken_dma_warn : 1;
62 struct device_node* node;
63 struct macio_dev *mdev;
64 u32 timings[4];
65 volatile u32 __iomem * *kauai_fcr;
66 ide_hwif_t *hwif;
67
68 /* Those fields are duplicating what is in hwif. We currently
69 * can't use the hwif ones because of some assumptions that are
70 * beeing done by the generic code about the kind of dma controller
71 * and format of the dma table. This will have to be fixed though.
72 */
73 volatile struct dbdma_regs __iomem * dma_regs;
74 struct dbdma_cmd* dma_table_cpu;
75} pmac_ide_hwif_t;
76
77enum {
78 controller_ohare, /* OHare based */
79 controller_heathrow, /* Heathrow/Paddington */
80 controller_kl_ata3, /* KeyLargo ATA-3 */
81 controller_kl_ata4, /* KeyLargo ATA-4 */
82 controller_un_ata6, /* UniNorth2 ATA-6 */
83 controller_k2_ata6, /* K2 ATA-6 */
84 controller_sh_ata6, /* Shasta ATA-6 */
85};
86
87static const char* model_name[] = {
88 "OHare ATA", /* OHare based */
89 "Heathrow ATA", /* Heathrow/Paddington */
90 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
91 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
92 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
93 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
94 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
95};
96
97/*
98 * Extra registers, both 32-bit little-endian
99 */
100#define IDE_TIMING_CONFIG 0x200
101#define IDE_INTERRUPT 0x300
102
103/* Kauai (U2) ATA has different register setup */
104#define IDE_KAUAI_PIO_CONFIG 0x200
105#define IDE_KAUAI_ULTRA_CONFIG 0x210
106#define IDE_KAUAI_POLL_CONFIG 0x220
107
108/*
109 * Timing configuration register definitions
110 */
111
112/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
113#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
114#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
115#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
116#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
117
118/* 133Mhz cell, found in shasta.
119 * See comments about 100 Mhz Uninorth 2...
120 * Note that PIO_MASK and MDMA_MASK seem to overlap
121 */
122#define TR_133_PIOREG_PIO_MASK 0xff000fff
123#define TR_133_PIOREG_MDMA_MASK 0x00fff800
124#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
125#define TR_133_UDMAREG_UDMA_EN 0x00000001
126
127/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
128 * this one yet, it appears as a pci device (106b/0033) on uninorth
129 * internal PCI bus and it's clock is controlled like gem or fw. It
130 * appears to be an evolution of keylargo ATA4 with a timing register
131 * extended to 2 32bits registers and a similar DBDMA channel. Other
132 * registers seem to exist but I can't tell much about them.
133 *
134 * So far, I'm using pre-calculated tables for this extracted from
135 * the values used by the MacOS X driver.
136 *
137 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
138 * register controls the UDMA timings. At least, it seems bit 0
139 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
140 * cycle time in units of 10ns. Bits 8..15 are used by I don't
141 * know their meaning yet
142 */
143#define TR_100_PIOREG_PIO_MASK 0xff000fff
144#define TR_100_PIOREG_MDMA_MASK 0x00fff000
145#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
146#define TR_100_UDMAREG_UDMA_EN 0x00000001
147
148
149/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
150 * 40 connector cable and to 4 on 80 connector one.
151 * Clock unit is 15ns (66Mhz)
152 *
153 * 3 Values can be programmed:
154 * - Write data setup, which appears to match the cycle time. They
155 * also call it DIOW setup.
156 * - Ready to pause time (from spec)
157 * - Address setup. That one is weird. I don't see where exactly
158 * it fits in UDMA cycles, I got it's name from an obscure piece
159 * of commented out code in Darwin. They leave it to 0, we do as
160 * well, despite a comment that would lead to think it has a
161 * min value of 45ns.
162 * Apple also add 60ns to the write data setup (or cycle time ?) on
163 * reads.
164 */
165#define TR_66_UDMA_MASK 0xfff00000
166#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
167#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
168#define TR_66_UDMA_ADDRSETUP_SHIFT 29
169#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
170#define TR_66_UDMA_RDY2PAUS_SHIFT 25
171#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
172#define TR_66_UDMA_WRDATASETUP_SHIFT 21
173#define TR_66_MDMA_MASK 0x000ffc00
174#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
175#define TR_66_MDMA_RECOVERY_SHIFT 15
176#define TR_66_MDMA_ACCESS_MASK 0x00007c00
177#define TR_66_MDMA_ACCESS_SHIFT 10
178#define TR_66_PIO_MASK 0x000003ff
179#define TR_66_PIO_RECOVERY_MASK 0x000003e0
180#define TR_66_PIO_RECOVERY_SHIFT 5
181#define TR_66_PIO_ACCESS_MASK 0x0000001f
182#define TR_66_PIO_ACCESS_SHIFT 0
183
184/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
185 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
186 *
187 * The access time and recovery time can be programmed. Some older
188 * Darwin code base limit OHare to 150ns cycle time. I decided to do
189 * the same here fore safety against broken old hardware ;)
190 * The HalfTick bit, when set, adds half a clock (15ns) to the access
191 * time and removes one from recovery. It's not supported on KeyLargo
192 * implementation afaik. The E bit appears to be set for PIO mode 0 and
193 * is used to reach long timings used in this mode.
194 */
195#define TR_33_MDMA_MASK 0x003ff800
196#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
197#define TR_33_MDMA_RECOVERY_SHIFT 16
198#define TR_33_MDMA_ACCESS_MASK 0x0000f800
199#define TR_33_MDMA_ACCESS_SHIFT 11
200#define TR_33_MDMA_HALFTICK 0x00200000
201#define TR_33_PIO_MASK 0x000007ff
202#define TR_33_PIO_E 0x00000400
203#define TR_33_PIO_RECOVERY_MASK 0x000003e0
204#define TR_33_PIO_RECOVERY_SHIFT 5
205#define TR_33_PIO_ACCESS_MASK 0x0000001f
206#define TR_33_PIO_ACCESS_SHIFT 0
207
208/*
209 * Interrupt register definitions
210 */
211#define IDE_INTR_DMA 0x80000000
212#define IDE_INTR_DEVICE 0x40000000
213
214/*
215 * FCR Register on Kauai. Not sure what bit 0x4 is ...
216 */
217#define KAUAI_FCR_UATA_MAGIC 0x00000004
218#define KAUAI_FCR_UATA_RESET_N 0x00000002
219#define KAUAI_FCR_UATA_ENABLE 0x00000001
220
221/* Rounded Multiword DMA timings
222 *
223 * I gave up finding a generic formula for all controller
224 * types and instead, built tables based on timing values
225 * used by Apple in Darwin's implementation.
226 */
227struct mdma_timings_t {
228 int accessTime;
229 int recoveryTime;
230 int cycleTime;
231};
232
233struct mdma_timings_t mdma_timings_33[] =
234{
235 { 240, 240, 480 },
236 { 180, 180, 360 },
237 { 135, 135, 270 },
238 { 120, 120, 240 },
239 { 105, 105, 210 },
240 { 90, 90, 180 },
241 { 75, 75, 150 },
242 { 75, 45, 120 },
243 { 0, 0, 0 }
244};
245
246struct mdma_timings_t mdma_timings_33k[] =
247{
248 { 240, 240, 480 },
249 { 180, 180, 360 },
250 { 150, 150, 300 },
251 { 120, 120, 240 },
252 { 90, 120, 210 },
253 { 90, 90, 180 },
254 { 90, 60, 150 },
255 { 90, 30, 120 },
256 { 0, 0, 0 }
257};
258
259struct mdma_timings_t mdma_timings_66[] =
260{
261 { 240, 240, 480 },
262 { 180, 180, 360 },
263 { 135, 135, 270 },
264 { 120, 120, 240 },
265 { 105, 105, 210 },
266 { 90, 90, 180 },
267 { 90, 75, 165 },
268 { 75, 45, 120 },
269 { 0, 0, 0 }
270};
271
272/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
273struct {
274 int addrSetup; /* ??? */
275 int rdy2pause;
276 int wrDataSetup;
277} kl66_udma_timings[] =
278{
279 { 0, 180, 120 }, /* Mode 0 */
280 { 0, 150, 90 }, /* 1 */
281 { 0, 120, 60 }, /* 2 */
282 { 0, 90, 45 }, /* 3 */
283 { 0, 90, 30 } /* 4 */
284};
285
286/* UniNorth 2 ATA/100 timings */
287struct kauai_timing {
288 int cycle_time;
289 u32 timing_reg;
290};
291
292static struct kauai_timing kauai_pio_timings[] =
293{
294 { 930 , 0x08000fff },
295 { 600 , 0x08000a92 },
296 { 383 , 0x0800060f },
297 { 360 , 0x08000492 },
298 { 330 , 0x0800048f },
299 { 300 , 0x080003cf },
300 { 270 , 0x080003cc },
301 { 240 , 0x0800038b },
302 { 239 , 0x0800030c },
303 { 180 , 0x05000249 },
304 { 120 , 0x04000148 },
305 { 0 , 0 },
306};
307
308static struct kauai_timing kauai_mdma_timings[] =
309{
310 { 1260 , 0x00fff000 },
311 { 480 , 0x00618000 },
312 { 360 , 0x00492000 },
313 { 270 , 0x0038e000 },
314 { 240 , 0x0030c000 },
315 { 210 , 0x002cb000 },
316 { 180 , 0x00249000 },
317 { 150 , 0x00209000 },
318 { 120 , 0x00148000 },
319 { 0 , 0 },
320};
321
322static struct kauai_timing kauai_udma_timings[] =
323{
324 { 120 , 0x000070c0 },
325 { 90 , 0x00005d80 },
326 { 60 , 0x00004a60 },
327 { 45 , 0x00003a50 },
328 { 30 , 0x00002a30 },
329 { 20 , 0x00002921 },
330 { 0 , 0 },
331};
332
333static struct kauai_timing shasta_pio_timings[] =
334{
335 { 930 , 0x08000fff },
336 { 600 , 0x0A000c97 },
337 { 383 , 0x07000712 },
338 { 360 , 0x040003cd },
339 { 330 , 0x040003cd },
340 { 300 , 0x040003cd },
341 { 270 , 0x040003cd },
342 { 240 , 0x040003cd },
343 { 239 , 0x040003cd },
344 { 180 , 0x0400028b },
345 { 120 , 0x0400010a },
346 { 0 , 0 },
347};
348
349static struct kauai_timing shasta_mdma_timings[] =
350{
351 { 1260 , 0x00fff000 },
352 { 480 , 0x00820800 },
353 { 360 , 0x00820800 },
354 { 270 , 0x00820800 },
355 { 240 , 0x00820800 },
356 { 210 , 0x00820800 },
357 { 180 , 0x00820800 },
358 { 150 , 0x0028b000 },
359 { 120 , 0x001ca000 },
360 { 0 , 0 },
361};
362
363static struct kauai_timing shasta_udma133_timings[] =
364{
365 { 120 , 0x00035901, },
366 { 90 , 0x000348b1, },
367 { 60 , 0x00033881, },
368 { 45 , 0x00033861, },
369 { 30 , 0x00033841, },
370 { 20 , 0x00033031, },
371 { 15 , 0x00033021, },
372 { 0 , 0 },
373};
374
375
376static inline u32
377kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
378{
379 int i;
380
381 for (i=0; table[i].cycle_time; i++)
382 if (cycle_time > table[i+1].cycle_time)
383 return table[i].timing_reg;
384 BUG();
385 return 0;
386}
387
388/* allow up to 256 DBDMA commands per xfer */
389#define MAX_DCMDS 256
390
391/*
392 * Wait 1s for disk to answer on IDE bus after a hard reset
393 * of the device (via GPIO/FCR).
394 *
395 * Some devices seem to "pollute" the bus even after dropping
396 * the BSY bit (typically some combo drives slave on the UDMA
397 * bus) after a hard reset. Since we hard reset all drives on
398 * KeyLargo ATA66, we have to keep that delay around. I may end
399 * up not hard resetting anymore on these and keep the delay only
400 * for older interfaces instead (we have to reset when coming
401 * from MacOS...) --BenH.
402 */
403#define IDE_WAKEUP_DELAY (1*HZ)
404
405static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
406
407#define PMAC_IDE_REG(x) \
408 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
409
410/*
411 * Apply the timings of the proper unit (master/slave) to the shared
412 * timing register when selecting that unit. This version is for
413 * ASICs with a single timing register
414 */
415static void pmac_ide_apply_timings(ide_drive_t *drive)
416{
417 ide_hwif_t *hwif = drive->hwif;
418 pmac_ide_hwif_t *pmif =
419 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
420
421 if (drive->dn & 1)
422 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
423 else
424 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
425 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
426}
427
428/*
429 * Apply the timings of the proper unit (master/slave) to the shared
430 * timing register when selecting that unit. This version is for
431 * ASICs with a dual timing register (Kauai)
432 */
433static void pmac_ide_kauai_apply_timings(ide_drive_t *drive)
434{
435 ide_hwif_t *hwif = drive->hwif;
436 pmac_ide_hwif_t *pmif =
437 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
438
439 if (drive->dn & 1) {
440 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
441 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
442 } else {
443 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
444 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
445 }
446 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
447}
448
449/*
450 * Force an update of controller timing values for a given drive
451 */
452static void
453pmac_ide_do_update_timings(ide_drive_t *drive)
454{
455 ide_hwif_t *hwif = drive->hwif;
456 pmac_ide_hwif_t *pmif =
457 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
458
459 if (pmif->kind == controller_sh_ata6 ||
460 pmif->kind == controller_un_ata6 ||
461 pmif->kind == controller_k2_ata6)
462 pmac_ide_kauai_apply_timings(drive);
463 else
464 pmac_ide_apply_timings(drive);
465}
466
467static void pmac_dev_select(ide_drive_t *drive)
468{
469 pmac_ide_apply_timings(drive);
470
471 writeb(drive->select | ATA_DEVICE_OBS,
472 (void __iomem *)drive->hwif->io_ports.device_addr);
473}
474
475static void pmac_kauai_dev_select(ide_drive_t *drive)
476{
477 pmac_ide_kauai_apply_timings(drive);
478
479 writeb(drive->select | ATA_DEVICE_OBS,
480 (void __iomem *)drive->hwif->io_ports.device_addr);
481}
482
483static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
484{
485 writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
486 (void)readl((void __iomem *)(hwif->io_ports.data_addr
487 + IDE_TIMING_CONFIG));
488}
489
490static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl)
491{
492 writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
493 (void)readl((void __iomem *)(hwif->io_ports.data_addr
494 + IDE_TIMING_CONFIG));
495}
496
497/*
498 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
499 */
500static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
501{
502 pmac_ide_hwif_t *pmif =
503 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
504 const u8 pio = drive->pio_mode - XFER_PIO_0;
505 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
506 u32 *timings, t;
507 unsigned accessTicks, recTicks;
508 unsigned accessTime, recTime;
509 unsigned int cycle_time;
510
511 /* which drive is it ? */
512 timings = &pmif->timings[drive->dn & 1];
513 t = *timings;
514
515 cycle_time = ide_pio_cycle_time(drive, pio);
516
517 switch (pmif->kind) {
518 case controller_sh_ata6: {
519 /* 133Mhz cell */
520 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
521 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
522 break;
523 }
524 case controller_un_ata6:
525 case controller_k2_ata6: {
526 /* 100Mhz cell */
527 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
528 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
529 break;
530 }
531 case controller_kl_ata4:
532 /* 66Mhz cell */
533 recTime = cycle_time - tim->active - tim->setup;
534 recTime = max(recTime, 150U);
535 accessTime = tim->active;
536 accessTime = max(accessTime, 150U);
537 accessTicks = SYSCLK_TICKS_66(accessTime);
538 accessTicks = min(accessTicks, 0x1fU);
539 recTicks = SYSCLK_TICKS_66(recTime);
540 recTicks = min(recTicks, 0x1fU);
541 t = (t & ~TR_66_PIO_MASK) |
542 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
543 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
544 break;
545 default: {
546 /* 33Mhz cell */
547 int ebit = 0;
548 recTime = cycle_time - tim->active - tim->setup;
549 recTime = max(recTime, 150U);
550 accessTime = tim->active;
551 accessTime = max(accessTime, 150U);
552 accessTicks = SYSCLK_TICKS(accessTime);
553 accessTicks = min(accessTicks, 0x1fU);
554 accessTicks = max(accessTicks, 4U);
555 recTicks = SYSCLK_TICKS(recTime);
556 recTicks = min(recTicks, 0x1fU);
557 recTicks = max(recTicks, 5U) - 4;
558 if (recTicks > 9) {
559 recTicks--; /* guess, but it's only for PIO0, so... */
560 ebit = 1;
561 }
562 t = (t & ~TR_33_PIO_MASK) |
563 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
564 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
565 if (ebit)
566 t |= TR_33_PIO_E;
567 break;
568 }
569 }
570
571#ifdef IDE_PMAC_DEBUG
572 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
573 drive->name, pio, *timings);
574#endif
575
576 *timings = t;
577 pmac_ide_do_update_timings(drive);
578}
579
580/*
581 * Calculate KeyLargo ATA/66 UDMA timings
582 */
583static int
584set_timings_udma_ata4(u32 *timings, u8 speed)
585{
586 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
587
588 if (speed > XFER_UDMA_4)
589 return 1;
590
591 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
592 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
593 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
594
595 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
596 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
597 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
598 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
599 TR_66_UDMA_EN;
600#ifdef IDE_PMAC_DEBUG
601 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
602 speed & 0xf, *timings);
603#endif
604
605 return 0;
606}
607
608/*
609 * Calculate Kauai ATA/100 UDMA timings
610 */
611static int
612set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
613{
614 struct ide_timing *t = ide_timing_find_mode(speed);
615 u32 tr;
616
617 if (speed > XFER_UDMA_5 || t == NULL)
618 return 1;
619 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
620 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
621 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
622
623 return 0;
624}
625
626/*
627 * Calculate Shasta ATA/133 UDMA timings
628 */
629static int
630set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
631{
632 struct ide_timing *t = ide_timing_find_mode(speed);
633 u32 tr;
634
635 if (speed > XFER_UDMA_6 || t == NULL)
636 return 1;
637 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
638 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
639 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
640
641 return 0;
642}
643
644/*
645 * Calculate MDMA timings for all cells
646 */
647static void
648set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
649 u8 speed)
650{
651 u16 *id = drive->id;
652 int cycleTime, accessTime = 0, recTime = 0;
653 unsigned accessTicks, recTicks;
654 struct mdma_timings_t* tm = NULL;
655 int i;
656
657 /* Get default cycle time for mode */
658 switch(speed & 0xf) {
659 case 0: cycleTime = 480; break;
660 case 1: cycleTime = 150; break;
661 case 2: cycleTime = 120; break;
662 default:
663 BUG();
664 break;
665 }
666
667 /* Check if drive provides explicit DMA cycle time */
668 if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
669 cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
670
671 /* OHare limits according to some old Apple sources */
672 if ((intf_type == controller_ohare) && (cycleTime < 150))
673 cycleTime = 150;
674 /* Get the proper timing array for this controller */
675 switch(intf_type) {
676 case controller_sh_ata6:
677 case controller_un_ata6:
678 case controller_k2_ata6:
679 break;
680 case controller_kl_ata4:
681 tm = mdma_timings_66;
682 break;
683 case controller_kl_ata3:
684 tm = mdma_timings_33k;
685 break;
686 default:
687 tm = mdma_timings_33;
688 break;
689 }
690 if (tm != NULL) {
691 /* Lookup matching access & recovery times */
692 i = -1;
693 for (;;) {
694 if (tm[i+1].cycleTime < cycleTime)
695 break;
696 i++;
697 }
698 cycleTime = tm[i].cycleTime;
699 accessTime = tm[i].accessTime;
700 recTime = tm[i].recoveryTime;
701
702#ifdef IDE_PMAC_DEBUG
703 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
704 drive->name, cycleTime, accessTime, recTime);
705#endif
706 }
707 switch(intf_type) {
708 case controller_sh_ata6: {
709 /* 133Mhz cell */
710 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
711 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
712 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
713 }
714 case controller_un_ata6:
715 case controller_k2_ata6: {
716 /* 100Mhz cell */
717 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
718 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
719 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
720 }
721 break;
722 case controller_kl_ata4:
723 /* 66Mhz cell */
724 accessTicks = SYSCLK_TICKS_66(accessTime);
725 accessTicks = min(accessTicks, 0x1fU);
726 accessTicks = max(accessTicks, 0x1U);
727 recTicks = SYSCLK_TICKS_66(recTime);
728 recTicks = min(recTicks, 0x1fU);
729 recTicks = max(recTicks, 0x3U);
730 /* Clear out mdma bits and disable udma */
731 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
732 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
733 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
734 break;
735 case controller_kl_ata3:
736 /* 33Mhz cell on KeyLargo */
737 accessTicks = SYSCLK_TICKS(accessTime);
738 accessTicks = max(accessTicks, 1U);
739 accessTicks = min(accessTicks, 0x1fU);
740 accessTime = accessTicks * IDE_SYSCLK_NS;
741 recTicks = SYSCLK_TICKS(recTime);
742 recTicks = max(recTicks, 1U);
743 recTicks = min(recTicks, 0x1fU);
744 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
745 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
746 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
747 break;
748 default: {
749 /* 33Mhz cell on others */
750 int halfTick = 0;
751 int origAccessTime = accessTime;
752 int origRecTime = recTime;
753
754 accessTicks = SYSCLK_TICKS(accessTime);
755 accessTicks = max(accessTicks, 1U);
756 accessTicks = min(accessTicks, 0x1fU);
757 accessTime = accessTicks * IDE_SYSCLK_NS;
758 recTicks = SYSCLK_TICKS(recTime);
759 recTicks = max(recTicks, 2U) - 1;
760 recTicks = min(recTicks, 0x1fU);
761 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
762 if ((accessTicks > 1) &&
763 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
764 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
765 halfTick = 1;
766 accessTicks--;
767 }
768 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
769 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
770 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
771 if (halfTick)
772 *timings |= TR_33_MDMA_HALFTICK;
773 }
774 }
775#ifdef IDE_PMAC_DEBUG
776 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
777 drive->name, speed & 0xf, *timings);
778#endif
779}
780
781static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
782{
783 pmac_ide_hwif_t *pmif =
784 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
785 int ret = 0;
786 u32 *timings, *timings2, tl[2];
787 u8 unit = drive->dn & 1;
788 const u8 speed = drive->dma_mode;
789
790 timings = &pmif->timings[unit];
791 timings2 = &pmif->timings[unit+2];
792
793 /* Copy timings to local image */
794 tl[0] = *timings;
795 tl[1] = *timings2;
796
797 if (speed >= XFER_UDMA_0) {
798 if (pmif->kind == controller_kl_ata4)
799 ret = set_timings_udma_ata4(&tl[0], speed);
800 else if (pmif->kind == controller_un_ata6
801 || pmif->kind == controller_k2_ata6)
802 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
803 else if (pmif->kind == controller_sh_ata6)
804 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
805 else
806 ret = -1;
807 } else
808 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
809
810 if (ret)
811 return;
812
813 /* Apply timings to controller */
814 *timings = tl[0];
815 *timings2 = tl[1];
816
817 pmac_ide_do_update_timings(drive);
818}
819
820/*
821 * Blast some well known "safe" values to the timing registers at init or
822 * wakeup from sleep time, before we do real calculation
823 */
824static void
825sanitize_timings(pmac_ide_hwif_t *pmif)
826{
827 unsigned int value, value2 = 0;
828
829 switch(pmif->kind) {
830 case controller_sh_ata6:
831 value = 0x0a820c97;
832 value2 = 0x00033031;
833 break;
834 case controller_un_ata6:
835 case controller_k2_ata6:
836 value = 0x08618a92;
837 value2 = 0x00002921;
838 break;
839 case controller_kl_ata4:
840 value = 0x0008438c;
841 break;
842 case controller_kl_ata3:
843 value = 0x00084526;
844 break;
845 case controller_heathrow:
846 case controller_ohare:
847 default:
848 value = 0x00074526;
849 break;
850 }
851 pmif->timings[0] = pmif->timings[1] = value;
852 pmif->timings[2] = pmif->timings[3] = value2;
853}
854
855static int on_media_bay(pmac_ide_hwif_t *pmif)
856{
857 return pmif->mdev && pmif->mdev->media_bay != NULL;
858}
859
860/* Suspend call back, should be called after the child devices
861 * have actually been suspended
862 */
863static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
864{
865 /* We clear the timings */
866 pmif->timings[0] = 0;
867 pmif->timings[1] = 0;
868
869 disable_irq(pmif->irq);
870
871 /* The media bay will handle itself just fine */
872 if (on_media_bay(pmif))
873 return 0;
874
875 /* Kauai has bus control FCRs directly here */
876 if (pmif->kauai_fcr) {
877 u32 fcr = readl(pmif->kauai_fcr);
878 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
879 writel(fcr, pmif->kauai_fcr);
880 }
881
882 /* Disable the bus on older machines and the cell on kauai */
883 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
884 0);
885
886 return 0;
887}
888
889/* Resume call back, should be called before the child devices
890 * are resumed
891 */
892static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
893{
894 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
895 if (!on_media_bay(pmif)) {
896 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
897 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
898 msleep(10);
899 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
900
901 /* Kauai has it different */
902 if (pmif->kauai_fcr) {
903 u32 fcr = readl(pmif->kauai_fcr);
904 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
905 writel(fcr, pmif->kauai_fcr);
906 }
907
908 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
909 }
910
911 /* Sanitize drive timings */
912 sanitize_timings(pmif);
913
914 enable_irq(pmif->irq);
915
916 return 0;
917}
918
919static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
920{
921 pmac_ide_hwif_t *pmif =
922 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
923 struct device_node *np = pmif->node;
924 const char *cable = of_get_property(np, "cable-type", NULL);
925 struct device_node *root = of_find_node_by_path("/");
926 const char *model = of_get_property(root, "model", NULL);
927
928 /* Get cable type from device-tree. */
929 if (cable && !strncmp(cable, "80-", 3)) {
930 /* Some drives fail to detect 80c cable in PowerBook */
931 /* These machine use proprietary short IDE cable anyway */
932 if (!strncmp(model, "PowerBook", 9))
933 return ATA_CBL_PATA40_SHORT;
934 else
935 return ATA_CBL_PATA80;
936 }
937
938 /*
939 * G5's seem to have incorrect cable type in device-tree.
940 * Let's assume they have a 80 conductor cable, this seem
941 * to be always the case unless the user mucked around.
942 */
943 if (of_device_is_compatible(np, "K2-UATA") ||
944 of_device_is_compatible(np, "shasta-ata"))
945 return ATA_CBL_PATA80;
946
947 return ATA_CBL_PATA40;
948}
949
950static void pmac_ide_init_dev(ide_drive_t *drive)
951{
952 ide_hwif_t *hwif = drive->hwif;
953 pmac_ide_hwif_t *pmif =
954 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
955
956 if (on_media_bay(pmif)) {
957 if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
958 drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
959 return;
960 }
961 drive->dev_flags |= IDE_DFLAG_NOPROBE;
962 }
963}
964
965static const struct ide_tp_ops pmac_tp_ops = {
966 .exec_command = pmac_exec_command,
967 .read_status = ide_read_status,
968 .read_altstatus = ide_read_altstatus,
969 .write_devctl = pmac_write_devctl,
970
971 .dev_select = pmac_dev_select,
972 .tf_load = ide_tf_load,
973 .tf_read = ide_tf_read,
974
975 .input_data = ide_input_data,
976 .output_data = ide_output_data,
977};
978
979static const struct ide_tp_ops pmac_ata6_tp_ops = {
980 .exec_command = pmac_exec_command,
981 .read_status = ide_read_status,
982 .read_altstatus = ide_read_altstatus,
983 .write_devctl = pmac_write_devctl,
984
985 .dev_select = pmac_kauai_dev_select,
986 .tf_load = ide_tf_load,
987 .tf_read = ide_tf_read,
988
989 .input_data = ide_input_data,
990 .output_data = ide_output_data,
991};
992
993static const struct ide_port_ops pmac_ide_ata4_port_ops = {
994 .init_dev = pmac_ide_init_dev,
995 .set_pio_mode = pmac_ide_set_pio_mode,
996 .set_dma_mode = pmac_ide_set_dma_mode,
997 .cable_detect = pmac_ide_cable_detect,
998};
999
1000static const struct ide_port_ops pmac_ide_port_ops = {
1001 .init_dev = pmac_ide_init_dev,
1002 .set_pio_mode = pmac_ide_set_pio_mode,
1003 .set_dma_mode = pmac_ide_set_dma_mode,
1004};
1005
1006static const struct ide_dma_ops pmac_dma_ops;
1007
1008static const struct ide_port_info pmac_port_info = {
1009 .name = DRV_NAME,
1010 .init_dma = pmac_ide_init_dma,
1011 .chipset = ide_pmac,
1012 .tp_ops = &pmac_tp_ops,
1013 .port_ops = &pmac_ide_port_ops,
1014 .dma_ops = &pmac_dma_ops,
1015 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1016 IDE_HFLAG_POST_SET_MODE |
1017 IDE_HFLAG_MMIO |
1018 IDE_HFLAG_UNMASK_IRQS,
1019 .pio_mask = ATA_PIO4,
1020 .mwdma_mask = ATA_MWDMA2,
1021};
1022
1023/*
1024 * Setup, register & probe an IDE channel driven by this driver, this is
1025 * called by one of the 2 probe functions (macio or PCI).
1026 */
1027static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif,
1028 struct ide_hw *hw)
1029{
1030 struct device_node *np = pmif->node;
1031 const int *bidp;
1032 struct ide_host *host;
1033 ide_hwif_t *hwif;
1034 struct ide_hw *hws[] = { hw };
1035 struct ide_port_info d = pmac_port_info;
1036 int rc;
1037
1038 pmif->broken_dma = pmif->broken_dma_warn = 0;
1039 if (of_device_is_compatible(np, "shasta-ata")) {
1040 pmif->kind = controller_sh_ata6;
1041 d.tp_ops = &pmac_ata6_tp_ops;
1042 d.port_ops = &pmac_ide_ata4_port_ops;
1043 d.udma_mask = ATA_UDMA6;
1044 } else if (of_device_is_compatible(np, "kauai-ata")) {
1045 pmif->kind = controller_un_ata6;
1046 d.tp_ops = &pmac_ata6_tp_ops;
1047 d.port_ops = &pmac_ide_ata4_port_ops;
1048 d.udma_mask = ATA_UDMA5;
1049 } else if (of_device_is_compatible(np, "K2-UATA")) {
1050 pmif->kind = controller_k2_ata6;
1051 d.tp_ops = &pmac_ata6_tp_ops;
1052 d.port_ops = &pmac_ide_ata4_port_ops;
1053 d.udma_mask = ATA_UDMA5;
1054 } else if (of_device_is_compatible(np, "keylargo-ata")) {
1055 if (strcmp(np->name, "ata-4") == 0) {
1056 pmif->kind = controller_kl_ata4;
1057 d.port_ops = &pmac_ide_ata4_port_ops;
1058 d.udma_mask = ATA_UDMA4;
1059 } else
1060 pmif->kind = controller_kl_ata3;
1061 } else if (of_device_is_compatible(np, "heathrow-ata")) {
1062 pmif->kind = controller_heathrow;
1063 } else {
1064 pmif->kind = controller_ohare;
1065 pmif->broken_dma = 1;
1066 }
1067
1068 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1069 pmif->aapl_bus_id = bidp ? *bidp : 0;
1070
1071 /* On Kauai-type controllers, we make sure the FCR is correct */
1072 if (pmif->kauai_fcr)
1073 writel(KAUAI_FCR_UATA_MAGIC |
1074 KAUAI_FCR_UATA_RESET_N |
1075 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1076
1077 /* Make sure we have sane timings */
1078 sanitize_timings(pmif);
1079
1080 /* If we are on a media bay, wait for it to settle and lock it */
1081 if (pmif->mdev)
1082 lock_media_bay(pmif->mdev->media_bay);
1083
1084 host = ide_host_alloc(&d, hws, 1);
1085 if (host == NULL) {
1086 rc = -ENOMEM;
1087 goto bail;
1088 }
1089 hwif = pmif->hwif = host->ports[0];
1090
1091 if (on_media_bay(pmif)) {
1092 /* Fixup bus ID for media bay */
1093 if (!bidp)
1094 pmif->aapl_bus_id = 1;
1095 } else if (pmif->kind == controller_ohare) {
1096 /* The code below is having trouble on some ohare machines
1097 * (timing related ?). Until I can put my hand on one of these
1098 * units, I keep the old way
1099 */
1100 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1101 } else {
1102 /* This is necessary to enable IDE when net-booting */
1103 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1104 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1105 msleep(10);
1106 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1107 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1108 }
1109
1110 printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1111 "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1112 pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1113 on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
1114
1115 rc = ide_host_register(host, &d, hws);
1116 if (rc)
1117 pmif->hwif = NULL;
1118
1119 if (pmif->mdev)
1120 unlock_media_bay(pmif->mdev->media_bay);
1121
1122 bail:
1123 if (rc && host)
1124 ide_host_free(host);
1125 return rc;
1126}
1127
1128static void __devinit pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
1129{
1130 int i;
1131
1132 for (i = 0; i < 8; ++i)
1133 hw->io_ports_array[i] = base + i * 0x10;
1134
1135 hw->io_ports.ctl_addr = base + 0x160;
1136}
1137
1138/*
1139 * Attach to a macio probed interface
1140 */
1141static int __devinit
1142pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1143{
1144 void __iomem *base;
1145 unsigned long regbase;
1146 pmac_ide_hwif_t *pmif;
1147 int irq, rc;
1148 struct ide_hw hw;
1149
1150 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1151 if (pmif == NULL)
1152 return -ENOMEM;
1153
1154 if (macio_resource_count(mdev) == 0) {
1155 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1156 mdev->ofdev.dev.of_node->full_name);
1157 rc = -ENXIO;
1158 goto out_free_pmif;
1159 }
1160
1161 /* Request memory resource for IO ports */
1162 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1163 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1164 "%s!\n", mdev->ofdev.dev.of_node->full_name);
1165 rc = -EBUSY;
1166 goto out_free_pmif;
1167 }
1168
1169 /* XXX This is bogus. Should be fixed in the registry by checking
1170 * the kind of host interrupt controller, a bit like gatwick
1171 * fixes in irq.c. That works well enough for the single case
1172 * where that happens though...
1173 */
1174 if (macio_irq_count(mdev) == 0) {
1175 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1176 "13\n", mdev->ofdev.dev.of_node->full_name);
1177 irq = irq_create_mapping(NULL, 13);
1178 } else
1179 irq = macio_irq(mdev, 0);
1180
1181 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1182 regbase = (unsigned long) base;
1183
1184 pmif->mdev = mdev;
1185 pmif->node = mdev->ofdev.dev.of_node;
1186 pmif->regbase = regbase;
1187 pmif->irq = irq;
1188 pmif->kauai_fcr = NULL;
1189
1190 if (macio_resource_count(mdev) >= 2) {
1191 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1192 printk(KERN_WARNING "ide-pmac: can't request DMA "
1193 "resource for %s!\n",
1194 mdev->ofdev.dev.of_node->full_name);
1195 else
1196 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1197 } else
1198 pmif->dma_regs = NULL;
1199
1200 dev_set_drvdata(&mdev->ofdev.dev, pmif);
1201
1202 memset(&hw, 0, sizeof(hw));
1203 pmac_ide_init_ports(&hw, pmif->regbase);
1204 hw.irq = irq;
1205 hw.dev = &mdev->bus->pdev->dev;
1206 hw.parent = &mdev->ofdev.dev;
1207
1208 rc = pmac_ide_setup_device(pmif, &hw);
1209 if (rc != 0) {
1210 /* The inteface is released to the common IDE layer */
1211 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1212 iounmap(base);
1213 if (pmif->dma_regs) {
1214 iounmap(pmif->dma_regs);
1215 macio_release_resource(mdev, 1);
1216 }
1217 macio_release_resource(mdev, 0);
1218 kfree(pmif);
1219 }
1220
1221 return rc;
1222
1223out_free_pmif:
1224 kfree(pmif);
1225 return rc;
1226}
1227
1228static int
1229pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1230{
1231 pmac_ide_hwif_t *pmif =
1232 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1233 int rc = 0;
1234
1235 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1236 && (mesg.event & PM_EVENT_SLEEP)) {
1237 rc = pmac_ide_do_suspend(pmif);
1238 if (rc == 0)
1239 mdev->ofdev.dev.power.power_state = mesg;
1240 }
1241
1242 return rc;
1243}
1244
1245static int
1246pmac_ide_macio_resume(struct macio_dev *mdev)
1247{
1248 pmac_ide_hwif_t *pmif =
1249 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1250 int rc = 0;
1251
1252 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1253 rc = pmac_ide_do_resume(pmif);
1254 if (rc == 0)
1255 mdev->ofdev.dev.power.power_state = PMSG_ON;
1256 }
1257
1258 return rc;
1259}
1260
1261/*
1262 * Attach to a PCI probed interface
1263 */
1264static int __devinit
1265pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1266{
1267 struct device_node *np;
1268 pmac_ide_hwif_t *pmif;
1269 void __iomem *base;
1270 unsigned long rbase, rlen;
1271 int rc;
1272 struct ide_hw hw;
1273
1274 np = pci_device_to_OF_node(pdev);
1275 if (np == NULL) {
1276 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1277 return -ENODEV;
1278 }
1279
1280 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1281 if (pmif == NULL)
1282 return -ENOMEM;
1283
1284 if (pci_enable_device(pdev)) {
1285 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1286 "%s\n", np->full_name);
1287 rc = -ENXIO;
1288 goto out_free_pmif;
1289 }
1290 pci_set_master(pdev);
1291
1292 if (pci_request_regions(pdev, "Kauai ATA")) {
1293 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1294 "%s\n", np->full_name);
1295 rc = -ENXIO;
1296 goto out_free_pmif;
1297 }
1298
1299 pmif->mdev = NULL;
1300 pmif->node = np;
1301
1302 rbase = pci_resource_start(pdev, 0);
1303 rlen = pci_resource_len(pdev, 0);
1304
1305 base = ioremap(rbase, rlen);
1306 pmif->regbase = (unsigned long) base + 0x2000;
1307 pmif->dma_regs = base + 0x1000;
1308 pmif->kauai_fcr = base;
1309 pmif->irq = pdev->irq;
1310
1311 pci_set_drvdata(pdev, pmif);
1312
1313 memset(&hw, 0, sizeof(hw));
1314 pmac_ide_init_ports(&hw, pmif->regbase);
1315 hw.irq = pdev->irq;
1316 hw.dev = &pdev->dev;
1317
1318 rc = pmac_ide_setup_device(pmif, &hw);
1319 if (rc != 0) {
1320 /* The inteface is released to the common IDE layer */
1321 pci_set_drvdata(pdev, NULL);
1322 iounmap(base);
1323 pci_release_regions(pdev);
1324 kfree(pmif);
1325 }
1326
1327 return rc;
1328
1329out_free_pmif:
1330 kfree(pmif);
1331 return rc;
1332}
1333
1334static int
1335pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1336{
1337 pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1338 int rc = 0;
1339
1340 if (mesg.event != pdev->dev.power.power_state.event
1341 && (mesg.event & PM_EVENT_SLEEP)) {
1342 rc = pmac_ide_do_suspend(pmif);
1343 if (rc == 0)
1344 pdev->dev.power.power_state = mesg;
1345 }
1346
1347 return rc;
1348}
1349
1350static int
1351pmac_ide_pci_resume(struct pci_dev *pdev)
1352{
1353 pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1354 int rc = 0;
1355
1356 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1357 rc = pmac_ide_do_resume(pmif);
1358 if (rc == 0)
1359 pdev->dev.power.power_state = PMSG_ON;
1360 }
1361
1362 return rc;
1363}
1364
1365#ifdef CONFIG_PMAC_MEDIABAY
1366static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
1367{
1368 pmac_ide_hwif_t *pmif =
1369 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1370
1371 switch(mb_state) {
1372 case MB_CD:
1373 if (!pmif->hwif->present)
1374 ide_port_scan(pmif->hwif);
1375 break;
1376 default:
1377 if (pmif->hwif->present)
1378 ide_port_unregister_devices(pmif->hwif);
1379 }
1380}
1381#endif /* CONFIG_PMAC_MEDIABAY */
1382
1383
1384static struct of_device_id pmac_ide_macio_match[] =
1385{
1386 {
1387 .name = "IDE",
1388 },
1389 {
1390 .name = "ATA",
1391 },
1392 {
1393 .type = "ide",
1394 },
1395 {
1396 .type = "ata",
1397 },
1398 {},
1399};
1400
1401static struct macio_driver pmac_ide_macio_driver =
1402{
1403 .driver = {
1404 .name = "ide-pmac",
1405 .owner = THIS_MODULE,
1406 .of_match_table = pmac_ide_macio_match,
1407 },
1408 .probe = pmac_ide_macio_attach,
1409 .suspend = pmac_ide_macio_suspend,
1410 .resume = pmac_ide_macio_resume,
1411#ifdef CONFIG_PMAC_MEDIABAY
1412 .mediabay_event = pmac_ide_macio_mb_event,
1413#endif
1414};
1415
1416static const struct pci_device_id pmac_ide_pci_match[] = {
1417 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1418 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1419 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1420 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1421 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1422 {},
1423};
1424
1425static struct pci_driver pmac_ide_pci_driver = {
1426 .name = "ide-pmac",
1427 .id_table = pmac_ide_pci_match,
1428 .probe = pmac_ide_pci_attach,
1429 .suspend = pmac_ide_pci_suspend,
1430 .resume = pmac_ide_pci_resume,
1431};
1432MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1433
1434int __init pmac_ide_probe(void)
1435{
1436 int error;
1437
1438 if (!machine_is(powermac))
1439 return -ENODEV;
1440
1441#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1442 error = pci_register_driver(&pmac_ide_pci_driver);
1443 if (error)
1444 goto out;
1445 error = macio_register_driver(&pmac_ide_macio_driver);
1446 if (error) {
1447 pci_unregister_driver(&pmac_ide_pci_driver);
1448 goto out;
1449 }
1450#else
1451 error = macio_register_driver(&pmac_ide_macio_driver);
1452 if (error)
1453 goto out;
1454 error = pci_register_driver(&pmac_ide_pci_driver);
1455 if (error) {
1456 macio_unregister_driver(&pmac_ide_macio_driver);
1457 goto out;
1458 }
1459#endif
1460out:
1461 return error;
1462}
1463
1464/*
1465 * pmac_ide_build_dmatable builds the DBDMA command list
1466 * for a transfer and sets the DBDMA channel to point to it.
1467 */
1468static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
1469{
1470 ide_hwif_t *hwif = drive->hwif;
1471 pmac_ide_hwif_t *pmif =
1472 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1473 struct dbdma_cmd *table;
1474 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1475 struct scatterlist *sg;
1476 int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1477 int i = cmd->sg_nents, count = 0;
1478
1479 /* DMA table is already aligned */
1480 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1481
1482 /* Make sure DMA controller is stopped (necessary ?) */
1483 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1484 while (readl(&dma->status) & RUN)
1485 udelay(1);
1486
1487 /* Build DBDMA commands list */
1488 sg = hwif->sg_table;
1489 while (i && sg_dma_len(sg)) {
1490 u32 cur_addr;
1491 u32 cur_len;
1492
1493 cur_addr = sg_dma_address(sg);
1494 cur_len = sg_dma_len(sg);
1495
1496 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1497 if (pmif->broken_dma_warn == 0) {
1498 printk(KERN_WARNING "%s: DMA on non aligned address, "
1499 "switching to PIO on Ohare chipset\n", drive->name);
1500 pmif->broken_dma_warn = 1;
1501 }
1502 return 0;
1503 }
1504 while (cur_len) {
1505 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1506
1507 if (count++ >= MAX_DCMDS) {
1508 printk(KERN_WARNING "%s: DMA table too small\n",
1509 drive->name);
1510 return 0;
1511 }
1512 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1513 st_le16(&table->req_count, tc);
1514 st_le32(&table->phy_addr, cur_addr);
1515 table->cmd_dep = 0;
1516 table->xfer_status = 0;
1517 table->res_count = 0;
1518 cur_addr += tc;
1519 cur_len -= tc;
1520 ++table;
1521 }
1522 sg = sg_next(sg);
1523 i--;
1524 }
1525
1526 /* convert the last command to an input/output last command */
1527 if (count) {
1528 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1529 /* add the stop command to the end of the list */
1530 memset(table, 0, sizeof(struct dbdma_cmd));
1531 st_le16(&table->command, DBDMA_STOP);
1532 mb();
1533 writel(hwif->dmatable_dma, &dma->cmdptr);
1534 return 1;
1535 }
1536
1537 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1538
1539 return 0; /* revert to PIO for this request */
1540}
1541
1542/*
1543 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1544 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1545 */
1546static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
1547{
1548 ide_hwif_t *hwif = drive->hwif;
1549 pmac_ide_hwif_t *pmif =
1550 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1551 u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
1552 u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1553
1554 if (pmac_ide_build_dmatable(drive, cmd) == 0)
1555 return 1;
1556
1557 /* Apple adds 60ns to wrDataSetup on reads */
1558 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1559 writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),
1560 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1561 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1562 }
1563
1564 return 0;
1565}
1566
1567/*
1568 * Kick the DMA controller into life after the DMA command has been issued
1569 * to the drive.
1570 */
1571static void
1572pmac_ide_dma_start(ide_drive_t *drive)
1573{
1574 ide_hwif_t *hwif = drive->hwif;
1575 pmac_ide_hwif_t *pmif =
1576 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1577 volatile struct dbdma_regs __iomem *dma;
1578
1579 dma = pmif->dma_regs;
1580
1581 writel((RUN << 16) | RUN, &dma->control);
1582 /* Make sure it gets to the controller right now */
1583 (void)readl(&dma->control);
1584}
1585
1586/*
1587 * After a DMA transfer, make sure the controller is stopped
1588 */
1589static int
1590pmac_ide_dma_end (ide_drive_t *drive)
1591{
1592 ide_hwif_t *hwif = drive->hwif;
1593 pmac_ide_hwif_t *pmif =
1594 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1595 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1596 u32 dstat;
1597
1598 dstat = readl(&dma->status);
1599 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1600
1601 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1602 * in theory, but with ATAPI decices doing buffer underruns, that would
1603 * cause us to disable DMA, which isn't what we want
1604 */
1605 return (dstat & (RUN|DEAD)) != RUN;
1606}
1607
1608/*
1609 * Check out that the interrupt we got was for us. We can't always know this
1610 * for sure with those Apple interfaces (well, we could on the recent ones but
1611 * that's not implemented yet), on the other hand, we don't have shared interrupts
1612 * so it's not really a problem
1613 */
1614static int
1615pmac_ide_dma_test_irq (ide_drive_t *drive)
1616{
1617 ide_hwif_t *hwif = drive->hwif;
1618 pmac_ide_hwif_t *pmif =
1619 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1620 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1621 unsigned long status, timeout;
1622
1623 /* We have to things to deal with here:
1624 *
1625 * - The dbdma won't stop if the command was started
1626 * but completed with an error without transferring all
1627 * datas. This happens when bad blocks are met during
1628 * a multi-block transfer.
1629 *
1630 * - The dbdma fifo hasn't yet finished flushing to
1631 * to system memory when the disk interrupt occurs.
1632 *
1633 */
1634
1635 /* If ACTIVE is cleared, the STOP command have passed and
1636 * transfer is complete.
1637 */
1638 status = readl(&dma->status);
1639 if (!(status & ACTIVE))
1640 return 1;
1641
1642 /* If dbdma didn't execute the STOP command yet, the
1643 * active bit is still set. We consider that we aren't
1644 * sharing interrupts (which is hopefully the case with
1645 * those controllers) and so we just try to flush the
1646 * channel for pending data in the fifo
1647 */
1648 udelay(1);
1649 writel((FLUSH << 16) | FLUSH, &dma->control);
1650 timeout = 0;
1651 for (;;) {
1652 udelay(1);
1653 status = readl(&dma->status);
1654 if ((status & FLUSH) == 0)
1655 break;
1656 if (++timeout > 100) {
1657 printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
1658 hwif->index);
1659 break;
1660 }
1661 }
1662 return 1;
1663}
1664
1665static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1666{
1667}
1668
1669static void
1670pmac_ide_dma_lost_irq (ide_drive_t *drive)
1671{
1672 ide_hwif_t *hwif = drive->hwif;
1673 pmac_ide_hwif_t *pmif =
1674 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1675 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1676 unsigned long status = readl(&dma->status);
1677
1678 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1679}
1680
1681static const struct ide_dma_ops pmac_dma_ops = {
1682 .dma_host_set = pmac_ide_dma_host_set,
1683 .dma_setup = pmac_ide_dma_setup,
1684 .dma_start = pmac_ide_dma_start,
1685 .dma_end = pmac_ide_dma_end,
1686 .dma_test_irq = pmac_ide_dma_test_irq,
1687 .dma_lost_irq = pmac_ide_dma_lost_irq,
1688};
1689
1690/*
1691 * Allocate the data structures needed for using DMA with an interface
1692 * and fill the proper list of functions pointers
1693 */
1694static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1695 const struct ide_port_info *d)
1696{
1697 pmac_ide_hwif_t *pmif =
1698 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1699 struct pci_dev *dev = to_pci_dev(hwif->dev);
1700
1701 /* We won't need pci_dev if we switch to generic consistent
1702 * DMA routines ...
1703 */
1704 if (dev == NULL || pmif->dma_regs == 0)
1705 return -ENODEV;
1706 /*
1707 * Allocate space for the DBDMA commands.
1708 * The +2 is +1 for the stop command and +1 to allow for
1709 * aligning the start address to a multiple of 16 bytes.
1710 */
1711 pmif->dma_table_cpu = pci_alloc_consistent(
1712 dev,
1713 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1714 &hwif->dmatable_dma);
1715 if (pmif->dma_table_cpu == NULL) {
1716 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1717 hwif->name);
1718 return -ENOMEM;
1719 }
1720
1721 hwif->sg_max_nents = MAX_DCMDS;
1722
1723 return 0;
1724}
1725
1726module_init(pmac_ide_probe);
1727
1728MODULE_LICENSE("GPL");