1/*
  2 * SPDX-License-Identifier: MIT
  3 */
  4
  5#include "gem/i915_gem_mman.h"
  6#include "gt/intel_engine_user.h"
  7
  8#include "i915_cmd_parser.h"
  9#include "i915_drv.h"
 10#include "i915_getparam.h"
 11#include "i915_perf.h"
 12
 13int i915_getparam_ioctl(struct drm_device *dev, void *data,
 14			struct drm_file *file_priv)
 15{
 16	struct drm_i915_private *i915 = to_i915(dev);
 17	struct pci_dev *pdev = to_pci_dev(dev->dev);
 18	const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
 19	drm_i915_getparam_t *param = data;
 20	int value = 0;
 21
 22	switch (param->param) {
 23	case I915_PARAM_IRQ_ACTIVE:
 24	case I915_PARAM_ALLOW_BATCHBUFFER:
 25	case I915_PARAM_LAST_DISPATCH:
 26	case I915_PARAM_HAS_EXEC_CONSTANTS:
 27		/* Reject all old ums/dri params. */
 28		return -ENODEV;
 29	case I915_PARAM_CHIPSET_ID:
 30		value = pdev->device;
 31		break;
 32	case I915_PARAM_REVISION:
 33		value = pdev->revision;
 34		break;
 35	case I915_PARAM_NUM_FENCES_AVAIL:
 36		value = to_gt(i915)->ggtt->num_fences;
 37		break;
 38	case I915_PARAM_HAS_OVERLAY:
 39		value = !!i915->display.overlay;
 40		break;
 41	case I915_PARAM_HAS_BSD:
 42		value = !!intel_engine_lookup_user(i915,
 43						   I915_ENGINE_CLASS_VIDEO, 0);
 44		break;
 45	case I915_PARAM_HAS_BLT:
 46		value = !!intel_engine_lookup_user(i915,
 47						   I915_ENGINE_CLASS_COPY, 0);
 48		break;
 49	case I915_PARAM_HAS_VEBOX:
 50		value = !!intel_engine_lookup_user(i915,
 51						   I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
 52		break;
 53	case I915_PARAM_HAS_BSD2:
 54		value = !!intel_engine_lookup_user(i915,
 55						   I915_ENGINE_CLASS_VIDEO, 1);
 56		break;
 57	case I915_PARAM_HAS_LLC:
 58		value = HAS_LLC(i915);
 59		break;
 60	case I915_PARAM_HAS_WT:
 61		value = HAS_WT(i915);
 62		break;
 63	case I915_PARAM_HAS_ALIASING_PPGTT:
 64		value = INTEL_PPGTT(i915);
 65		break;
 66	case I915_PARAM_HAS_SEMAPHORES:
 67		value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
 68		break;
 69	case I915_PARAM_HAS_SECURE_BATCHES:
 70		value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
 71		break;
 72	case I915_PARAM_CMD_PARSER_VERSION:
 73		value = i915_cmd_parser_get_version(i915);
 74		break;
 75	case I915_PARAM_SUBSLICE_TOTAL:
 76		value = intel_sseu_subslice_total(sseu);
 77		if (!value)
 78			return -ENODEV;
 79		break;
 80	case I915_PARAM_EU_TOTAL:
 81		value = sseu->eu_total;
 82		if (!value)
 83			return -ENODEV;
 84		break;
 85	case I915_PARAM_HAS_GPU_RESET:
 86		value = i915->params.enable_hangcheck &&
 87			intel_has_gpu_reset(to_gt(i915));
 88		if (value && intel_has_reset_engine(to_gt(i915)))
 89			value = 2;
 90		break;
 91	case I915_PARAM_HAS_RESOURCE_STREAMER:
 92		value = 0;
 93		break;
 94	case I915_PARAM_HAS_POOLED_EU:
 95		value = HAS_POOLED_EU(i915);
 96		break;
 97	case I915_PARAM_MIN_EU_IN_POOL:
 98		value = sseu->min_eu_in_pool;
 99		break;
100	case I915_PARAM_HUC_STATUS:
101		value = intel_huc_check_status(&to_gt(i915)->uc.huc);
102		if (value < 0)
103			return value;
104		break;
105	case I915_PARAM_MMAP_GTT_VERSION:
106		/* Though we've started our numbering from 1, and so class all
107		 * earlier versions as 0, in effect their value is undefined as
108		 * the ioctl will report EINVAL for the unknown param!
109		 */
110		value = i915_gem_mmap_gtt_version();
111		break;
112	case I915_PARAM_HAS_SCHEDULER:
113		value = i915->caps.scheduler;
114		break;
115
116	case I915_PARAM_MMAP_VERSION:
117		/* Remember to bump this if the version changes! */
118	case I915_PARAM_HAS_GEM:
119	case I915_PARAM_HAS_PAGEFLIPPING:
120	case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
121	case I915_PARAM_HAS_RELAXED_FENCING:
122	case I915_PARAM_HAS_COHERENT_RINGS:
123	case I915_PARAM_HAS_RELAXED_DELTA:
124	case I915_PARAM_HAS_GEN7_SOL_RESET:
125	case I915_PARAM_HAS_WAIT_TIMEOUT:
126	case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
127	case I915_PARAM_HAS_PINNED_BATCHES:
128	case I915_PARAM_HAS_EXEC_NO_RELOC:
129	case I915_PARAM_HAS_EXEC_HANDLE_LUT:
130	case I915_PARAM_HAS_COHERENT_PHYS_GTT:
131	case I915_PARAM_HAS_EXEC_SOFTPIN:
132	case I915_PARAM_HAS_EXEC_ASYNC:
133	case I915_PARAM_HAS_EXEC_FENCE:
134	case I915_PARAM_HAS_EXEC_CAPTURE:
135	case I915_PARAM_HAS_EXEC_BATCH_FIRST:
136	case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
137	case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
138	case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
139	case I915_PARAM_HAS_USERPTR_PROBE:
140		/* For the time being all of these are always true;
141		 * if some supported hardware does not have one of these
142		 * features this value needs to be provided from
143		 * INTEL_INFO(), a feature macro, or similar.
144		 */
145		value = 1;
146		break;
147	case I915_PARAM_HAS_CONTEXT_ISOLATION:
148		value = intel_engines_has_context_isolation(i915);
149		break;
150	case I915_PARAM_SLICE_MASK:
151		/* Not supported from Xe_HP onward; use topology queries */
152		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
153			return -EINVAL;
154
155		value = sseu->slice_mask;
156		if (!value)
157			return -ENODEV;
158		break;
159	case I915_PARAM_SUBSLICE_MASK:
160		/* Not supported from Xe_HP onward; use topology queries */
161		if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
162			return -EINVAL;
163
164		/* Only copy bits from the first slice */
165		value = intel_sseu_get_hsw_subslices(sseu, 0);
166		if (!value)
167			return -ENODEV;
168		break;
169	case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
170		value = to_gt(i915)->clock_frequency;
171		break;
172	case I915_PARAM_MMAP_GTT_COHERENT:
173		value = INTEL_INFO(i915)->has_coherent_ggtt;
174		break;
175	case I915_PARAM_PERF_REVISION:
176		value = i915_perf_ioctl_version();
177		break;
178	case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
179		value = i915_perf_oa_timestamp_frequency(i915);
180		break;
181	default:
182		drm_dbg(&i915->drm, "Unknown parameter %d\n", param->param);
183		return -EINVAL;
184	}
185
186	if (put_user(value, param->value))
187		return -EFAULT;
188
189	return 0;
190}