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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2021 Intel Corporation
4 */
5
6#include "g4x_dp.h"
7#include "i915_reg.h"
8#include "intel_crt.h"
9#include "intel_de.h"
10#include "intel_display_types.h"
11#include "intel_fdi.h"
12#include "intel_lvds.h"
13#include "intel_pch_display.h"
14#include "intel_pch_refclk.h"
15#include "intel_pps.h"
16#include "intel_sdvo.h"
17
18bool intel_has_pch_trancoder(struct drm_i915_private *i915,
19 enum pipe pch_transcoder)
20{
21 return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) ||
22 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A);
23}
24
25enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
26{
27 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
28
29 if (HAS_PCH_LPT(i915))
30 return PIPE_A;
31 else
32 return crtc->pipe;
33}
34
35static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
36 enum pipe pipe, enum port port,
37 i915_reg_t dp_reg)
38{
39 enum pipe port_pipe;
40 bool state;
41
42 state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
43
44 I915_STATE_WARN(state && port_pipe == pipe,
45 "PCH DP %c enabled on transcoder %c, should be disabled\n",
46 port_name(port), pipe_name(pipe));
47
48 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
49 "IBX PCH DP %c still using transcoder B\n",
50 port_name(port));
51}
52
53static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
54 enum pipe pipe, enum port port,
55 i915_reg_t hdmi_reg)
56{
57 enum pipe port_pipe;
58 bool state;
59
60 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
61
62 I915_STATE_WARN(state && port_pipe == pipe,
63 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
64 port_name(port), pipe_name(pipe));
65
66 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
67 "IBX PCH HDMI %c still using transcoder B\n",
68 port_name(port));
69}
70
71static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
72 enum pipe pipe)
73{
74 enum pipe port_pipe;
75
76 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
77 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
78 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
79
80 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
81 port_pipe == pipe,
82 "PCH VGA enabled on transcoder %c, should be disabled\n",
83 pipe_name(pipe));
84
85 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
86 port_pipe == pipe,
87 "PCH LVDS enabled on transcoder %c, should be disabled\n",
88 pipe_name(pipe));
89
90 /* PCH SDVOB multiplex with HDMIB */
91 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
92 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
93 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
94}
95
96static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
97 enum pipe pipe)
98{
99 u32 val;
100 bool enabled;
101
102 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
103 enabled = !!(val & TRANS_ENABLE);
104 I915_STATE_WARN(enabled,
105 "transcoder assertion failed, should be off on pipe %c but is still active\n",
106 pipe_name(pipe));
107}
108
109static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
110 enum port port, i915_reg_t hdmi_reg)
111{
112 u32 val = intel_de_read(dev_priv, hdmi_reg);
113
114 if (val & SDVO_ENABLE ||
115 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
116 return;
117
118 drm_dbg_kms(&dev_priv->drm,
119 "Sanitizing transcoder select for HDMI %c\n",
120 port_name(port));
121
122 val &= ~SDVO_PIPE_SEL_MASK;
123 val |= SDVO_PIPE_SEL(PIPE_A);
124
125 intel_de_write(dev_priv, hdmi_reg, val);
126}
127
128static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
129 enum port port, i915_reg_t dp_reg)
130{
131 u32 val = intel_de_read(dev_priv, dp_reg);
132
133 if (val & DP_PORT_EN ||
134 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
135 return;
136
137 drm_dbg_kms(&dev_priv->drm,
138 "Sanitizing transcoder select for DP %c\n",
139 port_name(port));
140
141 val &= ~DP_PIPE_SEL_MASK;
142 val |= DP_PIPE_SEL(PIPE_A);
143
144 intel_de_write(dev_priv, dp_reg, val);
145}
146
147static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
148{
149 /*
150 * The BIOS may select transcoder B on some of the PCH
151 * ports even it doesn't enable the port. This would trip
152 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
153 * Sanitize the transcoder select bits to prevent that. We
154 * assume that the BIOS never actually enabled the port,
155 * because if it did we'd actually have to toggle the port
156 * on and back off to make the transcoder A select stick
157 * (see. intel_dp_link_down(), intel_disable_hdmi(),
158 * intel_disable_sdvo()).
159 */
160 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
161 ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
162 ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
163
164 /* PCH SDVOB multiplex with HDMIB */
165 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
166 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
167 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
168}
169
170static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
171 const struct intel_link_m_n *m_n)
172{
173 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
174 enum pipe pipe = crtc->pipe;
175
176 intel_set_m_n(dev_priv, m_n,
177 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
178 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
179}
180
181static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
182 const struct intel_link_m_n *m_n)
183{
184 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
185 enum pipe pipe = crtc->pipe;
186
187 intel_set_m_n(dev_priv, m_n,
188 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
189 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
190}
191
192void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
193 struct intel_link_m_n *m_n)
194{
195 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
196 enum pipe pipe = crtc->pipe;
197
198 intel_get_m_n(dev_priv, m_n,
199 PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
200 PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
201}
202
203void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
204 struct intel_link_m_n *m_n)
205{
206 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
207 enum pipe pipe = crtc->pipe;
208
209 intel_get_m_n(dev_priv, m_n,
210 PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
211 PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
212}
213
214static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
215 enum pipe pch_transcoder)
216{
217 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
218 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
219 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
220
221 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
222 intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
223 intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
224 intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
225 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
226 intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
227
228 intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
229 intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
230 intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
231 intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
232 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
233 intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
234 intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
235 intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
236}
237
238static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
239{
240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
241 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
242 enum pipe pipe = crtc->pipe;
243 i915_reg_t reg;
244 u32 val, pipeconf_val;
245
246 /* Make sure PCH DPLL is enabled */
247 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
248
249 /* FDI must be feeding us bits for PCH ports */
250 assert_fdi_tx_enabled(dev_priv, pipe);
251 assert_fdi_rx_enabled(dev_priv, pipe);
252
253 if (HAS_PCH_CPT(dev_priv)) {
254 reg = TRANS_CHICKEN2(pipe);
255 val = intel_de_read(dev_priv, reg);
256 /*
257 * Workaround: Set the timing override bit
258 * before enabling the pch transcoder.
259 */
260 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
261 /* Configure frame start delay to match the CPU */
262 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
263 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
264 intel_de_write(dev_priv, reg, val);
265 }
266
267 reg = PCH_TRANSCONF(pipe);
268 val = intel_de_read(dev_priv, reg);
269 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
270
271 if (HAS_PCH_IBX(dev_priv)) {
272 /* Configure frame start delay to match the CPU */
273 val &= ~TRANS_FRAME_START_DELAY_MASK;
274 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
275
276 /*
277 * Make the BPC in transcoder be consistent with
278 * that in pipeconf reg. For HDMI we must use 8bpc
279 * here for both 8bpc and 12bpc.
280 */
281 val &= ~PIPECONF_BPC_MASK;
282 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
283 val |= PIPECONF_BPC_8;
284 else
285 val |= pipeconf_val & PIPECONF_BPC_MASK;
286 }
287
288 val &= ~TRANS_INTERLACE_MASK;
289 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
290 if (HAS_PCH_IBX(dev_priv) &&
291 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
292 val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
293 else
294 val |= TRANS_INTERLACE_INTERLACED;
295 } else {
296 val |= TRANS_INTERLACE_PROGRESSIVE;
297 }
298
299 intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
300 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
301 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
302 pipe_name(pipe));
303}
304
305static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
306{
307 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
308 enum pipe pipe = crtc->pipe;
309 i915_reg_t reg;
310 u32 val;
311
312 /* FDI relies on the transcoder */
313 assert_fdi_tx_disabled(dev_priv, pipe);
314 assert_fdi_rx_disabled(dev_priv, pipe);
315
316 /* Ports must be off as well */
317 assert_pch_ports_disabled(dev_priv, pipe);
318
319 reg = PCH_TRANSCONF(pipe);
320 val = intel_de_read(dev_priv, reg);
321 val &= ~TRANS_ENABLE;
322 intel_de_write(dev_priv, reg, val);
323 /* wait for PCH transcoder off, transcoder state */
324 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
325 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
326 pipe_name(pipe));
327
328 if (HAS_PCH_CPT(dev_priv)) {
329 /* Workaround: Clear the timing override chicken bit again. */
330 reg = TRANS_CHICKEN2(pipe);
331 val = intel_de_read(dev_priv, reg);
332 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
333 intel_de_write(dev_priv, reg, val);
334 }
335}
336
337void ilk_pch_pre_enable(struct intel_atomic_state *state,
338 struct intel_crtc *crtc)
339{
340 const struct intel_crtc_state *crtc_state =
341 intel_atomic_get_new_crtc_state(state, crtc);
342
343 /*
344 * Note: FDI PLL enabling _must_ be done before we enable the
345 * cpu pipes, hence this is separate from all the other fdi/pch
346 * enabling.
347 */
348 ilk_fdi_pll_enable(crtc_state);
349}
350
351/*
352 * Enable PCH resources required for PCH ports:
353 * - PCH PLLs
354 * - FDI training & RX/TX
355 * - update transcoder timings
356 * - DP transcoding bits
357 * - transcoder
358 */
359void ilk_pch_enable(struct intel_atomic_state *state,
360 struct intel_crtc *crtc)
361{
362 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
363 const struct intel_crtc_state *crtc_state =
364 intel_atomic_get_new_crtc_state(state, crtc);
365 enum pipe pipe = crtc->pipe;
366 u32 temp;
367
368 assert_pch_transcoder_disabled(dev_priv, pipe);
369
370 /* For PCH output, training FDI link */
371 intel_fdi_link_train(crtc, crtc_state);
372
373 /*
374 * We need to program the right clock selection
375 * before writing the pixel multiplier into the DPLL.
376 */
377 if (HAS_PCH_CPT(dev_priv)) {
378 u32 sel;
379
380 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
381 temp |= TRANS_DPLL_ENABLE(pipe);
382 sel = TRANS_DPLLB_SEL(pipe);
383 if (crtc_state->shared_dpll ==
384 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
385 temp |= sel;
386 else
387 temp &= ~sel;
388 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
389 }
390
391 /*
392 * XXX: pch pll's can be enabled any time before we enable the PCH
393 * transcoder, and we actually should do this to not upset any PCH
394 * transcoder that already use the clock when we share it.
395 *
396 * Note that enable_shared_dpll tries to do the right thing, but
397 * get_shared_dpll unconditionally resets the pll - we need that
398 * to have the right LVDS enable sequence.
399 */
400 intel_enable_shared_dpll(crtc_state);
401
402 /* set transcoder timing, panel must allow it */
403 assert_pps_unlocked(dev_priv, pipe);
404 if (intel_crtc_has_dp_encoder(crtc_state)) {
405 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
406 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
407 }
408 ilk_pch_transcoder_set_timings(crtc_state, pipe);
409
410 intel_fdi_normal_train(crtc);
411
412 /* For PCH DP, enable TRANS_DP_CTL */
413 if (HAS_PCH_CPT(dev_priv) &&
414 intel_crtc_has_dp_encoder(crtc_state)) {
415 const struct drm_display_mode *adjusted_mode =
416 &crtc_state->hw.adjusted_mode;
417 u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
418 i915_reg_t reg = TRANS_DP_CTL(pipe);
419 enum port port;
420
421 temp = intel_de_read(dev_priv, reg);
422 temp &= ~(TRANS_DP_PORT_SEL_MASK |
423 TRANS_DP_VSYNC_ACTIVE_HIGH |
424 TRANS_DP_HSYNC_ACTIVE_HIGH |
425 TRANS_DP_BPC_MASK);
426 temp |= TRANS_DP_OUTPUT_ENABLE;
427 temp |= bpc << 9; /* same format but at 11:9 */
428
429 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
430 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
431 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
432 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
433
434 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
435 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
436 temp |= TRANS_DP_PORT_SEL(port);
437
438 intel_de_write(dev_priv, reg, temp);
439 }
440
441 ilk_enable_pch_transcoder(crtc_state);
442}
443
444void ilk_pch_disable(struct intel_atomic_state *state,
445 struct intel_crtc *crtc)
446{
447 ilk_fdi_disable(crtc);
448}
449
450void ilk_pch_post_disable(struct intel_atomic_state *state,
451 struct intel_crtc *crtc)
452{
453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
454 enum pipe pipe = crtc->pipe;
455
456 ilk_disable_pch_transcoder(crtc);
457
458 if (HAS_PCH_CPT(dev_priv)) {
459 i915_reg_t reg;
460 u32 temp;
461
462 /* disable TRANS_DP_CTL */
463 reg = TRANS_DP_CTL(pipe);
464 temp = intel_de_read(dev_priv, reg);
465 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
466 TRANS_DP_PORT_SEL_MASK);
467 temp |= TRANS_DP_PORT_SEL_NONE;
468 intel_de_write(dev_priv, reg, temp);
469
470 /* disable DPLL_SEL */
471 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
472 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
473 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
474 }
475
476 ilk_fdi_pll_disable(crtc);
477}
478
479static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
480{
481 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
482 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
483
484 /* read out port_clock from the DPLL */
485 i9xx_crtc_clock_get(crtc, crtc_state);
486
487 /*
488 * In case there is an active pipe without active ports,
489 * we may need some idea for the dotclock anyway.
490 * Calculate one based on the FDI configuration.
491 */
492 crtc_state->hw.adjusted_mode.crtc_clock =
493 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
494 &crtc_state->fdi_m_n);
495}
496
497void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
498{
499 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
501 struct intel_shared_dpll *pll;
502 enum pipe pipe = crtc->pipe;
503 enum intel_dpll_id pll_id;
504 bool pll_active;
505 u32 tmp;
506
507 if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
508 return;
509
510 crtc_state->has_pch_encoder = true;
511
512 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
513 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
514 FDI_DP_PORT_WIDTH_SHIFT) + 1;
515
516 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
517 &crtc_state->fdi_m_n);
518
519 if (HAS_PCH_IBX(dev_priv)) {
520 /*
521 * The pipe->pch transcoder and pch transcoder->pll
522 * mapping is fixed.
523 */
524 pll_id = (enum intel_dpll_id) pipe;
525 } else {
526 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
527 if (tmp & TRANS_DPLLB_SEL(pipe))
528 pll_id = DPLL_ID_PCH_PLL_B;
529 else
530 pll_id = DPLL_ID_PCH_PLL_A;
531 }
532
533 crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
534 pll = crtc_state->shared_dpll;
535
536 pll_active = intel_dpll_get_hw_state(dev_priv, pll,
537 &crtc_state->dpll_hw_state);
538 drm_WARN_ON(&dev_priv->drm, !pll_active);
539
540 tmp = crtc_state->dpll_hw_state.dpll;
541 crtc_state->pixel_multiplier =
542 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
543 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
544
545 ilk_pch_clock_get(crtc_state);
546}
547
548static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
549{
550 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
553 u32 val, pipeconf_val;
554
555 /* FDI must be feeding us bits for PCH ports */
556 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
557 assert_fdi_rx_enabled(dev_priv, PIPE_A);
558
559 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
560 /* Workaround: set timing override bit. */
561 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
562 /* Configure frame start delay to match the CPU */
563 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
564 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
565 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
566
567 val = TRANS_ENABLE;
568 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
569
570 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
571 val |= TRANS_INTERLACE_INTERLACED;
572 else
573 val |= TRANS_INTERLACE_PROGRESSIVE;
574
575 intel_de_write(dev_priv, LPT_TRANSCONF, val);
576 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
577 TRANS_STATE_ENABLE, 100))
578 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
579}
580
581static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
582{
583 u32 val;
584
585 val = intel_de_read(dev_priv, LPT_TRANSCONF);
586 val &= ~TRANS_ENABLE;
587 intel_de_write(dev_priv, LPT_TRANSCONF, val);
588 /* wait for PCH transcoder off, transcoder state */
589 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
590 TRANS_STATE_ENABLE, 50))
591 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
592
593 /* Workaround: clear timing override bit. */
594 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
595 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
596 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
597}
598
599void lpt_pch_enable(struct intel_atomic_state *state,
600 struct intel_crtc *crtc)
601{
602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
603 const struct intel_crtc_state *crtc_state =
604 intel_atomic_get_new_crtc_state(state, crtc);
605
606 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
607
608 lpt_program_iclkip(crtc_state);
609
610 /* Set transcoder timing. */
611 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
612
613 lpt_enable_pch_transcoder(crtc_state);
614}
615
616void lpt_pch_disable(struct intel_atomic_state *state,
617 struct intel_crtc *crtc)
618{
619 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
620
621 lpt_disable_pch_transcoder(dev_priv);
622
623 lpt_disable_iclkip(dev_priv);
624}
625
626void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
627{
628 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
630 u32 tmp;
631
632 if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
633 return;
634
635 crtc_state->has_pch_encoder = true;
636
637 tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
638 crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
639 FDI_DP_PORT_WIDTH_SHIFT) + 1;
640
641 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
642 &crtc_state->fdi_m_n);
643
644 crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
645}
646
647void intel_pch_sanitize(struct drm_i915_private *i915)
648{
649 if (HAS_PCH_IBX(i915))
650 ibx_sanitize_pch_ports(i915);
651}