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1/*
2 * Copyright © 2012-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DPLL_MGR_H_
26#define _INTEL_DPLL_MGR_H_
27
28#include <linux/types.h>
29
30#include "intel_wakeref.h"
31
32/*FIXME: Move this to a more appropriate place. */
33#define abs_diff(a, b) ({ \
34 typeof(a) __a = (a); \
35 typeof(b) __b = (b); \
36 (void) (&__a == &__b); \
37 __a > __b ? (__a - __b) : (__b - __a); })
38
39enum tc_port;
40struct drm_i915_private;
41struct intel_atomic_state;
42struct intel_crtc;
43struct intel_crtc_state;
44struct intel_encoder;
45struct intel_shared_dpll;
46struct intel_shared_dpll_funcs;
47
48/**
49 * enum intel_dpll_id - possible DPLL ids
50 *
51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
52 */
53enum intel_dpll_id {
54 /**
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
56 */
57 DPLL_ID_PRIVATE = -1,
58
59 /**
60 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
61 */
62 DPLL_ID_PCH_PLL_A = 0,
63 /**
64 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
65 */
66 DPLL_ID_PCH_PLL_B = 1,
67
68
69 /**
70 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
71 */
72 DPLL_ID_WRPLL1 = 0,
73 /**
74 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
75 */
76 DPLL_ID_WRPLL2 = 1,
77 /**
78 * @DPLL_ID_SPLL: HSW and BDW SPLL
79 */
80 DPLL_ID_SPLL = 2,
81 /**
82 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
83 */
84 DPLL_ID_LCPLL_810 = 3,
85 /**
86 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
87 */
88 DPLL_ID_LCPLL_1350 = 4,
89 /**
90 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
91 */
92 DPLL_ID_LCPLL_2700 = 5,
93
94
95 /**
96 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
97 */
98 DPLL_ID_SKL_DPLL0 = 0,
99 /**
100 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
101 */
102 DPLL_ID_SKL_DPLL1 = 1,
103 /**
104 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
105 */
106 DPLL_ID_SKL_DPLL2 = 2,
107 /**
108 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
109 */
110 DPLL_ID_SKL_DPLL3 = 3,
111
112
113 /**
114 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
115 */
116 DPLL_ID_ICL_DPLL0 = 0,
117 /**
118 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
119 */
120 DPLL_ID_ICL_DPLL1 = 1,
121 /**
122 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
123 */
124 DPLL_ID_EHL_DPLL4 = 2,
125 /**
126 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
127 */
128 DPLL_ID_ICL_TBTPLL = 2,
129 /**
130 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
131 * TGL TC PLL 1 port 1 (TC1)
132 */
133 DPLL_ID_ICL_MGPLL1 = 3,
134 /**
135 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
136 * TGL TC PLL 1 port 2 (TC2)
137 */
138 DPLL_ID_ICL_MGPLL2 = 4,
139 /**
140 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
141 * TGL TC PLL 1 port 3 (TC3)
142 */
143 DPLL_ID_ICL_MGPLL3 = 5,
144 /**
145 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
146 * TGL TC PLL 1 port 4 (TC4)
147 */
148 DPLL_ID_ICL_MGPLL4 = 6,
149 /**
150 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
151 */
152 DPLL_ID_TGL_MGPLL5 = 7,
153 /**
154 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
155 */
156 DPLL_ID_TGL_MGPLL6 = 8,
157
158 /**
159 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
160 */
161 DPLL_ID_DG1_DPLL0 = 0,
162 /**
163 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
164 */
165 DPLL_ID_DG1_DPLL1 = 1,
166 /**
167 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
168 */
169 DPLL_ID_DG1_DPLL2 = 2,
170 /**
171 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
172 */
173 DPLL_ID_DG1_DPLL3 = 3,
174};
175
176#define I915_NUM_PLLS 9
177
178enum icl_port_dpll_id {
179 ICL_PORT_DPLL_DEFAULT,
180 ICL_PORT_DPLL_MG_PHY,
181
182 ICL_PORT_DPLL_COUNT,
183};
184
185struct intel_dpll_hw_state {
186 /* i9xx, pch plls */
187 u32 dpll;
188 u32 dpll_md;
189 u32 fp0;
190 u32 fp1;
191
192 /* hsw, bdw */
193 u32 wrpll;
194 u32 spll;
195
196 /* skl */
197 /*
198 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
199 * lower part of ctrl1 and they get shifted into position when writing
200 * the register. This allows us to easily compare the state to share
201 * the DPLL.
202 */
203 u32 ctrl1;
204 /* HDMI only, 0 when used for DP */
205 u32 cfgcr1, cfgcr2;
206
207 /* icl */
208 u32 cfgcr0;
209
210 /* tgl */
211 u32 div0;
212
213 /* bxt */
214 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
215
216 /*
217 * ICL uses the following, already defined:
218 * u32 cfgcr0, cfgcr1;
219 */
220 u32 mg_refclkin_ctl;
221 u32 mg_clktop2_coreclkctl1;
222 u32 mg_clktop2_hsclkctl;
223 u32 mg_pll_div0;
224 u32 mg_pll_div1;
225 u32 mg_pll_lf;
226 u32 mg_pll_frac_lock;
227 u32 mg_pll_ssc;
228 u32 mg_pll_bias;
229 u32 mg_pll_tdc_coldst_bias;
230 u32 mg_pll_bias_mask;
231 u32 mg_pll_tdc_coldst_bias_mask;
232};
233
234/**
235 * struct intel_shared_dpll_state - hold the DPLL atomic state
236 *
237 * This structure holds an atomic state for the DPLL, that can represent
238 * either its current state (in struct &intel_shared_dpll) or a desired
239 * future state which would be applied by an atomic mode set (stored in
240 * a struct &intel_atomic_state).
241 *
242 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
243 */
244struct intel_shared_dpll_state {
245 /**
246 * @pipe_mask: mask of pipes using this DPLL, active or not
247 */
248 u8 pipe_mask;
249
250 /**
251 * @hw_state: hardware configuration for the DPLL stored in
252 * struct &intel_dpll_hw_state.
253 */
254 struct intel_dpll_hw_state hw_state;
255};
256
257/**
258 * struct dpll_info - display PLL platform specific info
259 */
260struct dpll_info {
261 /**
262 * @name: DPLL name; used for logging
263 */
264 const char *name;
265
266 /**
267 * @funcs: platform specific hooks
268 */
269 const struct intel_shared_dpll_funcs *funcs;
270
271 /**
272 * @id: unique indentifier for this DPLL; should match the index in the
273 * dev_priv->shared_dplls array
274 */
275 enum intel_dpll_id id;
276
277#define INTEL_DPLL_ALWAYS_ON (1 << 0)
278 /**
279 * @flags:
280 *
281 * INTEL_DPLL_ALWAYS_ON
282 * Inform the state checker that the DPLL is kept enabled even if
283 * not in use by any CRTC.
284 */
285 u32 flags;
286};
287
288/**
289 * struct intel_shared_dpll - display PLL with tracked state and users
290 */
291struct intel_shared_dpll {
292 /**
293 * @state:
294 *
295 * Store the state for the pll, including its hw state
296 * and CRTCs using it.
297 */
298 struct intel_shared_dpll_state state;
299
300 /**
301 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
302 */
303 u8 active_mask;
304
305 /**
306 * @on: is the PLL actually active? Disabled during modeset
307 */
308 bool on;
309
310 /**
311 * @info: platform specific info
312 */
313 const struct dpll_info *info;
314
315 /**
316 * @wakeref: In some platforms a device-level runtime pm reference may
317 * need to be grabbed to disable DC states while this DPLL is enabled
318 */
319 intel_wakeref_t wakeref;
320};
321
322#define SKL_DPLL0 0
323#define SKL_DPLL1 1
324#define SKL_DPLL2 2
325#define SKL_DPLL3 3
326
327/* shared dpll functions */
328struct intel_shared_dpll *
329intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
330 enum intel_dpll_id id);
331void assert_shared_dpll(struct drm_i915_private *dev_priv,
332 struct intel_shared_dpll *pll,
333 bool state);
334#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
335#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
336int intel_compute_shared_dplls(struct intel_atomic_state *state,
337 struct intel_crtc *crtc,
338 struct intel_encoder *encoder);
339int intel_reserve_shared_dplls(struct intel_atomic_state *state,
340 struct intel_crtc *crtc,
341 struct intel_encoder *encoder);
342void intel_release_shared_dplls(struct intel_atomic_state *state,
343 struct intel_crtc *crtc);
344void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
345 enum icl_port_dpll_id port_dpll_id);
346void intel_update_active_dpll(struct intel_atomic_state *state,
347 struct intel_crtc *crtc,
348 struct intel_encoder *encoder);
349int intel_dpll_get_freq(struct drm_i915_private *i915,
350 const struct intel_shared_dpll *pll,
351 const struct intel_dpll_hw_state *pll_state);
352bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
353 struct intel_shared_dpll *pll,
354 struct intel_dpll_hw_state *hw_state);
355void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
356void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
357void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
358void intel_shared_dpll_init(struct drm_i915_private *dev_priv);
359void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
360void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
361void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
362
363void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
364 const struct intel_dpll_hw_state *hw_state);
365enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
366bool intel_dpll_is_combophy(enum intel_dpll_id id);
367
368void intel_shared_dpll_state_verify(struct intel_crtc *crtc,
369 struct intel_crtc_state *old_crtc_state,
370 struct intel_crtc_state *new_crtc_state);
371void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915);
372
373#endif /* _INTEL_DPLL_MGR_H_ */