1/*
   2 * Copyright © 2008 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 * Authors:
  24 *    Keith Packard <keithp@keithp.com>
  25 *
  26 */
  27
  28#include <linux/export.h>
  29#include <linux/i2c.h>
  30#include <linux/notifier.h>
  31#include <linux/slab.h>
  32#include <linux/string_helpers.h>
  33#include <linux/timekeeping.h>
  34#include <linux/types.h>
  35
  36#include <asm/byteorder.h>
  37
  38#include <drm/display/drm_dp_helper.h>
  39#include <drm/display/drm_dsc_helper.h>
  40#include <drm/display/drm_hdmi_helper.h>
  41#include <drm/drm_atomic_helper.h>
  42#include <drm/drm_crtc.h>
  43#include <drm/drm_edid.h>
  44#include <drm/drm_probe_helper.h>
  45
  46#include "g4x_dp.h"
  47#include "i915_debugfs.h"
  48#include "i915_drv.h"
  49#include "i915_reg.h"
  50#include "intel_atomic.h"
  51#include "intel_audio.h"
  52#include "intel_backlight.h"
  53#include "intel_combo_phy_regs.h"
  54#include "intel_connector.h"
  55#include "intel_crtc.h"
  56#include "intel_ddi.h"
  57#include "intel_de.h"
  58#include "intel_display_types.h"
  59#include "intel_dp.h"
  60#include "intel_dp_aux.h"
  61#include "intel_dp_hdcp.h"
  62#include "intel_dp_link_training.h"
  63#include "intel_dp_mst.h"
  64#include "intel_dpio_phy.h"
  65#include "intel_dpll.h"
  66#include "intel_fifo_underrun.h"
  67#include "intel_hdcp.h"
  68#include "intel_hdmi.h"
  69#include "intel_hotplug.h"
  70#include "intel_lspcon.h"
  71#include "intel_lvds.h"
  72#include "intel_panel.h"
  73#include "intel_pch_display.h"
  74#include "intel_pps.h"
  75#include "intel_psr.h"
  76#include "intel_tc.h"
  77#include "intel_vdsc.h"
  78#include "intel_vrr.h"
  79
  80/* DP DSC throughput values used for slice count calculations KPixels/s */
  81#define DP_DSC_PEAK_PIXEL_RATE			2720000
  82#define DP_DSC_MAX_ENC_THROUGHPUT_0		340000
  83#define DP_DSC_MAX_ENC_THROUGHPUT_1		400000
  84
  85/* DP DSC FEC Overhead factor = 1/(0.972261) */
  86#define DP_DSC_FEC_OVERHEAD_FACTOR		972261
  87
  88/* Compliance test status bits  */
  89#define INTEL_DP_RESOLUTION_SHIFT_MASK	0
  90#define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  91#define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  92#define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  93
  94
  95/* Constants for DP DSC configurations */
  96static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
  97
  98/* With Single pipe configuration, HW is capable of supporting maximum
  99 * of 4 slices per line.
 100 */
 101static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 102
 103/**
 104 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 105 * @intel_dp: DP struct
 106 *
 107 * If a CPU or PCH DP output is attached to an eDP panel, this function
 108 * will return true, and false otherwise.
 109 *
 110 * This function is not safe to use prior to encoder type being set.
 111 */
 112bool intel_dp_is_edp(struct intel_dp *intel_dp)
 113{
 114	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 115
 116	return dig_port->base.type == INTEL_OUTPUT_EDP;
 117}
 118
 119static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 120static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 121
 122/* Is link rate UHBR and thus 128b/132b? */
 123bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 124{
 125	return crtc_state->port_clock >= 1000000;
 126}
 127
 128static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 129{
 130	intel_dp->sink_rates[0] = 162000;
 131	intel_dp->num_sink_rates = 1;
 132}
 133
 134/* update sink rates from dpcd */
 135static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 136{
 137	static const int dp_rates[] = {
 138		162000, 270000, 540000, 810000
 139	};
 140	int i, max_rate;
 141	int max_lttpr_rate;
 142
 143	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 144		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 145		static const int quirk_rates[] = { 162000, 270000, 324000 };
 146
 147		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 148		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 149
 150		return;
 151	}
 152
 153	/*
 154	 * Sink rates for 8b/10b.
 155	 */
 156	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 157	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 158	if (max_lttpr_rate)
 159		max_rate = min(max_rate, max_lttpr_rate);
 160
 161	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 162		if (dp_rates[i] > max_rate)
 163			break;
 164		intel_dp->sink_rates[i] = dp_rates[i];
 165	}
 166
 167	/*
 168	 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 169	 * rates and 10 Gbps.
 170	 */
 171	if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 172		u8 uhbr_rates = 0;
 173
 174		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 175
 176		drm_dp_dpcd_readb(&intel_dp->aux,
 177				  DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 178
 179		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 180			/* We have a repeater */
 181			if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 182			    intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 183							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 184			    DP_PHY_REPEATER_128B132B_SUPPORTED) {
 185				/* Repeater supports 128b/132b, valid UHBR rates */
 186				uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 187									  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 188			} else {
 189				/* Does not support 128b/132b */
 190				uhbr_rates = 0;
 191			}
 192		}
 193
 194		if (uhbr_rates & DP_UHBR10)
 195			intel_dp->sink_rates[i++] = 1000000;
 196		if (uhbr_rates & DP_UHBR13_5)
 197			intel_dp->sink_rates[i++] = 1350000;
 198		if (uhbr_rates & DP_UHBR20)
 199			intel_dp->sink_rates[i++] = 2000000;
 200	}
 201
 202	intel_dp->num_sink_rates = i;
 203}
 204
 205static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 206{
 207	struct intel_connector *connector = intel_dp->attached_connector;
 208	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 209	struct intel_encoder *encoder = &intel_dig_port->base;
 210
 211	intel_dp_set_dpcd_sink_rates(intel_dp);
 212
 213	if (intel_dp->num_sink_rates)
 214		return;
 215
 216	drm_err(&dp_to_i915(intel_dp)->drm,
 217		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 218		connector->base.base.id, connector->base.name,
 219		encoder->base.base.id, encoder->base.name);
 220
 221	intel_dp_set_default_sink_rates(intel_dp);
 222}
 223
 224static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 225{
 226	intel_dp->max_sink_lane_count = 1;
 227}
 228
 229static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 230{
 231	struct intel_connector *connector = intel_dp->attached_connector;
 232	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 233	struct intel_encoder *encoder = &intel_dig_port->base;
 234
 235	intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 236
 237	switch (intel_dp->max_sink_lane_count) {
 238	case 1:
 239	case 2:
 240	case 4:
 241		return;
 242	}
 243
 244	drm_err(&dp_to_i915(intel_dp)->drm,
 245		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 246		connector->base.base.id, connector->base.name,
 247		encoder->base.base.id, encoder->base.name,
 248		intel_dp->max_sink_lane_count);
 249
 250	intel_dp_set_default_max_sink_lane_count(intel_dp);
 251}
 252
 253/* Get length of rates array potentially limited by max_rate. */
 254static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 255{
 256	int i;
 257
 258	/* Limit results by potentially reduced max rate */
 259	for (i = 0; i < len; i++) {
 260		if (rates[len - i - 1] <= max_rate)
 261			return len - i;
 262	}
 263
 264	return 0;
 265}
 266
 267/* Get length of common rates array potentially limited by max_rate. */
 268static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 269					  int max_rate)
 270{
 271	return intel_dp_rate_limit_len(intel_dp->common_rates,
 272				       intel_dp->num_common_rates, max_rate);
 273}
 274
 275static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 276{
 277	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 278			index < 0 || index >= intel_dp->num_common_rates))
 279		return 162000;
 280
 281	return intel_dp->common_rates[index];
 282}
 283
 284/* Theoretical max between source and sink */
 285static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 286{
 287	return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 288}
 289
 290static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 291{
 292	int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base);
 293	int max_lanes = dig_port->max_lanes;
 294
 295	if (vbt_max_lanes)
 296		max_lanes = min(max_lanes, vbt_max_lanes);
 297
 298	return max_lanes;
 299}
 300
 301/* Theoretical max between source and sink */
 302static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 303{
 304	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 305	int source_max = intel_dp_max_source_lane_count(dig_port);
 306	int sink_max = intel_dp->max_sink_lane_count;
 307	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 308	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 309
 310	if (lttpr_max)
 311		sink_max = min(sink_max, lttpr_max);
 312
 313	return min3(source_max, sink_max, fia_max);
 314}
 315
 316int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 317{
 318	switch (intel_dp->max_link_lane_count) {
 319	case 1:
 320	case 2:
 321	case 4:
 322		return intel_dp->max_link_lane_count;
 323	default:
 324		MISSING_CASE(intel_dp->max_link_lane_count);
 325		return 1;
 326	}
 327}
 328
 329/*
 330 * The required data bandwidth for a mode with given pixel clock and bpp. This
 331 * is the required net bandwidth independent of the data bandwidth efficiency.
 332 */
 333int
 334intel_dp_link_required(int pixel_clock, int bpp)
 335{
 336	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 337	return DIV_ROUND_UP(pixel_clock * bpp, 8);
 338}
 339
 340/*
 341 * Given a link rate and lanes, get the data bandwidth.
 342 *
 343 * Data bandwidth is the actual payload rate, which depends on the data
 344 * bandwidth efficiency and the link rate.
 345 *
 346 * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 347 * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 348 * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 349 * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 350 * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 351 * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 352 *
 353 * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 354 * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 355 * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 356 * does not match the symbol clock, the port clock (not even if you think in
 357 * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 358 * rate in units of 10000 bps.
 359 */
 360int
 361intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 362{
 363	if (max_link_rate >= 1000000) {
 364		/*
 365		 * UHBR rates always use 128b/132b channel encoding, and have
 366		 * 97.71% data bandwidth efficiency. Consider max_link_rate the
 367		 * link bit rate in units of 10000 bps.
 368		 */
 369		int max_link_rate_kbps = max_link_rate * 10;
 370
 371		max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 372		max_link_rate = max_link_rate_kbps / 8;
 373	}
 374
 375	/*
 376	 * Lower than UHBR rates always use 8b/10b channel encoding, and have
 377	 * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 378	 * out to be a nop by coincidence, and can be skipped:
 379	 *
 380	 *	int max_link_rate_kbps = max_link_rate * 10;
 381	 *	max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 382	 *	max_link_rate = max_link_rate_kbps / 8;
 383	 */
 384
 385	return max_link_rate * max_lanes;
 386}
 387
 388bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 389{
 390	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 391	struct intel_encoder *encoder = &intel_dig_port->base;
 392	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 393
 394	return DISPLAY_VER(dev_priv) >= 12 ||
 395		(DISPLAY_VER(dev_priv) == 11 &&
 396		 encoder->port != PORT_A);
 397}
 398
 399static int dg2_max_source_rate(struct intel_dp *intel_dp)
 400{
 401	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 402}
 403
 404static int icl_max_source_rate(struct intel_dp *intel_dp)
 405{
 406	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 407	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 408	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 409
 410	if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 411		return 540000;
 412
 413	return 810000;
 414}
 415
 416static int ehl_max_source_rate(struct intel_dp *intel_dp)
 417{
 418	if (intel_dp_is_edp(intel_dp))
 419		return 540000;
 420
 421	return 810000;
 422}
 423
 424static int vbt_max_link_rate(struct intel_dp *intel_dp)
 425{
 426	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 427	int max_rate;
 428
 429	max_rate = intel_bios_dp_max_link_rate(encoder);
 430
 431	if (intel_dp_is_edp(intel_dp)) {
 432		struct intel_connector *connector = intel_dp->attached_connector;
 433		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 434
 435		if (max_rate && edp_max_rate)
 436			max_rate = min(max_rate, edp_max_rate);
 437		else if (edp_max_rate)
 438			max_rate = edp_max_rate;
 439	}
 440
 441	return max_rate;
 442}
 443
 444static void
 445intel_dp_set_source_rates(struct intel_dp *intel_dp)
 446{
 447	/* The values must be in increasing order */
 448	static const int icl_rates[] = {
 449		162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 450		1000000, 1350000,
 451	};
 452	static const int bxt_rates[] = {
 453		162000, 216000, 243000, 270000, 324000, 432000, 540000
 454	};
 455	static const int skl_rates[] = {
 456		162000, 216000, 270000, 324000, 432000, 540000
 457	};
 458	static const int hsw_rates[] = {
 459		162000, 270000, 540000
 460	};
 461	static const int g4x_rates[] = {
 462		162000, 270000
 463	};
 464	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 465	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 466	const int *source_rates;
 467	int size, max_rate = 0, vbt_max_rate;
 468
 469	/* This should only be done once */
 470	drm_WARN_ON(&dev_priv->drm,
 471		    intel_dp->source_rates || intel_dp->num_source_rates);
 472
 473	if (DISPLAY_VER(dev_priv) >= 11) {
 474		source_rates = icl_rates;
 475		size = ARRAY_SIZE(icl_rates);
 476		if (IS_DG2(dev_priv))
 477			max_rate = dg2_max_source_rate(intel_dp);
 478		else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 479			 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 480			max_rate = 810000;
 481		else if (IS_JSL_EHL(dev_priv))
 482			max_rate = ehl_max_source_rate(intel_dp);
 483		else
 484			max_rate = icl_max_source_rate(intel_dp);
 485	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 486		source_rates = bxt_rates;
 487		size = ARRAY_SIZE(bxt_rates);
 488	} else if (DISPLAY_VER(dev_priv) == 9) {
 489		source_rates = skl_rates;
 490		size = ARRAY_SIZE(skl_rates);
 491	} else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 492		   IS_BROADWELL(dev_priv)) {
 493		source_rates = hsw_rates;
 494		size = ARRAY_SIZE(hsw_rates);
 495	} else {
 496		source_rates = g4x_rates;
 497		size = ARRAY_SIZE(g4x_rates);
 498	}
 499
 500	vbt_max_rate = vbt_max_link_rate(intel_dp);
 501	if (max_rate && vbt_max_rate)
 502		max_rate = min(max_rate, vbt_max_rate);
 503	else if (vbt_max_rate)
 504		max_rate = vbt_max_rate;
 505
 506	if (max_rate)
 507		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 508
 509	intel_dp->source_rates = source_rates;
 510	intel_dp->num_source_rates = size;
 511}
 512
 513static int intersect_rates(const int *source_rates, int source_len,
 514			   const int *sink_rates, int sink_len,
 515			   int *common_rates)
 516{
 517	int i = 0, j = 0, k = 0;
 518
 519	while (i < source_len && j < sink_len) {
 520		if (source_rates[i] == sink_rates[j]) {
 521			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 522				return k;
 523			common_rates[k] = source_rates[i];
 524			++k;
 525			++i;
 526			++j;
 527		} else if (source_rates[i] < sink_rates[j]) {
 528			++i;
 529		} else {
 530			++j;
 531		}
 532	}
 533	return k;
 534}
 535
 536/* return index of rate in rates array, or -1 if not found */
 537static int intel_dp_rate_index(const int *rates, int len, int rate)
 538{
 539	int i;
 540
 541	for (i = 0; i < len; i++)
 542		if (rate == rates[i])
 543			return i;
 544
 545	return -1;
 546}
 547
 548static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 549{
 550	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 551
 552	drm_WARN_ON(&i915->drm,
 553		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 554
 555	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 556						     intel_dp->num_source_rates,
 557						     intel_dp->sink_rates,
 558						     intel_dp->num_sink_rates,
 559						     intel_dp->common_rates);
 560
 561	/* Paranoia, there should always be something in common. */
 562	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 563		intel_dp->common_rates[0] = 162000;
 564		intel_dp->num_common_rates = 1;
 565	}
 566}
 567
 568static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 569				       u8 lane_count)
 570{
 571	/*
 572	 * FIXME: we need to synchronize the current link parameters with
 573	 * hardware readout. Currently fast link training doesn't work on
 574	 * boot-up.
 575	 */
 576	if (link_rate == 0 ||
 577	    link_rate > intel_dp->max_link_rate)
 578		return false;
 579
 580	if (lane_count == 0 ||
 581	    lane_count > intel_dp_max_lane_count(intel_dp))
 582		return false;
 583
 584	return true;
 585}
 586
 587static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 588						     int link_rate,
 589						     u8 lane_count)
 590{
 591	/* FIXME figure out what we actually want here */
 592	const struct drm_display_mode *fixed_mode =
 593		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 594	int mode_rate, max_rate;
 595
 596	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 597	max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 598	if (mode_rate > max_rate)
 599		return false;
 600
 601	return true;
 602}
 603
 604int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 605					    int link_rate, u8 lane_count)
 606{
 607	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 608	int index;
 609
 610	/*
 611	 * TODO: Enable fallback on MST links once MST link compute can handle
 612	 * the fallback params.
 613	 */
 614	if (intel_dp->is_mst) {
 615		drm_err(&i915->drm, "Link Training Unsuccessful\n");
 616		return -1;
 617	}
 618
 619	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 620		drm_dbg_kms(&i915->drm,
 621			    "Retrying Link training for eDP with max parameters\n");
 622		intel_dp->use_max_params = true;
 623		return 0;
 624	}
 625
 626	index = intel_dp_rate_index(intel_dp->common_rates,
 627				    intel_dp->num_common_rates,
 628				    link_rate);
 629	if (index > 0) {
 630		if (intel_dp_is_edp(intel_dp) &&
 631		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 632							      intel_dp_common_rate(intel_dp, index - 1),
 633							      lane_count)) {
 634			drm_dbg_kms(&i915->drm,
 635				    "Retrying Link training for eDP with same parameters\n");
 636			return 0;
 637		}
 638		intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 639		intel_dp->max_link_lane_count = lane_count;
 640	} else if (lane_count > 1) {
 641		if (intel_dp_is_edp(intel_dp) &&
 642		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 643							      intel_dp_max_common_rate(intel_dp),
 644							      lane_count >> 1)) {
 645			drm_dbg_kms(&i915->drm,
 646				    "Retrying Link training for eDP with same parameters\n");
 647			return 0;
 648		}
 649		intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 650		intel_dp->max_link_lane_count = lane_count >> 1;
 651	} else {
 652		drm_err(&i915->drm, "Link Training Unsuccessful\n");
 653		return -1;
 654	}
 655
 656	return 0;
 657}
 658
 659u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 660{
 661	return div_u64(mul_u32_u32(mode_clock, 1000000U),
 662		       DP_DSC_FEC_OVERHEAD_FACTOR);
 663}
 664
 665static int
 666small_joiner_ram_size_bits(struct drm_i915_private *i915)
 667{
 668	if (DISPLAY_VER(i915) >= 13)
 669		return 17280 * 8;
 670	else if (DISPLAY_VER(i915) >= 11)
 671		return 7680 * 8;
 672	else
 673		return 6144 * 8;
 674}
 675
 676static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 677				       u32 link_clock, u32 lane_count,
 678				       u32 mode_clock, u32 mode_hdisplay,
 679				       bool bigjoiner,
 680				       u32 pipe_bpp)
 681{
 682	u32 bits_per_pixel, max_bpp_small_joiner_ram;
 683	int i;
 684
 685	/*
 686	 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 687	 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 688	 * for SST -> TimeSlotsPerMTP is 1,
 689	 * for MST -> TimeSlotsPerMTP has to be calculated
 690	 */
 691	bits_per_pixel = (link_clock * lane_count * 8) /
 692			 intel_dp_mode_to_fec_clock(mode_clock);
 693
 694	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 695	max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 696		mode_hdisplay;
 697
 698	if (bigjoiner)
 699		max_bpp_small_joiner_ram *= 2;
 700
 701	/*
 702	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 703	 * check, output bpp from small joiner RAM check)
 704	 */
 705	bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 706
 707	if (bigjoiner) {
 708		u32 max_bpp_bigjoiner =
 709			i915->display.cdclk.max_cdclk_freq * 48 /
 710			intel_dp_mode_to_fec_clock(mode_clock);
 711
 712		bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 713	}
 714
 715	/* Error out if the max bpp is less than smallest allowed valid bpp */
 716	if (bits_per_pixel < valid_dsc_bpp[0]) {
 717		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 718			    bits_per_pixel, valid_dsc_bpp[0]);
 719		return 0;
 720	}
 721
 722	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 723	if (DISPLAY_VER(i915) >= 13) {
 724		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 725	} else {
 726		/* Find the nearest match in the array of known BPPs from VESA */
 727		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 728			if (bits_per_pixel < valid_dsc_bpp[i + 1])
 729				break;
 730		}
 731		bits_per_pixel = valid_dsc_bpp[i];
 732	}
 733
 734	/*
 735	 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 736	 * fractional part is 0
 737	 */
 738	return bits_per_pixel << 4;
 739}
 740
 741static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 742				       int mode_clock, int mode_hdisplay,
 743				       bool bigjoiner)
 744{
 745	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 746	u8 min_slice_count, i;
 747	int max_slice_width;
 748
 749	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 750		min_slice_count = DIV_ROUND_UP(mode_clock,
 751					       DP_DSC_MAX_ENC_THROUGHPUT_0);
 752	else
 753		min_slice_count = DIV_ROUND_UP(mode_clock,
 754					       DP_DSC_MAX_ENC_THROUGHPUT_1);
 755
 756	max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 757	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 758		drm_dbg_kms(&i915->drm,
 759			    "Unsupported slice width %d by DP DSC Sink device\n",
 760			    max_slice_width);
 761		return 0;
 762	}
 763	/* Also take into account max slice width */
 764	min_slice_count = max_t(u8, min_slice_count,
 765				DIV_ROUND_UP(mode_hdisplay,
 766					     max_slice_width));
 767
 768	/* Find the closest match to the valid slice count values */
 769	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 770		u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 771
 772		if (test_slice_count >
 773		    drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 774			break;
 775
 776		/* big joiner needs small joiner to be enabled */
 777		if (bigjoiner && test_slice_count < 4)
 778			continue;
 779
 780		if (min_slice_count <= test_slice_count)
 781			return test_slice_count;
 782	}
 783
 784	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 785		    min_slice_count);
 786	return 0;
 787}
 788
 789static enum intel_output_format
 790intel_dp_output_format(struct intel_connector *connector,
 791		       bool ycbcr_420_output)
 792{
 793	struct intel_dp *intel_dp = intel_attached_dp(connector);
 794
 795	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 796		return INTEL_OUTPUT_FORMAT_RGB;
 797
 798	if (intel_dp->dfp.rgb_to_ycbcr &&
 799	    intel_dp->dfp.ycbcr_444_to_420)
 800		return INTEL_OUTPUT_FORMAT_RGB;
 801
 802	if (intel_dp->dfp.ycbcr_444_to_420)
 803		return INTEL_OUTPUT_FORMAT_YCBCR444;
 804	else
 805		return INTEL_OUTPUT_FORMAT_YCBCR420;
 806}
 807
 808int intel_dp_min_bpp(enum intel_output_format output_format)
 809{
 810	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 811		return 6 * 3;
 812	else
 813		return 8 * 3;
 814}
 815
 816static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 817{
 818	/*
 819	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 820	 * format of the number of bytes per pixel will be half the number
 821	 * of bytes of RGB pixel.
 822	 */
 823	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 824		bpp /= 2;
 825
 826	return bpp;
 827}
 828
 829static int
 830intel_dp_mode_min_output_bpp(struct intel_connector *connector,
 831			     const struct drm_display_mode *mode)
 832{
 833	const struct drm_display_info *info = &connector->base.display_info;
 834	enum intel_output_format output_format =
 835		intel_dp_output_format(connector, drm_mode_is_420_only(info, mode));
 836
 837	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 838}
 839
 840static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 841				  int hdisplay)
 842{
 843	/*
 844	 * Older platforms don't like hdisplay==4096 with DP.
 845	 *
 846	 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 847	 * and frame counter increment), but we don't get vblank interrupts,
 848	 * and the pipe underruns immediately. The link also doesn't seem
 849	 * to get trained properly.
 850	 *
 851	 * On CHV the vblank interrupts don't seem to disappear but
 852	 * otherwise the symptoms are similar.
 853	 *
 854	 * TODO: confirm the behaviour on HSW+
 855	 */
 856	return hdisplay == 4096 && !HAS_DDI(dev_priv);
 857}
 858
 859static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
 860{
 861	struct intel_connector *connector = intel_dp->attached_connector;
 862	const struct drm_display_info *info = &connector->base.display_info;
 863	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
 864
 865	/* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
 866	if (max_tmds_clock && info->max_tmds_clock)
 867		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
 868
 869	return max_tmds_clock;
 870}
 871
 872static enum drm_mode_status
 873intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
 874			  int clock, int bpc, bool ycbcr420_output,
 875			  bool respect_downstream_limits)
 876{
 877	int tmds_clock, min_tmds_clock, max_tmds_clock;
 878
 879	if (!respect_downstream_limits)
 880		return MODE_OK;
 881
 882	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
 883
 884	min_tmds_clock = intel_dp->dfp.min_tmds_clock;
 885	max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
 886
 887	if (min_tmds_clock && tmds_clock < min_tmds_clock)
 888		return MODE_CLOCK_LOW;
 889
 890	if (max_tmds_clock && tmds_clock > max_tmds_clock)
 891		return MODE_CLOCK_HIGH;
 892
 893	return MODE_OK;
 894}
 895
 896static enum drm_mode_status
 897intel_dp_mode_valid_downstream(struct intel_connector *connector,
 898			       const struct drm_display_mode *mode,
 899			       int target_clock)
 900{
 901	struct intel_dp *intel_dp = intel_attached_dp(connector);
 902	const struct drm_display_info *info = &connector->base.display_info;
 903	enum drm_mode_status status;
 904	bool ycbcr_420_only;
 905
 906	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
 907	if (intel_dp->dfp.pcon_max_frl_bw) {
 908		int target_bw;
 909		int max_frl_bw;
 910		int bpp = intel_dp_mode_min_output_bpp(connector, mode);
 911
 912		target_bw = bpp * target_clock;
 913
 914		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
 915
 916		/* converting bw from Gbps to Kbps*/
 917		max_frl_bw = max_frl_bw * 1000000;
 918
 919		if (target_bw > max_frl_bw)
 920			return MODE_CLOCK_HIGH;
 921
 922		return MODE_OK;
 923	}
 924
 925	if (intel_dp->dfp.max_dotclock &&
 926	    target_clock > intel_dp->dfp.max_dotclock)
 927		return MODE_CLOCK_HIGH;
 928
 929	ycbcr_420_only = drm_mode_is_420_only(info, mode);
 930
 931	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 932	status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 933					   8, ycbcr_420_only, true);
 934
 935	if (status != MODE_OK) {
 936		if (ycbcr_420_only ||
 937		    !connector->base.ycbcr_420_allowed ||
 938		    !drm_mode_is_420_also(info, mode))
 939			return status;
 940
 941		status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
 942						   8, true, true);
 943		if (status != MODE_OK)
 944			return status;
 945	}
 946
 947	return MODE_OK;
 948}
 949
 950static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
 951				    int hdisplay, int clock)
 952{
 953	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 954
 955	if (!intel_dp_can_bigjoiner(intel_dp))
 956		return false;
 957
 958	return clock > i915->max_dotclk_freq || hdisplay > 5120;
 959}
 960
 961static enum drm_mode_status
 962intel_dp_mode_valid(struct drm_connector *_connector,
 963		    struct drm_display_mode *mode)
 964{
 965	struct intel_connector *connector = to_intel_connector(_connector);
 966	struct intel_dp *intel_dp = intel_attached_dp(connector);
 967	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 968	const struct drm_display_mode *fixed_mode;
 969	int target_clock = mode->clock;
 970	int max_rate, mode_rate, max_lanes, max_link_clock;
 971	int max_dotclk = dev_priv->max_dotclk_freq;
 972	u16 dsc_max_output_bpp = 0;
 973	u8 dsc_slice_count = 0;
 974	enum drm_mode_status status;
 975	bool dsc = false, bigjoiner = false;
 976
 977	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 978		return MODE_NO_DBLESCAN;
 979
 980	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 981		return MODE_H_ILLEGAL;
 982
 983	fixed_mode = intel_panel_fixed_mode(connector, mode);
 984	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 985		status = intel_panel_mode_valid(connector, mode);
 986		if (status != MODE_OK)
 987			return status;
 988
 989		target_clock = fixed_mode->clock;
 990	}
 991
 992	if (mode->clock < 10000)
 993		return MODE_CLOCK_LOW;
 994
 995	if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
 996		bigjoiner = true;
 997		max_dotclk *= 2;
 998	}
 999	if (target_clock > max_dotclk)
1000		return MODE_CLOCK_HIGH;
1001
1002	max_link_clock = intel_dp_max_link_rate(intel_dp);
1003	max_lanes = intel_dp_max_lane_count(intel_dp);
1004
1005	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1006	mode_rate = intel_dp_link_required(target_clock,
1007					   intel_dp_mode_min_output_bpp(connector, mode));
1008
1009	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1010		return MODE_H_ILLEGAL;
1011
1012	/*
1013	 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1014	 * integer value since we support only integer values of bpp.
1015	 */
1016	if (DISPLAY_VER(dev_priv) >= 10 &&
1017	    drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
1018		/*
1019		 * TBD pass the connector BPC,
1020		 * for now U8_MAX so that max BPC on that platform would be picked
1021		 */
1022		int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
1023
1024		if (intel_dp_is_edp(intel_dp)) {
1025			dsc_max_output_bpp =
1026				drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
1027			dsc_slice_count =
1028				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1029								true);
1030		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
1031			dsc_max_output_bpp =
1032				intel_dp_dsc_get_output_bpp(dev_priv,
1033							    max_link_clock,
1034							    max_lanes,
1035							    target_clock,
1036							    mode->hdisplay,
1037							    bigjoiner,
1038							    pipe_bpp) >> 4;
1039			dsc_slice_count =
1040				intel_dp_dsc_get_slice_count(intel_dp,
1041							     target_clock,
1042							     mode->hdisplay,
1043							     bigjoiner);
1044		}
1045
1046		dsc = dsc_max_output_bpp && dsc_slice_count;
1047	}
1048
1049	/*
1050	 * Big joiner configuration needs DSC for TGL which is not true for
1051	 * XE_LPD where uncompressed joiner is supported.
1052	 */
1053	if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1054		return MODE_CLOCK_HIGH;
1055
1056	if (mode_rate > max_rate && !dsc)
1057		return MODE_CLOCK_HIGH;
1058
1059	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1060	if (status != MODE_OK)
1061		return status;
1062
1063	return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1064}
1065
1066bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1067{
1068	return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1069}
1070
1071bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1072{
1073	return DISPLAY_VER(i915) >= 10;
1074}
1075
1076static void snprintf_int_array(char *str, size_t len,
1077			       const int *array, int nelem)
1078{
1079	int i;
1080
1081	str[0] = '\0';
1082
1083	for (i = 0; i < nelem; i++) {
1084		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1085		if (r >= len)
1086			return;
1087		str += r;
1088		len -= r;
1089	}
1090}
1091
1092static void intel_dp_print_rates(struct intel_dp *intel_dp)
1093{
1094	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1095	char str[128]; /* FIXME: too big for stack? */
1096
1097	if (!drm_debug_enabled(DRM_UT_KMS))
1098		return;
1099
1100	snprintf_int_array(str, sizeof(str),
1101			   intel_dp->source_rates, intel_dp->num_source_rates);
1102	drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1103
1104	snprintf_int_array(str, sizeof(str),
1105			   intel_dp->sink_rates, intel_dp->num_sink_rates);
1106	drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1107
1108	snprintf_int_array(str, sizeof(str),
1109			   intel_dp->common_rates, intel_dp->num_common_rates);
1110	drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1111}
1112
1113int
1114intel_dp_max_link_rate(struct intel_dp *intel_dp)
1115{
1116	int len;
1117
1118	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1119
1120	return intel_dp_common_rate(intel_dp, len - 1);
1121}
1122
1123int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1124{
1125	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1126	int i = intel_dp_rate_index(intel_dp->sink_rates,
1127				    intel_dp->num_sink_rates, rate);
1128
1129	if (drm_WARN_ON(&i915->drm, i < 0))
1130		i = 0;
1131
1132	return i;
1133}
1134
1135void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1136			   u8 *link_bw, u8 *rate_select)
1137{
1138	/* eDP 1.4 rate select method. */
1139	if (intel_dp->use_rate_select) {
1140		*link_bw = 0;
1141		*rate_select =
1142			intel_dp_rate_select(intel_dp, port_clock);
1143	} else {
1144		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1145		*rate_select = 0;
1146	}
1147}
1148
1149static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1150					 const struct intel_crtc_state *pipe_config)
1151{
1152	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1153
1154	/* On TGL, FEC is supported on all Pipes */
1155	if (DISPLAY_VER(dev_priv) >= 12)
1156		return true;
1157
1158	if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
1159		return true;
1160
1161	return false;
1162}
1163
1164static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1165				  const struct intel_crtc_state *pipe_config)
1166{
1167	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1168		drm_dp_sink_supports_fec(intel_dp->fec_capable);
1169}
1170
1171static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1172				  const struct intel_crtc_state *crtc_state)
1173{
1174	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1175		return false;
1176
1177	return intel_dsc_source_support(crtc_state) &&
1178		drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1179}
1180
1181static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
1182				 const struct intel_crtc_state *crtc_state)
1183{
1184	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1185		(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
1186		 intel_dp->dfp.ycbcr_444_to_420);
1187}
1188
1189static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1190				     const struct intel_crtc_state *crtc_state,
1191				     int bpc, bool respect_downstream_limits)
1192{
1193	bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
1194	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1195
1196	/*
1197	 * Current bpc could already be below 8bpc due to
1198	 * FDI bandwidth constraints or other limits.
1199	 * HDMI minimum is 8bpc however.
1200	 */
1201	bpc = max(bpc, 8);
1202
1203	/*
1204	 * We will never exceed downstream TMDS clock limits while
1205	 * attempting deep color. If the user insists on forcing an
1206	 * out of spec mode they will have to be satisfied with 8bpc.
1207	 */
1208	if (!respect_downstream_limits)
1209		bpc = 8;
1210
1211	for (; bpc >= 8; bpc -= 2) {
1212		if (intel_hdmi_bpc_possible(crtc_state, bpc,
1213					    intel_dp->has_hdmi_sink, ycbcr420_output) &&
1214		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output,
1215					      respect_downstream_limits) == MODE_OK)
1216			return bpc;
1217	}
1218
1219	return -EINVAL;
1220}
1221
1222static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1223			    const struct intel_crtc_state *crtc_state,
1224			    bool respect_downstream_limits)
1225{
1226	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1227	struct intel_connector *intel_connector = intel_dp->attached_connector;
1228	int bpp, bpc;
1229
1230	bpc = crtc_state->pipe_bpp / 3;
1231
1232	if (intel_dp->dfp.max_bpc)
1233		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1234
1235	if (intel_dp->dfp.min_tmds_clock) {
1236		int max_hdmi_bpc;
1237
1238		max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1239							 respect_downstream_limits);
1240		if (max_hdmi_bpc < 0)
1241			return 0;
1242
1243		bpc = min(bpc, max_hdmi_bpc);
1244	}
1245
1246	bpp = bpc * 3;
1247	if (intel_dp_is_edp(intel_dp)) {
1248		/* Get bpp from vbt only for panels that dont have bpp in edid */
1249		if (intel_connector->base.display_info.bpc == 0 &&
1250		    intel_connector->panel.vbt.edp.bpp &&
1251		    intel_connector->panel.vbt.edp.bpp < bpp) {
1252			drm_dbg_kms(&dev_priv->drm,
1253				    "clamping bpp for eDP panel to BIOS-provided %i\n",
1254				    intel_connector->panel.vbt.edp.bpp);
1255			bpp = intel_connector->panel.vbt.edp.bpp;
1256		}
1257	}
1258
1259	return bpp;
1260}
1261
1262/* Adjust link config limits based on compliance test requests. */
1263void
1264intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1265				  struct intel_crtc_state *pipe_config,
1266				  struct link_config_limits *limits)
1267{
1268	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1269
1270	/* For DP Compliance we override the computed bpp for the pipe */
1271	if (intel_dp->compliance.test_data.bpc != 0) {
1272		int bpp = 3 * intel_dp->compliance.test_data.bpc;
1273
1274		limits->min_bpp = limits->max_bpp = bpp;
1275		pipe_config->dither_force_disable = bpp == 6 * 3;
1276
1277		drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1278	}
1279
1280	/* Use values requested by Compliance Test Request */
1281	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1282		int index;
1283
1284		/* Validate the compliance test data since max values
1285		 * might have changed due to link train fallback.
1286		 */
1287		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1288					       intel_dp->compliance.test_lane_count)) {
1289			index = intel_dp_rate_index(intel_dp->common_rates,
1290						    intel_dp->num_common_rates,
1291						    intel_dp->compliance.test_link_rate);
1292			if (index >= 0)
1293				limits->min_rate = limits->max_rate =
1294					intel_dp->compliance.test_link_rate;
1295			limits->min_lane_count = limits->max_lane_count =
1296				intel_dp->compliance.test_lane_count;
1297		}
1298	}
1299}
1300
1301static bool has_seamless_m_n(struct intel_connector *connector)
1302{
1303	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1304
1305	/*
1306	 * Seamless M/N reprogramming only implemented
1307	 * for BDW+ double buffered M/N registers so far.
1308	 */
1309	return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1310		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1311}
1312
1313static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1314			       const struct drm_connector_state *conn_state)
1315{
1316	struct intel_connector *connector = to_intel_connector(conn_state->connector);
1317	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1318
1319	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
1320	if (has_seamless_m_n(connector))
1321		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1322	else
1323		return adjusted_mode->crtc_clock;
1324}
1325
1326/* Optimize link config in order: max bpp, min clock, min lanes */
1327static int
1328intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1329				  struct intel_crtc_state *pipe_config,
1330				  const struct drm_connector_state *conn_state,
1331				  const struct link_config_limits *limits)
1332{
1333	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1334	int mode_rate, link_rate, link_avail;
1335
1336	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1337		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1338
1339		mode_rate = intel_dp_link_required(clock, output_bpp);
1340
1341		for (i = 0; i < intel_dp->num_common_rates; i++) {
1342			link_rate = intel_dp_common_rate(intel_dp, i);
1343			if (link_rate < limits->min_rate ||
1344			    link_rate > limits->max_rate)
1345				continue;
1346
1347			for (lane_count = limits->min_lane_count;
1348			     lane_count <= limits->max_lane_count;
1349			     lane_count <<= 1) {
1350				link_avail = intel_dp_max_data_rate(link_rate,
1351								    lane_count);
1352
1353				if (mode_rate <= link_avail) {
1354					pipe_config->lane_count = lane_count;
1355					pipe_config->pipe_bpp = bpp;
1356					pipe_config->port_clock = link_rate;
1357
1358					return 0;
1359				}
1360			}
1361		}
1362	}
1363
1364	return -EINVAL;
1365}
1366
1367static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc)
1368{
1369	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1370	int i, num_bpc;
1371	u8 dsc_bpc[3] = {0};
1372	u8 dsc_max_bpc;
1373
1374	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1375	if (DISPLAY_VER(i915) >= 12)
1376		dsc_max_bpc = min_t(u8, 12, max_req_bpc);
1377	else
1378		dsc_max_bpc = min_t(u8, 10, max_req_bpc);
1379
1380	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1381						       dsc_bpc);
1382	for (i = 0; i < num_bpc; i++) {
1383		if (dsc_max_bpc >= dsc_bpc[i])
1384			return dsc_bpc[i] * 3;
1385	}
1386
1387	return 0;
1388}
1389
1390static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp)
1391{
1392	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1393
1394	return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1395}
1396
1397static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp)
1398{
1399	return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1400		DP_DSC_MINOR_SHIFT;
1401}
1402
1403static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
1404				       struct intel_crtc_state *crtc_state)
1405{
1406	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1407	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1408	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1409	u8 line_buf_depth;
1410	int ret;
1411
1412	/*
1413	 * RC_MODEL_SIZE is currently a constant across all configurations.
1414	 *
1415	 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1416	 * DP_DSC_RC_BUF_SIZE for this.
1417	 */
1418	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1419	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1420
1421	/*
1422	 * Slice Height of 8 works for all currently available panels. So start
1423	 * with that if pic_height is an integral multiple of 8. Eventually add
1424	 * logic to try multiple slice heights.
1425	 */
1426	if (vdsc_cfg->pic_height % 8 == 0)
1427		vdsc_cfg->slice_height = 8;
1428	else if (vdsc_cfg->pic_height % 4 == 0)
1429		vdsc_cfg->slice_height = 4;
1430	else
1431		vdsc_cfg->slice_height = 2;
1432
1433	ret = intel_dsc_compute_params(crtc_state);
1434	if (ret)
1435		return ret;
1436
1437	vdsc_cfg->dsc_version_major =
1438		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1439		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1440	vdsc_cfg->dsc_version_minor =
1441		min(intel_dp_source_dsc_version_minor(intel_dp),
1442		    intel_dp_sink_dsc_version_minor(intel_dp));
1443
1444	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1445		DP_DSC_RGB;
1446
1447	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
1448	if (!line_buf_depth) {
1449		drm_dbg_kms(&i915->drm,
1450			    "DSC Sink Line Buffer Depth invalid\n");
1451		return -EINVAL;
1452	}
1453
1454	if (vdsc_cfg->dsc_version_minor == 2)
1455		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1456			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1457	else
1458		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1459			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1460
1461	vdsc_cfg->block_pred_enable =
1462		intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1463		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1464
1465	return drm_dsc_compute_rc_parameters(vdsc_cfg);
1466}
1467
1468static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1469				       struct intel_crtc_state *pipe_config,
1470				       struct drm_connector_state *conn_state,
1471				       struct link_config_limits *limits)
1472{
1473	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1474	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1475	const struct drm_display_mode *adjusted_mode =
1476		&pipe_config->hw.adjusted_mode;
1477	int pipe_bpp;
1478	int ret;
1479
1480	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1481		intel_dp_supports_fec(intel_dp, pipe_config);
1482
1483	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1484		return -EINVAL;
1485
1486	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
1487
1488	if (intel_dp->force_dsc_bpc) {
1489		pipe_bpp = intel_dp->force_dsc_bpc * 3;
1490		drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
1491	}
1492
1493	/* Min Input BPC for ICL+ is 8 */
1494	if (pipe_bpp < 8 * 3) {
1495		drm_dbg_kms(&dev_priv->drm,
1496			    "No DSC support for less than 8bpc\n");
1497		return -EINVAL;
1498	}
1499
1500	/*
1501	 * For now enable DSC for max bpp, max link rate, max lane count.
1502	 * Optimize this later for the minimum possible link rate/lane count
1503	 * with DSC enabled for the requested mode.
1504	 */
1505	pipe_config->pipe_bpp = pipe_bpp;
1506	pipe_config->port_clock = limits->max_rate;
1507	pipe_config->lane_count = limits->max_lane_count;
1508
1509	if (intel_dp_is_edp(intel_dp)) {
1510		pipe_config->dsc.compressed_bpp =
1511			min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1512			      pipe_config->pipe_bpp);
1513		pipe_config->dsc.slice_count =
1514			drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1515							true);
1516	} else {
1517		u16 dsc_max_output_bpp;
1518		u8 dsc_dp_slice_count;
1519
1520		dsc_max_output_bpp =
1521			intel_dp_dsc_get_output_bpp(dev_priv,
1522						    pipe_config->port_clock,
1523						    pipe_config->lane_count,
1524						    adjusted_mode->crtc_clock,
1525						    adjusted_mode->crtc_hdisplay,
1526						    pipe_config->bigjoiner_pipes,
1527						    pipe_bpp);
1528		dsc_dp_slice_count =
1529			intel_dp_dsc_get_slice_count(intel_dp,
1530						     adjusted_mode->crtc_clock,
1531						     adjusted_mode->crtc_hdisplay,
1532						     pipe_config->bigjoiner_pipes);
1533		if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1534			drm_dbg_kms(&dev_priv->drm,
1535				    "Compressed BPP/Slice Count not supported\n");
1536			return -EINVAL;
1537		}
1538		pipe_config->dsc.compressed_bpp = min_t(u16,
1539							       dsc_max_output_bpp >> 4,
1540							       pipe_config->pipe_bpp);
1541		pipe_config->dsc.slice_count = dsc_dp_slice_count;
1542	}
1543
1544	/*
1545	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1546	 * is greater than the maximum Cdclock and if slice count is even
1547	 * then we need to use 2 VDSC instances.
1548	 */
1549	if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq ||
1550	    pipe_config->bigjoiner_pipes) {
1551		if (pipe_config->dsc.slice_count < 2) {
1552			drm_dbg_kms(&dev_priv->drm,
1553				    "Cannot split stream to use 2 VDSC instances\n");
1554			return -EINVAL;
1555		}
1556
1557		pipe_config->dsc.dsc_split = true;
1558	}
1559
1560	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
1561	if (ret < 0) {
1562		drm_dbg_kms(&dev_priv->drm,
1563			    "Cannot compute valid DSC parameters for Input Bpp = %d "
1564			    "Compressed BPP = %d\n",
1565			    pipe_config->pipe_bpp,
1566			    pipe_config->dsc.compressed_bpp);
1567		return ret;
1568	}
1569
1570	pipe_config->dsc.compression_enable = true;
1571	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
1572		    "Compressed Bpp = %d Slice Count = %d\n",
1573		    pipe_config->pipe_bpp,
1574		    pipe_config->dsc.compressed_bpp,
1575		    pipe_config->dsc.slice_count);
1576
1577	return 0;
1578}
1579
1580static int
1581intel_dp_compute_link_config(struct intel_encoder *encoder,
1582			     struct intel_crtc_state *pipe_config,
1583			     struct drm_connector_state *conn_state,
1584			     bool respect_downstream_limits)
1585{
1586	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1587	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1588	const struct drm_display_mode *adjusted_mode =
1589		&pipe_config->hw.adjusted_mode;
1590	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1591	struct link_config_limits limits;
1592	bool joiner_needs_dsc = false;
1593	int ret;
1594
1595	limits.min_rate = intel_dp_common_rate(intel_dp, 0);
1596	limits.max_rate = intel_dp_max_link_rate(intel_dp);
1597
1598	limits.min_lane_count = 1;
1599	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1600
1601	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
1602	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
1603
1604	if (intel_dp->use_max_params) {
1605		/*
1606		 * Use the maximum clock and number of lanes the eDP panel
1607		 * advertizes being capable of in case the initial fast
1608		 * optimal params failed us. The panels are generally
1609		 * designed to support only a single clock and lane
1610		 * configuration, and typically on older panels these
1611		 * values correspond to the native resolution of the panel.
1612		 */
1613		limits.min_lane_count = limits.max_lane_count;
1614		limits.min_rate = limits.max_rate;
1615	}
1616
1617	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1618
1619	drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
1620		    "max rate %d max bpp %d pixel clock %iKHz\n",
1621		    limits.max_lane_count, limits.max_rate,
1622		    limits.max_bpp, adjusted_mode->crtc_clock);
1623
1624	if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
1625				    adjusted_mode->crtc_clock))
1626		pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
1627
1628	/*
1629	 * Pipe joiner needs compression up to display 12 due to bandwidth
1630	 * limitation. DG2 onwards pipe joiner can be enabled without
1631	 * compression.
1632	 */
1633	joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
1634
1635	/*
1636	 * Optimize for slow and wide for everything, because there are some
1637	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
1638	 */
1639	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
1640
1641	if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
1642		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
1643			    str_yes_no(ret), str_yes_no(joiner_needs_dsc),
1644			    str_yes_no(intel_dp->force_dsc_en));
1645		ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
1646						  conn_state, &limits);
1647		if (ret < 0)
1648			return ret;
1649	}
1650
1651	if (pipe_config->dsc.compression_enable) {
1652		drm_dbg_kms(&i915->drm,
1653			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
1654			    pipe_config->lane_count, pipe_config->port_clock,
1655			    pipe_config->pipe_bpp,
1656			    pipe_config->dsc.compressed_bpp);
1657
1658		drm_dbg_kms(&i915->drm,
1659			    "DP link rate required %i available %i\n",
1660			    intel_dp_link_required(adjusted_mode->crtc_clock,
1661						   pipe_config->dsc.compressed_bpp),
1662			    intel_dp_max_data_rate(pipe_config->port_clock,
1663						   pipe_config->lane_count));
1664	} else {
1665		drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
1666			    pipe_config->lane_count, pipe_config->port_clock,
1667			    pipe_config->pipe_bpp);
1668
1669		drm_dbg_kms(&i915->drm,
1670			    "DP link rate required %i available %i\n",
1671			    intel_dp_link_required(adjusted_mode->crtc_clock,
1672						   pipe_config->pipe_bpp),
1673			    intel_dp_max_data_rate(pipe_config->port_clock,
1674						   pipe_config->lane_count));
1675	}
1676	return 0;
1677}
1678
1679bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1680				  const struct drm_connector_state *conn_state)
1681{
1682	const struct intel_digital_connector_state *intel_conn_state =
1683		to_intel_digital_connector_state(conn_state);
1684	const struct drm_display_mode *adjusted_mode =
1685		&crtc_state->hw.adjusted_mode;
1686
1687	/*
1688	 * Our YCbCr output is always limited range.
1689	 * crtc_state->limited_color_range only applies to RGB,
1690	 * and it must never be set for YCbCr or we risk setting
1691	 * some conflicting bits in PIPECONF which will mess up
1692	 * the colors on the monitor.
1693	 */
1694	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
1695		return false;
1696
1697	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1698		/*
1699		 * See:
1700		 * CEA-861-E - 5.1 Default Encoding Parameters
1701		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1702		 */
1703		return crtc_state->pipe_bpp != 18 &&
1704			drm_default_rgb_quant_range(adjusted_mode) ==
1705			HDMI_QUANTIZATION_RANGE_LIMITED;
1706	} else {
1707		return intel_conn_state->broadcast_rgb ==
1708			INTEL_BROADCAST_RGB_LIMITED;
1709	}
1710}
1711
1712static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
1713				    enum port port)
1714{
1715	if (IS_G4X(dev_priv))
1716		return false;
1717	if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
1718		return false;
1719
1720	return true;
1721}
1722
1723static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
1724					     const struct drm_connector_state *conn_state,
1725					     struct drm_dp_vsc_sdp *vsc)
1726{
1727	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1728	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1729
1730	/*
1731	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1732	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
1733	 * Colorimetry Format indication.
1734	 */
1735	vsc->revision = 0x5;
1736	vsc->length = 0x13;
1737
1738	/* DP 1.4a spec, Table 2-120 */
1739	switch (crtc_state->output_format) {
1740	case INTEL_OUTPUT_FORMAT_YCBCR444:
1741		vsc->pixelformat = DP_PIXELFORMAT_YUV444;
1742		break;
1743	case INTEL_OUTPUT_FORMAT_YCBCR420:
1744		vsc->pixelformat = DP_PIXELFORMAT_YUV420;
1745		break;
1746	case INTEL_OUTPUT_FORMAT_RGB:
1747	default:
1748		vsc->pixelformat = DP_PIXELFORMAT_RGB;
1749	}
1750
1751	switch (conn_state->colorspace) {
1752	case DRM_MODE_COLORIMETRY_BT709_YCC:
1753		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1754		break;
1755	case DRM_MODE_COLORIMETRY_XVYCC_601:
1756		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
1757		break;
1758	case DRM_MODE_COLORIMETRY_XVYCC_709:
1759		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
1760		break;
1761	case DRM_MODE_COLORIMETRY_SYCC_601:
1762		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
1763		break;
1764	case DRM_MODE_COLORIMETRY_OPYCC_601:
1765		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
1766		break;
1767	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1768		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
1769		break;
1770	case DRM_MODE_COLORIMETRY_BT2020_RGB:
1771		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
1772		break;
1773	case DRM_MODE_COLORIMETRY_BT2020_YCC:
1774		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
1775		break;
1776	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1777	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1778		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
1779		break;
1780	default:
1781		/*
1782		 * RGB->YCBCR color conversion uses the BT.709
1783		 * color space.
1784		 */
1785		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1786			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
1787		else
1788			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
1789		break;
1790	}
1791
1792	vsc->bpc = crtc_state->pipe_bpp / 3;
1793
1794	/* only RGB pixelformat supports 6 bpc */
1795	drm_WARN_ON(&dev_priv->drm,
1796		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
1797
1798	/* all YCbCr are always limited range */
1799	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
1800	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1801}
1802
1803static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
1804				     struct intel_crtc_state *crtc_state,
1805				     const struct drm_connector_state *conn_state)
1806{
1807	struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
1808
1809	/* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
1810	if (crtc_state->has_psr)
1811		return;
1812
1813	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1814		return;
1815
1816	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1817	vsc->sdp_type = DP_SDP_VSC;
1818	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1819					 &crtc_state->infoframes.vsc);
1820}
1821
1822void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
1823				  const struct intel_crtc_state *crtc_state,
1824				  const struct drm_connector_state *conn_state,
1825				  struct drm_dp_vsc_sdp *vsc)
1826{
1827	vsc->sdp_type = DP_SDP_VSC;
1828
1829	if (crtc_state->has_psr2) {
1830		if (intel_dp->psr.colorimetry_support &&
1831		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
1832			/* [PSR2, +Colorimetry] */
1833			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
1834							 vsc);
1835		} else {
1836			/*
1837			 * [PSR2, -Colorimetry]
1838			 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
1839			 * 3D stereo + PSR/PSR2 + Y-coordinate.
1840			 */
1841			vsc->revision = 0x4;
1842			vsc->length = 0xe;
1843		}
1844	} else {
1845		/*
1846		 * [PSR1]
1847		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
1848		 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
1849		 * higher).
1850		 */
1851		vsc->revision = 0x2;
1852		vsc->length = 0x8;
1853	}
1854}
1855
1856static void
1857intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
1858					    struct intel_crtc_state *crtc_state,
1859					    const struct drm_connector_state *conn_state)
1860{
1861	int ret;
1862	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1863	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
1864
1865	if (!conn_state->hdr_output_metadata)
1866		return;
1867
1868	ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
1869
1870	if (ret) {
1871		drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
1872		return;
1873	}
1874
1875	crtc_state->infoframes.enable |=
1876		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
1877}
1878
1879static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
1880				    enum transcoder cpu_transcoder)
1881{
1882	if (HAS_DOUBLE_BUFFERED_M_N(i915))
1883		return true;
1884
1885	return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
1886}
1887
1888static bool can_enable_drrs(struct intel_connector *connector,
1889			    const struct intel_crtc_state *pipe_config,
1890			    const struct drm_display_mode *downclock_mode)
1891{
1892	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1893
1894	if (pipe_config->vrr.enable)
1895		return false;
1896
1897	/*
1898	 * DRRS and PSR can't be enable together, so giving preference to PSR
1899	 * as it allows more power-savings by complete shutting down display,
1900	 * so to guarantee this, intel_drrs_compute_config() must be called
1901	 * after intel_psr_compute_config().
1902	 */
1903	if (pipe_config->has_psr)
1904		return false;
1905
1906	/* FIXME missing FDI M2/N2 etc. */
1907	if (pipe_config->has_pch_encoder)
1908		return false;
1909
1910	if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
1911		return false;
1912
1913	return downclock_mode &&
1914		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1915}
1916
1917static void
1918intel_dp_drrs_compute_config(struct intel_connector *connector,
1919			     struct intel_crtc_state *pipe_config,
1920			     int output_bpp)
1921{
1922	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1923	const struct drm_display_mode *downclock_mode =
1924		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
1925	int pixel_clock;
1926
1927	if (has_seamless_m_n(connector))
1928		pipe_config->seamless_m_n = true;
1929
1930	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
1931		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
1932			intel_zero_m_n(&pipe_config->dp_m2_n2);
1933		return;
1934	}
1935
1936	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
1937		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
1938
1939	pipe_config->has_drrs = true;
1940
1941	pixel_clock = downclock_mode->clock;
1942	if (pipe_config->splitter.enable)
1943		pixel_clock /= pipe_config->splitter.link_count;
1944
1945	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
1946			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
1947			       pipe_config->fec_enable);
1948
1949	/* FIXME: abstract this better */
1950	if (pipe_config->splitter.enable)
1951		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
1952}
1953
1954static bool intel_dp_has_audio(struct intel_encoder *encoder,
1955			       const struct intel_crtc_state *crtc_state,
1956			       const struct drm_connector_state *conn_state)
1957{
1958	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1959	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1960	const struct intel_digital_connector_state *intel_conn_state =
1961		to_intel_digital_connector_state(conn_state);
1962
1963	if (!intel_dp_port_has_audio(i915, encoder->port))
1964		return false;
1965
1966	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1967		return intel_dp->has_audio;
1968	else
1969		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1970}
1971
1972static int
1973intel_dp_compute_output_format(struct intel_encoder *encoder,
1974			       struct intel_crtc_state *crtc_state,
1975			       struct drm_connector_state *conn_state,
1976			       bool respect_downstream_limits)
1977{
1978	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1979	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1980	struct intel_connector *connector = intel_dp->attached_connector;
1981	const struct drm_display_info *info = &connector->base.display_info;
1982	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1983	bool ycbcr_420_only;
1984	int ret;
1985
1986	ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
1987
1988	crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
1989
1990	if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
1991		drm_dbg_kms(&i915->drm,
1992			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
1993		crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
1994	}
1995
1996	ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
1997					   respect_downstream_limits);
1998	if (ret) {
1999		if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
2000		    !connector->base.ycbcr_420_allowed ||
2001		    !drm_mode_is_420_also(info, adjusted_mode))
2002			return ret;
2003
2004		crtc_state->output_format = intel_dp_output_format(connector, true);
2005		ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2006						   respect_downstream_limits);
2007	}
2008
2009	return ret;
2010}
2011
2012int
2013intel_dp_compute_config(struct intel_encoder *encoder,
2014			struct intel_crtc_state *pipe_config,
2015			struct drm_connector_state *conn_state)
2016{
2017	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2018	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2019	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2020	const struct drm_display_mode *fixed_mode;
2021	struct intel_connector *connector = intel_dp->attached_connector;
2022	int ret = 0, output_bpp;
2023
2024	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2025		pipe_config->has_pch_encoder = true;
2026
2027	pipe_config->has_audio = intel_dp_has_audio(encoder, pipe_config, conn_state);
2028
2029	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2030	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2031		ret = intel_panel_compute_config(connector, adjusted_mode);
2032		if (ret)
2033			return ret;
2034	}
2035
2036	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2037		return -EINVAL;
2038
2039	if (HAS_GMCH(dev_priv) &&
2040	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2041		return -EINVAL;
2042
2043	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2044		return -EINVAL;
2045
2046	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2047		return -EINVAL;
2048
2049	/*
2050	 * Try to respect downstream TMDS clock limits first, if
2051	 * that fails assume the user might know something we don't.
2052	 */
2053	ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2054	if (ret)
2055		ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2056	if (ret)
2057		return ret;
2058
2059	if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2060	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2061		ret = intel_panel_fitting(pipe_config, conn_state);
2062		if (ret)
2063			return ret;
2064	}
2065
2066	pipe_config->limited_color_range =
2067		intel_dp_limited_color_range(pipe_config, conn_state);
2068
2069	if (pipe_config->dsc.compression_enable)
2070		output_bpp = pipe_config->dsc.compressed_bpp;
2071	else
2072		output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2073						 pipe_config->pipe_bpp);
2074
2075	if (intel_dp->mso_link_count) {
2076		int n = intel_dp->mso_link_count;
2077		int overlap = intel_dp->mso_pixel_overlap;
2078
2079		pipe_config->splitter.enable = true;
2080		pipe_config->splitter.link_count = n;
2081		pipe_config->splitter.pixel_overlap = overlap;
2082
2083		drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2084			    n, overlap);
2085
2086		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2087		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2088		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2089		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2090		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2091		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2092		adjusted_mode->crtc_clock /= n;
2093	}
2094
2095	intel_link_compute_m_n(output_bpp,
2096			       pipe_config->lane_count,
2097			       adjusted_mode->crtc_clock,
2098			       pipe_config->port_clock,
2099			       &pipe_config->dp_m_n,
2100			       pipe_config->fec_enable);
2101
2102	/* FIXME: abstract this better */
2103	if (pipe_config->splitter.enable)
2104		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2105
2106	if (!HAS_DDI(dev_priv))
2107		g4x_dp_set_clock(encoder, pipe_config);
2108
2109	intel_vrr_compute_config(pipe_config, conn_state);
2110	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2111	intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
2112	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2113	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2114
2115	return 0;
2116}
2117
2118void intel_dp_set_link_params(struct intel_dp *intel_dp,
2119			      int link_rate, int lane_count)
2120{
2121	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2122	intel_dp->link_trained = false;
2123	intel_dp->link_rate = link_rate;
2124	intel_dp->lane_count = lane_count;
2125}
2126
2127static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2128{
2129	intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2130	intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2131}
2132
2133/* Enable backlight PWM and backlight PP control. */
2134void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2135			    const struct drm_connector_state *conn_state)
2136{
2137	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2138	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2139
2140	if (!intel_dp_is_edp(intel_dp))
2141		return;
2142
2143	drm_dbg_kms(&i915->drm, "\n");
2144
2145	intel_backlight_enable(crtc_state, conn_state);
2146	intel_pps_backlight_on(intel_dp);
2147}
2148
2149/* Disable backlight PP control and backlight PWM. */
2150void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2151{
2152	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2153	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2154
2155	if (!intel_dp_is_edp(intel_dp))
2156		return;
2157
2158	drm_dbg_kms(&i915->drm, "\n");
2159
2160	intel_pps_backlight_off(intel_dp);
2161	intel_backlight_disable(old_conn_state);
2162}
2163
2164static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2165{
2166	/*
2167	 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2168	 * be capable of signalling downstream hpd with a long pulse.
2169	 * Whether or not that means D3 is safe to use is not clear,
2170	 * but let's assume so until proven otherwise.
2171	 *
2172	 * FIXME should really check all downstream ports...
2173	 */
2174	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2175		drm_dp_is_branch(intel_dp->dpcd) &&
2176		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2177}
2178
2179void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2180					   const struct intel_crtc_state *crtc_state,
2181					   bool enable)
2182{
2183	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2184	int ret;
2185
2186	if (!crtc_state->dsc.compression_enable)
2187		return;
2188
2189	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2190				 enable ? DP_DECOMPRESSION_EN : 0);
2191	if (ret < 0)
2192		drm_dbg_kms(&i915->drm,
2193			    "Failed to %s sink decompression state\n",
2194			    str_enable_disable(enable));
2195}
2196
2197static void
2198intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2199{
2200	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2201	u8 oui[] = { 0x00, 0xaa, 0x01 };
2202	u8 buf[3] = { 0 };
2203
2204	/*
2205	 * During driver init, we want to be careful and avoid changing the source OUI if it's
2206	 * already set to what we want, so as to avoid clearing any state by accident
2207	 */
2208	if (careful) {
2209		if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2210			drm_err(&i915->drm, "Failed to read source OUI\n");
2211
2212		if (memcmp(oui, buf, sizeof(oui)) == 0)
2213			return;
2214	}
2215
2216	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2217		drm_err(&i915->drm, "Failed to write source OUI\n");
2218
2219	intel_dp->last_oui_write = jiffies;
2220}
2221
2222void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2223{
2224	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2225
2226	drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
2227	wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
2228}
2229
2230/* If the device supports it, try to set the power state appropriately */
2231void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2232{
2233	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2234	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2235	int ret, i;
2236
2237	/* Should have a valid DPCD by this point */
2238	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2239		return;
2240
2241	if (mode != DP_SET_POWER_D0) {
2242		if (downstream_hpd_needs_d0(intel_dp))
2243			return;
2244
2245		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2246	} else {
2247		struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2248
2249		lspcon_resume(dp_to_dig_port(intel_dp));
2250
2251		/* Write the source OUI as early as possible */
2252		if (intel_dp_is_edp(intel_dp))
2253			intel_edp_init_source_oui(intel_dp, false);
2254
2255		/*
2256		 * When turning on, we need to retry for 1ms to give the sink
2257		 * time to wake up.
2258		 */
2259		for (i = 0; i < 3; i++) {
2260			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2261			if (ret == 1)
2262				break;
2263			msleep(1);
2264		}
2265
2266		if (ret == 1 && lspcon->active)
2267			lspcon_wait_pcon_mode(lspcon);
2268	}
2269
2270	if (ret != 1)
2271		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
2272			    encoder->base.base.id, encoder->base.name,
2273			    mode == DP_SET_POWER_D0 ? "D0" : "D3");
2274}
2275
2276static bool
2277intel_dp_get_dpcd(struct intel_dp *intel_dp);
2278
2279/**
2280 * intel_dp_sync_state - sync the encoder state during init/resume
2281 * @encoder: intel encoder to sync
2282 * @crtc_state: state for the CRTC connected to the encoder
2283 *
2284 * Sync any state stored in the encoder wrt. HW state during driver init
2285 * and system resume.
2286 */
2287void intel_dp_sync_state(struct intel_encoder *encoder,
2288			 const struct intel_crtc_state *crtc_state)
2289{
2290	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2291
2292	if (!crtc_state)
2293		return;
2294
2295	/*
2296	 * Don't clobber DPCD if it's been already read out during output
2297	 * setup (eDP) or detect.
2298	 */
2299	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2300		intel_dp_get_dpcd(intel_dp);
2301
2302	intel_dp_reset_max_link_params(intel_dp);
2303}
2304
2305bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
2306				    struct intel_crtc_state *crtc_state)
2307{
2308	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2309	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2310	bool fastset = true;
2311
2312	/*
2313	 * If BIOS has set an unsupported or non-standard link rate for some
2314	 * reason force an encoder recompute and full modeset.
2315	 */
2316	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
2317				crtc_state->port_clock) < 0) {
2318		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
2319			    encoder->base.base.id, encoder->base.name);
2320		crtc_state->uapi.connectors_changed = true;
2321		fastset = false;
2322	}
2323
2324	/*
2325	 * FIXME hack to force full modeset when DSC is being used.
2326	 *
2327	 * As long as we do not have full state readout and config comparison
2328	 * of crtc_state->dsc, we have no way to ensure reliable fastset.
2329	 * Remove once we have readout for DSC.
2330	 */
2331	if (crtc_state->dsc.compression_enable) {
2332		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
2333			    encoder->base.base.id, encoder->base.name);
2334		crtc_state->uapi.mode_changed = true;
2335		fastset = false;
2336	}
2337
2338	if (CAN_PSR(intel_dp)) {
2339		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
2340			    encoder->base.base.id, encoder->base.name);
2341		crtc_state->uapi.mode_changed = true;
2342		fastset = false;
2343	}
2344
2345	return fastset;
2346}
2347
2348static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
2349{
2350	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2351
2352	/* Clear the cached register set to avoid using stale values */
2353
2354	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
2355
2356	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
2357			     intel_dp->pcon_dsc_dpcd,
2358			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
2359		drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
2360			DP_PCON_DSC_ENCODER);
2361
2362	drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
2363		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
2364}
2365
2366static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
2367{
2368	int bw_gbps[] = {9, 18, 24, 32, 40, 48};
2369	int i;
2370
2371	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
2372		if (frl_bw_mask & (1 << i))
2373			return bw_gbps[i];
2374	}
2375	return 0;
2376}
2377
2378static int intel_dp_pcon_set_frl_mask(int max_frl)
2379{
2380	switch (max_frl) {
2381	case 48:
2382		return DP_PCON_FRL_BW_MASK_48GBPS;
2383	case 40:
2384		return DP_PCON_FRL_BW_MASK_40GBPS;
2385	case 32:
2386		return DP_PCON_FRL_BW_MASK_32GBPS;
2387	case 24:
2388		return DP_PCON_FRL_BW_MASK_24GBPS;
2389	case 18:
2390		return DP_PCON_FRL_BW_MASK_18GBPS;
2391	case 9:
2392		return DP_PCON_FRL_BW_MASK_9GBPS;
2393	}
2394
2395	return 0;
2396}
2397
2398static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
2399{
2400	struct intel_connector *intel_connector = intel_dp->attached_connector;
2401	struct drm_connector *connector = &intel_connector->base;
2402	int max_frl_rate;
2403	int max_lanes, rate_per_lane;
2404	int max_dsc_lanes, dsc_rate_per_lane;
2405
2406	max_lanes = connector->display_info.hdmi.max_lanes;
2407	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
2408	max_frl_rate = max_lanes * rate_per_lane;
2409
2410	if (connector->display_info.hdmi.dsc_cap.v_1p2) {
2411		max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
2412		dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
2413		if (max_dsc_lanes && dsc_rate_per_lane)
2414			max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
2415	}
2416
2417	return max_frl_rate;
2418}
2419
2420static bool
2421intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
2422			     u8 max_frl_bw_mask, u8 *frl_trained_mask)
2423{
2424	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
2425	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
2426	    *frl_trained_mask >= max_frl_bw_mask)
2427		return true;
2428
2429	return false;
2430}
2431
2432static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
2433{
2434#define TIMEOUT_FRL_READY_MS 500
2435#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
2436
2437	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2438	int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
2439	u8 max_frl_bw_mask = 0, frl_trained_mask;
2440	bool is_active;
2441
2442	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
2443	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
2444
2445	max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
2446	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
2447
2448	max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
2449
2450	if (max_frl_bw <= 0)
2451		return -EINVAL;
2452
2453	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
2454	drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
2455
2456	if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
2457		goto frl_trained;
2458
2459	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
2460	if (ret < 0)
2461		return ret;
2462	/* Wait for PCON to be FRL Ready */
2463	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
2464
2465	if (!is_active)
2466		return -ETIMEDOUT;
2467
2468	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
2469					  DP_PCON_ENABLE_SEQUENTIAL_LINK);
2470	if (ret < 0)
2471		return ret;
2472	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
2473					  DP_PCON_FRL_LINK_TRAIN_NORMAL);
2474	if (ret < 0)
2475		return ret;
2476	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
2477	if (ret < 0)
2478		return ret;
2479	/*
2480	 * Wait for FRL to be completed
2481	 * Check if the HDMI Link is up and active.
2482	 */
2483	wait_for(is_active =
2484		 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
2485		 TIMEOUT_HDMI_LINK_ACTIVE_MS);
2486
2487	if (!is_active)
2488		return -ETIMEDOUT;
2489
2490frl_trained:
2491	drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
2492	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
2493	intel_dp->frl.is_trained = true;
2494	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
2495
2496	return 0;
2497}
2498
2499static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
2500{
2501	if (drm_dp_is_branch(intel_dp->dpcd) &&
2502	    intel_dp->has_hdmi_sink &&
2503	    intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
2504		return true;
2505
2506	return false;
2507}
2508
2509static
2510int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
2511{
2512	int ret;
2513	u8 buf = 0;
2514
2515	/* Set PCON source control mode */
2516	buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
2517
2518	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2519	if (ret < 0)
2520		return ret;
2521
2522	/* Set HDMI LINK ENABLE */
2523	buf |= DP_PCON_ENABLE_HDMI_LINK;
2524	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2525	if (ret < 0)
2526		return ret;
2527
2528	return 0;
2529}
2530
2531void intel_dp_check_frl_training(struct intel_dp *intel_dp)
2532{
2533	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2534
2535	/*
2536	 * Always go for FRL training if:
2537	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
2538	 * -sink is HDMI2.1
2539	 */
2540	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
2541	    !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
2542	    intel_dp->frl.is_trained)
2543		return;
2544
2545	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
2546		int ret, mode;
2547
2548		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
2549		ret = intel_dp_pcon_set_tmds_mode(intel_dp);
2550		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
2551
2552		if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
2553			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
2554	} else {
2555		drm_dbg(&dev_priv->drm, "FRL training Completed\n");
2556	}
2557}
2558
2559static int
2560intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
2561{
2562	int vactive = crtc_state->hw.adjusted_mode.vdisplay;
2563
2564	return intel_hdmi_dsc_get_slice_height(vactive);
2565}
2566
2567static int
2568intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
2569			     const struct intel_crtc_state *crtc_state)
2570{
2571	struct intel_connector *intel_connector = intel_dp->attached_connector;
2572	struct drm_connector *connector = &intel_connector->base;
2573	int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
2574	int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
2575	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
2576	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
2577
2578	return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
2579					     pcon_max_slice_width,
2580					     hdmi_max_slices, hdmi_throughput);
2581}
2582
2583static int
2584intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
2585			  const struct intel_crtc_state *crtc_state,
2586			  int num_slices, int slice_width)
2587{
2588	struct intel_connector *intel_connector = intel_dp->attached_connector;
2589	struct drm_connector *connector = &intel_connector->base;
2590	int output_format = crtc_state->output_format;
2591	bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
2592	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
2593	int hdmi_max_chunk_bytes =
2594		connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
2595
2596	return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
2597				      num_slices, output_format, hdmi_all_bpp,
2598				      hdmi_max_chunk_bytes);
2599}
2600
2601void
2602intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
2603			    const struct intel_crtc_state *crtc_state)
2604{
2605	u8 pps_param[6];
2606	int slice_height;
2607	int slice_width;
2608	int num_slices;
2609	int bits_per_pixel;
2610	int ret;
2611	struct intel_connector *intel_connector = intel_dp->attached_connector;
2612	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2613	struct drm_connector *connector;
2614	bool hdmi_is_dsc_1_2;
2615
2616	if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
2617		return;
2618
2619	if (!intel_connector)
2620		return;
2621	connector = &intel_connector->base;
2622	hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
2623
2624	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
2625	    !hdmi_is_dsc_1_2)
2626		return;
2627
2628	slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
2629	if (!slice_height)
2630		return;
2631
2632	num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
2633	if (!num_slices)
2634		return;
2635
2636	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
2637				   num_slices);
2638
2639	bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
2640						   num_slices, slice_width);
2641	if (!bits_per_pixel)
2642		return;
2643
2644	pps_param[0] = slice_height & 0xFF;
2645	pps_param[1] = slice_height >> 8;
2646	pps_param[2] = slice_width & 0xFF;
2647	pps_param[3] = slice_width >> 8;
2648	pps_param[4] = bits_per_pixel & 0xFF;
2649	pps_param[5] = (bits_per_pixel >> 8) & 0x3;
2650
2651	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
2652	if (ret < 0)
2653		drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
2654}
2655
2656void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
2657					   const struct intel_crtc_state *crtc_state)
2658{
2659	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2660	u8 tmp;
2661
2662	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
2663		return;
2664
2665	if (!drm_dp_is_branch(intel_dp->dpcd))
2666		return;
2667
2668	tmp = intel_dp->has_hdmi_sink ?
2669		DP_HDMI_DVI_OUTPUT_CONFIG : 0;
2670
2671	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2672			       DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
2673		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
2674			    str_enable_disable(intel_dp->has_hdmi_sink));
2675
2676	tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2677		intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
2678
2679	if (drm_dp_dpcd_writeb(&intel_dp->aux,
2680			       DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
2681		drm_dbg_kms(&i915->drm,
2682			    "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
2683			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
2684
2685	tmp = intel_dp->dfp.rgb_to_ycbcr ?
2686		DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
2687
2688	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
2689		drm_dbg_kms(&i915->drm,
2690			   "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
2691			   str_enable_disable(tmp));
2692}
2693
2694bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
2695{
2696	u8 dprx = 0;
2697
2698	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
2699			      &dprx) != 1)
2700		return false;
2701	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
2702}
2703
2704static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
2705{
2706	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2707
2708	/*
2709	 * Clear the cached register set to avoid using stale values
2710	 * for the sinks that do not support DSC.
2711	 */
2712	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
2713
2714	/* Clear fec_capable to avoid using stale values */
2715	intel_dp->fec_capable = 0;
2716
2717	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
2718	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
2719	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2720		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
2721				     intel_dp->dsc_dpcd,
2722				     sizeof(intel_dp->dsc_dpcd)) < 0)
2723			drm_err(&i915->drm,
2724				"Failed to read DPCD register 0x%x\n",
2725				DP_DSC_SUPPORT);
2726
2727		drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
2728			    (int)sizeof(intel_dp->dsc_dpcd),
2729			    intel_dp->dsc_dpcd);
2730
2731		/* FEC is supported only on DP 1.4 */
2732		if (!intel_dp_is_edp(intel_dp) &&
2733		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
2734				      &intel_dp->fec_capable) < 0)
2735			drm_err(&i915->drm,
2736				"Failed to read FEC DPCD register\n");
2737
2738		drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
2739			    intel_dp->fec_capable);
2740	}
2741}
2742
2743static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
2744				     struct drm_display_mode *mode)
2745{
2746	struct intel_dp *intel_dp = intel_attached_dp(connector);
2747	struct drm_i915_private *i915 = to_i915(connector->base.dev);
2748	int n = intel_dp->mso_link_count;
2749	int overlap = intel_dp->mso_pixel_overlap;
2750
2751	if (!mode || !n)
2752		return;
2753
2754	mode->hdisplay = (mode->hdisplay - overlap) * n;
2755	mode->hsync_start = (mode->hsync_start - overlap) * n;
2756	mode->hsync_end = (mode->hsync_end - overlap) * n;
2757	mode->htotal = (mode->htotal - overlap) * n;
2758	mode->clock *= n;
2759
2760	drm_mode_set_name(mode);
2761
2762	drm_dbg_kms(&i915->drm,
2763		    "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
2764		    connector->base.base.id, connector->base.name,
2765		    DRM_MODE_ARG(mode));
2766}
2767
2768void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
2769{
2770	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2771	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2772	struct intel_connector *connector = intel_dp->attached_connector;
2773
2774	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
2775		/*
2776		 * This is a big fat ugly hack.
2777		 *
2778		 * Some machines in UEFI boot mode provide us a VBT that has 18
2779		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2780		 * unknown we fail to light up. Yet the same BIOS boots up with
2781		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2782		 * max, not what it tells us to use.
2783		 *
2784		 * Note: This will still be broken if the eDP panel is not lit
2785		 * up by the BIOS, and thus we can't get the mode at module
2786		 * load.
2787		 */
2788		drm_dbg_kms(&dev_priv->drm,
2789			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2790			    pipe_bpp, connector->panel.vbt.edp.bpp);
2791		connector->panel.vbt.edp.bpp = pipe_bpp;
2792	}
2793}
2794
2795static void intel_edp_mso_init(struct intel_dp *intel_dp)
2796{
2797	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2798	struct intel_connector *connector = intel_dp->attached_connector;
2799	struct drm_display_info *info = &connector->base.display_info;
2800	u8 mso;
2801
2802	if (intel_dp->edp_dpcd[0] < DP_EDP_14)
2803		return;
2804
2805	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
2806		drm_err(&i915->drm, "Failed to read MSO cap\n");
2807		return;
2808	}
2809
2810	/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
2811	mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
2812	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
2813		drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
2814		mso = 0;
2815	}
2816
2817	if (mso) {
2818		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
2819			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
2820			    info->mso_pixel_overlap);
2821		if (!HAS_MSO(i915)) {
2822			drm_err(&i915->drm, "No source MSO support, disabling\n");
2823			mso = 0;
2824		}
2825	}
2826
2827	intel_dp->mso_link_count = mso;
2828	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
2829}
2830
2831static bool
2832intel_edp_init_dpcd(struct intel_dp *intel_dp)
2833{
2834	struct drm_i915_private *dev_priv =
2835		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
2836
2837	/* this function is meant to be called only once */
2838	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
2839
2840	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
2841		return false;
2842
2843	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2844			 drm_dp_is_branch(intel_dp->dpcd));
2845
2846	/*
2847	 * Read the eDP display control registers.
2848	 *
2849	 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
2850	 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
2851	 * set, but require eDP 1.4+ detection (e.g. for supported link rates
2852	 * method). The display control registers should read zero if they're
2853	 * not supported anyway.
2854	 */
2855	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
2856			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
2857			     sizeof(intel_dp->edp_dpcd)) {
2858		drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
2859			    (int)sizeof(intel_dp->edp_dpcd),
2860			    intel_dp->edp_dpcd);
2861
2862		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
2863	}
2864
2865	/*
2866	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
2867	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
2868	 */
2869	intel_psr_init_dpcd(intel_dp);
2870
2871	/* Clear the default sink rates */
2872	intel_dp->num_sink_rates = 0;
2873
2874	/* Read the eDP 1.4+ supported link rates. */
2875	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
2876		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
2877		int i;
2878
2879		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
2880				sink_rates, sizeof(sink_rates));
2881
2882		for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
2883			int val = le16_to_cpu(sink_rates[i]);
2884
2885			if (val == 0)
2886				break;
2887
2888			/* Value read multiplied by 200kHz gives the per-lane
2889			 * link rate in kHz. The source rates are, however,
2890			 * stored in terms of LS_Clk kHz. The full conversion
2891			 * back to symbols is
2892			 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
2893			 */
2894			intel_dp->sink_rates[i] = (val * 200) / 10;
2895		}
2896		intel_dp->num_sink_rates = i;
2897	}
2898
2899	/*
2900	 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
2901	 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
2902	 */
2903	if (intel_dp->num_sink_rates)
2904		intel_dp->use_rate_select = true;
2905	else
2906		intel_dp_set_sink_rates(intel_dp);
2907	intel_dp_set_max_sink_lane_count(intel_dp);
2908
2909	/* Read the eDP DSC DPCD registers */
2910	if (DISPLAY_VER(dev_priv) >= 10)
2911		intel_dp_get_dsc_sink_cap(intel_dp);
2912
2913	/*
2914	 * If needed, program our source OUI so we can make various Intel-specific AUX services
2915	 * available (such as HDR backlight controls)
2916	 */
2917	intel_edp_init_source_oui(intel_dp, true);
2918
2919	return true;
2920}
2921
2922static bool
2923intel_dp_has_sink_count(struct intel_dp *intel_dp)
2924{
2925	if (!intel_dp->attached_connector)
2926		return false;
2927
2928	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
2929					  intel_dp->dpcd,
2930					  &intel_dp->desc);
2931}
2932
2933static bool
2934intel_dp_get_dpcd(struct intel_dp *intel_dp)
2935{
2936	int ret;
2937
2938	if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
2939		return false;
2940
2941	/*
2942	 * Don't clobber cached eDP rates. Also skip re-reading
2943	 * the OUI/ID since we know it won't change.
2944	 */
2945	if (!intel_dp_is_edp(intel_dp)) {
2946		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
2947				 drm_dp_is_branch(intel_dp->dpcd));
2948
2949		intel_dp_set_sink_rates(intel_dp);
2950		intel_dp_set_max_sink_lane_count(intel_dp);
2951		intel_dp_set_common_rates(intel_dp);
2952	}
2953
2954	if (intel_dp_has_sink_count(intel_dp)) {
2955		ret = drm_dp_read_sink_count(&intel_dp->aux);
2956		if (ret < 0)
2957			return false;
2958
2959		/*
2960		 * Sink count can change between short pulse hpd hence
2961		 * a member variable in intel_dp will track any changes
2962		 * between short pulse interrupts.
2963		 */
2964		intel_dp->sink_count = ret;
2965
2966		/*
2967		 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
2968		 * a dongle is present but no display. Unless we require to know
2969		 * if a dongle is present or not, we don't need to update
2970		 * downstream port information. So, an early return here saves
2971		 * time from performing other operations which are not required.
2972		 */
2973		if (!intel_dp->sink_count)
2974			return false;
2975	}
2976
2977	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
2978					   intel_dp->downstream_ports) == 0;
2979}
2980
2981static bool
2982intel_dp_can_mst(struct intel_dp *intel_dp)
2983{
2984	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2985
2986	return i915->params.enable_dp_mst &&
2987		intel_dp_mst_source_support(intel_dp) &&
2988		drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2989}
2990
2991static void
2992intel_dp_configure_mst(struct intel_dp *intel_dp)
2993{
2994	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2995	struct intel_encoder *encoder =
2996		&dp_to_dig_port(intel_dp)->base;
2997	bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
2998
2999	drm_dbg_kms(&i915->drm,
3000		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3001		    encoder->base.base.id, encoder->base.name,
3002		    str_yes_no(intel_dp_mst_source_support(intel_dp)),
3003		    str_yes_no(sink_can_mst),
3004		    str_yes_no(i915->params.enable_dp_mst));
3005
3006	if (!intel_dp_mst_source_support(intel_dp))
3007		return;
3008
3009	intel_dp->is_mst = sink_can_mst &&
3010		i915->params.enable_dp_mst;
3011
3012	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3013					intel_dp->is_mst);
3014}
3015
3016static bool
3017intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3018{
3019	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3020}
3021
3022static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3023{
3024	int retry;
3025
3026	for (retry = 0; retry < 3; retry++) {
3027		if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3028				      &esi[1], 3) == 3)
3029			return true;
3030	}
3031
3032	return false;
3033}
3034
3035bool
3036intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3037		       const struct drm_connector_state *conn_state)
3038{
3039	/*
3040	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3041	 * of Color Encoding Format and Content Color Gamut], in order to
3042	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3043	 */
3044	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3045		return true;
3046
3047	switch (conn_state->colorspace) {
3048	case DRM_MODE_COLORIMETRY_SYCC_601:
3049	case DRM_MODE_COLORIMETRY_OPYCC_601:
3050	case DRM_MODE_COLORIMETRY_BT2020_YCC:
3051	case DRM_MODE_COLORIMETRY_BT2020_RGB:
3052	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3053		return true;
3054	default:
3055		break;
3056	}
3057
3058	return false;
3059}
3060
3061static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3062				     struct dp_sdp *sdp, size_t size)
3063{
3064	size_t length = sizeof(struct dp_sdp);
3065
3066	if (size < length)
3067		return -ENOSPC;
3068
3069	memset(sdp, 0, size);
3070
3071	/*
3072	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3073	 * VSC SDP Header Bytes
3074	 */
3075	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3076	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3077	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3078	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3079
3080	/*
3081	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3082	 * per DP 1.4a spec.
3083	 */
3084	if (vsc->revision != 0x5)
3085		goto out;
3086
3087	/* VSC SDP Payload for DB16 through DB18 */
3088	/* Pixel Encoding and Colorimetry Formats  */
3089	sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3090	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3091
3092	switch (vsc->bpc) {
3093	case 6:
3094		/* 6bpc: 0x0 */
3095		break;
3096	case 8:
3097		sdp->db[17] = 0x1; /* DB17[3:0] */
3098		break;
3099	case 10:
3100		sdp->db[17] = 0x2;
3101		break;
3102	case 12:
3103		sdp->db[17] = 0x3;
3104		break;
3105	case 16:
3106		sdp->db[17] = 0x4;
3107		break;
3108	default:
3109		MISSING_CASE(vsc->bpc);
3110		break;
3111	}
3112	/* Dynamic Range and Component Bit Depth */
3113	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3114		sdp->db[17] |= 0x80;  /* DB17[7] */
3115
3116	/* Content Type */
3117	sdp->db[18] = vsc->content_type & 0x7;
3118
3119out:
3120	return length;
3121}
3122
3123static ssize_t
3124intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3125					 const struct hdmi_drm_infoframe *drm_infoframe,
3126					 struct dp_sdp *sdp,
3127					 size_t size)
3128{
3129	size_t length = sizeof(struct dp_sdp);
3130	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3131	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3132	ssize_t len;
3133
3134	if (size < length)
3135		return -ENOSPC;
3136
3137	memset(sdp, 0, size);
3138
3139	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3140	if (len < 0) {
3141		drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3142		return -ENOSPC;
3143	}
3144
3145	if (len != infoframe_size) {
3146		drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3147		return -ENOSPC;
3148	}
3149
3150	/*
3151	 * Set up the infoframe sdp packet for HDR static metadata.
3152	 * Prepare VSC Header for SU as per DP 1.4a spec,
3153	 * Table 2-100 and Table 2-101
3154	 */
3155
3156	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3157	sdp->sdp_header.HB0 = 0;
3158	/*
3159	 * Packet Type 80h + Non-audio INFOFRAME Type value
3160	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
3161	 * - 80h + Non-audio INFOFRAME Type value
3162	 * - InfoFrame Type: 0x07
3163	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3164	 */
3165	sdp->sdp_header.HB1 = drm_infoframe->type;
3166	/*
3167	 * Least Significant Eight Bits of (Data Byte Count – 1)
3168	 * infoframe_size - 1
3169	 */
3170	sdp->sdp_header.HB2 = 0x1D;
3171	/* INFOFRAME SDP Version Number */
3172	sdp->sdp_header.HB3 = (0x13 << 2);
3173	/* CTA Header Byte 2 (INFOFRAME Version Number) */
3174	sdp->db[0] = drm_infoframe->version;
3175	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3176	sdp->db[1] = drm_infoframe->length;
3177	/*
3178	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3179	 * HDMI_INFOFRAME_HEADER_SIZE
3180	 */
3181	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3182	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3183	       HDMI_DRM_INFOFRAME_SIZE);
3184
3185	/*
3186	 * Size of DP infoframe sdp packet for HDR static metadata consists of
3187	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
3188	 * - Two Data Blocks: 2 bytes
3189	 *    CTA Header Byte2 (INFOFRAME Version Number)
3190	 *    CTA Header Byte3 (Length of INFOFRAME)
3191	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3192	 *
3193	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3194	 * infoframe size. But GEN11+ has larger than that size, write_infoframe
3195	 * will pad rest of the size.
3196	 */
3197	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3198}
3199
3200static void intel_write_dp_sdp(struct intel_encoder *encoder,
3201			       const struct intel_crtc_state *crtc_state,
3202			       unsigned int type)
3203{
3204	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3205	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3206	struct dp_sdp sdp = {};
3207	ssize_t len;
3208
3209	if ((crtc_state->infoframes.enable &
3210	     intel_hdmi_infoframe_enable(type)) == 0)
3211		return;
3212
3213	switch (type) {
3214	case DP_SDP_VSC:
3215		len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
3216					    sizeof(sdp));
3217		break;
3218	case HDMI_PACKET_TYPE_GAMUT_METADATA:
3219		len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
3220							       &crtc_state->infoframes.drm.drm,
3221							       &sdp, sizeof(sdp));
3222		break;
3223	default:
3224		MISSING_CASE(type);
3225		return;
3226	}
3227
3228	if (drm_WARN_ON(&dev_priv->drm, len < 0))
3229		return;
3230
3231	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
3232}
3233
3234void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
3235			    const struct intel_crtc_state *crtc_state,
3236			    const struct drm_dp_vsc_sdp *vsc)
3237{
3238	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3239	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3240	struct dp_sdp sdp = {};
3241	ssize_t len;
3242
3243	len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
3244
3245	if (drm_WARN_ON(&dev_priv->drm, len < 0))
3246		return;
3247
3248	dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
3249					&sdp, len);
3250}
3251
3252void intel_dp_set_infoframes(struct intel_encoder *encoder,
3253			     bool enable,
3254			     const struct intel_crtc_state *crtc_state,
3255			     const struct drm_connector_state *conn_state)
3256{
3257	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3258	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
3259	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
3260			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
3261			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
3262	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
3263
3264	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
3265	/* When PSR is enabled, this routine doesn't disable VSC DIP */
3266	if (!crtc_state->has_psr)
3267		val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
3268
3269	intel_de_write(dev_priv, reg, val);
3270	intel_de_posting_read(dev_priv, reg);
3271
3272	if (!enable)
3273		return;
3274
3275	/* When PSR is enabled, VSC SDP is handled by PSR routine */
3276	if (!crtc_state->has_psr)
3277		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
3278
3279	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
3280}
3281
3282static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
3283				   const void *buffer, size_t size)
3284{
3285	const struct dp_sdp *sdp = buffer;
3286
3287	if (size < sizeof(struct dp_sdp))
3288		return -EINVAL;
3289
3290	memset(vsc, 0, sizeof(*vsc));
3291
3292	if (sdp->sdp_header.HB0 != 0)
3293		return -EINVAL;
3294
3295	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
3296		return -EINVAL;
3297
3298	vsc->sdp_type = sdp->sdp_header.HB1;
3299	vsc->revision = sdp->sdp_header.HB2;
3300	vsc->length = sdp->sdp_header.HB3;
3301
3302	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
3303	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
3304		/*
3305		 * - HB2 = 0x2, HB3 = 0x8
3306		 *   VSC SDP supporting 3D stereo + PSR
3307		 * - HB2 = 0x4, HB3 = 0xe
3308		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
3309		 *   first scan line of the SU region (applies to eDP v1.4b
3310		 *   and higher).
3311		 */
3312		return 0;
3313	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
3314		/*
3315		 * - HB2 = 0x5, HB3 = 0x13
3316		 *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
3317		 *   Format.
3318		 */
3319		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
3320		vsc->colorimetry = sdp->db[16] & 0xf;
3321		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
3322
3323		switch (sdp->db[17] & 0x7) {
3324		case 0x0:
3325			vsc->bpc = 6;
3326			break;
3327		case 0x1:
3328			vsc->bpc = 8;
3329			break;
3330		case 0x2:
3331			vsc->bpc = 10;
3332			break;
3333		case 0x3:
3334			vsc->bpc = 12;
3335			break;
3336		case 0x4:
3337			vsc->bpc = 16;
3338			break;
3339		default:
3340			MISSING_CASE(sdp->db[17] & 0x7);
3341			return -EINVAL;
3342		}
3343
3344		vsc->content_type = sdp->db[18] & 0x7;
3345	} else {
3346		return -EINVAL;
3347	}
3348
3349	return 0;
3350}
3351
3352static int
3353intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
3354					   const void *buffer, size_t size)
3355{
3356	int ret;
3357
3358	const struct dp_sdp *sdp = buffer;
3359
3360	if (size < sizeof(struct dp_sdp))
3361		return -EINVAL;
3362
3363	if (sdp->sdp_header.HB0 != 0)
3364		return -EINVAL;
3365
3366	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
3367		return -EINVAL;
3368
3369	/*
3370	 * Least Significant Eight Bits of (Data Byte Count – 1)
3371	 * 1Dh (i.e., Data Byte Count = 30 bytes).
3372	 */
3373	if (sdp->sdp_header.HB2 != 0x1D)
3374		return -EINVAL;
3375
3376	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
3377	if ((sdp->sdp_header.HB3 & 0x3) != 0)
3378		return -EINVAL;
3379
3380	/* INFOFRAME SDP Version Number */
3381	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
3382		return -EINVAL;
3383
3384	/* CTA Header Byte 2 (INFOFRAME Version Number) */
3385	if (sdp->db[0] != 1)
3386		return -EINVAL;
3387
3388	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3389	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
3390		return -EINVAL;
3391
3392	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
3393					     HDMI_DRM_INFOFRAME_SIZE);
3394
3395	return ret;
3396}
3397
3398static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
3399				  struct intel_crtc_state *crtc_state,
3400				  struct drm_dp_vsc_sdp *vsc)
3401{
3402	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3403	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3404	unsigned int type = DP_SDP_VSC;
3405	struct dp_sdp sdp = {};
3406	int ret;
3407
3408	/* When PSR is enabled, VSC SDP is handled by PSR routine */
3409	if (crtc_state->has_psr)
3410		return;
3411
3412	if ((crtc_state->infoframes.enable &
3413	     intel_hdmi_infoframe_enable(type)) == 0)
3414		return;
3415
3416	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
3417
3418	ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
3419
3420	if (ret)
3421		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
3422}
3423
3424static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
3425						     struct intel_crtc_state *crtc_state,
3426						     struct hdmi_drm_infoframe *drm_infoframe)
3427{
3428	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3429	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3430	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
3431	struct dp_sdp sdp = {};
3432	int ret;
3433
3434	if ((crtc_state->infoframes.enable &
3435	    intel_hdmi_infoframe_enable(type)) == 0)
3436		return;
3437
3438	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
3439				 sizeof(sdp));
3440
3441	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
3442							 sizeof(sdp));
3443
3444	if (ret)
3445		drm_dbg_kms(&dev_priv->drm,
3446			    "Failed to unpack DP HDR Metadata Infoframe SDP\n");
3447}
3448
3449void intel_read_dp_sdp(struct intel_encoder *encoder,
3450		       struct intel_crtc_state *crtc_state,
3451		       unsigned int type)
3452{
3453	switch (type) {
3454	case DP_SDP_VSC:
3455		intel_read_dp_vsc_sdp(encoder, crtc_state,
3456				      &crtc_state->infoframes.vsc);
3457		break;
3458	case HDMI_PACKET_TYPE_GAMUT_METADATA:
3459		intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
3460							 &crtc_state->infoframes.drm.drm);
3461		break;
3462	default:
3463		MISSING_CASE(type);
3464		break;
3465	}
3466}
3467
3468static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3469{
3470	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3471	int status = 0;
3472	int test_link_rate;
3473	u8 test_lane_count, test_link_bw;
3474	/* (DP CTS 1.2)
3475	 * 4.3.1.11
3476	 */
3477	/* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3478	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3479				   &test_lane_count);
3480
3481	if (status <= 0) {
3482		drm_dbg_kms(&i915->drm, "Lane count read failed\n");
3483		return DP_TEST_NAK;
3484	}
3485	test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3486
3487	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3488				   &test_link_bw);
3489	if (status <= 0) {
3490		drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
3491		return DP_TEST_NAK;
3492	}
3493	test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3494
3495	/* Validate the requested link rate and lane count */
3496	if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3497					test_lane_count))
3498		return DP_TEST_NAK;
3499
3500	intel_dp->compliance.test_lane_count = test_lane_count;
3501	intel_dp->compliance.test_link_rate = test_link_rate;
3502
3503	return DP_TEST_ACK;
3504}
3505
3506static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3507{
3508	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3509	u8 test_pattern;
3510	u8 test_misc;
3511	__be16 h_width, v_height;
3512	int status = 0;
3513
3514	/* Read the TEST_PATTERN (DP CTS 3.1.5) */
3515	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3516				   &test_pattern);
3517	if (status <= 0) {
3518		drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
3519		return DP_TEST_NAK;
3520	}
3521	if (test_pattern != DP_COLOR_RAMP)
3522		return DP_TEST_NAK;
3523
3524	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3525				  &h_width, 2);
3526	if (status <= 0) {
3527		drm_dbg_kms(&i915->drm, "H Width read failed\n");
3528		return DP_TEST_NAK;
3529	}
3530
3531	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3532				  &v_height, 2);
3533	if (status <= 0) {
3534		drm_dbg_kms(&i915->drm, "V Height read failed\n");
3535		return DP_TEST_NAK;
3536	}
3537
3538	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3539				   &test_misc);
3540	if (status <= 0) {
3541		drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
3542		return DP_TEST_NAK;
3543	}
3544	if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3545		return DP_TEST_NAK;
3546	if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3547		return DP_TEST_NAK;
3548	switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
3549	case DP_TEST_BIT_DEPTH_6:
3550		intel_dp->compliance.test_data.bpc = 6;
3551		break;
3552	case DP_TEST_BIT_DEPTH_8:
3553		intel_dp->compliance.test_data.bpc = 8;
3554		break;
3555	default:
3556		return DP_TEST_NAK;
3557	}
3558
3559	intel_dp->compliance.test_data.video_pattern = test_pattern;
3560	intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
3561	intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
3562	/* Set test active flag here so userspace doesn't interrupt things */
3563	intel_dp->compliance.test_active = true;
3564
3565	return DP_TEST_ACK;
3566}
3567
3568static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
3569{
3570	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3571	u8 test_result = DP_TEST_ACK;
3572	struct intel_connector *intel_connector = intel_dp->attached_connector;
3573	struct drm_connector *connector = &intel_connector->base;
3574
3575	if (intel_connector->detect_edid == NULL ||
3576	    connector->edid_corrupt ||
3577	    intel_dp->aux.i2c_defer_count > 6) {
3578		/* Check EDID read for NACKs, DEFERs and corruption
3579		 * (DP CTS 1.2 Core r1.1)
3580		 *    4.2.2.4 : Failed EDID read, I2C_NAK
3581		 *    4.2.2.5 : Failed EDID read, I2C_DEFER
3582		 *    4.2.2.6 : EDID corruption detected
3583		 * Use failsafe mode for all cases
3584		 */
3585		if (intel_dp->aux.i2c_nack_count > 0 ||
3586			intel_dp->aux.i2c_defer_count > 0)
3587			drm_dbg_kms(&i915->drm,
3588				    "EDID read had %d NACKs, %d DEFERs\n",
3589				    intel_dp->aux.i2c_nack_count,
3590				    intel_dp->aux.i2c_defer_count);
3591		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
3592	} else {
3593		struct edid *block = intel_connector->detect_edid;
3594
3595		/* We have to write the checksum
3596		 * of the last block read
3597		 */
3598		block += intel_connector->detect_edid->extensions;
3599
3600		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
3601				       block->checksum) <= 0)
3602			drm_dbg_kms(&i915->drm,
3603				    "Failed to write EDID checksum\n");
3604
3605		test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3606		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
3607	}
3608
3609	/* Set test active flag here so userspace doesn't interrupt things */
3610	intel_dp->compliance.test_active = true;
3611
3612	return test_result;
3613}
3614
3615static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
3616					const struct intel_crtc_state *crtc_state)
3617{
3618	struct drm_i915_private *dev_priv =
3619			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3620	struct drm_dp_phy_test_params *data =
3621			&intel_dp->compliance.test_data.phytest;
3622	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3623	enum pipe pipe = crtc->pipe;
3624	u32 pattern_val;
3625
3626	switch (data->phy_pattern) {
3627	case DP_PHY_TEST_PATTERN_NONE:
3628		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
3629		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
3630		break;
3631	case DP_PHY_TEST_PATTERN_D10_2:
3632		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
3633		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3634			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
3635		break;
3636	case DP_PHY_TEST_PATTERN_ERROR_COUNT:
3637		drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
3638		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3639			       DDI_DP_COMP_CTL_ENABLE |
3640			       DDI_DP_COMP_CTL_SCRAMBLED_0);
3641		break;
3642	case DP_PHY_TEST_PATTERN_PRBS7:
3643		drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
3644		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3645			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
3646		break;
3647	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3648		/*
3649		 * FIXME: Ideally pattern should come from DPCD 0x250. As
3650		 * current firmware of DPR-100 could not set it, so hardcoding
3651		 * now for complaince test.
3652		 */
3653		drm_dbg_kms(&dev_priv->drm,
3654			    "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
3655		pattern_val = 0x3e0f83e0;
3656		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
3657		pattern_val = 0x0f83e0f8;
3658		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
3659		pattern_val = 0x0000f83e;
3660		intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
3661		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3662			       DDI_DP_COMP_CTL_ENABLE |
3663			       DDI_DP_COMP_CTL_CUSTOM80);
3664		break;
3665	case DP_PHY_TEST_PATTERN_CP2520:
3666		/*
3667		 * FIXME: Ideally pattern should come from DPCD 0x24A. As
3668		 * current firmware of DPR-100 could not set it, so hardcoding
3669		 * now for complaince test.
3670		 */
3671		drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
3672		pattern_val = 0xFB;
3673		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
3674			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
3675			       pattern_val);
3676		break;
3677	default:
3678		WARN(1, "Invalid Phy Test Pattern\n");
3679	}
3680}
3681
3682static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
3683					 const struct intel_crtc_state *crtc_state)
3684{
3685	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3686	struct drm_dp_phy_test_params *data =
3687		&intel_dp->compliance.test_data.phytest;
3688	u8 link_status[DP_LINK_STATUS_SIZE];
3689
3690	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3691					     link_status) < 0) {
3692		drm_dbg_kms(&i915->drm, "failed to get link status\n");
3693		return;
3694	}
3695
3696	/* retrieve vswing & pre-emphasis setting */
3697	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
3698				  link_status);
3699
3700	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
3701
3702	intel_dp_phy_pattern_update(intel_dp, crtc_state);
3703
3704	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3705			  intel_dp->train_set, crtc_state->lane_count);
3706
3707	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
3708				    link_status[DP_DPCD_REV]);
3709}
3710
3711static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3712{
3713	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3714	struct drm_dp_phy_test_params *data =
3715		&intel_dp->compliance.test_data.phytest;
3716
3717	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
3718		drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
3719		return DP_TEST_NAK;
3720	}
3721
3722	/* Set test active flag here so userspace doesn't interrupt things */
3723	intel_dp->compliance.test_active = true;
3724
3725	return DP_TEST_ACK;
3726}
3727
3728static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3729{
3730	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3731	u8 response = DP_TEST_NAK;
3732	u8 request = 0;
3733	int status;
3734
3735	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
3736	if (status <= 0) {
3737		drm_dbg_kms(&i915->drm,
3738			    "Could not read test request from sink\n");
3739		goto update_status;
3740	}
3741
3742	switch (request) {
3743	case DP_TEST_LINK_TRAINING:
3744		drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
3745		response = intel_dp_autotest_link_training(intel_dp);
3746		break;
3747	case DP_TEST_LINK_VIDEO_PATTERN:
3748		drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
3749		response = intel_dp_autotest_video_pattern(intel_dp);
3750		break;
3751	case DP_TEST_LINK_EDID_READ:
3752		drm_dbg_kms(&i915->drm, "EDID test requested\n");
3753		response = intel_dp_autotest_edid(intel_dp);
3754		break;
3755	case DP_TEST_LINK_PHY_TEST_PATTERN:
3756		drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
3757		response = intel_dp_autotest_phy_pattern(intel_dp);
3758		break;
3759	default:
3760		drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
3761			    request);
3762		break;
3763	}
3764
3765	if (response & DP_TEST_ACK)
3766		intel_dp->compliance.test_type = request;
3767
3768update_status:
3769	status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
3770	if (status <= 0)
3771		drm_dbg_kms(&i915->drm,
3772			    "Could not write test response to sink\n");
3773}
3774
3775static bool intel_dp_link_ok(struct intel_dp *intel_dp,
3776			     u8 link_status[DP_LINK_STATUS_SIZE])
3777{
3778	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3779	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3780	bool uhbr = intel_dp->link_rate >= 1000000;
3781	bool ok;
3782
3783	if (uhbr)
3784		ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
3785							  intel_dp->lane_count);
3786	else
3787		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
3788
3789	if (ok)
3790		return true;
3791
3792	intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
3793	drm_dbg_kms(&i915->drm,
3794		    "[ENCODER:%d:%s] %s link not ok, retraining\n",
3795		    encoder->base.base.id, encoder->base.name,
3796		    uhbr ? "128b/132b" : "8b/10b");
3797
3798	return false;
3799}
3800
3801static void
3802intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
3803{
3804	bool handled = false;
3805
3806	drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3807	if (handled)
3808		ack[1] |= esi[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
3809
3810	if (esi[1] & DP_CP_IRQ) {
3811		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
3812		ack[1] |= DP_CP_IRQ;
3813	}
3814}
3815
3816static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
3817{
3818	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3819	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3820	u8 link_status[DP_LINK_STATUS_SIZE] = {};
3821	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
3822
3823	if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
3824			     esi_link_status_size) != esi_link_status_size) {
3825		drm_err(&i915->drm,
3826			"[ENCODER:%d:%s] Failed to read link status\n",
3827			encoder->base.base.id, encoder->base.name);
3828		return false;
3829	}
3830
3831	return intel_dp_link_ok(intel_dp, link_status);
3832}
3833
3834/**
3835 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
3836 * @intel_dp: Intel DP struct
3837 *
3838 * Read any pending MST interrupts, call MST core to handle these and ack the
3839 * interrupts. Check if the main and AUX link state is ok.
3840 *
3841 * Returns:
3842 * - %true if pending interrupts were serviced (or no interrupts were
3843 *   pending) w/o detecting an error condition.
3844 * - %false if an error condition - like AUX failure or a loss of link - is
3845 *   detected, which needs servicing from the hotplug work.
3846 */
3847static bool
3848intel_dp_check_mst_status(struct intel_dp *intel_dp)
3849{
3850	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3851	bool link_ok = true;
3852
3853	drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
3854
3855	for (;;) {
3856		u8 esi[4] = {};
3857		u8 ack[4] = {};
3858
3859		if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
3860			drm_dbg_kms(&i915->drm,
3861				    "failed to get ESI - device may have failed\n");
3862			link_ok = false;
3863
3864			break;
3865		}
3866
3867		drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
3868
3869		if (intel_dp->active_mst_links > 0 && link_ok &&
3870		    esi[3] & LINK_STATUS_CHANGED) {
3871			if (!intel_dp_mst_link_status(intel_dp))
3872				link_ok = false;
3873			ack[3] |= LINK_STATUS_CHANGED;
3874		}
3875
3876		intel_dp_mst_hpd_irq(intel_dp, esi, ack);
3877
3878		if (!memchr_inv(ack, 0, sizeof(ack)))
3879			break;
3880
3881		if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
3882			drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
3883	}
3884
3885	return link_ok;
3886}
3887
3888static void
3889intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
3890{
3891	bool is_active;
3892	u8 buf = 0;
3893
3894	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
3895	if (intel_dp->frl.is_trained && !is_active) {
3896		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
3897			return;
3898
3899		buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
3900		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
3901			return;
3902
3903		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
3904
3905		intel_dp->frl.is_trained = false;
3906
3907		/* Restart FRL training or fall back to TMDS mode */
3908		intel_dp_check_frl_training(intel_dp);
3909	}
3910}
3911
3912static bool
3913intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
3914{
3915	u8 link_status[DP_LINK_STATUS_SIZE];
3916
3917	if (!intel_dp->link_trained)
3918		return false;
3919
3920	/*
3921	 * While PSR source HW is enabled, it will control main-link sending
3922	 * frames, enabling and disabling it so trying to do a retrain will fail
3923	 * as the link would or not be on or it could mix training patterns
3924	 * and frame data at the same time causing retrain to fail.
3925	 * Also when exiting PSR, HW will retrain the link anyways fixing
3926	 * any link status error.
3927	 */
3928	if (intel_psr_enabled(intel_dp))
3929		return false;
3930
3931	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
3932					     link_status) < 0)
3933		return false;
3934
3935	/*
3936	 * Validate the cached values of intel_dp->link_rate and
3937	 * intel_dp->lane_count before attempting to retrain.
3938	 *
3939	 * FIXME would be nice to user the crtc state here, but since
3940	 * we need to call this from the short HPD handler that seems
3941	 * a bit hard.
3942	 */
3943	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
3944					intel_dp->lane_count))
3945		return false;
3946
3947	/* Retrain if link not ok */
3948	return !intel_dp_link_ok(intel_dp, link_status);
3949}
3950
3951static bool intel_dp_has_connector(struct intel_dp *intel_dp,
3952				   const struct drm_connector_state *conn_state)
3953{
3954	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3955	struct intel_encoder *encoder;
3956	enum pipe pipe;
3957
3958	if (!conn_state->best_encoder)
3959		return false;
3960
3961	/* SST */
3962	encoder = &dp_to_dig_port(intel_dp)->base;
3963	if (conn_state->best_encoder == &encoder->base)
3964		return true;
3965
3966	/* MST */
3967	for_each_pipe(i915, pipe) {
3968		encoder = &intel_dp->mst_encoders[pipe]->base;
3969		if (conn_state->best_encoder == &encoder->base)
3970			return true;
3971	}
3972
3973	return false;
3974}
3975
3976static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
3977				      struct drm_modeset_acquire_ctx *ctx,
3978				      u8 *pipe_mask)
3979{
3980	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3981	struct drm_connector_list_iter conn_iter;
3982	struct intel_connector *connector;
3983	int ret = 0;
3984
3985	*pipe_mask = 0;
3986
3987	if (!intel_dp_needs_link_retrain(intel_dp))
3988		return 0;
3989
3990	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
3991	for_each_intel_connector_iter(connector, &conn_iter) {
3992		struct drm_connector_state *conn_state =
3993			connector->base.state;
3994		struct intel_crtc_state *crtc_state;
3995		struct intel_crtc *crtc;
3996
3997		if (!intel_dp_has_connector(intel_dp, conn_state))
3998			continue;
3999
4000		crtc = to_intel_crtc(conn_state->crtc);
4001		if (!crtc)
4002			continue;
4003
4004		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4005		if (ret)
4006			break;
4007
4008		crtc_state = to_intel_crtc_state(crtc->base.state);
4009
4010		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4011
4012		if (!crtc_state->hw.active)
4013			continue;
4014
4015		if (conn_state->commit &&
4016		    !try_wait_for_completion(&conn_state->commit->hw_done))
4017			continue;
4018
4019		*pipe_mask |= BIT(crtc->pipe);
4020	}
4021	drm_connector_list_iter_end(&conn_iter);
4022
4023	if (!intel_dp_needs_link_retrain(intel_dp))
4024		*pipe_mask = 0;
4025
4026	return ret;
4027}
4028
4029static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4030{
4031	struct intel_connector *connector = intel_dp->attached_connector;
4032
4033	return connector->base.status == connector_status_connected ||
4034		intel_dp->is_mst;
4035}
4036
4037int intel_dp_retrain_link(struct intel_encoder *encoder,
4038			  struct drm_modeset_acquire_ctx *ctx)
4039{
4040	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4041	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4042	struct intel_crtc *crtc;
4043	u8 pipe_mask;
4044	int ret;
4045
4046	if (!intel_dp_is_connected(intel_dp))
4047		return 0;
4048
4049	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4050			       ctx);
4051	if (ret)
4052		return ret;
4053
4054	ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask);
4055	if (ret)
4056		return ret;
4057
4058	if (pipe_mask == 0)
4059		return 0;
4060
4061	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4062		    encoder->base.base.id, encoder->base.name);
4063
4064	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4065		const struct intel_crtc_state *crtc_state =
4066			to_intel_crtc_state(crtc->base.state);
4067
4068		/* Suppress underruns caused by re-training */
4069		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4070		if (crtc_state->has_pch_encoder)
4071			intel_set_pch_fifo_underrun_reporting(dev_priv,
4072							      intel_crtc_pch_transcoder(crtc), false);
4073	}
4074
4075	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4076		const struct intel_crtc_state *crtc_state =
4077			to_intel_crtc_state(crtc->base.state);
4078
4079		/* retrain on the MST master transcoder */
4080		if (DISPLAY_VER(dev_priv) >= 12 &&
4081		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4082		    !intel_dp_mst_is_master_trans(crtc_state))
4083			continue;
4084
4085		intel_dp_check_frl_training(intel_dp);
4086		intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4087		intel_dp_start_link_train(intel_dp, crtc_state);
4088		intel_dp_stop_link_train(intel_dp, crtc_state);
4089		break;
4090	}
4091
4092	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4093		const struct intel_crtc_state *crtc_state =
4094			to_intel_crtc_state(crtc->base.state);
4095
4096		/* Keep underrun reporting disabled until things are stable */
4097		intel_crtc_wait_for_next_vblank(crtc);
4098
4099		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4100		if (crtc_state->has_pch_encoder)
4101			intel_set_pch_fifo_underrun_reporting(dev_priv,
4102							      intel_crtc_pch_transcoder(crtc), true);
4103	}
4104
4105	return 0;
4106}
4107
4108static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4109				  struct drm_modeset_acquire_ctx *ctx,
4110				  u8 *pipe_mask)
4111{
4112	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4113	struct drm_connector_list_iter conn_iter;
4114	struct intel_connector *connector;
4115	int ret = 0;
4116
4117	*pipe_mask = 0;
4118
4119	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4120	for_each_intel_connector_iter(connector, &conn_iter) {
4121		struct drm_connector_state *conn_state =
4122			connector->base.state;
4123		struct intel_crtc_state *crtc_state;
4124		struct intel_crtc *crtc;
4125
4126		if (!intel_dp_has_connector(intel_dp, conn_state))
4127			continue;
4128
4129		crtc = to_intel_crtc(conn_state->crtc);
4130		if (!crtc)
4131			continue;
4132
4133		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4134		if (ret)
4135			break;
4136
4137		crtc_state = to_intel_crtc_state(crtc->base.state);
4138
4139		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4140
4141		if (!crtc_state->hw.active)
4142			continue;
4143
4144		if (conn_state->commit &&
4145		    !try_wait_for_completion(&conn_state->commit->hw_done))
4146			continue;
4147
4148		*pipe_mask |= BIT(crtc->pipe);
4149	}
4150	drm_connector_list_iter_end(&conn_iter);
4151
4152	return ret;
4153}
4154
4155static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4156				struct drm_modeset_acquire_ctx *ctx)
4157{
4158	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4159	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4160	struct intel_crtc *crtc;
4161	u8 pipe_mask;
4162	int ret;
4163
4164	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4165			       ctx);
4166	if (ret)
4167		return ret;
4168
4169	ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4170	if (ret)
4171		return ret;
4172
4173	if (pipe_mask == 0)
4174		return 0;
4175
4176	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4177		    encoder->base.base.id, encoder->base.name);
4178
4179	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4180		const struct intel_crtc_state *crtc_state =
4181			to_intel_crtc_state(crtc->base.state);
4182
4183		/* test on the MST master transcoder */
4184		if (DISPLAY_VER(dev_priv) >= 12 &&
4185		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4186		    !intel_dp_mst_is_master_trans(crtc_state))
4187			continue;
4188
4189		intel_dp_process_phy_request(intel_dp, crtc_state);
4190		break;
4191	}
4192
4193	return 0;
4194}
4195
4196void intel_dp_phy_test(struct intel_encoder *encoder)
4197{
4198	struct drm_modeset_acquire_ctx ctx;
4199	int ret;
4200
4201	drm_modeset_acquire_init(&ctx, 0);
4202
4203	for (;;) {
4204		ret = intel_dp_do_phy_test(encoder, &ctx);
4205
4206		if (ret == -EDEADLK) {
4207			drm_modeset_backoff(&ctx);
4208			continue;
4209		}
4210
4211		break;
4212	}
4213
4214	drm_modeset_drop_locks(&ctx);
4215	drm_modeset_acquire_fini(&ctx);
4216	drm_WARN(encoder->base.dev, ret,
4217		 "Acquiring modeset locks failed with %i\n", ret);
4218}
4219
4220static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
4221{
4222	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4223	u8 val;
4224
4225	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4226		return;
4227
4228	if (drm_dp_dpcd_readb(&intel_dp->aux,
4229			      DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4230		return;
4231
4232	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4233
4234	if (val & DP_AUTOMATED_TEST_REQUEST)
4235		intel_dp_handle_test_request(intel_dp);
4236
4237	if (val & DP_CP_IRQ)
4238		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4239
4240	if (val & DP_SINK_SPECIFIC_IRQ)
4241		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
4242}
4243
4244static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
4245{
4246	u8 val;
4247
4248	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4249		return;
4250
4251	if (drm_dp_dpcd_readb(&intel_dp->aux,
4252			      DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
4253		return;
4254
4255	if (drm_dp_dpcd_writeb(&intel_dp->aux,
4256			       DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
4257		return;
4258
4259	if (val & HDMI_LINK_STATUS_CHANGED)
4260		intel_dp_handle_hdmi_link_status_change(intel_dp);
4261}
4262
4263/*
4264 * According to DP spec
4265 * 5.1.2:
4266 *  1. Read DPCD
4267 *  2. Configure link according to Receiver Capabilities
4268 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4269 *  4. Check link status on receipt of hot-plug interrupt
4270 *
4271 * intel_dp_short_pulse -  handles short pulse interrupts
4272 * when full detection is not required.
4273 * Returns %true if short pulse is handled and full detection
4274 * is NOT required and %false otherwise.
4275 */
4276static bool
4277intel_dp_short_pulse(struct intel_dp *intel_dp)
4278{
4279	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4280	u8 old_sink_count = intel_dp->sink_count;
4281	bool ret;
4282
4283	/*
4284	 * Clearing compliance test variables to allow capturing
4285	 * of values for next automated test request.
4286	 */
4287	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4288
4289	/*
4290	 * Now read the DPCD to see if it's actually running
4291	 * If the current value of sink count doesn't match with
4292	 * the value that was stored earlier or dpcd read failed
4293	 * we need to do full detection
4294	 */
4295	ret = intel_dp_get_dpcd(intel_dp);
4296
4297	if ((old_sink_count != intel_dp->sink_count) || !ret) {
4298		/* No need to proceed if we are going to do full detect */
4299		return false;
4300	}
4301
4302	intel_dp_check_device_service_irq(intel_dp);
4303	intel_dp_check_link_service_irq(intel_dp);
4304
4305	/* Handle CEC interrupts, if any */
4306	drm_dp_cec_irq(&intel_dp->aux);
4307
4308	/* defer to the hotplug work for link retraining if needed */
4309	if (intel_dp_needs_link_retrain(intel_dp))
4310		return false;
4311
4312	intel_psr_short_pulse(intel_dp);
4313
4314	switch (intel_dp->compliance.test_type) {
4315	case DP_TEST_LINK_TRAINING:
4316		drm_dbg_kms(&dev_priv->drm,
4317			    "Link Training Compliance Test requested\n");
4318		/* Send a Hotplug Uevent to userspace to start modeset */
4319		drm_kms_helper_hotplug_event(&dev_priv->drm);
4320		break;
4321	case DP_TEST_LINK_PHY_TEST_PATTERN:
4322		drm_dbg_kms(&dev_priv->drm,
4323			    "PHY test pattern Compliance Test requested\n");
4324		/*
4325		 * Schedule long hpd to do the test
4326		 *
4327		 * FIXME get rid of the ad-hoc phy test modeset code
4328		 * and properly incorporate it into the normal modeset.
4329		 */
4330		return false;
4331	}
4332
4333	return true;
4334}
4335
4336/* XXX this is probably wrong for multiple downstream ports */
4337static enum drm_connector_status
4338intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4339{
4340	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4341	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4342	u8 *dpcd = intel_dp->dpcd;
4343	u8 type;
4344
4345	if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
4346		return connector_status_connected;
4347
4348	lspcon_resume(dig_port);
4349
4350	if (!intel_dp_get_dpcd(intel_dp))
4351		return connector_status_disconnected;
4352
4353	/* if there's no downstream port, we're done */
4354	if (!drm_dp_is_branch(dpcd))
4355		return connector_status_connected;
4356
4357	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4358	if (intel_dp_has_sink_count(intel_dp) &&
4359	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4360		return intel_dp->sink_count ?
4361		connector_status_connected : connector_status_disconnected;
4362	}
4363
4364	if (intel_dp_can_mst(intel_dp))
4365		return connector_status_connected;
4366
4367	/* If no HPD, poke DDC gently */
4368	if (drm_probe_ddc(&intel_dp->aux.ddc))
4369		return connector_status_connected;
4370
4371	/* Well we tried, say unknown for unreliable port types */
4372	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4373		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4374		if (type == DP_DS_PORT_TYPE_VGA ||
4375		    type == DP_DS_PORT_TYPE_NON_EDID)
4376			return connector_status_unknown;
4377	} else {
4378		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4379			DP_DWN_STRM_PORT_TYPE_MASK;
4380		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4381		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
4382			return connector_status_unknown;
4383	}
4384
4385	/* Anything else is out of spec, warn and ignore */
4386	drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
4387	return connector_status_disconnected;
4388}
4389
4390static enum drm_connector_status
4391edp_detect(struct intel_dp *intel_dp)
4392{
4393	return connector_status_connected;
4394}
4395
4396/*
4397 * intel_digital_port_connected - is the specified port connected?
4398 * @encoder: intel_encoder
4399 *
4400 * In cases where there's a connector physically connected but it can't be used
4401 * by our hardware we also return false, since the rest of the driver should
4402 * pretty much treat the port as disconnected. This is relevant for type-C
4403 * (starting on ICL) where there's ownership involved.
4404 *
4405 * Return %true if port is connected, %false otherwise.
4406 */
4407bool intel_digital_port_connected(struct intel_encoder *encoder)
4408{
4409	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4410	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4411	bool is_connected = false;
4412	intel_wakeref_t wakeref;
4413
4414	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
4415		is_connected = dig_port->connected(encoder);
4416
4417	return is_connected;
4418}
4419
4420static struct edid *
4421intel_dp_get_edid(struct intel_dp *intel_dp)
4422{
4423	struct intel_connector *intel_connector = intel_dp->attached_connector;
4424
4425	/* use cached edid if we have one */
4426	if (intel_connector->edid) {
4427		/* invalid edid */
4428		if (IS_ERR(intel_connector->edid))
4429			return NULL;
4430
4431		return drm_edid_duplicate(intel_connector->edid);
4432	} else
4433		return drm_get_edid(&intel_connector->base,
4434				    &intel_dp->aux.ddc);
4435}
4436
4437static void
4438intel_dp_update_dfp(struct intel_dp *intel_dp,
4439		    const struct edid *edid)
4440{
4441	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4442	struct intel_connector *connector = intel_dp->attached_connector;
4443
4444	intel_dp->dfp.max_bpc =
4445		drm_dp_downstream_max_bpc(intel_dp->dpcd,
4446					  intel_dp->downstream_ports, edid);
4447
4448	intel_dp->dfp.max_dotclock =
4449		drm_dp_downstream_max_dotclock(intel_dp->dpcd,
4450					       intel_dp->downstream_ports);
4451
4452	intel_dp->dfp.min_tmds_clock =
4453		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
4454						 intel_dp->downstream_ports,
4455						 edid);
4456	intel_dp->dfp.max_tmds_clock =
4457		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
4458						 intel_dp->downstream_ports,
4459						 edid);
4460
4461	intel_dp->dfp.pcon_max_frl_bw =
4462		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
4463					   intel_dp->downstream_ports);
4464
4465	drm_dbg_kms(&i915->drm,
4466		    "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
4467		    connector->base.base.id, connector->base.name,
4468		    intel_dp->dfp.max_bpc,
4469		    intel_dp->dfp.max_dotclock,
4470		    intel_dp->dfp.min_tmds_clock,
4471		    intel_dp->dfp.max_tmds_clock,
4472		    intel_dp->dfp.pcon_max_frl_bw);
4473
4474	intel_dp_get_pcon_dsc_cap(intel_dp);
4475}
4476
4477static void
4478intel_dp_update_420(struct intel_dp *intel_dp)
4479{
4480	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4481	struct intel_connector *connector = intel_dp->attached_connector;
4482	bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
4483
4484	/* No YCbCr output support on gmch platforms */
4485	if (HAS_GMCH(i915))
4486		return;
4487
4488	/*
4489	 * ILK doesn't seem capable of DP YCbCr output. The
4490	 * displayed image is severly corrupted. SNB+ is fine.
4491	 */
4492	if (IS_IRONLAKE(i915))
4493		return;
4494
4495	is_branch = drm_dp_is_branch(intel_dp->dpcd);
4496	ycbcr_420_passthrough =
4497		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
4498						  intel_dp->downstream_ports);
4499	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
4500	ycbcr_444_to_420 =
4501		dp_to_dig_port(intel_dp)->lspcon.active ||
4502		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
4503							intel_dp->downstream_ports);
4504	rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
4505								 intel_dp->downstream_ports,
4506								 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
4507
4508	if (DISPLAY_VER(i915) >= 11) {
4509		/* Let PCON convert from RGB->YCbCr if possible */
4510		if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
4511			intel_dp->dfp.rgb_to_ycbcr = true;
4512			intel_dp->dfp.ycbcr_444_to_420 = true;
4513			connector->base.ycbcr_420_allowed = true;
4514		} else {
4515		/* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
4516			intel_dp->dfp.ycbcr_444_to_420 =
4517				ycbcr_444_to_420 && !ycbcr_420_passthrough;
4518
4519			connector->base.ycbcr_420_allowed =
4520				!is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
4521		}
4522	} else {
4523		/* 4:4:4->4:2:0 conversion is the only way */
4524		intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
4525
4526		connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
4527	}
4528
4529	drm_dbg_kms(&i915->drm,
4530		    "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
4531		    connector->base.base.id, connector->base.name,
4532		    str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
4533		    str_yes_no(connector->base.ycbcr_420_allowed),
4534		    str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
4535}
4536
4537static void
4538intel_dp_set_edid(struct intel_dp *intel_dp)
4539{
4540	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4541	struct intel_connector *connector = intel_dp->attached_connector;
4542	struct edid *edid;
4543	bool vrr_capable;
4544
4545	intel_dp_unset_edid(intel_dp);
4546	edid = intel_dp_get_edid(intel_dp);
4547	connector->detect_edid = edid;
4548
4549	vrr_capable = intel_vrr_is_capable(connector);
4550	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
4551		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
4552	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
4553
4554	intel_dp_update_dfp(intel_dp, edid);
4555	intel_dp_update_420(intel_dp);
4556
4557	if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
4558		intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
4559		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4560	}
4561
4562	drm_dp_cec_set_edid(&intel_dp->aux, edid);
4563}
4564
4565static void
4566intel_dp_unset_edid(struct intel_dp *intel_dp)
4567{
4568	struct intel_connector *connector = intel_dp->attached_connector;
4569
4570	drm_dp_cec_unset_edid(&intel_dp->aux);
4571	kfree(connector->detect_edid);
4572	connector->detect_edid = NULL;
4573
4574	intel_dp->has_hdmi_sink = false;
4575	intel_dp->has_audio = false;
4576
4577	intel_dp->dfp.max_bpc = 0;
4578	intel_dp->dfp.max_dotclock = 0;
4579	intel_dp->dfp.min_tmds_clock = 0;
4580	intel_dp->dfp.max_tmds_clock = 0;
4581
4582	intel_dp->dfp.pcon_max_frl_bw = 0;
4583
4584	intel_dp->dfp.ycbcr_444_to_420 = false;
4585	connector->base.ycbcr_420_allowed = false;
4586
4587	drm_connector_set_vrr_capable_property(&connector->base,
4588					       false);
4589}
4590
4591static int
4592intel_dp_detect(struct drm_connector *connector,
4593		struct drm_modeset_acquire_ctx *ctx,
4594		bool force)
4595{
4596	struct drm_i915_private *dev_priv = to_i915(connector->dev);
4597	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4598	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4599	struct intel_encoder *encoder = &dig_port->base;
4600	enum drm_connector_status status;
4601
4602	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4603		    connector->base.id, connector->name);
4604	drm_WARN_ON(&dev_priv->drm,
4605		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4606
4607	if (!INTEL_DISPLAY_ENABLED(dev_priv))
4608		return connector_status_disconnected;
4609
4610	/* Can't disconnect eDP */
4611	if (intel_dp_is_edp(intel_dp))
4612		status = edp_detect(intel_dp);
4613	else if (intel_digital_port_connected(encoder))
4614		status = intel_dp_detect_dpcd(intel_dp);
4615	else
4616		status = connector_status_disconnected;
4617
4618	if (status == connector_status_disconnected) {
4619		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4620		memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4621
4622		if (intel_dp->is_mst) {
4623			drm_dbg_kms(&dev_priv->drm,
4624				    "MST device may have disappeared %d vs %d\n",
4625				    intel_dp->is_mst,
4626				    intel_dp->mst_mgr.mst_state);
4627			intel_dp->is_mst = false;
4628			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4629							intel_dp->is_mst);
4630		}
4631
4632		goto out;
4633	}
4634
4635	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4636	if (DISPLAY_VER(dev_priv) >= 11)
4637		intel_dp_get_dsc_sink_cap(intel_dp);
4638
4639	intel_dp_configure_mst(intel_dp);
4640
4641	/*
4642	 * TODO: Reset link params when switching to MST mode, until MST
4643	 * supports link training fallback params.
4644	 */
4645	if (intel_dp->reset_link_params || intel_dp->is_mst) {
4646		intel_dp_reset_max_link_params(intel_dp);
4647		intel_dp->reset_link_params = false;
4648	}
4649
4650	intel_dp_print_rates(intel_dp);
4651
4652	if (intel_dp->is_mst) {
4653		/*
4654		 * If we are in MST mode then this connector
4655		 * won't appear connected or have anything
4656		 * with EDID on it
4657		 */
4658		status = connector_status_disconnected;
4659		goto out;
4660	}
4661
4662	/*
4663	 * Some external monitors do not signal loss of link synchronization
4664	 * with an IRQ_HPD, so force a link status check.
4665	 */
4666	if (!intel_dp_is_edp(intel_dp)) {
4667		int ret;
4668
4669		ret = intel_dp_retrain_link(encoder, ctx);
4670		if (ret)
4671			return ret;
4672	}
4673
4674	/*
4675	 * Clearing NACK and defer counts to get their exact values
4676	 * while reading EDID which are required by Compliance tests
4677	 * 4.2.2.4 and 4.2.2.5
4678	 */
4679	intel_dp->aux.i2c_nack_count = 0;
4680	intel_dp->aux.i2c_defer_count = 0;
4681
4682	intel_dp_set_edid(intel_dp);
4683	if (intel_dp_is_edp(intel_dp) ||
4684	    to_intel_connector(connector)->detect_edid)
4685		status = connector_status_connected;
4686
4687	intel_dp_check_device_service_irq(intel_dp);
4688
4689out:
4690	if (status != connector_status_connected && !intel_dp->is_mst)
4691		intel_dp_unset_edid(intel_dp);
4692
4693	/*
4694	 * Make sure the refs for power wells enabled during detect are
4695	 * dropped to avoid a new detect cycle triggered by HPD polling.
4696	 */
4697	intel_display_power_flush_work(dev_priv);
4698
4699	if (!intel_dp_is_edp(intel_dp))
4700		drm_dp_set_subconnector_property(connector,
4701						 status,
4702						 intel_dp->dpcd,
4703						 intel_dp->downstream_ports);
4704	return status;
4705}
4706
4707static void
4708intel_dp_force(struct drm_connector *connector)
4709{
4710	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4711	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4712	struct intel_encoder *intel_encoder = &dig_port->base;
4713	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4714	enum intel_display_power_domain aux_domain =
4715		intel_aux_power_domain(dig_port);
4716	intel_wakeref_t wakeref;
4717
4718	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
4719		    connector->base.id, connector->name);
4720	intel_dp_unset_edid(intel_dp);
4721
4722	if (connector->status != connector_status_connected)
4723		return;
4724
4725	wakeref = intel_display_power_get(dev_priv, aux_domain);
4726
4727	intel_dp_set_edid(intel_dp);
4728
4729	intel_display_power_put(dev_priv, aux_domain, wakeref);
4730}
4731
4732static int intel_dp_get_modes(struct drm_connector *connector)
4733{
4734	struct intel_connector *intel_connector = to_intel_connector(connector);
4735	struct edid *edid;
4736	int num_modes = 0;
4737
4738	edid = intel_connector->detect_edid;
4739	if (edid)
4740		num_modes = intel_connector_update_modes(connector, edid);
4741
4742	/* Also add fixed mode, which may or may not be present in EDID */
4743	if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
4744		num_modes += intel_panel_get_modes(intel_connector);
4745
4746	if (num_modes)
4747		return num_modes;
4748
4749	if (!edid) {
4750		struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
4751		struct drm_display_mode *mode;
4752
4753		mode = drm_dp_downstream_mode(connector->dev,
4754					      intel_dp->dpcd,
4755					      intel_dp->downstream_ports);
4756		if (mode) {
4757			drm_mode_probed_add(connector, mode);
4758			num_modes++;
4759		}
4760	}
4761
4762	return num_modes;
4763}
4764
4765static int
4766intel_dp_connector_register(struct drm_connector *connector)
4767{
4768	struct drm_i915_private *i915 = to_i915(connector->dev);
4769	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4770	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4771	struct intel_lspcon *lspcon = &dig_port->lspcon;
4772	int ret;
4773
4774	ret = intel_connector_register(connector);
4775	if (ret)
4776		return ret;
4777
4778	drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
4779		    intel_dp->aux.name, connector->kdev->kobj.name);
4780
4781	intel_dp->aux.dev = connector->kdev;
4782	ret = drm_dp_aux_register(&intel_dp->aux);
4783	if (!ret)
4784		drm_dp_cec_register_connector(&intel_dp->aux, connector);
4785
4786	if (!intel_bios_is_lspcon_present(i915, dig_port->base.port))
4787		return ret;
4788
4789	/*
4790	 * ToDo: Clean this up to handle lspcon init and resume more
4791	 * efficiently and streamlined.
4792	 */
4793	if (lspcon_init(dig_port)) {
4794		lspcon_detect_hdr_capability(lspcon);
4795		if (lspcon->hdr_supported)
4796			drm_connector_attach_hdr_output_metadata_property(connector);
4797	}
4798
4799	return ret;
4800}
4801
4802static void
4803intel_dp_connector_unregister(struct drm_connector *connector)
4804{
4805	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
4806
4807	drm_dp_cec_unregister_connector(&intel_dp->aux);
4808	drm_dp_aux_unregister(&intel_dp->aux);
4809	intel_connector_unregister(connector);
4810}
4811
4812void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
4813{
4814	struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4815	struct intel_dp *intel_dp = &dig_port->dp;
4816
4817	intel_dp_mst_encoder_cleanup(dig_port);
4818
4819	intel_pps_vdd_off_sync(intel_dp);
4820
4821	/*
4822	 * Ensure power off delay is respected on module remove, so that we can
4823	 * reduce delays at driver probe. See pps_init_timestamps().
4824	 */
4825	intel_pps_wait_power_cycle(intel_dp);
4826
4827	intel_dp_aux_fini(intel_dp);
4828}
4829
4830void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4831{
4832	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4833
4834	intel_pps_vdd_off_sync(intel_dp);
4835}
4836
4837void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
4838{
4839	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
4840
4841	intel_pps_wait_power_cycle(intel_dp);
4842}
4843
4844static int intel_modeset_tile_group(struct intel_atomic_state *state,
4845				    int tile_group_id)
4846{
4847	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4848	struct drm_connector_list_iter conn_iter;
4849	struct drm_connector *connector;
4850	int ret = 0;
4851
4852	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
4853	drm_for_each_connector_iter(connector, &conn_iter) {
4854		struct drm_connector_state *conn_state;
4855		struct intel_crtc_state *crtc_state;
4856		struct intel_crtc *crtc;
4857
4858		if (!connector->has_tile ||
4859		    connector->tile_group->id != tile_group_id)
4860			continue;
4861
4862		conn_state = drm_atomic_get_connector_state(&state->base,
4863							    connector);
4864		if (IS_ERR(conn_state)) {
4865			ret = PTR_ERR(conn_state);
4866			break;
4867		}
4868
4869		crtc = to_intel_crtc(conn_state->crtc);
4870
4871		if (!crtc)
4872			continue;
4873
4874		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
4875		crtc_state->uapi.mode_changed = true;
4876
4877		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4878		if (ret)
4879			break;
4880	}
4881	drm_connector_list_iter_end(&conn_iter);
4882
4883	return ret;
4884}
4885
4886static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
4887{
4888	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4889	struct intel_crtc *crtc;
4890
4891	if (transcoders == 0)
4892		return 0;
4893
4894	for_each_intel_crtc(&dev_priv->drm, crtc) {
4895		struct intel_crtc_state *crtc_state;
4896		int ret;
4897
4898		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4899		if (IS_ERR(crtc_state))
4900			return PTR_ERR(crtc_state);
4901
4902		if (!crtc_state->hw.enable)
4903			continue;
4904
4905		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
4906			continue;
4907
4908		crtc_state->uapi.mode_changed = true;
4909
4910		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
4911		if (ret)
4912			return ret;
4913
4914		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
4915		if (ret)
4916			return ret;
4917
4918		transcoders &= ~BIT(crtc_state->cpu_transcoder);
4919	}
4920
4921	drm_WARN_ON(&dev_priv->drm, transcoders != 0);
4922
4923	return 0;
4924}
4925
4926static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
4927				      struct drm_connector *connector)
4928{
4929	const struct drm_connector_state *old_conn_state =
4930		drm_atomic_get_old_connector_state(&state->base, connector);
4931	const struct intel_crtc_state *old_crtc_state;
4932	struct intel_crtc *crtc;
4933	u8 transcoders;
4934
4935	crtc = to_intel_crtc(old_conn_state->crtc);
4936	if (!crtc)
4937		return 0;
4938
4939	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
4940
4941	if (!old_crtc_state->hw.active)
4942		return 0;
4943
4944	transcoders = old_crtc_state->sync_mode_slaves_mask;
4945	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
4946		transcoders |= BIT(old_crtc_state->master_transcoder);
4947
4948	return intel_modeset_affected_transcoders(state,
4949						  transcoders);
4950}
4951
4952static int intel_dp_connector_atomic_check(struct drm_connector *conn,
4953					   struct drm_atomic_state *_state)
4954{
4955	struct drm_i915_private *dev_priv = to_i915(conn->dev);
4956	struct intel_atomic_state *state = to_intel_atomic_state(_state);
4957	struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
4958	struct intel_connector *intel_conn = to_intel_connector(conn);
4959	struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
4960	int ret;
4961
4962	ret = intel_digital_connector_atomic_check(conn, &state->base);
4963	if (ret)
4964		return ret;
4965
4966	if (intel_dp_mst_source_support(intel_dp)) {
4967		ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
4968		if (ret)
4969			return ret;
4970	}
4971
4972	/*
4973	 * We don't enable port sync on BDW due to missing w/as and
4974	 * due to not having adjusted the modeset sequence appropriately.
4975	 */
4976	if (DISPLAY_VER(dev_priv) < 9)
4977		return 0;
4978
4979	if (!intel_connector_needs_modeset(state, conn))
4980		return 0;
4981
4982	if (conn->has_tile) {
4983		ret = intel_modeset_tile_group(state, conn->tile_group->id);
4984		if (ret)
4985			return ret;
4986	}
4987
4988	return intel_modeset_synced_crtcs(state, conn);
4989}
4990
4991static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
4992{
4993	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
4994	struct drm_i915_private *i915 = to_i915(connector->dev);
4995
4996	spin_lock_irq(&i915->irq_lock);
4997	i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
4998	spin_unlock_irq(&i915->irq_lock);
4999	queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
5000}
5001
5002static const struct drm_connector_funcs intel_dp_connector_funcs = {
5003	.force = intel_dp_force,
5004	.fill_modes = drm_helper_probe_single_connector_modes,
5005	.atomic_get_property = intel_digital_connector_atomic_get_property,
5006	.atomic_set_property = intel_digital_connector_atomic_set_property,
5007	.late_register = intel_dp_connector_register,
5008	.early_unregister = intel_dp_connector_unregister,
5009	.destroy = intel_connector_destroy,
5010	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5011	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
5012	.oob_hotplug_event = intel_dp_oob_hotplug_event,
5013};
5014
5015static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5016	.detect_ctx = intel_dp_detect,
5017	.get_modes = intel_dp_get_modes,
5018	.mode_valid = intel_dp_mode_valid,
5019	.atomic_check = intel_dp_connector_atomic_check,
5020};
5021
5022enum irqreturn
5023intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5024{
5025	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5026	struct intel_dp *intel_dp = &dig_port->dp;
5027
5028	if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5029	    (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5030		/*
5031		 * vdd off can generate a long/short pulse on eDP which
5032		 * would require vdd on to handle it, and thus we
5033		 * would end up in an endless cycle of
5034		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5035		 */
5036		drm_dbg_kms(&i915->drm,
5037			    "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5038			    long_hpd ? "long" : "short",
5039			    dig_port->base.base.base.id,
5040			    dig_port->base.base.name);
5041		return IRQ_HANDLED;
5042	}
5043
5044	drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5045		    dig_port->base.base.base.id,
5046		    dig_port->base.base.name,
5047		    long_hpd ? "long" : "short");
5048
5049	if (long_hpd) {
5050		intel_dp->reset_link_params = true;
5051		return IRQ_NONE;
5052	}
5053
5054	if (intel_dp->is_mst) {
5055		if (!intel_dp_check_mst_status(intel_dp))
5056			return IRQ_NONE;
5057	} else if (!intel_dp_short_pulse(intel_dp)) {
5058		return IRQ_NONE;
5059	}
5060
5061	return IRQ_HANDLED;
5062}
5063
5064/* check the VBT to see whether the eDP is on another port */
5065bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5066{
5067	/*
5068	 * eDP not supported on g4x. so bail out early just
5069	 * for a bit extra safety in case the VBT is bonkers.
5070	 */
5071	if (DISPLAY_VER(dev_priv) < 5)
5072		return false;
5073
5074	if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5075		return true;
5076
5077	return intel_bios_is_port_edp(dev_priv, port);
5078}
5079
5080static bool
5081has_gamut_metadata_dip(struct drm_i915_private *i915, enum port port)
5082{
5083	if (intel_bios_is_lspcon_present(i915, port))
5084		return false;
5085
5086	if (DISPLAY_VER(i915) >= 11)
5087		return true;
5088
5089	if (port == PORT_A)
5090		return false;
5091
5092	if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5093	    DISPLAY_VER(i915) >= 9)
5094		return true;
5095
5096	return false;
5097}
5098
5099static void
5100intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5101{
5102	struct drm_i915_private *dev_priv = to_i915(connector->dev);
5103	enum port port = dp_to_dig_port(intel_dp)->base.port;
5104
5105	if (!intel_dp_is_edp(intel_dp))
5106		drm_connector_attach_dp_subconnector_property(connector);
5107
5108	if (!IS_G4X(dev_priv) && port != PORT_A)
5109		intel_attach_force_audio_property(connector);
5110
5111	intel_attach_broadcast_rgb_property(connector);
5112	if (HAS_GMCH(dev_priv))
5113		drm_connector_attach_max_bpc_property(connector, 6, 10);
5114	else if (DISPLAY_VER(dev_priv) >= 5)
5115		drm_connector_attach_max_bpc_property(connector, 6, 12);
5116
5117	/* Register HDMI colorspace for case of lspcon */
5118	if (intel_bios_is_lspcon_present(dev_priv, port)) {
5119		drm_connector_attach_content_type_property(connector);
5120		intel_attach_hdmi_colorspace_property(connector);
5121	} else {
5122		intel_attach_dp_colorspace_property(connector);
5123	}
5124
5125	if (has_gamut_metadata_dip(dev_priv, port))
5126		drm_connector_attach_hdr_output_metadata_property(connector);
5127
5128	if (HAS_VRR(dev_priv))
5129		drm_connector_attach_vrr_capable_property(connector);
5130}
5131
5132static void
5133intel_edp_add_properties(struct intel_dp *intel_dp)
5134{
5135	struct intel_connector *connector = intel_dp->attached_connector;
5136	struct drm_i915_private *i915 = to_i915(connector->base.dev);
5137	const struct drm_display_mode *fixed_mode =
5138		intel_panel_preferred_fixed_mode(connector);
5139
5140	intel_attach_scaling_mode_property(&connector->base);
5141
5142	drm_connector_set_panel_orientation_with_quirk(&connector->base,
5143						       i915->display.vbt.orientation,
5144						       fixed_mode->hdisplay,
5145						       fixed_mode->vdisplay);
5146}
5147
5148static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
5149				      struct intel_connector *connector)
5150{
5151	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5152	enum pipe pipe = INVALID_PIPE;
5153
5154	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
5155		/*
5156		 * Figure out the current pipe for the initial backlight setup.
5157		 * If the current pipe isn't valid, try the PPS pipe, and if that
5158		 * fails just assume pipe A.
5159		 */
5160		pipe = vlv_active_pipe(intel_dp);
5161
5162		if (pipe != PIPE_A && pipe != PIPE_B)
5163			pipe = intel_dp->pps.pps_pipe;
5164
5165		if (pipe != PIPE_A && pipe != PIPE_B)
5166			pipe = PIPE_A;
5167
5168		drm_dbg_kms(&i915->drm,
5169			    "[CONNECTOR:%d:%s] using pipe %c for initial backlight setup\n",
5170			    connector->base.base.id, connector->base.name,
5171			    pipe_name(pipe));
5172	}
5173
5174	intel_backlight_setup(connector, pipe);
5175}
5176
5177static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5178				     struct intel_connector *intel_connector)
5179{
5180	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5181	struct drm_connector *connector = &intel_connector->base;
5182	struct drm_display_mode *fixed_mode;
5183	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5184	bool has_dpcd;
5185	struct edid *edid;
5186
5187	if (!intel_dp_is_edp(intel_dp))
5188		return true;
5189
5190	/*
5191	 * On IBX/CPT we may get here with LVDS already registered. Since the
5192	 * driver uses the only internal power sequencer available for both
5193	 * eDP and LVDS bail out early in this case to prevent interfering
5194	 * with an already powered-on LVDS power sequencer.
5195	 */
5196	if (intel_get_lvds_encoder(dev_priv)) {
5197		drm_WARN_ON(&dev_priv->drm,
5198			    !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5199		drm_info(&dev_priv->drm,
5200			 "LVDS was detected, not registering eDP\n");
5201
5202		return false;
5203	}
5204
5205	intel_pps_init(intel_dp);
5206
5207	/* Cache DPCD and EDID for edp. */
5208	has_dpcd = intel_edp_init_dpcd(intel_dp);
5209
5210	if (!has_dpcd) {
5211		/* if this fails, presume the device is a ghost */
5212		drm_info(&dev_priv->drm,
5213			 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
5214			 encoder->base.base.id, encoder->base.name);
5215		goto out_vdd_off;
5216	}
5217
5218	mutex_lock(&dev_priv->drm.mode_config.mutex);
5219	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5220	if (!edid) {
5221		/* Fallback to EDID from ACPI OpRegion, if any */
5222		edid = intel_opregion_get_edid(intel_connector);
5223		if (edid)
5224			drm_dbg_kms(&dev_priv->drm,
5225				    "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
5226				    connector->base.id, connector->name);
5227	}
5228	if (edid) {
5229		if (drm_add_edid_modes(connector, edid)) {
5230			drm_connector_update_edid_property(connector, edid);
5231		} else {
5232			kfree(edid);
5233			edid = ERR_PTR(-EINVAL);
5234		}
5235	} else {
5236		edid = ERR_PTR(-ENOENT);
5237	}
5238	intel_connector->edid = edid;
5239
5240	intel_bios_init_panel(dev_priv, &intel_connector->panel,
5241			      encoder->devdata, IS_ERR(edid) ? NULL : edid);
5242
5243	intel_panel_add_edid_fixed_modes(intel_connector, true);
5244
5245	/* MSO requires information from the EDID */
5246	intel_edp_mso_init(intel_dp);
5247
5248	/* multiply the mode clock and horizontal timings for MSO */
5249	list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
5250		intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
5251
5252	/* fallback to VBT if available for eDP */
5253	if (!intel_panel_preferred_fixed_mode(intel_connector))
5254		intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
5255
5256	mutex_unlock(&dev_priv->drm.mode_config.mutex);
5257
5258	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
5259		drm_info(&dev_priv->drm,
5260			 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
5261			 encoder->base.base.id, encoder->base.name);
5262		goto out_vdd_off;
5263	}
5264
5265	intel_panel_init(intel_connector);
5266
5267	intel_edp_backlight_setup(intel_dp, intel_connector);
5268
5269	intel_edp_add_properties(intel_dp);
5270
5271	intel_pps_init_late(intel_dp);
5272
5273	return true;
5274
5275out_vdd_off:
5276	intel_pps_vdd_off_sync(intel_dp);
5277
5278	return false;
5279}
5280
5281static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5282{
5283	struct intel_connector *intel_connector;
5284	struct drm_connector *connector;
5285
5286	intel_connector = container_of(work, typeof(*intel_connector),
5287				       modeset_retry_work);
5288	connector = &intel_connector->base;
5289	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
5290		    connector->name);
5291
5292	/* Grab the locks before changing connector property*/
5293	mutex_lock(&connector->dev->mode_config.mutex);
5294	/* Set connector link status to BAD and send a Uevent to notify
5295	 * userspace to do a modeset.
5296	 */
5297	drm_connector_set_link_status_property(connector,
5298					       DRM_MODE_LINK_STATUS_BAD);
5299	mutex_unlock(&connector->dev->mode_config.mutex);
5300	/* Send Hotplug uevent so userspace can reprobe */
5301	drm_kms_helper_connector_hotplug_event(connector);
5302}
5303
5304bool
5305intel_dp_init_connector(struct intel_digital_port *dig_port,
5306			struct intel_connector *intel_connector)
5307{
5308	struct drm_connector *connector = &intel_connector->base;
5309	struct intel_dp *intel_dp = &dig_port->dp;
5310	struct intel_encoder *intel_encoder = &dig_port->base;
5311	struct drm_device *dev = intel_encoder->base.dev;
5312	struct drm_i915_private *dev_priv = to_i915(dev);
5313	enum port port = intel_encoder->port;
5314	enum phy phy = intel_port_to_phy(dev_priv, port);
5315	int type;
5316
5317	/* Initialize the work for modeset in case of link train failure */
5318	INIT_WORK(&intel_connector->modeset_retry_work,
5319		  intel_dp_modeset_retry_work_fn);
5320
5321	if (drm_WARN(dev, dig_port->max_lanes < 1,
5322		     "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
5323		     dig_port->max_lanes, intel_encoder->base.base.id,
5324		     intel_encoder->base.name))
5325		return false;
5326
5327	intel_dp->reset_link_params = true;
5328	intel_dp->pps.pps_pipe = INVALID_PIPE;
5329	intel_dp->pps.active_pipe = INVALID_PIPE;
5330
5331	/* Preserve the current hw state. */
5332	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
5333	intel_dp->attached_connector = intel_connector;
5334
5335	if (intel_dp_is_port_edp(dev_priv, port)) {
5336		/*
5337		 * Currently we don't support eDP on TypeC ports, although in
5338		 * theory it could work on TypeC legacy ports.
5339		 */
5340		drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
5341		type = DRM_MODE_CONNECTOR_eDP;
5342		intel_encoder->type = INTEL_OUTPUT_EDP;
5343
5344		/* eDP only on port B and/or C on vlv/chv */
5345		if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
5346				      IS_CHERRYVIEW(dev_priv)) &&
5347				port != PORT_B && port != PORT_C))
5348			return false;
5349	} else {
5350		type = DRM_MODE_CONNECTOR_DisplayPort;
5351	}
5352
5353	intel_dp_set_default_sink_rates(intel_dp);
5354	intel_dp_set_default_max_sink_lane_count(intel_dp);
5355
5356	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5357		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
5358
5359	drm_dbg_kms(&dev_priv->drm,
5360		    "Adding %s connector on [ENCODER:%d:%s]\n",
5361		    type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5362		    intel_encoder->base.base.id, intel_encoder->base.name);
5363
5364	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5365	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5366
5367	if (!HAS_GMCH(dev_priv))
5368		connector->interlace_allowed = true;
5369
5370	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
5371
5372	intel_dp_aux_init(intel_dp);
5373
5374	intel_connector_attach_encoder(intel_connector, intel_encoder);
5375
5376	if (HAS_DDI(dev_priv))
5377		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5378	else
5379		intel_connector->get_hw_state = intel_connector_get_hw_state;
5380
5381	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5382		intel_dp_aux_fini(intel_dp);
5383		goto fail;
5384	}
5385
5386	intel_dp_set_source_rates(intel_dp);
5387	intel_dp_set_common_rates(intel_dp);
5388	intel_dp_reset_max_link_params(intel_dp);
5389
5390	/* init MST on ports that can support it */
5391	intel_dp_mst_encoder_init(dig_port,
5392				  intel_connector->base.base.id);
5393
5394	intel_dp_add_properties(intel_dp, connector);
5395
5396	if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
5397		int ret = intel_dp_hdcp_init(dig_port, intel_connector);
5398		if (ret)
5399			drm_dbg_kms(&dev_priv->drm,
5400				    "HDCP init failed, skipping.\n");
5401	}
5402
5403	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5404	 * 0xd.  Failure to do so will result in spurious interrupts being
5405	 * generated on the port when a cable is not attached.
5406	 */
5407	if (IS_G45(dev_priv)) {
5408		u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
5409		intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
5410			       (temp & ~0xf) | 0xd);
5411	}
5412
5413	intel_dp->frl.is_trained = false;
5414	intel_dp->frl.trained_rate_gbps = 0;
5415
5416	intel_psr_init(intel_dp);
5417
5418	return true;
5419
5420fail:
5421	drm_connector_cleanup(connector);
5422
5423	return false;
5424}
5425
5426void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
5427{
5428	struct intel_encoder *encoder;
5429
5430	if (!HAS_DISPLAY(dev_priv))
5431		return;
5432
5433	for_each_intel_encoder(&dev_priv->drm, encoder) {
5434		struct intel_dp *intel_dp;
5435
5436		if (encoder->type != INTEL_OUTPUT_DDI)
5437			continue;
5438
5439		intel_dp = enc_to_intel_dp(encoder);
5440
5441		if (!intel_dp_mst_source_support(intel_dp))
5442			continue;
5443
5444		if (intel_dp->is_mst)
5445			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
5446	}
5447}
5448
5449void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
5450{
5451	struct intel_encoder *encoder;
5452
5453	if (!HAS_DISPLAY(dev_priv))
5454		return;
5455
5456	for_each_intel_encoder(&dev_priv->drm, encoder) {
5457		struct intel_dp *intel_dp;
5458		int ret;
5459
5460		if (encoder->type != INTEL_OUTPUT_DDI)
5461			continue;
5462
5463		intel_dp = enc_to_intel_dp(encoder);
5464
5465		if (!intel_dp_mst_source_support(intel_dp))
5466			continue;
5467
5468		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
5469						     true);
5470		if (ret) {
5471			intel_dp->is_mst = false;
5472			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5473							false);
5474		}
5475	}
5476}