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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu_ras_eeprom.h"
25#include "amdgpu.h"
26#include "amdgpu_ras.h"
27#include <linux/bits.h>
28#include "atom.h"
29#include "amdgpu_eeprom.h"
30#include "amdgpu_atomfirmware.h"
31#include <linux/debugfs.h>
32#include <linux/uaccess.h>
33
34#include "amdgpu_reset.h"
35
36/* These are memory addresses as would be seen by one or more EEPROM
37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a
38 * set of EEPROM devices. They form a continuous memory space.
39 *
40 * The I2C device address includes the device type identifier, 1010b,
41 * which is a reserved value and indicates that this is an I2C EEPROM
42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory
43 * address, namely bits 18, 17, and 16. This makes up the 7 bit
44 * address sent on the I2C bus with bit 0 being the direction bit,
45 * which is not represented here, and sent by the hardware directly.
46 *
47 * For instance,
48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0.
49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h.
50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h.
51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
52 * address memory in a device or a device on the I2C bus, depending on
53 * the status of pins 1-3. See top of amdgpu_eeprom.c.
54 *
55 * The RAS table lives either at address 0 or address 40000h of EEPROM.
56 */
57#define EEPROM_I2C_MADDR_0 0x0
58#define EEPROM_I2C_MADDR_4 0x40000
59
60/*
61 * The 2 macros bellow represent the actual size in bytes that
62 * those entities occupy in the EEPROM memory.
63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
64 * uses uint64 to store 6b fields such as retired_page.
65 */
66#define RAS_TABLE_HEADER_SIZE 20
67#define RAS_TABLE_RECORD_SIZE 24
68
69/* Table hdr is 'AMDR' */
70#define RAS_TABLE_HDR_VAL 0x414d4452
71#define RAS_TABLE_VER 0x00010000
72
73/* Bad GPU tag ‘BADG’ */
74#define RAS_TABLE_HDR_BAD 0x42414447
75
76/* Assume 2-Mbit size EEPROM and take up the whole space. */
77#define RAS_TBL_SIZE_BYTES (256 * 1024)
78#define RAS_TABLE_START 0
79#define RAS_HDR_START RAS_TABLE_START
80#define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
81#define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
82 / RAS_TABLE_RECORD_SIZE)
83
84/* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
85 * offset off of RAS_TABLE_START. That is, this is something you can
86 * add to control->i2c_address, and then tell I2C layer to read
87 * from/write to there. _N is the so called absolute index,
88 * because it starts right after the table header.
89 */
90#define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
91 (_N) * RAS_TABLE_RECORD_SIZE)
92
93#define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
94 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
95
96/* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
97 * of "fri", return the absolute record index off of the end of
98 * the table header.
99 */
100#define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
101 (_C)->ras_max_record_count)
102
103#define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
104 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
105
106#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
107
108static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
109{
110 if (adev->asic_type == CHIP_IP_DISCOVERY) {
111 switch (adev->ip_versions[MP1_HWIP][0]) {
112 case IP_VERSION(13, 0, 0):
113 case IP_VERSION(13, 0, 10):
114 return true;
115 default:
116 return false;
117 }
118 }
119
120 return adev->asic_type == CHIP_VEGA20 ||
121 adev->asic_type == CHIP_ARCTURUS ||
122 adev->asic_type == CHIP_SIENNA_CICHLID ||
123 adev->asic_type == CHIP_ALDEBARAN;
124}
125
126static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
127 struct amdgpu_ras_eeprom_control *control)
128{
129 struct atom_context *atom_ctx = adev->mode_info.atom_context;
130
131 if (!control || !atom_ctx)
132 return false;
133
134 if (strnstr(atom_ctx->vbios_version,
135 "D342",
136 sizeof(atom_ctx->vbios_version)))
137 control->i2c_address = EEPROM_I2C_MADDR_0;
138 else
139 control->i2c_address = EEPROM_I2C_MADDR_4;
140
141 return true;
142}
143
144static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev,
145 struct amdgpu_ras_eeprom_control *control)
146{
147 switch (adev->ip_versions[MP1_HWIP][0]) {
148 case IP_VERSION(13, 0, 0):
149 case IP_VERSION(13, 0, 10):
150 control->i2c_address = EEPROM_I2C_MADDR_4;
151 return true;
152 default:
153 return false;
154 }
155}
156
157static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
158 struct amdgpu_ras_eeprom_control *control)
159{
160 struct atom_context *atom_ctx = adev->mode_info.atom_context;
161 u8 i2c_addr;
162
163 if (!control)
164 return false;
165
166 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
167 /* The address given by VBIOS is an 8-bit, wire-format
168 * address, i.e. the most significant byte.
169 *
170 * Normalize it to a 19-bit EEPROM address. Remove the
171 * device type identifier and make it a 7-bit address;
172 * then make it a 19-bit EEPROM address. See top of
173 * amdgpu_eeprom.c.
174 */
175 i2c_addr = (i2c_addr & 0x0F) >> 1;
176 control->i2c_address = ((u32) i2c_addr) << 16;
177
178 return true;
179 }
180
181 switch (adev->asic_type) {
182 case CHIP_VEGA20:
183 control->i2c_address = EEPROM_I2C_MADDR_0;
184 break;
185
186 case CHIP_ARCTURUS:
187 return __get_eeprom_i2c_addr_arct(adev, control);
188
189 case CHIP_SIENNA_CICHLID:
190 control->i2c_address = EEPROM_I2C_MADDR_0;
191 break;
192
193 case CHIP_ALDEBARAN:
194 if (strnstr(atom_ctx->vbios_version, "D673",
195 sizeof(atom_ctx->vbios_version)))
196 control->i2c_address = EEPROM_I2C_MADDR_4;
197 else
198 control->i2c_address = EEPROM_I2C_MADDR_0;
199 break;
200
201 case CHIP_IP_DISCOVERY:
202 return __get_eeprom_i2c_addr_ip_discovery(adev, control);
203
204 default:
205 return false;
206 }
207
208 switch (adev->ip_versions[MP1_HWIP][0]) {
209 case IP_VERSION(13, 0, 0):
210 control->i2c_address = EEPROM_I2C_MADDR_4;
211 break;
212
213 default:
214 break;
215 }
216
217 return true;
218}
219
220static void
221__encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
222 unsigned char *buf)
223{
224 u32 *pp = (uint32_t *)buf;
225
226 pp[0] = cpu_to_le32(hdr->header);
227 pp[1] = cpu_to_le32(hdr->version);
228 pp[2] = cpu_to_le32(hdr->first_rec_offset);
229 pp[3] = cpu_to_le32(hdr->tbl_size);
230 pp[4] = cpu_to_le32(hdr->checksum);
231}
232
233static void
234__decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
235 unsigned char *buf)
236{
237 u32 *pp = (uint32_t *)buf;
238
239 hdr->header = le32_to_cpu(pp[0]);
240 hdr->version = le32_to_cpu(pp[1]);
241 hdr->first_rec_offset = le32_to_cpu(pp[2]);
242 hdr->tbl_size = le32_to_cpu(pp[3]);
243 hdr->checksum = le32_to_cpu(pp[4]);
244}
245
246static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
247{
248 u8 buf[RAS_TABLE_HEADER_SIZE];
249 struct amdgpu_device *adev = to_amdgpu_device(control);
250 int res;
251
252 memset(buf, 0, sizeof(buf));
253 __encode_table_header_to_buf(&control->tbl_hdr, buf);
254
255 /* i2c may be unstable in gpu reset */
256 down_read(&adev->reset_domain->sem);
257 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
258 control->i2c_address +
259 control->ras_header_offset,
260 buf, RAS_TABLE_HEADER_SIZE);
261 up_read(&adev->reset_domain->sem);
262
263 if (res < 0) {
264 DRM_ERROR("Failed to write EEPROM table header:%d", res);
265 } else if (res < RAS_TABLE_HEADER_SIZE) {
266 DRM_ERROR("Short write:%d out of %d\n",
267 res, RAS_TABLE_HEADER_SIZE);
268 res = -EIO;
269 } else {
270 res = 0;
271 }
272
273 return res;
274}
275
276static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
277{
278 int ii;
279 u8 *pp, csum;
280 size_t sz;
281
282 /* Header checksum, skip checksum field in the calculation */
283 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
284 pp = (u8 *) &control->tbl_hdr;
285 csum = 0;
286 for (ii = 0; ii < sz; ii++, pp++)
287 csum += *pp;
288
289 return csum;
290}
291
292static int amdgpu_ras_eeprom_correct_header_tag(
293 struct amdgpu_ras_eeprom_control *control,
294 uint32_t header)
295{
296 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
297 u8 *hh;
298 int res;
299 u8 csum;
300
301 csum = -hdr->checksum;
302
303 hh = (void *) &hdr->header;
304 csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
305 hh = (void *) &header;
306 csum += hh[0] + hh[1] + hh[2] + hh[3];
307 csum = -csum;
308 mutex_lock(&control->ras_tbl_mutex);
309 hdr->header = header;
310 hdr->checksum = csum;
311 res = __write_table_header(control);
312 mutex_unlock(&control->ras_tbl_mutex);
313
314 return res;
315}
316
317/**
318 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
319 * @control: pointer to control structure
320 *
321 * Reset the contents of the header of the RAS EEPROM table.
322 * Return 0 on success, -errno on error.
323 */
324int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
325{
326 struct amdgpu_device *adev = to_amdgpu_device(control);
327 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
328 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
329 u8 csum;
330 int res;
331
332 mutex_lock(&control->ras_tbl_mutex);
333
334 hdr->header = RAS_TABLE_HDR_VAL;
335 hdr->version = RAS_TABLE_VER;
336 hdr->first_rec_offset = RAS_RECORD_START;
337 hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
338
339 csum = __calc_hdr_byte_sum(control);
340 csum = -csum;
341 hdr->checksum = csum;
342 res = __write_table_header(control);
343
344 control->ras_num_recs = 0;
345 control->ras_fri = 0;
346
347 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);
348
349 control->bad_channel_bitmap = 0;
350 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);
351 con->update_channel_flag = false;
352
353 amdgpu_ras_debugfs_set_ret_size(control);
354
355 mutex_unlock(&control->ras_tbl_mutex);
356
357 return res;
358}
359
360static void
361__encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
362 struct eeprom_table_record *record,
363 unsigned char *buf)
364{
365 __le64 tmp = 0;
366 int i = 0;
367
368 /* Next are all record fields according to EEPROM page spec in LE foramt */
369 buf[i++] = record->err_type;
370
371 buf[i++] = record->bank;
372
373 tmp = cpu_to_le64(record->ts);
374 memcpy(buf + i, &tmp, 8);
375 i += 8;
376
377 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
378 memcpy(buf + i, &tmp, 6);
379 i += 6;
380
381 buf[i++] = record->mem_channel;
382 buf[i++] = record->mcumc_id;
383
384 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
385 memcpy(buf + i, &tmp, 6);
386}
387
388static void
389__decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
390 struct eeprom_table_record *record,
391 unsigned char *buf)
392{
393 __le64 tmp = 0;
394 int i = 0;
395
396 /* Next are all record fields according to EEPROM page spec in LE foramt */
397 record->err_type = buf[i++];
398
399 record->bank = buf[i++];
400
401 memcpy(&tmp, buf + i, 8);
402 record->ts = le64_to_cpu(tmp);
403 i += 8;
404
405 memcpy(&tmp, buf + i, 6);
406 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
407 i += 6;
408
409 record->mem_channel = buf[i++];
410 record->mcumc_id = buf[i++];
411
412 memcpy(&tmp, buf + i, 6);
413 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
414}
415
416bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
417{
418 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
419
420 if (!__is_ras_eeprom_supported(adev))
421 return false;
422
423 /* skip check eeprom table for VEGA20 Gaming */
424 if (!con)
425 return false;
426 else
427 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
428 return false;
429
430 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
431 dev_warn(adev->dev, "This GPU is in BAD status.");
432 dev_warn(adev->dev, "Please retire it or set a larger "
433 "threshold value when reloading driver.\n");
434 return true;
435 }
436
437 return false;
438}
439
440/**
441 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
442 * @control: pointer to control structure
443 * @buf: pointer to buffer containing data to write
444 * @fri: start writing at this index
445 * @num: number of records to write
446 *
447 * The caller must hold the table mutex in @control.
448 * Return 0 on success, -errno otherwise.
449 */
450static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
451 u8 *buf, const u32 fri, const u32 num)
452{
453 struct amdgpu_device *adev = to_amdgpu_device(control);
454 u32 buf_size;
455 int res;
456
457 /* i2c may be unstable in gpu reset */
458 down_read(&adev->reset_domain->sem);
459 buf_size = num * RAS_TABLE_RECORD_SIZE;
460 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
461 control->i2c_address +
462 RAS_INDEX_TO_OFFSET(control, fri),
463 buf, buf_size);
464 up_read(&adev->reset_domain->sem);
465 if (res < 0) {
466 DRM_ERROR("Writing %d EEPROM table records error:%d",
467 num, res);
468 } else if (res < buf_size) {
469 /* Short write, return error.
470 */
471 DRM_ERROR("Wrote %d records out of %d",
472 res / RAS_TABLE_RECORD_SIZE, num);
473 res = -EIO;
474 } else {
475 res = 0;
476 }
477
478 return res;
479}
480
481static int
482amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
483 struct eeprom_table_record *record,
484 const u32 num)
485{
486 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
487 u32 a, b, i;
488 u8 *buf, *pp;
489 int res;
490
491 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
492 if (!buf)
493 return -ENOMEM;
494
495 /* Encode all of them in one go.
496 */
497 pp = buf;
498 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
499 __encode_table_record_to_buf(control, &record[i], pp);
500
501 /* update bad channel bitmap */
502 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
503 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
504 con->update_channel_flag = true;
505 }
506 }
507
508 /* a, first record index to write into.
509 * b, last record index to write into.
510 * a = first index to read (fri) + number of records in the table,
511 * b = a + @num - 1.
512 * Let N = control->ras_max_num_record_count, then we have,
513 * case 0: 0 <= a <= b < N,
514 * just append @num records starting at a;
515 * case 1: 0 <= a < N <= b,
516 * append (N - a) records starting at a, and
517 * append the remainder, b % N + 1, starting at 0.
518 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
519 * case 2a: 0 <= a <= b < N
520 * append num records starting at a; and fix fri if b overwrote it,
521 * and since a <= b, if b overwrote it then a must've also,
522 * and if b didn't overwrite it, then a didn't also.
523 * case 2b: 0 <= b < a < N
524 * write num records starting at a, which wraps around 0=N
525 * and overwrite fri unconditionally. Now from case 2a,
526 * this means that b eclipsed fri to overwrite it and wrap
527 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
528 * set fri = b + 1 (mod N).
529 * Now, since fri is updated in every case, except the trivial case 0,
530 * the number of records present in the table after writing, is,
531 * num_recs - 1 = b - fri (mod N), and we take the positive value,
532 * by adding an arbitrary multiple of N before taking the modulo N
533 * as shown below.
534 */
535 a = control->ras_fri + control->ras_num_recs;
536 b = a + num - 1;
537 if (b < control->ras_max_record_count) {
538 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
539 } else if (a < control->ras_max_record_count) {
540 u32 g0, g1;
541
542 g0 = control->ras_max_record_count - a;
543 g1 = b % control->ras_max_record_count + 1;
544 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
545 if (res)
546 goto Out;
547 res = __amdgpu_ras_eeprom_write(control,
548 buf + g0 * RAS_TABLE_RECORD_SIZE,
549 0, g1);
550 if (res)
551 goto Out;
552 if (g1 > control->ras_fri)
553 control->ras_fri = g1 % control->ras_max_record_count;
554 } else {
555 a %= control->ras_max_record_count;
556 b %= control->ras_max_record_count;
557
558 if (a <= b) {
559 /* Note that, b - a + 1 = num. */
560 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
561 if (res)
562 goto Out;
563 if (b >= control->ras_fri)
564 control->ras_fri = (b + 1) % control->ras_max_record_count;
565 } else {
566 u32 g0, g1;
567
568 /* b < a, which means, we write from
569 * a to the end of the table, and from
570 * the start of the table to b.
571 */
572 g0 = control->ras_max_record_count - a;
573 g1 = b + 1;
574 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
575 if (res)
576 goto Out;
577 res = __amdgpu_ras_eeprom_write(control,
578 buf + g0 * RAS_TABLE_RECORD_SIZE,
579 0, g1);
580 if (res)
581 goto Out;
582 control->ras_fri = g1 % control->ras_max_record_count;
583 }
584 }
585 control->ras_num_recs = 1 + (control->ras_max_record_count + b
586 - control->ras_fri)
587 % control->ras_max_record_count;
588Out:
589 kfree(buf);
590 return res;
591}
592
593static int
594amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
595{
596 struct amdgpu_device *adev = to_amdgpu_device(control);
597 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
598 u8 *buf, *pp, csum;
599 u32 buf_size;
600 int res;
601
602 /* Modify the header if it exceeds.
603 */
604 if (amdgpu_bad_page_threshold != 0 &&
605 control->ras_num_recs >= ras->bad_page_cnt_threshold) {
606 dev_warn(adev->dev,
607 "Saved bad pages %d reaches threshold value %d\n",
608 control->ras_num_recs, ras->bad_page_cnt_threshold);
609 control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
610 }
611
612 control->tbl_hdr.version = RAS_TABLE_VER;
613 control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri);
614 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
615 control->tbl_hdr.checksum = 0;
616
617 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
618 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
619 if (!buf) {
620 DRM_ERROR("allocating memory for table of size %d bytes failed\n",
621 control->tbl_hdr.tbl_size);
622 res = -ENOMEM;
623 goto Out;
624 }
625
626 down_read(&adev->reset_domain->sem);
627 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
628 control->i2c_address +
629 control->ras_record_offset,
630 buf, buf_size);
631 up_read(&adev->reset_domain->sem);
632 if (res < 0) {
633 DRM_ERROR("EEPROM failed reading records:%d\n",
634 res);
635 goto Out;
636 } else if (res < buf_size) {
637 DRM_ERROR("EEPROM read %d out of %d bytes\n",
638 res, buf_size);
639 res = -EIO;
640 goto Out;
641 }
642
643 /* Recalc the checksum.
644 */
645 csum = 0;
646 for (pp = buf; pp < buf + buf_size; pp++)
647 csum += *pp;
648
649 csum += __calc_hdr_byte_sum(control);
650 /* avoid sign extension when assigning to "checksum" */
651 csum = -csum;
652 control->tbl_hdr.checksum = csum;
653 res = __write_table_header(control);
654Out:
655 kfree(buf);
656 return res;
657}
658
659/**
660 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
661 * @control: pointer to control structure
662 * @record: array of records to append
663 * @num: number of records in @record array
664 *
665 * Append @num records to the table, calculate the checksum and write
666 * the table back to EEPROM. The maximum number of records that
667 * can be appended is between 1 and control->ras_max_record_count,
668 * regardless of how many records are already stored in the table.
669 *
670 * Return 0 on success or if EEPROM is not supported, -errno on error.
671 */
672int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
673 struct eeprom_table_record *record,
674 const u32 num)
675{
676 struct amdgpu_device *adev = to_amdgpu_device(control);
677 int res;
678
679 if (!__is_ras_eeprom_supported(adev))
680 return 0;
681
682 if (num == 0) {
683 DRM_ERROR("will not append 0 records\n");
684 return -EINVAL;
685 } else if (num > control->ras_max_record_count) {
686 DRM_ERROR("cannot append %d records than the size of table %d\n",
687 num, control->ras_max_record_count);
688 return -EINVAL;
689 }
690
691 mutex_lock(&control->ras_tbl_mutex);
692
693 res = amdgpu_ras_eeprom_append_table(control, record, num);
694 if (!res)
695 res = amdgpu_ras_eeprom_update_header(control);
696 if (!res)
697 amdgpu_ras_debugfs_set_ret_size(control);
698
699 mutex_unlock(&control->ras_tbl_mutex);
700 return res;
701}
702
703/**
704 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
705 * @control: pointer to control structure
706 * @buf: pointer to buffer to read into
707 * @fri: first record index, start reading at this index, absolute index
708 * @num: number of records to read
709 *
710 * The caller must hold the table mutex in @control.
711 * Return 0 on success, -errno otherwise.
712 */
713static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
714 u8 *buf, const u32 fri, const u32 num)
715{
716 struct amdgpu_device *adev = to_amdgpu_device(control);
717 u32 buf_size;
718 int res;
719
720 /* i2c may be unstable in gpu reset */
721 down_read(&adev->reset_domain->sem);
722 buf_size = num * RAS_TABLE_RECORD_SIZE;
723 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
724 control->i2c_address +
725 RAS_INDEX_TO_OFFSET(control, fri),
726 buf, buf_size);
727 up_read(&adev->reset_domain->sem);
728 if (res < 0) {
729 DRM_ERROR("Reading %d EEPROM table records error:%d",
730 num, res);
731 } else if (res < buf_size) {
732 /* Short read, return error.
733 */
734 DRM_ERROR("Read %d records out of %d",
735 res / RAS_TABLE_RECORD_SIZE, num);
736 res = -EIO;
737 } else {
738 res = 0;
739 }
740
741 return res;
742}
743
744/**
745 * amdgpu_ras_eeprom_read -- read EEPROM
746 * @control: pointer to control structure
747 * @record: array of records to read into
748 * @num: number of records in @record
749 *
750 * Reads num records from the RAS table in EEPROM and
751 * writes the data into @record array.
752 *
753 * Returns 0 on success, -errno on error.
754 */
755int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
756 struct eeprom_table_record *record,
757 const u32 num)
758{
759 struct amdgpu_device *adev = to_amdgpu_device(control);
760 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
761 int i, res;
762 u8 *buf, *pp;
763 u32 g0, g1;
764
765 if (!__is_ras_eeprom_supported(adev))
766 return 0;
767
768 if (num == 0) {
769 DRM_ERROR("will not read 0 records\n");
770 return -EINVAL;
771 } else if (num > control->ras_num_recs) {
772 DRM_ERROR("too many records to read:%d available:%d\n",
773 num, control->ras_num_recs);
774 return -EINVAL;
775 }
776
777 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
778 if (!buf)
779 return -ENOMEM;
780
781 /* Determine how many records to read, from the first record
782 * index, fri, to the end of the table, and from the beginning
783 * of the table, such that the total number of records is
784 * @num, and we handle wrap around when fri > 0 and
785 * fri + num > RAS_MAX_RECORD_COUNT.
786 *
787 * First we compute the index of the last element
788 * which would be fetched from each region,
789 * g0 is in [fri, fri + num - 1], and
790 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
791 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
792 * the last element to fetch, we set g0 to _the number_
793 * of elements to fetch, @num, since we know that the last
794 * indexed to be fetched does not exceed the table.
795 *
796 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
797 * we set g0 to the number of elements to read
798 * until the end of the table, and g1 to the number of
799 * elements to read from the beginning of the table.
800 */
801 g0 = control->ras_fri + num - 1;
802 g1 = g0 % control->ras_max_record_count;
803 if (g0 < control->ras_max_record_count) {
804 g0 = num;
805 g1 = 0;
806 } else {
807 g0 = control->ras_max_record_count - control->ras_fri;
808 g1 += 1;
809 }
810
811 mutex_lock(&control->ras_tbl_mutex);
812 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
813 if (res)
814 goto Out;
815 if (g1) {
816 res = __amdgpu_ras_eeprom_read(control,
817 buf + g0 * RAS_TABLE_RECORD_SIZE,
818 0, g1);
819 if (res)
820 goto Out;
821 }
822
823 res = 0;
824
825 /* Read up everything? Then transform.
826 */
827 pp = buf;
828 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
829 __decode_table_record_from_buf(control, &record[i], pp);
830
831 /* update bad channel bitmap */
832 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
833 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
834 con->update_channel_flag = true;
835 }
836 }
837Out:
838 kfree(buf);
839 mutex_unlock(&control->ras_tbl_mutex);
840
841 return res;
842}
843
844uint32_t amdgpu_ras_eeprom_max_record_count(void)
845{
846 return RAS_MAX_RECORD_COUNT;
847}
848
849static ssize_t
850amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
851 size_t size, loff_t *pos)
852{
853 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
854 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
855 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
856 u8 data[50];
857 int res;
858
859 if (!size)
860 return size;
861
862 if (!ras || !control) {
863 res = snprintf(data, sizeof(data), "Not supported\n");
864 } else {
865 res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
866 RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
867 }
868
869 if (*pos >= res)
870 return 0;
871
872 res -= *pos;
873 res = min_t(size_t, res, size);
874
875 if (copy_to_user(buf, &data[*pos], res))
876 return -EFAULT;
877
878 *pos += res;
879
880 return res;
881}
882
883const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
884 .owner = THIS_MODULE,
885 .read = amdgpu_ras_debugfs_eeprom_size_read,
886 .write = NULL,
887 .llseek = default_llseek,
888};
889
890static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
891static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
892#define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
893static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
894static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
895#define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
896
897static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
898 "ignore",
899 "re",
900 "ue",
901};
902
903static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
904{
905 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
906 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
907}
908
909void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
910{
911 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
912 eeprom_control);
913 struct dentry *de = ras->de_ras_eeprom_table;
914
915 if (de)
916 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
917}
918
919static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
920 size_t size, loff_t *pos)
921{
922 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
923 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
924 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
925 const size_t orig_size = size;
926 int res = -EFAULT;
927 size_t data_len;
928
929 mutex_lock(&control->ras_tbl_mutex);
930
931 /* We want *pos - data_len > 0, which means there's
932 * bytes to be printed from data.
933 */
934 data_len = strlen(tbl_hdr_str);
935 if (*pos < data_len) {
936 data_len -= *pos;
937 data_len = min_t(size_t, data_len, size);
938 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
939 goto Out;
940 buf += data_len;
941 size -= data_len;
942 *pos += data_len;
943 }
944
945 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
946 if (*pos < data_len && size > 0) {
947 u8 data[tbl_hdr_fmt_size + 1];
948 loff_t lpos;
949
950 snprintf(data, sizeof(data), tbl_hdr_fmt,
951 control->tbl_hdr.header,
952 control->tbl_hdr.version,
953 control->tbl_hdr.first_rec_offset,
954 control->tbl_hdr.tbl_size,
955 control->tbl_hdr.checksum);
956
957 data_len -= *pos;
958 data_len = min_t(size_t, data_len, size);
959 lpos = *pos - strlen(tbl_hdr_str);
960 if (copy_to_user(buf, &data[lpos], data_len))
961 goto Out;
962 buf += data_len;
963 size -= data_len;
964 *pos += data_len;
965 }
966
967 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
968 if (*pos < data_len && size > 0) {
969 loff_t lpos;
970
971 data_len -= *pos;
972 data_len = min_t(size_t, data_len, size);
973 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
974 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
975 goto Out;
976 buf += data_len;
977 size -= data_len;
978 *pos += data_len;
979 }
980
981 data_len = amdgpu_ras_debugfs_table_size(control);
982 if (*pos < data_len && size > 0) {
983 u8 dare[RAS_TABLE_RECORD_SIZE];
984 u8 data[rec_hdr_fmt_size + 1];
985 struct eeprom_table_record record;
986 int s, r;
987
988 /* Find the starting record index
989 */
990 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
991 strlen(rec_hdr_str);
992 s = s / rec_hdr_fmt_size;
993 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
994 strlen(rec_hdr_str);
995 r = r % rec_hdr_fmt_size;
996
997 for ( ; size > 0 && s < control->ras_num_recs; s++) {
998 u32 ai = RAS_RI_TO_AI(control, s);
999 /* Read a single record
1000 */
1001 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
1002 if (res)
1003 goto Out;
1004 __decode_table_record_from_buf(control, &record, dare);
1005 snprintf(data, sizeof(data), rec_hdr_fmt,
1006 s,
1007 RAS_INDEX_TO_OFFSET(control, ai),
1008 record_err_type_str[record.err_type],
1009 record.bank,
1010 record.ts,
1011 record.offset,
1012 record.mem_channel,
1013 record.mcumc_id,
1014 record.retired_page);
1015
1016 data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
1017 if (copy_to_user(buf, &data[r], data_len)) {
1018 res = -EFAULT;
1019 goto Out;
1020 }
1021 buf += data_len;
1022 size -= data_len;
1023 *pos += data_len;
1024 r = 0;
1025 }
1026 }
1027 res = 0;
1028Out:
1029 mutex_unlock(&control->ras_tbl_mutex);
1030 return res < 0 ? res : orig_size - size;
1031}
1032
1033static ssize_t
1034amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
1035 size_t size, loff_t *pos)
1036{
1037 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1038 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1039 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1040 u8 data[81];
1041 int res;
1042
1043 if (!size)
1044 return size;
1045
1046 if (!ras || !control) {
1047 res = snprintf(data, sizeof(data), "Not supported\n");
1048 if (*pos >= res)
1049 return 0;
1050
1051 res -= *pos;
1052 res = min_t(size_t, res, size);
1053
1054 if (copy_to_user(buf, &data[*pos], res))
1055 return -EFAULT;
1056
1057 *pos += res;
1058
1059 return res;
1060 } else {
1061 return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
1062 }
1063}
1064
1065const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
1066 .owner = THIS_MODULE,
1067 .read = amdgpu_ras_debugfs_eeprom_table_read,
1068 .write = NULL,
1069 .llseek = default_llseek,
1070};
1071
1072/**
1073 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
1074 * @control: pointer to control structure
1075 *
1076 * Check the checksum of the stored in EEPROM RAS table.
1077 *
1078 * Return 0 if the checksum is correct,
1079 * positive if it is not correct, and
1080 * -errno on I/O error.
1081 */
1082static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
1083{
1084 struct amdgpu_device *adev = to_amdgpu_device(control);
1085 int buf_size, res;
1086 u8 csum, *buf, *pp;
1087
1088 buf_size = RAS_TABLE_HEADER_SIZE +
1089 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1090 buf = kzalloc(buf_size, GFP_KERNEL);
1091 if (!buf) {
1092 DRM_ERROR("Out of memory checking RAS table checksum.\n");
1093 return -ENOMEM;
1094 }
1095
1096 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1097 control->i2c_address +
1098 control->ras_header_offset,
1099 buf, buf_size);
1100 if (res < buf_size) {
1101 DRM_ERROR("Partial read for checksum, res:%d\n", res);
1102 /* On partial reads, return -EIO.
1103 */
1104 if (res >= 0)
1105 res = -EIO;
1106 goto Out;
1107 }
1108
1109 csum = 0;
1110 for (pp = buf; pp < buf + buf_size; pp++)
1111 csum += *pp;
1112Out:
1113 kfree(buf);
1114 return res < 0 ? res : csum;
1115}
1116
1117int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
1118 bool *exceed_err_limit)
1119{
1120 struct amdgpu_device *adev = to_amdgpu_device(control);
1121 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1122 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1123 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1124 int res;
1125
1126 *exceed_err_limit = false;
1127
1128 if (!__is_ras_eeprom_supported(adev))
1129 return 0;
1130
1131 /* Verify i2c adapter is initialized */
1132 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1133 return -ENOENT;
1134
1135 if (!__get_eeprom_i2c_addr(adev, control))
1136 return -EINVAL;
1137
1138 control->ras_header_offset = RAS_HDR_START;
1139 control->ras_record_offset = RAS_RECORD_START;
1140 control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1141 mutex_init(&control->ras_tbl_mutex);
1142
1143 /* Read the table header from EEPROM address */
1144 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1145 control->i2c_address + control->ras_header_offset,
1146 buf, RAS_TABLE_HEADER_SIZE);
1147 if (res < RAS_TABLE_HEADER_SIZE) {
1148 DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
1149 return res >= 0 ? -EIO : res;
1150 }
1151
1152 __decode_table_header_from_buf(hdr, buf);
1153
1154 control->ras_num_recs = RAS_NUM_RECS(hdr);
1155 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1156
1157 if (hdr->header == RAS_TABLE_HDR_VAL) {
1158 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
1159 control->ras_num_recs);
1160 res = __verify_ras_table_checksum(control);
1161 if (res)
1162 DRM_ERROR("RAS table incorrect checksum or error:%d\n",
1163 res);
1164
1165 /* Warn if we are at 90% of the threshold or above
1166 */
1167 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold)
1168 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d",
1169 control->ras_num_recs,
1170 ras->bad_page_cnt_threshold);
1171 } else if (hdr->header == RAS_TABLE_HDR_BAD &&
1172 amdgpu_bad_page_threshold != 0) {
1173 res = __verify_ras_table_checksum(control);
1174 if (res)
1175 DRM_ERROR("RAS Table incorrect checksum or error:%d\n",
1176 res);
1177 if (ras->bad_page_cnt_threshold > control->ras_num_recs) {
1178 /* This means that, the threshold was increased since
1179 * the last time the system was booted, and now,
1180 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1181 * so that at least one more record can be saved,
1182 * before the page count threshold is reached.
1183 */
1184 dev_info(adev->dev,
1185 "records:%d threshold:%d, resetting "
1186 "RAS table header signature",
1187 control->ras_num_recs,
1188 ras->bad_page_cnt_threshold);
1189 res = amdgpu_ras_eeprom_correct_header_tag(control,
1190 RAS_TABLE_HDR_VAL);
1191 } else {
1192 dev_err(adev->dev, "RAS records:%d exceed threshold:%d",
1193 control->ras_num_recs, ras->bad_page_cnt_threshold);
1194 if (amdgpu_bad_page_threshold == -2) {
1195 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -2.");
1196 res = 0;
1197 } else {
1198 *exceed_err_limit = true;
1199 dev_err(adev->dev,
1200 "RAS records:%d exceed threshold:%d, "
1201 "GPU will not be initialized. Replace this GPU or increase the threshold",
1202 control->ras_num_recs, ras->bad_page_cnt_threshold);
1203 }
1204 }
1205 } else {
1206 DRM_INFO("Creating a new EEPROM table");
1207
1208 res = amdgpu_ras_eeprom_reset_table(control);
1209 }
1210
1211 return res < 0 ? res : 0;
1212}