1/*
 2 * Copyright 2019 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23
24
25void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
26		uint32_t sh_mem_config,
27		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
28		uint32_t sh_mem_bases);
29int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,
30		unsigned int vmid);
31int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id);
32int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
33			uint32_t queue_id, uint32_t __user *wptr,
34			uint32_t wptr_shift, uint32_t wptr_mask,
35			struct mm_struct *mm);
36int kgd_gfx_v9_hiq_mqd_load(struct amdgpu_device *adev, void *mqd,
37			    uint32_t pipe_id, uint32_t queue_id,
38			    uint32_t doorbell_off);
39int kgd_gfx_v9_hqd_dump(struct amdgpu_device *adev,
40			uint32_t pipe_id, uint32_t queue_id,
41			uint32_t (**dump)[2], uint32_t *n_regs);
42bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,
43			uint64_t queue_address, uint32_t pipe_id,
44			uint32_t queue_id);
45int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,
46				enum kfd_preempt_type reset_type,
47				unsigned int utimeout, uint32_t pipe_id,
48				uint32_t queue_id);
49int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,
50					uint32_t gfx_index_val,
51					uint32_t sq_cmd);
52bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
53					uint8_t vmid, uint16_t *p_pasid);
54
55void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,
56			uint32_t vmid, uint64_t page_table_base);
57void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
58		int *pasid_wave_cnt, int *max_waves_per_cu);
59void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,
60		uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr);