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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12#ifndef _UFSHCD_H
13#define _UFSHCD_H
14
15#include <linux/bitfield.h>
16#include <linux/blk-crypto-profile.h>
17#include <linux/blk-mq.h>
18#include <linux/devfreq.h>
19#include <linux/fault-inject.h>
20#include <linux/debugfs.h>
21#include <linux/msi.h>
22#include <linux/pm_runtime.h>
23#include <linux/dma-direction.h>
24#include <scsi/scsi_device.h>
25#include <scsi/scsi_host.h>
26#include <ufs/unipro.h>
27#include <ufs/ufs.h>
28#include <ufs/ufs_quirks.h>
29#include <ufs/ufshci.h>
30
31#define UFSHCD "ufshcd"
32
33struct scsi_device;
34struct ufs_hba;
35
36enum dev_cmd_type {
37 DEV_CMD_TYPE_NOP = 0x0,
38 DEV_CMD_TYPE_QUERY = 0x1,
39 DEV_CMD_TYPE_RPMB = 0x2,
40};
41
42enum ufs_event_type {
43 /* uic specific errors */
44 UFS_EVT_PA_ERR = 0,
45 UFS_EVT_DL_ERR,
46 UFS_EVT_NL_ERR,
47 UFS_EVT_TL_ERR,
48 UFS_EVT_DME_ERR,
49
50 /* fatal errors */
51 UFS_EVT_AUTO_HIBERN8_ERR,
52 UFS_EVT_FATAL_ERR,
53 UFS_EVT_LINK_STARTUP_FAIL,
54 UFS_EVT_RESUME_ERR,
55 UFS_EVT_SUSPEND_ERR,
56 UFS_EVT_WL_SUSP_ERR,
57 UFS_EVT_WL_RES_ERR,
58
59 /* abnormal events */
60 UFS_EVT_DEV_RESET,
61 UFS_EVT_HOST_RESET,
62 UFS_EVT_ABORT,
63
64 UFS_EVT_CNT,
65};
66
67/**
68 * struct uic_command - UIC command structure
69 * @command: UIC command
70 * @argument1: UIC command argument 1
71 * @argument2: UIC command argument 2
72 * @argument3: UIC command argument 3
73 * @cmd_active: Indicate if UIC command is outstanding
74 * @done: UIC command completion
75 */
76struct uic_command {
77 const u32 command;
78 const u32 argument1;
79 u32 argument2;
80 u32 argument3;
81 int cmd_active;
82 struct completion done;
83};
84
85/* Used to differentiate the power management options */
86enum ufs_pm_op {
87 UFS_RUNTIME_PM,
88 UFS_SYSTEM_PM,
89 UFS_SHUTDOWN_PM,
90};
91
92/* Host <-> Device UniPro Link state */
93enum uic_link_state {
94 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
95 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
96 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
97 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
98};
99
100#define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
101#define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
102 UIC_LINK_ACTIVE_STATE)
103#define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
104 UIC_LINK_HIBERN8_STATE)
105#define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
106 UIC_LINK_BROKEN_STATE)
107#define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
108#define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
109 UIC_LINK_ACTIVE_STATE)
110#define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
111 UIC_LINK_HIBERN8_STATE)
112#define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
113 UIC_LINK_BROKEN_STATE)
114
115#define ufshcd_set_ufs_dev_active(h) \
116 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
117#define ufshcd_set_ufs_dev_sleep(h) \
118 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
119#define ufshcd_set_ufs_dev_poweroff(h) \
120 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
121#define ufshcd_set_ufs_dev_deepsleep(h) \
122 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
123#define ufshcd_is_ufs_dev_active(h) \
124 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
125#define ufshcd_is_ufs_dev_sleep(h) \
126 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
127#define ufshcd_is_ufs_dev_poweroff(h) \
128 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
129#define ufshcd_is_ufs_dev_deepsleep(h) \
130 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
131
132/*
133 * UFS Power management levels.
134 * Each level is in increasing order of power savings, except DeepSleep
135 * which is lower than PowerDown with power on but not PowerDown with
136 * power off.
137 */
138enum ufs_pm_level {
139 UFS_PM_LVL_0,
140 UFS_PM_LVL_1,
141 UFS_PM_LVL_2,
142 UFS_PM_LVL_3,
143 UFS_PM_LVL_4,
144 UFS_PM_LVL_5,
145 UFS_PM_LVL_6,
146 UFS_PM_LVL_MAX
147};
148
149struct ufs_pm_lvl_states {
150 enum ufs_dev_pwr_mode dev_state;
151 enum uic_link_state link_state;
152};
153
154/**
155 * struct ufshcd_lrb - local reference block
156 * @utr_descriptor_ptr: UTRD address of the command
157 * @ucd_req_ptr: UCD address of the command
158 * @ucd_rsp_ptr: Response UPIU address for this command
159 * @ucd_prdt_ptr: PRDT address of the command
160 * @utrd_dma_addr: UTRD dma address for debug
161 * @ucd_prdt_dma_addr: PRDT dma address for debug
162 * @ucd_rsp_dma_addr: UPIU response dma address for debug
163 * @ucd_req_dma_addr: UPIU request dma address for debug
164 * @cmd: pointer to SCSI command
165 * @scsi_status: SCSI status of the command
166 * @command_type: SCSI, UFS, Query.
167 * @task_tag: Task tag of the command
168 * @lun: LUN of the command
169 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
170 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
171 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
172 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
173 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
174 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
175 * @data_unit_num: the data unit number for the first block for inline crypto
176 * @req_abort_skip: skip request abort task flag
177 */
178struct ufshcd_lrb {
179 struct utp_transfer_req_desc *utr_descriptor_ptr;
180 struct utp_upiu_req *ucd_req_ptr;
181 struct utp_upiu_rsp *ucd_rsp_ptr;
182 struct ufshcd_sg_entry *ucd_prdt_ptr;
183
184 dma_addr_t utrd_dma_addr;
185 dma_addr_t ucd_req_dma_addr;
186 dma_addr_t ucd_rsp_dma_addr;
187 dma_addr_t ucd_prdt_dma_addr;
188
189 struct scsi_cmnd *cmd;
190 int scsi_status;
191
192 int command_type;
193 int task_tag;
194 u8 lun; /* UPIU LUN id field is only 8-bit wide */
195 bool intr_cmd;
196 ktime_t issue_time_stamp;
197 u64 issue_time_stamp_local_clock;
198 ktime_t compl_time_stamp;
199 u64 compl_time_stamp_local_clock;
200#ifdef CONFIG_SCSI_UFS_CRYPTO
201 int crypto_key_slot;
202 u64 data_unit_num;
203#endif
204
205 bool req_abort_skip;
206};
207
208/**
209 * struct ufs_query_req - parameters for building a query request
210 * @query_func: UPIU header query function
211 * @upiu_req: the query request data
212 */
213struct ufs_query_req {
214 u8 query_func;
215 struct utp_upiu_query upiu_req;
216};
217
218/**
219 * struct ufs_query_resp - UPIU QUERY
220 * @response: device response code
221 * @upiu_res: query response data
222 */
223struct ufs_query_res {
224 struct utp_upiu_query upiu_res;
225};
226
227/**
228 * struct ufs_query - holds relevant data structures for query request
229 * @request: request upiu and function
230 * @descriptor: buffer for sending/receiving descriptor
231 * @response: response upiu and response
232 */
233struct ufs_query {
234 struct ufs_query_req request;
235 u8 *descriptor;
236 struct ufs_query_res response;
237};
238
239/**
240 * struct ufs_dev_cmd - all assosiated fields with device management commands
241 * @type: device management command type - Query, NOP OUT
242 * @lock: lock to allow one command at a time
243 * @complete: internal commands completion
244 * @query: Device management query information
245 */
246struct ufs_dev_cmd {
247 enum dev_cmd_type type;
248 struct mutex lock;
249 struct completion *complete;
250 struct ufs_query query;
251};
252
253/**
254 * struct ufs_clk_info - UFS clock related info
255 * @list: list headed by hba->clk_list_head
256 * @clk: clock node
257 * @name: clock name
258 * @max_freq: maximum frequency supported by the clock
259 * @min_freq: min frequency that can be used for clock scaling
260 * @curr_freq: indicates the current frequency that it is set to
261 * @keep_link_active: indicates that the clk should not be disabled if
262 * link is active
263 * @enabled: variable to check against multiple enable/disable
264 */
265struct ufs_clk_info {
266 struct list_head list;
267 struct clk *clk;
268 const char *name;
269 u32 max_freq;
270 u32 min_freq;
271 u32 curr_freq;
272 bool keep_link_active;
273 bool enabled;
274};
275
276enum ufs_notify_change_status {
277 PRE_CHANGE,
278 POST_CHANGE,
279};
280
281struct ufs_pa_layer_attr {
282 u32 gear_rx;
283 u32 gear_tx;
284 u32 lane_rx;
285 u32 lane_tx;
286 u32 pwr_rx;
287 u32 pwr_tx;
288 u32 hs_rate;
289};
290
291struct ufs_pwr_mode_info {
292 bool is_valid;
293 struct ufs_pa_layer_attr info;
294};
295
296/**
297 * struct ufs_hba_variant_ops - variant specific callbacks
298 * @name: variant name
299 * @max_num_rtt: maximum RTT supported by the host
300 * @init: called when the driver is initialized
301 * @exit: called to cleanup everything done in init
302 * @set_dma_mask: For setting another DMA mask than indicated by the 64AS
303 * capability bit.
304 * @get_ufs_hci_version: called to get UFS HCI version
305 * @clk_scale_notify: notifies that clks are scaled up/down
306 * @setup_clocks: called before touching any of the controller registers
307 * @hce_enable_notify: called before and after HCE enable bit is set to allow
308 * variant specific Uni-Pro initialization.
309 * @link_startup_notify: called before and after Link startup is carried out
310 * to allow variant specific Uni-Pro initialization.
311 * @pwr_change_notify: called before and after a power mode change
312 * is carried out to allow vendor spesific capabilities
313 * to be set. PRE_CHANGE can modify final_params based
314 * on desired_pwr_mode, but POST_CHANGE must not alter
315 * the final_params parameter
316 * @setup_xfer_req: called before any transfer request is issued
317 * to set some things
318 * @setup_task_mgmt: called before any task management request is issued
319 * to set some things
320 * @hibern8_notify: called around hibern8 enter/exit
321 * @apply_dev_quirks: called to apply device specific quirks
322 * @fixup_dev_quirks: called to modify device specific quirks
323 * @suspend: called during host controller PM callback
324 * @resume: called during host controller PM callback
325 * @dbg_register_dump: used to dump controller debug information
326 * @phy_initialization: used to initialize phys
327 * @device_reset: called to issue a reset pulse on the UFS device
328 * @config_scaling_param: called to configure clock scaling parameters
329 * @program_key: program or evict an inline encryption key
330 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT
331 * @event_notify: called to notify important events
332 * @mcq_config_resource: called to configure MCQ platform resources
333 * @get_hba_mac: reports maximum number of outstanding commands supported by
334 * the controller. Should be implemented for UFSHCI 4.0 or later
335 * controllers that are not compliant with the UFSHCI 4.0 specification.
336 * @op_runtime_config: called to config Operation and runtime regs Pointers
337 * @get_outstanding_cqs: called to get outstanding completion queues
338 * @config_esi: called to config Event Specific Interrupt
339 * @config_scsi_dev: called to configure SCSI device parameters
340 */
341struct ufs_hba_variant_ops {
342 const char *name;
343 int max_num_rtt;
344 int (*init)(struct ufs_hba *);
345 void (*exit)(struct ufs_hba *);
346 u32 (*get_ufs_hci_version)(struct ufs_hba *);
347 int (*set_dma_mask)(struct ufs_hba *);
348 int (*clk_scale_notify)(struct ufs_hba *, bool,
349 enum ufs_notify_change_status);
350 int (*setup_clocks)(struct ufs_hba *, bool,
351 enum ufs_notify_change_status);
352 int (*hce_enable_notify)(struct ufs_hba *,
353 enum ufs_notify_change_status);
354 int (*link_startup_notify)(struct ufs_hba *,
355 enum ufs_notify_change_status);
356 int (*pwr_change_notify)(struct ufs_hba *,
357 enum ufs_notify_change_status status,
358 struct ufs_pa_layer_attr *desired_pwr_mode,
359 struct ufs_pa_layer_attr *final_params);
360 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,
361 bool is_scsi_cmd);
362 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
363 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
364 enum ufs_notify_change_status);
365 int (*apply_dev_quirks)(struct ufs_hba *hba);
366 void (*fixup_dev_quirks)(struct ufs_hba *hba);
367 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,
368 enum ufs_notify_change_status);
369 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
370 void (*dbg_register_dump)(struct ufs_hba *hba);
371 int (*phy_initialization)(struct ufs_hba *);
372 int (*device_reset)(struct ufs_hba *hba);
373 void (*config_scaling_param)(struct ufs_hba *hba,
374 struct devfreq_dev_profile *profile,
375 struct devfreq_simple_ondemand_data *data);
376 int (*program_key)(struct ufs_hba *hba,
377 const union ufs_crypto_cfg_entry *cfg, int slot);
378 int (*fill_crypto_prdt)(struct ufs_hba *hba,
379 const struct bio_crypt_ctx *crypt_ctx,
380 void *prdt, unsigned int num_segments);
381 void (*event_notify)(struct ufs_hba *hba,
382 enum ufs_event_type evt, void *data);
383 int (*mcq_config_resource)(struct ufs_hba *hba);
384 int (*get_hba_mac)(struct ufs_hba *hba);
385 int (*op_runtime_config)(struct ufs_hba *hba);
386 int (*get_outstanding_cqs)(struct ufs_hba *hba,
387 unsigned long *ocqs);
388 int (*config_esi)(struct ufs_hba *hba);
389 void (*config_scsi_dev)(struct scsi_device *sdev);
390};
391
392/* clock gating state */
393enum clk_gating_state {
394 CLKS_OFF,
395 CLKS_ON,
396 REQ_CLKS_OFF,
397 REQ_CLKS_ON,
398};
399
400/**
401 * struct ufs_clk_gating - UFS clock gating related info
402 * @gate_work: worker to turn off clocks after some delay as specified in
403 * delay_ms
404 * @ungate_work: worker to turn on clocks that will be used in case of
405 * interrupt context
406 * @clk_gating_workq: workqueue for clock gating work.
407 * @lock: serialize access to some struct ufs_clk_gating members. An outer lock
408 * relative to the host lock
409 * @state: the current clocks state
410 * @delay_ms: gating delay in ms
411 * @is_suspended: clk gating is suspended when set to 1 which can be used
412 * during suspend/resume
413 * @delay_attr: sysfs attribute to control delay_attr
414 * @enable_attr: sysfs attribute to enable/disable clock gating
415 * @is_enabled: Indicates the current status of clock gating
416 * @is_initialized: Indicates whether clock gating is initialized or not
417 * @active_reqs: number of requests that are pending and should be waited for
418 * completion before gating clocks.
419 */
420struct ufs_clk_gating {
421 struct delayed_work gate_work;
422 struct work_struct ungate_work;
423 struct workqueue_struct *clk_gating_workq;
424
425 spinlock_t lock;
426
427 enum clk_gating_state state;
428 unsigned long delay_ms;
429 bool is_suspended;
430 struct device_attribute delay_attr;
431 struct device_attribute enable_attr;
432 bool is_enabled;
433 bool is_initialized;
434 int active_reqs;
435};
436
437/**
438 * struct ufs_clk_scaling - UFS clock scaling related data
439 * @active_reqs: number of requests that are pending. If this is zero when
440 * devfreq ->target() function is called then schedule "suspend_work" to
441 * suspend devfreq.
442 * @tot_busy_t: Total busy time in current polling window
443 * @window_start_t: Start time (in jiffies) of the current polling window
444 * @busy_start_t: Start time of current busy period
445 * @enable_attr: sysfs attribute to enable/disable clock scaling
446 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
447 * one keeps track of previous power mode.
448 * @workq: workqueue to schedule devfreq suspend/resume work
449 * @suspend_work: worker to suspend devfreq
450 * @resume_work: worker to resume devfreq
451 * @target_freq: frequency requested by devfreq framework
452 * @min_gear: lowest HS gear to scale down to
453 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
454 * clkscale_enable sysfs node
455 * @is_allowed: tracks if scaling is currently allowed or not, used to block
456 * clock scaling which is not invoked from devfreq governor
457 * @is_initialized: Indicates whether clock scaling is initialized or not
458 * @is_busy_started: tracks if busy period has started or not
459 * @is_suspended: tracks if devfreq is suspended or not
460 */
461struct ufs_clk_scaling {
462 int active_reqs;
463 unsigned long tot_busy_t;
464 ktime_t window_start_t;
465 ktime_t busy_start_t;
466 struct device_attribute enable_attr;
467 struct ufs_pa_layer_attr saved_pwr_info;
468 struct workqueue_struct *workq;
469 struct work_struct suspend_work;
470 struct work_struct resume_work;
471 unsigned long target_freq;
472 u32 min_gear;
473 bool is_enabled;
474 bool is_allowed;
475 bool is_initialized;
476 bool is_busy_started;
477 bool is_suspended;
478 bool suspend_on_no_request;
479};
480
481#define UFS_EVENT_HIST_LENGTH 8
482/**
483 * struct ufs_event_hist - keeps history of errors
484 * @pos: index to indicate cyclic buffer position
485 * @val: cyclic buffer for registers value
486 * @tstamp: cyclic buffer for time stamp
487 * @cnt: error counter
488 */
489struct ufs_event_hist {
490 int pos;
491 u32 val[UFS_EVENT_HIST_LENGTH];
492 u64 tstamp[UFS_EVENT_HIST_LENGTH];
493 unsigned long long cnt;
494};
495
496/**
497 * struct ufs_stats - keeps usage/err statistics
498 * @last_intr_status: record the last interrupt status.
499 * @last_intr_ts: record the last interrupt timestamp.
500 * @hibern8_exit_cnt: Counter to keep track of number of exits,
501 * reset this after link-startup.
502 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
503 * Clear after the first successful command completion.
504 * @event: array with event history.
505 */
506struct ufs_stats {
507 u32 last_intr_status;
508 u64 last_intr_ts;
509
510 u32 hibern8_exit_cnt;
511 u64 last_hibern8_exit_tstamp;
512 struct ufs_event_hist event[UFS_EVT_CNT];
513};
514
515/**
516 * enum ufshcd_state - UFS host controller state
517 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
518 * processing.
519 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
520 * SCSI commands.
521 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
522 * SCSI commands may be submitted to the controller.
523 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
524 * newly submitted SCSI commands with error code DID_BAD_TARGET.
525 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
526 * failed. Fail all SCSI commands with error code DID_ERROR.
527 */
528enum ufshcd_state {
529 UFSHCD_STATE_RESET,
530 UFSHCD_STATE_OPERATIONAL,
531 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
532 UFSHCD_STATE_EH_SCHEDULED_FATAL,
533 UFSHCD_STATE_ERROR,
534};
535
536enum ufshcd_quirks {
537 /* Interrupt aggregation support is broken */
538 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
539
540 /*
541 * delay before each dme command is required as the unipro
542 * layer has shown instabilities
543 */
544 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
545
546 /*
547 * If UFS host controller is having issue in processing LCC (Line
548 * Control Command) coming from device then enable this quirk.
549 * When this quirk is enabled, host controller driver should disable
550 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
551 * attribute of device to 0).
552 */
553 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
554
555 /*
556 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
557 * inbound Link supports unterminated line in HS mode. Setting this
558 * attribute to 1 fixes moving to HS gear.
559 */
560 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
561
562 /*
563 * This quirk needs to be enabled if the host controller only allows
564 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
565 * SLOW AUTO).
566 */
567 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
568
569 /*
570 * This quirk needs to be enabled if the host controller doesn't
571 * advertise the correct version in UFS_VER register. If this quirk
572 * is enabled, standard UFS host driver will call the vendor specific
573 * ops (get_ufs_hci_version) to get the correct version.
574 */
575 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
576
577 /*
578 * Clear handling for transfer/task request list is just opposite.
579 */
580 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
581
582 /*
583 * This quirk needs to be enabled if host controller doesn't allow
584 * that the interrupt aggregation timer and counter are reset by s/w.
585 */
586 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
587
588 /*
589 * This quirks needs to be enabled if host controller cannot be
590 * enabled via HCE register.
591 */
592 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
593
594 /*
595 * This quirk needs to be enabled if the host controller regards
596 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
597 */
598 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
599
600 /*
601 * This quirk needs to be enabled if the host controller reports
602 * OCS FATAL ERROR with device error through sense data
603 */
604 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
605
606 /*
607 * This quirk needs to be enabled if the host controller has
608 * auto-hibernate capability but it doesn't work.
609 */
610 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
611
612 /*
613 * This quirk needs to disable manual flush for write booster
614 */
615 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
616
617 /*
618 * This quirk needs to disable unipro timeout values
619 * before power mode change
620 */
621 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
622
623 /*
624 * This quirk needs to be enabled if the host controller does not
625 * support UIC command
626 */
627 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
628
629 /*
630 * This quirk needs to be enabled if the host controller cannot
631 * support physical host configuration.
632 */
633 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
634
635 /*
636 * This quirk needs to be enabled if the host controller has
637 * auto-hibernate capability but it's FASTAUTO only.
638 */
639 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
640
641 /*
642 * This quirk needs to be enabled if the host controller needs
643 * to reinit the device after switching to maximum gear.
644 */
645 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
646
647 /*
648 * Some host raises interrupt (per queue) in addition to
649 * CQES (traditional) when ESI is disabled.
650 * Enable this quirk will disable CQES and use per queue interrupt.
651 */
652 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
653
654 /*
655 * Some host does not implement SQ Run Time Command (SQRTC) register
656 * thus need this quirk to skip related flow.
657 */
658 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
659
660 /*
661 * This quirk needs to be enabled if the host controller supports inline
662 * encryption but it needs to initialize the crypto capabilities in a
663 * nonstandard way and/or needs to override blk_crypto_ll_ops. If
664 * enabled, the standard code won't initialize the blk_crypto_profile;
665 * ufs_hba_variant_ops::init() must do it instead.
666 */
667 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22,
668
669 /*
670 * This quirk needs to be enabled if the host controller supports inline
671 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e.
672 * host controller initialization fails if that bit is set.
673 */
674 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23,
675
676 /*
677 * This quirk needs to be enabled if the host controller driver copies
678 * cryptographic keys into the PRDT in order to send them to hardware,
679 * and therefore the PRDT should be zeroized after each request (as per
680 * the standard best practice for managing keys).
681 */
682 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24,
683
684 /*
685 * This quirk indicates that the controller reports the value 1 (not
686 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the
687 * Controller Capabilities register although it supports the legacy
688 * single doorbell mode.
689 */
690 UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25,
691};
692
693enum ufshcd_caps {
694 /* Allow dynamic clk gating */
695 UFSHCD_CAP_CLK_GATING = 1 << 0,
696
697 /* Allow hiberb8 with clk gating */
698 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
699
700 /* Allow dynamic clk scaling */
701 UFSHCD_CAP_CLK_SCALING = 1 << 2,
702
703 /* Allow auto bkops to enabled during runtime suspend */
704 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
705
706 /*
707 * This capability allows host controller driver to use the UFS HCI's
708 * interrupt aggregation capability.
709 * CAUTION: Enabling this might reduce overall UFS throughput.
710 */
711 UFSHCD_CAP_INTR_AGGR = 1 << 4,
712
713 /*
714 * This capability allows the device auto-bkops to be always enabled
715 * except during suspend (both runtime and suspend).
716 * Enabling this capability means that device will always be allowed
717 * to do background operation when it's active but it might degrade
718 * the performance of ongoing read/write operations.
719 */
720 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
721
722 /*
723 * This capability allows host controller driver to automatically
724 * enable runtime power management by itself instead of waiting
725 * for userspace to control the power management.
726 */
727 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
728
729 /*
730 * This capability allows the host controller driver to turn-on
731 * WriteBooster, if the underlying device supports it and is
732 * provisioned to be used. This would increase the write performance.
733 */
734 UFSHCD_CAP_WB_EN = 1 << 7,
735
736 /*
737 * This capability allows the host controller driver to use the
738 * inline crypto engine, if it is present
739 */
740 UFSHCD_CAP_CRYPTO = 1 << 8,
741
742 /*
743 * This capability allows the controller regulators to be put into
744 * lpm mode aggressively during clock gating.
745 * This would increase power savings.
746 */
747 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
748
749 /*
750 * This capability allows the host controller driver to use DeepSleep,
751 * if it is supported by the UFS device. The host controller driver must
752 * support device hardware reset via the hba->device_reset() callback,
753 * in order to exit DeepSleep state.
754 */
755 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
756
757 /*
758 * This capability allows the host controller driver to use temperature
759 * notification if it is supported by the UFS device.
760 */
761 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,
762
763 /*
764 * Enable WriteBooster when scaling up the clock and disable
765 * WriteBooster when scaling the clock down.
766 */
767 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
768};
769
770struct ufs_hba_variant_params {
771 struct devfreq_dev_profile devfreq_profile;
772 struct devfreq_simple_ondemand_data ondemand_data;
773 u16 hba_enable_delay_us;
774 u32 wb_flush_threshold;
775};
776
777struct ufs_hba_monitor {
778 unsigned long chunk_size;
779
780 unsigned long nr_sec_rw[2];
781 ktime_t total_busy[2];
782
783 unsigned long nr_req[2];
784 /* latencies*/
785 ktime_t lat_sum[2];
786 ktime_t lat_max[2];
787 ktime_t lat_min[2];
788
789 u32 nr_queued[2];
790 ktime_t busy_start_ts[2];
791
792 ktime_t enabled_ts;
793 bool enabled;
794};
795
796/**
797 * struct ufshcd_res_info_t - MCQ related resource regions
798 *
799 * @name: resource name
800 * @resource: pointer to resource region
801 * @base: register base address
802 */
803struct ufshcd_res_info {
804 const char *name;
805 struct resource *resource;
806 void __iomem *base;
807};
808
809enum ufshcd_res {
810 RES_UFS,
811 RES_MCQ,
812 RES_MCQ_SQD,
813 RES_MCQ_SQIS,
814 RES_MCQ_CQD,
815 RES_MCQ_CQIS,
816 RES_MCQ_VS,
817 RES_MAX,
818};
819
820/**
821 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
822 *
823 * @offset: Doorbell Address Offset
824 * @stride: Steps proportional to queue [0...31]
825 * @base: base address
826 */
827struct ufshcd_mcq_opr_info_t {
828 unsigned long offset;
829 unsigned long stride;
830 void __iomem *base;
831};
832
833enum ufshcd_mcq_opr {
834 OPR_SQD,
835 OPR_SQIS,
836 OPR_CQD,
837 OPR_CQIS,
838 OPR_MAX,
839};
840
841/**
842 * struct ufs_hba - per adapter private structure
843 * @mmio_base: UFSHCI base register address
844 * @ucdl_base_addr: UFS Command Descriptor base address
845 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
846 * @utmrdl_base_addr: UTP Task Management Descriptor base address
847 * @ucdl_dma_addr: UFS Command Descriptor DMA address
848 * @utrdl_dma_addr: UTRDL DMA address
849 * @utmrdl_dma_addr: UTMRDL DMA address
850 * @host: Scsi_Host instance of the driver
851 * @dev: device handle
852 * @ufs_device_wlun: WLUN that controls the entire UFS device.
853 * @hwmon_device: device instance registered with the hwmon core.
854 * @curr_dev_pwr_mode: active UFS device power mode.
855 * @uic_link_state: active state of the link to the UFS device.
856 * @rpm_lvl: desired UFS power management level during runtime PM.
857 * @spm_lvl: desired UFS power management level during system PM.
858 * @pm_op_in_progress: whether or not a PM operation is in progress.
859 * @ahit: value of Auto-Hibernate Idle Timer register.
860 * @lrb: local reference block
861 * @outstanding_tasks: Bits representing outstanding task requests
862 * @outstanding_lock: Protects @outstanding_reqs.
863 * @outstanding_reqs: Bits representing outstanding transfer requests
864 * @capabilities: UFS Controller Capabilities
865 * @mcq_capabilities: UFS Multi Circular Queue capabilities
866 * @nutrs: Transfer Request Queue depth supported by controller
867 * @nortt - Max outstanding RTTs supported by controller
868 * @nutmrs: Task Management Queue depth supported by controller
869 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
870 * @ufs_version: UFS Version to which controller complies
871 * @vops: pointer to variant specific operations
872 * @vps: pointer to variant specific parameters
873 * @priv: pointer to variant specific private data
874 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
875 * @irq: Irq number of the controller
876 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
877 * @dev_ref_clk_freq: reference clock frequency
878 * @quirks: bitmask with information about deviations from the UFSHCI standard.
879 * @dev_quirks: bitmask with information about deviations from the UFS standard.
880 * @tmf_tag_set: TMF tag set.
881 * @tmf_queue: Used to allocate TMF tags.
882 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
883 * @active_uic_cmd: pointer to active UIC command.
884 * @uic_cmd_mutex: mutex used for serializing UIC command processing.
885 * @uic_async_done: completion used to wait for power mode or hibernation state
886 * changes.
887 * @ufshcd_state: UFSHCD state
888 * @eh_flags: Error handling flags
889 * @intr_mask: Interrupt Mask Bits
890 * @ee_ctrl_mask: Exception event control mask
891 * @ee_drv_mask: Exception event mask for driver
892 * @ee_usr_mask: Exception event mask for user (set via debugfs)
893 * @ee_ctrl_mutex: Used to serialize exception event information.
894 * @is_powered: flag to check if HBA is powered
895 * @shutting_down: flag to check if shutdown has been invoked
896 * @host_sem: semaphore used to serialize concurrent contexts
897 * @eh_wq: Workqueue that eh_work works on
898 * @eh_work: Worker to handle UFS errors that require s/w attention
899 * @eeh_work: Worker to handle exception events
900 * @errors: HBA errors
901 * @uic_error: UFS interconnect layer error status
902 * @saved_err: sticky error mask
903 * @saved_uic_err: sticky UIC error mask
904 * @ufs_stats: various error counters
905 * @force_reset: flag to force eh_work perform a full reset
906 * @force_pmc: flag to force a power mode change
907 * @silence_err_logs: flag to silence error logs
908 * @dev_cmd: ufs device management command information
909 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
910 * @nop_out_timeout: NOP OUT timeout value
911 * @dev_info: information about the UFS device
912 * @auto_bkops_enabled: to track whether bkops is enabled in device
913 * @vreg_info: UFS device voltage regulator information
914 * @clk_list_head: UFS host controller clocks list node head
915 * @use_pm_opp: Indicates whether OPP based scaling is used or not
916 * @req_abort_count: number of times ufshcd_abort() has been called
917 * @lanes_per_direction: number of lanes per data direction between the UFS
918 * controller and the UFS device.
919 * @pwr_info: holds current power mode
920 * @max_pwr_info: keeps the device max valid pwm
921 * @clk_gating: information related to clock gating
922 * @caps: bitmask with information about UFS controller capabilities
923 * @devfreq: frequency scaling information owned by the devfreq core
924 * @clk_scaling: frequency scaling information owned by the UFS driver
925 * @system_suspending: system suspend has been started and system resume has
926 * not yet finished.
927 * @is_sys_suspended: UFS device has been suspended because of system suspend
928 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
929 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
930 * device is known or not.
931 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
932 * @clk_scaling_lock: used to serialize device commands and clock scaling
933 * @desc_size: descriptor sizes reported by device
934 * @bsg_dev: struct device associated with the BSG queue
935 * @bsg_queue: BSG queue associated with the UFS controller
936 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
937 * management) after the UFS device has finished a WriteBooster buffer
938 * flush or auto BKOP.
939 * @monitor: statistics about UFS commands
940 * @crypto_capabilities: Content of crypto capabilities register (0x100)
941 * @crypto_cap_array: Array of crypto capabilities
942 * @crypto_cfg_register: Start of the crypto cfg array
943 * @crypto_profile: the crypto profile of this hba (if applicable)
944 * @debugfs_root: UFS controller debugfs root directory
945 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
946 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
947 * ee_ctrl_mask
948 * @luns_avail: number of regular and well known LUNs supported by the UFS
949 * device
950 * @nr_hw_queues: number of hardware queues configured
951 * @nr_queues: number of Queues of different queue types
952 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
953 * ufshcd_resume_complete()
954 * @ext_iid_sup: is EXT_IID is supported by UFSHC
955 * @mcq_sup: is mcq supported by UFSHC
956 * @mcq_enabled: is mcq ready to accept requests
957 * @res: array of resource info of MCQ registers
958 * @mcq_base: Multi circular queue registers base address
959 * @uhq: array of supported hardware queues
960 * @dev_cmd_queue: Queue for issuing device management commands
961 * @mcq_opr: MCQ operation and runtime registers
962 * @ufs_rtc_update_work: A work for UFS RTC periodic update
963 * @pm_qos_req: PM QoS request handle
964 * @pm_qos_enabled: flag to check if pm qos is enabled
965 */
966struct ufs_hba {
967 void __iomem *mmio_base;
968
969 /* Virtual memory reference */
970 struct utp_transfer_cmd_desc *ucdl_base_addr;
971 struct utp_transfer_req_desc *utrdl_base_addr;
972 struct utp_task_req_desc *utmrdl_base_addr;
973
974 /* DMA memory reference */
975 dma_addr_t ucdl_dma_addr;
976 dma_addr_t utrdl_dma_addr;
977 dma_addr_t utmrdl_dma_addr;
978
979 struct Scsi_Host *host;
980 struct device *dev;
981 struct scsi_device *ufs_device_wlun;
982
983#ifdef CONFIG_SCSI_UFS_HWMON
984 struct device *hwmon_device;
985#endif
986
987 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
988 enum uic_link_state uic_link_state;
989 /* Desired UFS power management level during runtime PM */
990 enum ufs_pm_level rpm_lvl;
991 /* Desired UFS power management level during system PM */
992 enum ufs_pm_level spm_lvl;
993 int pm_op_in_progress;
994
995 /* Auto-Hibernate Idle Timer register value */
996 u32 ahit;
997
998 struct ufshcd_lrb *lrb;
999
1000 unsigned long outstanding_tasks;
1001 spinlock_t outstanding_lock;
1002 unsigned long outstanding_reqs;
1003
1004 u32 capabilities;
1005 int nutrs;
1006 int nortt;
1007 u32 mcq_capabilities;
1008 int nutmrs;
1009 u32 reserved_slot;
1010 u32 ufs_version;
1011 const struct ufs_hba_variant_ops *vops;
1012 struct ufs_hba_variant_params *vps;
1013 void *priv;
1014#ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1015 size_t sg_entry_size;
1016#endif
1017 unsigned int irq;
1018 bool is_irq_enabled;
1019 enum ufs_ref_clk_freq dev_ref_clk_freq;
1020
1021 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
1022
1023 /* Device deviations from standard UFS device spec. */
1024 unsigned int dev_quirks;
1025
1026 struct blk_mq_tag_set tmf_tag_set;
1027 struct request_queue *tmf_queue;
1028 struct request **tmf_rqs;
1029
1030 struct uic_command *active_uic_cmd;
1031 struct mutex uic_cmd_mutex;
1032 struct completion *uic_async_done;
1033
1034 enum ufshcd_state ufshcd_state;
1035 u32 eh_flags;
1036 u32 intr_mask;
1037 u16 ee_ctrl_mask;
1038 u16 ee_drv_mask;
1039 u16 ee_usr_mask;
1040 struct mutex ee_ctrl_mutex;
1041 bool is_powered;
1042 bool shutting_down;
1043 struct semaphore host_sem;
1044
1045 /* Work Queues */
1046 struct workqueue_struct *eh_wq;
1047 struct work_struct eh_work;
1048 struct work_struct eeh_work;
1049
1050 /* HBA Errors */
1051 u32 errors;
1052 u32 uic_error;
1053 u32 saved_err;
1054 u32 saved_uic_err;
1055 struct ufs_stats ufs_stats;
1056 bool force_reset;
1057 bool force_pmc;
1058 bool silence_err_logs;
1059
1060 /* Device management request data */
1061 struct ufs_dev_cmd dev_cmd;
1062 ktime_t last_dme_cmd_tstamp;
1063 int nop_out_timeout;
1064
1065 /* Keeps information of the UFS device connected to this host */
1066 struct ufs_dev_info dev_info;
1067 bool auto_bkops_enabled;
1068 struct ufs_vreg_info vreg_info;
1069 struct list_head clk_list_head;
1070 bool use_pm_opp;
1071
1072 /* Number of requests aborts */
1073 int req_abort_count;
1074
1075 /* Number of lanes available (1 or 2) for Rx/Tx */
1076 u32 lanes_per_direction;
1077 struct ufs_pa_layer_attr pwr_info;
1078 struct ufs_pwr_mode_info max_pwr_info;
1079
1080 struct ufs_clk_gating clk_gating;
1081 /* Control to enable/disable host capabilities */
1082 u32 caps;
1083
1084 struct devfreq *devfreq;
1085 struct ufs_clk_scaling clk_scaling;
1086 bool system_suspending;
1087 bool is_sys_suspended;
1088
1089 enum bkops_status urgent_bkops_lvl;
1090 bool is_urgent_bkops_lvl_checked;
1091
1092 struct mutex wb_mutex;
1093 struct rw_semaphore clk_scaling_lock;
1094
1095 struct device bsg_dev;
1096 struct request_queue *bsg_queue;
1097 struct delayed_work rpm_dev_flush_recheck_work;
1098
1099 struct ufs_hba_monitor monitor;
1100
1101#ifdef CONFIG_SCSI_UFS_CRYPTO
1102 union ufs_crypto_capabilities crypto_capabilities;
1103 union ufs_crypto_cap_entry *crypto_cap_array;
1104 u32 crypto_cfg_register;
1105 struct blk_crypto_profile crypto_profile;
1106#endif
1107#ifdef CONFIG_DEBUG_FS
1108 struct dentry *debugfs_root;
1109 struct delayed_work debugfs_ee_work;
1110 u32 debugfs_ee_rate_limit_ms;
1111#endif
1112#ifdef CONFIG_SCSI_UFS_FAULT_INJECTION
1113 struct fault_attr trigger_eh_attr;
1114 struct fault_attr timeout_attr;
1115#endif
1116 u32 luns_avail;
1117 unsigned int nr_hw_queues;
1118 unsigned int nr_queues[HCTX_MAX_TYPES];
1119 bool complete_put;
1120 bool ext_iid_sup;
1121 bool scsi_host_added;
1122 bool mcq_sup;
1123 bool lsdb_sup;
1124 bool mcq_enabled;
1125 struct ufshcd_res_info res[RES_MAX];
1126 void __iomem *mcq_base;
1127 struct ufs_hw_queue *uhq;
1128 struct ufs_hw_queue *dev_cmd_queue;
1129 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1130
1131 struct delayed_work ufs_rtc_update_work;
1132 struct pm_qos_request pm_qos_req;
1133 bool pm_qos_enabled;
1134};
1135
1136/**
1137 * struct ufs_hw_queue - per hardware queue structure
1138 * @mcq_sq_head: base address of submission queue head pointer
1139 * @mcq_sq_tail: base address of submission queue tail pointer
1140 * @mcq_cq_head: base address of completion queue head pointer
1141 * @mcq_cq_tail: base address of completion queue tail pointer
1142 * @sqe_base_addr: submission queue entry base address
1143 * @sqe_dma_addr: submission queue dma address
1144 * @cqe_base_addr: completion queue base address
1145 * @cqe_dma_addr: completion queue dma address
1146 * @max_entries: max number of slots in this hardware queue
1147 * @id: hardware queue ID
1148 * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1149 * @sq_lock: serialize submission queue access
1150 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1151 * @cq_head_slot: current slot to which CQ head pointer is pointing
1152 * @cq_lock: Synchronize between multiple polling instances
1153 * @sq_mutex: prevent submission queue concurrent access
1154 */
1155struct ufs_hw_queue {
1156 void __iomem *mcq_sq_head;
1157 void __iomem *mcq_sq_tail;
1158 void __iomem *mcq_cq_head;
1159 void __iomem *mcq_cq_tail;
1160
1161 struct utp_transfer_req_desc *sqe_base_addr;
1162 dma_addr_t sqe_dma_addr;
1163 struct cq_entry *cqe_base_addr;
1164 dma_addr_t cqe_dma_addr;
1165 u32 max_entries;
1166 u32 id;
1167 u32 sq_tail_slot;
1168 spinlock_t sq_lock;
1169 u32 cq_tail_slot;
1170 u32 cq_head_slot;
1171 spinlock_t cq_lock;
1172 /* prevent concurrent access to submission queue */
1173 struct mutex sq_mutex;
1174};
1175
1176#define MCQ_QCFG_SIZE 0x40
1177
1178static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1179 enum ufshcd_mcq_opr opr, int idx)
1180{
1181 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1182}
1183
1184static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx)
1185{
1186 return reg + MCQ_QCFG_SIZE * idx;
1187}
1188
1189#ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1190static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1191{
1192 return hba->sg_entry_size;
1193}
1194
1195static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1196{
1197 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1198 hba->sg_entry_size = sg_entry_size;
1199}
1200#else
1201static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1202{
1203 return sizeof(struct ufshcd_sg_entry);
1204}
1205
1206#define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1207 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1208#endif
1209
1210static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1211{
1212 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1213}
1214
1215/* Returns true if clocks can be gated. Otherwise false */
1216static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1217{
1218 return hba->caps & UFSHCD_CAP_CLK_GATING;
1219}
1220static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1221{
1222 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1223}
1224static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1225{
1226 return hba->caps & UFSHCD_CAP_CLK_SCALING;
1227}
1228static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1229{
1230 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1231}
1232static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1233{
1234 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1235}
1236
1237static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1238{
1239 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1240 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1241}
1242
1243static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1244{
1245 return !!(ufshcd_is_link_hibern8(hba) &&
1246 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1247}
1248
1249static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1250{
1251 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1252 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1253}
1254
1255static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1256{
1257 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1258}
1259
1260static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1261{
1262 return hba->caps & UFSHCD_CAP_WB_EN;
1263}
1264
1265static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1266{
1267 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1268}
1269
1270#define ufsmcq_writel(hba, val, reg) \
1271 writel((val), (hba)->mcq_base + (reg))
1272#define ufsmcq_readl(hba, reg) \
1273 readl((hba)->mcq_base + (reg))
1274
1275#define ufsmcq_writelx(hba, val, reg) \
1276 writel_relaxed((val), (hba)->mcq_base + (reg))
1277#define ufsmcq_readlx(hba, reg) \
1278 readl_relaxed((hba)->mcq_base + (reg))
1279
1280#define ufshcd_writel(hba, val, reg) \
1281 writel((val), (hba)->mmio_base + (reg))
1282#define ufshcd_readl(hba, reg) \
1283 readl((hba)->mmio_base + (reg))
1284
1285/**
1286 * ufshcd_rmwl - perform read/modify/write for a controller register
1287 * @hba: per adapter instance
1288 * @mask: mask to apply on read value
1289 * @val: actual value to write
1290 * @reg: register address
1291 */
1292static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1293{
1294 u32 tmp;
1295
1296 tmp = ufshcd_readl(hba, reg);
1297 tmp &= ~mask;
1298 tmp |= (val & mask);
1299 ufshcd_writel(hba, tmp, reg);
1300}
1301
1302void ufshcd_enable_irq(struct ufs_hba *hba);
1303void ufshcd_disable_irq(struct ufs_hba *hba);
1304int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1305int ufshcd_hba_enable(struct ufs_hba *hba);
1306int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1307int ufshcd_link_recovery(struct ufs_hba *hba);
1308int ufshcd_make_hba_operational(struct ufs_hba *hba);
1309void ufshcd_remove(struct ufs_hba *);
1310int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1311int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1312void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1313void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1314void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1315void ufshcd_hba_stop(struct ufs_hba *hba);
1316void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1317void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1318unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba);
1319u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1320void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1321unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1322 struct ufs_hw_queue *hwq);
1323void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1324void ufshcd_mcq_enable(struct ufs_hba *hba);
1325void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1326void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1327
1328int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1329 struct dev_pm_opp *opp, void *data,
1330 bool scaling_down);
1331/**
1332 * ufshcd_set_variant - set variant specific data to the hba
1333 * @hba: per adapter instance
1334 * @variant: pointer to variant specific data
1335 */
1336static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1337{
1338 BUG_ON(!hba);
1339 hba->priv = variant;
1340}
1341
1342/**
1343 * ufshcd_get_variant - get variant specific data from the hba
1344 * @hba: per adapter instance
1345 */
1346static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1347{
1348 BUG_ON(!hba);
1349 return hba->priv;
1350}
1351
1352#ifdef CONFIG_PM
1353extern int ufshcd_runtime_suspend(struct device *dev);
1354extern int ufshcd_runtime_resume(struct device *dev);
1355#endif
1356#ifdef CONFIG_PM_SLEEP
1357extern int ufshcd_system_suspend(struct device *dev);
1358extern int ufshcd_system_resume(struct device *dev);
1359extern int ufshcd_system_freeze(struct device *dev);
1360extern int ufshcd_system_thaw(struct device *dev);
1361extern int ufshcd_system_restore(struct device *dev);
1362#endif
1363
1364extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1365 int agreed_gear,
1366 int adapt_val);
1367extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1368 u8 attr_set, u32 mib_val, u8 peer);
1369extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1370 u32 *mib_val, u8 peer);
1371extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1372 struct ufs_pa_layer_attr *desired_pwr_mode);
1373extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1374
1375/* UIC command interfaces for DME primitives */
1376#define DME_LOCAL 0
1377#define DME_PEER 1
1378#define ATTR_SET_NOR 0 /* NORMAL */
1379#define ATTR_SET_ST 1 /* STATIC */
1380
1381static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1382 u32 mib_val)
1383{
1384 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1385 mib_val, DME_LOCAL);
1386}
1387
1388static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1389 u32 mib_val)
1390{
1391 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1392 mib_val, DME_LOCAL);
1393}
1394
1395static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1396 u32 mib_val)
1397{
1398 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1399 mib_val, DME_PEER);
1400}
1401
1402static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1403 u32 mib_val)
1404{
1405 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1406 mib_val, DME_PEER);
1407}
1408
1409static inline int ufshcd_dme_get(struct ufs_hba *hba,
1410 u32 attr_sel, u32 *mib_val)
1411{
1412 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1413}
1414
1415static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1416 u32 attr_sel, u32 *mib_val)
1417{
1418 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1419}
1420
1421static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1422{
1423 return (pwr_info->pwr_rx == FAST_MODE ||
1424 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1425 (pwr_info->pwr_tx == FAST_MODE ||
1426 pwr_info->pwr_tx == FASTAUTO_MODE);
1427}
1428
1429static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1430{
1431 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1432}
1433
1434void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1435void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1436 const struct ufs_dev_quirk *fixups);
1437#define SD_ASCII_STD true
1438#define SD_RAW false
1439int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1440 u8 **buf, bool ascii);
1441
1442void ufshcd_hold(struct ufs_hba *hba);
1443void ufshcd_release(struct ufs_hba *hba);
1444
1445void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1446
1447int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1448
1449int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1450
1451int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1452 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1453 struct ufs_ehs *ehs_rsp, int sg_cnt,
1454 struct scatterlist *sg_list, enum dma_data_direction dir);
1455int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1456int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1457int ufshcd_suspend_prepare(struct device *dev);
1458int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1459void ufshcd_resume_complete(struct device *dev);
1460bool ufshcd_is_hba_active(struct ufs_hba *hba);
1461void ufshcd_pm_qos_init(struct ufs_hba *hba);
1462void ufshcd_pm_qos_exit(struct ufs_hba *hba);
1463
1464/* Wrapper functions for safely calling variant operations */
1465static inline int ufshcd_vops_init(struct ufs_hba *hba)
1466{
1467 if (hba->vops && hba->vops->init)
1468 return hba->vops->init(hba);
1469
1470 return 0;
1471}
1472
1473static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1474{
1475 if (hba->vops && hba->vops->phy_initialization)
1476 return hba->vops->phy_initialization(hba);
1477
1478 return 0;
1479}
1480
1481extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1482
1483int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1484 const char *prefix);
1485
1486int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1487int ufshcd_write_ee_control(struct ufs_hba *hba);
1488int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1489 const u16 *other_mask, u16 set, u16 clr);
1490
1491#endif /* End of Header */