Loading...
1/*
2 * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it>
3 * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it>
4 *
5 * This code is *strongly* based on EHCI-HCD code by David Brownell since
6 * the chip is a quasi-EHCI compatible.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/dmapool.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/timer.h>
34#include <linux/list.h>
35#include <linux/interrupt.h>
36#include <linux/usb.h>
37#include <linux/usb/hcd.h>
38#include <linux/moduleparam.h>
39#include <linux/dma-mapping.h>
40#include <linux/io.h>
41
42#include <asm/irq.h>
43#include <asm/system.h>
44#include <asm/unaligned.h>
45
46#include <linux/irq.h>
47#include <linux/platform_device.h>
48
49#include "oxu210hp.h"
50
51#define DRIVER_VERSION "0.0.50"
52
53/*
54 * Main defines
55 */
56
57#define oxu_dbg(oxu, fmt, args...) \
58 dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
59#define oxu_err(oxu, fmt, args...) \
60 dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
61#define oxu_info(oxu, fmt, args...) \
62 dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
63
64static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu)
65{
66 return container_of((void *) oxu, struct usb_hcd, hcd_priv);
67}
68
69static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd)
70{
71 return (struct oxu_hcd *) (hcd->hcd_priv);
72}
73
74/*
75 * Debug stuff
76 */
77
78#undef OXU_URB_TRACE
79#undef OXU_VERBOSE_DEBUG
80
81#ifdef OXU_VERBOSE_DEBUG
82#define oxu_vdbg oxu_dbg
83#else
84#define oxu_vdbg(oxu, fmt, args...) /* Nop */
85#endif
86
87#ifdef DEBUG
88
89static int __attribute__((__unused__))
90dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
91{
92 return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
93 label, label[0] ? " " : "", status,
94 (status & STS_ASS) ? " Async" : "",
95 (status & STS_PSS) ? " Periodic" : "",
96 (status & STS_RECL) ? " Recl" : "",
97 (status & STS_HALT) ? " Halt" : "",
98 (status & STS_IAA) ? " IAA" : "",
99 (status & STS_FATAL) ? " FATAL" : "",
100 (status & STS_FLR) ? " FLR" : "",
101 (status & STS_PCD) ? " PCD" : "",
102 (status & STS_ERR) ? " ERR" : "",
103 (status & STS_INT) ? " INT" : ""
104 );
105}
106
107static int __attribute__((__unused__))
108dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
109{
110 return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
111 label, label[0] ? " " : "", enable,
112 (enable & STS_IAA) ? " IAA" : "",
113 (enable & STS_FATAL) ? " FATAL" : "",
114 (enable & STS_FLR) ? " FLR" : "",
115 (enable & STS_PCD) ? " PCD" : "",
116 (enable & STS_ERR) ? " ERR" : "",
117 (enable & STS_INT) ? " INT" : ""
118 );
119}
120
121static const char *const fls_strings[] =
122 { "1024", "512", "256", "??" };
123
124static int dbg_command_buf(char *buf, unsigned len,
125 const char *label, u32 command)
126{
127 return scnprintf(buf, len,
128 "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
129 label, label[0] ? " " : "", command,
130 (command & CMD_PARK) ? "park" : "(park)",
131 CMD_PARK_CNT(command),
132 (command >> 16) & 0x3f,
133 (command & CMD_LRESET) ? " LReset" : "",
134 (command & CMD_IAAD) ? " IAAD" : "",
135 (command & CMD_ASE) ? " Async" : "",
136 (command & CMD_PSE) ? " Periodic" : "",
137 fls_strings[(command >> 2) & 0x3],
138 (command & CMD_RESET) ? " Reset" : "",
139 (command & CMD_RUN) ? "RUN" : "HALT"
140 );
141}
142
143static int dbg_port_buf(char *buf, unsigned len, const char *label,
144 int port, u32 status)
145{
146 char *sig;
147
148 /* signaling state */
149 switch (status & (3 << 10)) {
150 case 0 << 10:
151 sig = "se0";
152 break;
153 case 1 << 10:
154 sig = "k"; /* low speed */
155 break;
156 case 2 << 10:
157 sig = "j";
158 break;
159 default:
160 sig = "?";
161 break;
162 }
163
164 return scnprintf(buf, len,
165 "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
166 label, label[0] ? " " : "", port, status,
167 (status & PORT_POWER) ? " POWER" : "",
168 (status & PORT_OWNER) ? " OWNER" : "",
169 sig,
170 (status & PORT_RESET) ? " RESET" : "",
171 (status & PORT_SUSPEND) ? " SUSPEND" : "",
172 (status & PORT_RESUME) ? " RESUME" : "",
173 (status & PORT_OCC) ? " OCC" : "",
174 (status & PORT_OC) ? " OC" : "",
175 (status & PORT_PEC) ? " PEC" : "",
176 (status & PORT_PE) ? " PE" : "",
177 (status & PORT_CSC) ? " CSC" : "",
178 (status & PORT_CONNECT) ? " CONNECT" : ""
179 );
180}
181
182#else
183
184static inline int __attribute__((__unused__))
185dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
186{ return 0; }
187
188static inline int __attribute__((__unused__))
189dbg_command_buf(char *buf, unsigned len, const char *label, u32 command)
190{ return 0; }
191
192static inline int __attribute__((__unused__))
193dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
194{ return 0; }
195
196static inline int __attribute__((__unused__))
197dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status)
198{ return 0; }
199
200#endif /* DEBUG */
201
202/* functions have the "wrong" filename when they're output... */
203#define dbg_status(oxu, label, status) { \
204 char _buf[80]; \
205 dbg_status_buf(_buf, sizeof _buf, label, status); \
206 oxu_dbg(oxu, "%s\n", _buf); \
207}
208
209#define dbg_cmd(oxu, label, command) { \
210 char _buf[80]; \
211 dbg_command_buf(_buf, sizeof _buf, label, command); \
212 oxu_dbg(oxu, "%s\n", _buf); \
213}
214
215#define dbg_port(oxu, label, port, status) { \
216 char _buf[80]; \
217 dbg_port_buf(_buf, sizeof _buf, label, port, status); \
218 oxu_dbg(oxu, "%s\n", _buf); \
219}
220
221/*
222 * Module parameters
223 */
224
225/* Initial IRQ latency: faster than hw default */
226static int log2_irq_thresh; /* 0 to 6 */
227module_param(log2_irq_thresh, int, S_IRUGO);
228MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
229
230/* Initial park setting: slower than hw default */
231static unsigned park;
232module_param(park, uint, S_IRUGO);
233MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
234
235/* For flakey hardware, ignore overcurrent indicators */
236static int ignore_oc;
237module_param(ignore_oc, bool, S_IRUGO);
238MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications");
239
240
241static void ehci_work(struct oxu_hcd *oxu);
242static int oxu_hub_control(struct usb_hcd *hcd,
243 u16 typeReq, u16 wValue, u16 wIndex,
244 char *buf, u16 wLength);
245
246/*
247 * Local functions
248 */
249
250/* Low level read/write registers functions */
251static inline u32 oxu_readl(void *base, u32 reg)
252{
253 return readl(base + reg);
254}
255
256static inline void oxu_writel(void *base, u32 reg, u32 val)
257{
258 writel(val, base + reg);
259}
260
261static inline void timer_action_done(struct oxu_hcd *oxu,
262 enum ehci_timer_action action)
263{
264 clear_bit(action, &oxu->actions);
265}
266
267static inline void timer_action(struct oxu_hcd *oxu,
268 enum ehci_timer_action action)
269{
270 if (!test_and_set_bit(action, &oxu->actions)) {
271 unsigned long t;
272
273 switch (action) {
274 case TIMER_IAA_WATCHDOG:
275 t = EHCI_IAA_JIFFIES;
276 break;
277 case TIMER_IO_WATCHDOG:
278 t = EHCI_IO_JIFFIES;
279 break;
280 case TIMER_ASYNC_OFF:
281 t = EHCI_ASYNC_JIFFIES;
282 break;
283 case TIMER_ASYNC_SHRINK:
284 default:
285 t = EHCI_SHRINK_JIFFIES;
286 break;
287 }
288 t += jiffies;
289 /* all timings except IAA watchdog can be overridden.
290 * async queue SHRINK often precedes IAA. while it's ready
291 * to go OFF neither can matter, and afterwards the IO
292 * watchdog stops unless there's still periodic traffic.
293 */
294 if (action != TIMER_IAA_WATCHDOG
295 && t > oxu->watchdog.expires
296 && timer_pending(&oxu->watchdog))
297 return;
298 mod_timer(&oxu->watchdog, t);
299 }
300}
301
302/*
303 * handshake - spin reading hc until handshake completes or fails
304 * @ptr: address of hc register to be read
305 * @mask: bits to look at in result of read
306 * @done: value of those bits when handshake succeeds
307 * @usec: timeout in microseconds
308 *
309 * Returns negative errno, or zero on success
310 *
311 * Success happens when the "mask" bits have the specified value (hardware
312 * handshake done). There are two failure modes: "usec" have passed (major
313 * hardware flakeout), or the register reads as all-ones (hardware removed).
314 *
315 * That last failure should_only happen in cases like physical cardbus eject
316 * before driver shutdown. But it also seems to be caused by bugs in cardbus
317 * bridge shutdown: shutting down the bridge before the devices using it.
318 */
319static int handshake(struct oxu_hcd *oxu, void __iomem *ptr,
320 u32 mask, u32 done, int usec)
321{
322 u32 result;
323
324 do {
325 result = readl(ptr);
326 if (result == ~(u32)0) /* card removed */
327 return -ENODEV;
328 result &= mask;
329 if (result == done)
330 return 0;
331 udelay(1);
332 usec--;
333 } while (usec > 0);
334 return -ETIMEDOUT;
335}
336
337/* Force HC to halt state from unknown (EHCI spec section 2.3) */
338static int ehci_halt(struct oxu_hcd *oxu)
339{
340 u32 temp = readl(&oxu->regs->status);
341
342 /* disable any irqs left enabled by previous code */
343 writel(0, &oxu->regs->intr_enable);
344
345 if ((temp & STS_HALT) != 0)
346 return 0;
347
348 temp = readl(&oxu->regs->command);
349 temp &= ~CMD_RUN;
350 writel(temp, &oxu->regs->command);
351 return handshake(oxu, &oxu->regs->status,
352 STS_HALT, STS_HALT, 16 * 125);
353}
354
355/* Put TDI/ARC silicon into EHCI mode */
356static void tdi_reset(struct oxu_hcd *oxu)
357{
358 u32 __iomem *reg_ptr;
359 u32 tmp;
360
361 reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68);
362 tmp = readl(reg_ptr);
363 tmp |= 0x3;
364 writel(tmp, reg_ptr);
365}
366
367/* Reset a non-running (STS_HALT == 1) controller */
368static int ehci_reset(struct oxu_hcd *oxu)
369{
370 int retval;
371 u32 command = readl(&oxu->regs->command);
372
373 command |= CMD_RESET;
374 dbg_cmd(oxu, "reset", command);
375 writel(command, &oxu->regs->command);
376 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
377 oxu->next_statechange = jiffies;
378 retval = handshake(oxu, &oxu->regs->command,
379 CMD_RESET, 0, 250 * 1000);
380
381 if (retval)
382 return retval;
383
384 tdi_reset(oxu);
385
386 return retval;
387}
388
389/* Idle the controller (from running) */
390static void ehci_quiesce(struct oxu_hcd *oxu)
391{
392 u32 temp;
393
394#ifdef DEBUG
395 if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
396 BUG();
397#endif
398
399 /* wait for any schedule enables/disables to take effect */
400 temp = readl(&oxu->regs->command) << 10;
401 temp &= STS_ASS | STS_PSS;
402 if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
403 temp, 16 * 125) != 0) {
404 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
405 return;
406 }
407
408 /* then disable anything that's still active */
409 temp = readl(&oxu->regs->command);
410 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
411 writel(temp, &oxu->regs->command);
412
413 /* hardware can take 16 microframes to turn off ... */
414 if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
415 0, 16 * 125) != 0) {
416 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
417 return;
418 }
419}
420
421static int check_reset_complete(struct oxu_hcd *oxu, int index,
422 u32 __iomem *status_reg, int port_status)
423{
424 if (!(port_status & PORT_CONNECT)) {
425 oxu->reset_done[index] = 0;
426 return port_status;
427 }
428
429 /* if reset finished and it's still not enabled -- handoff */
430 if (!(port_status & PORT_PE)) {
431 oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n",
432 index+1);
433 return port_status;
434 } else
435 oxu_dbg(oxu, "port %d high speed\n", index + 1);
436
437 return port_status;
438}
439
440static void ehci_hub_descriptor(struct oxu_hcd *oxu,
441 struct usb_hub_descriptor *desc)
442{
443 int ports = HCS_N_PORTS(oxu->hcs_params);
444 u16 temp;
445
446 desc->bDescriptorType = 0x29;
447 desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */
448 desc->bHubContrCurrent = 0;
449
450 desc->bNbrPorts = ports;
451 temp = 1 + (ports / 8);
452 desc->bDescLength = 7 + 2 * temp;
453
454 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
455 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
456 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
457
458 temp = 0x0008; /* per-port overcurrent reporting */
459 if (HCS_PPC(oxu->hcs_params))
460 temp |= 0x0001; /* per-port power control */
461 else
462 temp |= 0x0002; /* no power switching */
463 desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp);
464}
465
466
467/* Allocate an OXU210HP on-chip memory data buffer
468 *
469 * An on-chip memory data buffer is required for each OXU210HP USB transfer.
470 * Each transfer descriptor has one or more on-chip memory data buffers.
471 *
472 * Data buffers are allocated from a fix sized pool of data blocks.
473 * To minimise fragmentation and give reasonable memory utlisation,
474 * data buffers are allocated with sizes the power of 2 multiples of
475 * the block size, starting on an address a multiple of the allocated size.
476 *
477 * FIXME: callers of this function require a buffer to be allocated for
478 * len=0. This is a waste of on-chip memory and should be fix. Then this
479 * function should be changed to not allocate a buffer for len=0.
480 */
481static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len)
482{
483 int n_blocks; /* minium blocks needed to hold len */
484 int a_blocks; /* blocks allocated */
485 int i, j;
486
487 /* Don't allocte bigger than supported */
488 if (len > BUFFER_SIZE * BUFFER_NUM) {
489 oxu_err(oxu, "buffer too big (%d)\n", len);
490 return -ENOMEM;
491 }
492
493 spin_lock(&oxu->mem_lock);
494
495 /* Number of blocks needed to hold len */
496 n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE;
497
498 /* Round the number of blocks up to the power of 2 */
499 for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1)
500 ;
501
502 /* Find a suitable available data buffer */
503 for (i = 0; i < BUFFER_NUM;
504 i += max(a_blocks, (int)oxu->db_used[i])) {
505
506 /* Check all the required blocks are available */
507 for (j = 0; j < a_blocks; j++)
508 if (oxu->db_used[i + j])
509 break;
510
511 if (j != a_blocks)
512 continue;
513
514 /* Allocate blocks found! */
515 qtd->buffer = (void *) &oxu->mem->db_pool[i];
516 qtd->buffer_dma = virt_to_phys(qtd->buffer);
517
518 qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks;
519 oxu->db_used[i] = a_blocks;
520
521 spin_unlock(&oxu->mem_lock);
522
523 return 0;
524 }
525
526 /* Failed */
527
528 spin_unlock(&oxu->mem_lock);
529
530 return -ENOMEM;
531}
532
533static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
534{
535 int index;
536
537 spin_lock(&oxu->mem_lock);
538
539 index = (qtd->buffer - (void *) &oxu->mem->db_pool[0])
540 / BUFFER_SIZE;
541 oxu->db_used[index] = 0;
542 qtd->qtd_buffer_len = 0;
543 qtd->buffer_dma = 0;
544 qtd->buffer = NULL;
545
546 spin_unlock(&oxu->mem_lock);
547}
548
549static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma)
550{
551 memset(qtd, 0, sizeof *qtd);
552 qtd->qtd_dma = dma;
553 qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
554 qtd->hw_next = EHCI_LIST_END;
555 qtd->hw_alt_next = EHCI_LIST_END;
556 INIT_LIST_HEAD(&qtd->qtd_list);
557}
558
559static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
560{
561 int index;
562
563 if (qtd->buffer)
564 oxu_buf_free(oxu, qtd);
565
566 spin_lock(&oxu->mem_lock);
567
568 index = qtd - &oxu->mem->qtd_pool[0];
569 oxu->qtd_used[index] = 0;
570
571 spin_unlock(&oxu->mem_lock);
572}
573
574static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu)
575{
576 int i;
577 struct ehci_qtd *qtd = NULL;
578
579 spin_lock(&oxu->mem_lock);
580
581 for (i = 0; i < QTD_NUM; i++)
582 if (!oxu->qtd_used[i])
583 break;
584
585 if (i < QTD_NUM) {
586 qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i];
587 memset(qtd, 0, sizeof *qtd);
588
589 qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
590 qtd->hw_next = EHCI_LIST_END;
591 qtd->hw_alt_next = EHCI_LIST_END;
592 INIT_LIST_HEAD(&qtd->qtd_list);
593
594 qtd->qtd_dma = virt_to_phys(qtd);
595
596 oxu->qtd_used[i] = 1;
597 }
598
599 spin_unlock(&oxu->mem_lock);
600
601 return qtd;
602}
603
604static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh)
605{
606 int index;
607
608 spin_lock(&oxu->mem_lock);
609
610 index = qh - &oxu->mem->qh_pool[0];
611 oxu->qh_used[index] = 0;
612
613 spin_unlock(&oxu->mem_lock);
614}
615
616static void qh_destroy(struct kref *kref)
617{
618 struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
619 struct oxu_hcd *oxu = qh->oxu;
620
621 /* clean qtds first, and know this is not linked */
622 if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
623 oxu_dbg(oxu, "unused qh not empty!\n");
624 BUG();
625 }
626 if (qh->dummy)
627 oxu_qtd_free(oxu, qh->dummy);
628 oxu_qh_free(oxu, qh);
629}
630
631static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu)
632{
633 int i;
634 struct ehci_qh *qh = NULL;
635
636 spin_lock(&oxu->mem_lock);
637
638 for (i = 0; i < QHEAD_NUM; i++)
639 if (!oxu->qh_used[i])
640 break;
641
642 if (i < QHEAD_NUM) {
643 qh = (struct ehci_qh *) &oxu->mem->qh_pool[i];
644 memset(qh, 0, sizeof *qh);
645
646 kref_init(&qh->kref);
647 qh->oxu = oxu;
648 qh->qh_dma = virt_to_phys(qh);
649 INIT_LIST_HEAD(&qh->qtd_list);
650
651 /* dummy td enables safe urb queuing */
652 qh->dummy = ehci_qtd_alloc(oxu);
653 if (qh->dummy == NULL) {
654 oxu_dbg(oxu, "no dummy td\n");
655 oxu->qh_used[i] = 0;
656 qh = NULL;
657 goto unlock;
658 }
659
660 oxu->qh_used[i] = 1;
661 }
662unlock:
663 spin_unlock(&oxu->mem_lock);
664
665 return qh;
666}
667
668/* to share a qh (cpu threads, or hc) */
669static inline struct ehci_qh *qh_get(struct ehci_qh *qh)
670{
671 kref_get(&qh->kref);
672 return qh;
673}
674
675static inline void qh_put(struct ehci_qh *qh)
676{
677 kref_put(&qh->kref, qh_destroy);
678}
679
680static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb)
681{
682 int index;
683
684 spin_lock(&oxu->mem_lock);
685
686 index = murb - &oxu->murb_pool[0];
687 oxu->murb_used[index] = 0;
688
689 spin_unlock(&oxu->mem_lock);
690}
691
692static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu)
693
694{
695 int i;
696 struct oxu_murb *murb = NULL;
697
698 spin_lock(&oxu->mem_lock);
699
700 for (i = 0; i < MURB_NUM; i++)
701 if (!oxu->murb_used[i])
702 break;
703
704 if (i < MURB_NUM) {
705 murb = &(oxu->murb_pool)[i];
706
707 oxu->murb_used[i] = 1;
708 }
709
710 spin_unlock(&oxu->mem_lock);
711
712 return murb;
713}
714
715/* The queue heads and transfer descriptors are managed from pools tied
716 * to each of the "per device" structures.
717 * This is the initialisation and cleanup code.
718 */
719static void ehci_mem_cleanup(struct oxu_hcd *oxu)
720{
721 kfree(oxu->murb_pool);
722 oxu->murb_pool = NULL;
723
724 if (oxu->async)
725 qh_put(oxu->async);
726 oxu->async = NULL;
727
728 del_timer(&oxu->urb_timer);
729
730 oxu->periodic = NULL;
731
732 /* shadow periodic table */
733 kfree(oxu->pshadow);
734 oxu->pshadow = NULL;
735}
736
737/* Remember to add cleanup code (above) if you add anything here.
738 */
739static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags)
740{
741 int i;
742
743 for (i = 0; i < oxu->periodic_size; i++)
744 oxu->mem->frame_list[i] = EHCI_LIST_END;
745 for (i = 0; i < QHEAD_NUM; i++)
746 oxu->qh_used[i] = 0;
747 for (i = 0; i < QTD_NUM; i++)
748 oxu->qtd_used[i] = 0;
749
750 oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags);
751 if (!oxu->murb_pool)
752 goto fail;
753
754 for (i = 0; i < MURB_NUM; i++)
755 oxu->murb_used[i] = 0;
756
757 oxu->async = oxu_qh_alloc(oxu);
758 if (!oxu->async)
759 goto fail;
760
761 oxu->periodic = (__le32 *) &oxu->mem->frame_list;
762 oxu->periodic_dma = virt_to_phys(oxu->periodic);
763
764 for (i = 0; i < oxu->periodic_size; i++)
765 oxu->periodic[i] = EHCI_LIST_END;
766
767 /* software shadow of hardware table */
768 oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags);
769 if (oxu->pshadow != NULL)
770 return 0;
771
772fail:
773 oxu_dbg(oxu, "couldn't init memory\n");
774 ehci_mem_cleanup(oxu);
775 return -ENOMEM;
776}
777
778/* Fill a qtd, returning how much of the buffer we were able to queue up.
779 */
780static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len,
781 int token, int maxpacket)
782{
783 int i, count;
784 u64 addr = buf;
785
786 /* one buffer entry per 4K ... first might be short or unaligned */
787 qtd->hw_buf[0] = cpu_to_le32((u32)addr);
788 qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32));
789 count = 0x1000 - (buf & 0x0fff); /* rest of that page */
790 if (likely(len < count)) /* ... iff needed */
791 count = len;
792 else {
793 buf += 0x1000;
794 buf &= ~0x0fff;
795
796 /* per-qtd limit: from 16K to 20K (best alignment) */
797 for (i = 1; count < len && i < 5; i++) {
798 addr = buf;
799 qtd->hw_buf[i] = cpu_to_le32((u32)addr);
800 qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32));
801 buf += 0x1000;
802 if ((count + 0x1000) < len)
803 count += 0x1000;
804 else
805 count = len;
806 }
807
808 /* short packets may only terminate transfers */
809 if (count != len)
810 count -= (count % maxpacket);
811 }
812 qtd->hw_token = cpu_to_le32((count << 16) | token);
813 qtd->length = count;
814
815 return count;
816}
817
818static inline void qh_update(struct oxu_hcd *oxu,
819 struct ehci_qh *qh, struct ehci_qtd *qtd)
820{
821 /* writes to an active overlay are unsafe */
822 BUG_ON(qh->qh_state != QH_STATE_IDLE);
823
824 qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma);
825 qh->hw_alt_next = EHCI_LIST_END;
826
827 /* Except for control endpoints, we make hardware maintain data
828 * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
829 * and set the pseudo-toggle in udev. Only usb_clear_halt() will
830 * ever clear it.
831 */
832 if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) {
833 unsigned is_out, epnum;
834
835 is_out = !(qtd->hw_token & cpu_to_le32(1 << 8));
836 epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f;
837 if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
838 qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE);
839 usb_settoggle(qh->dev, epnum, is_out, 1);
840 }
841 }
842
843 /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
844 wmb();
845 qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING);
846}
847
848/* If it weren't for a common silicon quirk (writing the dummy into the qh
849 * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
850 * recovery (including urb dequeue) would need software changes to a QH...
851 */
852static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh)
853{
854 struct ehci_qtd *qtd;
855
856 if (list_empty(&qh->qtd_list))
857 qtd = qh->dummy;
858 else {
859 qtd = list_entry(qh->qtd_list.next,
860 struct ehci_qtd, qtd_list);
861 /* first qtd may already be partially processed */
862 if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current)
863 qtd = NULL;
864 }
865
866 if (qtd)
867 qh_update(oxu, qh, qtd);
868}
869
870static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb,
871 size_t length, u32 token)
872{
873 /* count IN/OUT bytes, not SETUP (even short packets) */
874 if (likely(QTD_PID(token) != 2))
875 urb->actual_length += length - QTD_LENGTH(token);
876
877 /* don't modify error codes */
878 if (unlikely(urb->status != -EINPROGRESS))
879 return;
880
881 /* force cleanup after short read; not always an error */
882 if (unlikely(IS_SHORT_READ(token)))
883 urb->status = -EREMOTEIO;
884
885 /* serious "can't proceed" faults reported by the hardware */
886 if (token & QTD_STS_HALT) {
887 if (token & QTD_STS_BABBLE) {
888 /* FIXME "must" disable babbling device's port too */
889 urb->status = -EOVERFLOW;
890 } else if (token & QTD_STS_MMF) {
891 /* fs/ls interrupt xfer missed the complete-split */
892 urb->status = -EPROTO;
893 } else if (token & QTD_STS_DBE) {
894 urb->status = (QTD_PID(token) == 1) /* IN ? */
895 ? -ENOSR /* hc couldn't read data */
896 : -ECOMM; /* hc couldn't write data */
897 } else if (token & QTD_STS_XACT) {
898 /* timeout, bad crc, wrong PID, etc; retried */
899 if (QTD_CERR(token))
900 urb->status = -EPIPE;
901 else {
902 oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n",
903 urb->dev->devpath,
904 usb_pipeendpoint(urb->pipe),
905 usb_pipein(urb->pipe) ? "in" : "out");
906 urb->status = -EPROTO;
907 }
908 /* CERR nonzero + no errors + halt --> stall */
909 } else if (QTD_CERR(token))
910 urb->status = -EPIPE;
911 else /* unknown */
912 urb->status = -EPROTO;
913
914 oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n",
915 usb_pipedevice(urb->pipe),
916 usb_pipeendpoint(urb->pipe),
917 usb_pipein(urb->pipe) ? "in" : "out",
918 token, urb->status);
919 }
920}
921
922static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb)
923__releases(oxu->lock)
924__acquires(oxu->lock)
925{
926 if (likely(urb->hcpriv != NULL)) {
927 struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv;
928
929 /* S-mask in a QH means it's an interrupt urb */
930 if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) {
931
932 /* ... update hc-wide periodic stats (for usbfs) */
933 oxu_to_hcd(oxu)->self.bandwidth_int_reqs--;
934 }
935 qh_put(qh);
936 }
937
938 urb->hcpriv = NULL;
939 switch (urb->status) {
940 case -EINPROGRESS: /* success */
941 urb->status = 0;
942 default: /* fault */
943 break;
944 case -EREMOTEIO: /* fault or normal */
945 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
946 urb->status = 0;
947 break;
948 case -ECONNRESET: /* canceled */
949 case -ENOENT:
950 break;
951 }
952
953#ifdef OXU_URB_TRACE
954 oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n",
955 __func__, urb->dev->devpath, urb,
956 usb_pipeendpoint(urb->pipe),
957 usb_pipein(urb->pipe) ? "in" : "out",
958 urb->status,
959 urb->actual_length, urb->transfer_buffer_length);
960#endif
961
962 /* complete() can reenter this HCD */
963 spin_unlock(&oxu->lock);
964 usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status);
965 spin_lock(&oxu->lock);
966}
967
968static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
969static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
970
971static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
972static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
973
974#define HALT_BIT cpu_to_le32(QTD_STS_HALT)
975
976/* Process and free completed qtds for a qh, returning URBs to drivers.
977 * Chases up to qh->hw_current. Returns number of completions called,
978 * indicating how much "real" work we did.
979 */
980static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh)
981{
982 struct ehci_qtd *last = NULL, *end = qh->dummy;
983 struct list_head *entry, *tmp;
984 int stopped;
985 unsigned count = 0;
986 int do_status = 0;
987 u8 state;
988 struct oxu_murb *murb = NULL;
989
990 if (unlikely(list_empty(&qh->qtd_list)))
991 return count;
992
993 /* completions (or tasks on other cpus) must never clobber HALT
994 * till we've gone through and cleaned everything up, even when
995 * they add urbs to this qh's queue or mark them for unlinking.
996 *
997 * NOTE: unlinking expects to be done in queue order.
998 */
999 state = qh->qh_state;
1000 qh->qh_state = QH_STATE_COMPLETING;
1001 stopped = (state == QH_STATE_IDLE);
1002
1003 /* remove de-activated QTDs from front of queue.
1004 * after faults (including short reads), cleanup this urb
1005 * then let the queue advance.
1006 * if queue is stopped, handles unlinks.
1007 */
1008 list_for_each_safe(entry, tmp, &qh->qtd_list) {
1009 struct ehci_qtd *qtd;
1010 struct urb *urb;
1011 u32 token = 0;
1012
1013 qtd = list_entry(entry, struct ehci_qtd, qtd_list);
1014 urb = qtd->urb;
1015
1016 /* Clean up any state from previous QTD ...*/
1017 if (last) {
1018 if (likely(last->urb != urb)) {
1019 if (last->urb->complete == NULL) {
1020 murb = (struct oxu_murb *) last->urb;
1021 last->urb = murb->main;
1022 if (murb->last) {
1023 ehci_urb_done(oxu, last->urb);
1024 count++;
1025 }
1026 oxu_murb_free(oxu, murb);
1027 } else {
1028 ehci_urb_done(oxu, last->urb);
1029 count++;
1030 }
1031 }
1032 oxu_qtd_free(oxu, last);
1033 last = NULL;
1034 }
1035
1036 /* ignore urbs submitted during completions we reported */
1037 if (qtd == end)
1038 break;
1039
1040 /* hardware copies qtd out of qh overlay */
1041 rmb();
1042 token = le32_to_cpu(qtd->hw_token);
1043
1044 /* always clean up qtds the hc de-activated */
1045 if ((token & QTD_STS_ACTIVE) == 0) {
1046
1047 if ((token & QTD_STS_HALT) != 0) {
1048 stopped = 1;
1049
1050 /* magic dummy for some short reads; qh won't advance.
1051 * that silicon quirk can kick in with this dummy too.
1052 */
1053 } else if (IS_SHORT_READ(token) &&
1054 !(qtd->hw_alt_next & EHCI_LIST_END)) {
1055 stopped = 1;
1056 goto halt;
1057 }
1058
1059 /* stop scanning when we reach qtds the hc is using */
1060 } else if (likely(!stopped &&
1061 HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) {
1062 break;
1063
1064 } else {
1065 stopped = 1;
1066
1067 if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)))
1068 urb->status = -ESHUTDOWN;
1069
1070 /* ignore active urbs unless some previous qtd
1071 * for the urb faulted (including short read) or
1072 * its urb was canceled. we may patch qh or qtds.
1073 */
1074 if (likely(urb->status == -EINPROGRESS))
1075 continue;
1076
1077 /* issue status after short control reads */
1078 if (unlikely(do_status != 0)
1079 && QTD_PID(token) == 0 /* OUT */) {
1080 do_status = 0;
1081 continue;
1082 }
1083
1084 /* token in overlay may be most current */
1085 if (state == QH_STATE_IDLE
1086 && cpu_to_le32(qtd->qtd_dma)
1087 == qh->hw_current)
1088 token = le32_to_cpu(qh->hw_token);
1089
1090 /* force halt for unlinked or blocked qh, so we'll
1091 * patch the qh later and so that completions can't
1092 * activate it while we "know" it's stopped.
1093 */
1094 if ((HALT_BIT & qh->hw_token) == 0) {
1095halt:
1096 qh->hw_token |= HALT_BIT;
1097 wmb();
1098 }
1099 }
1100
1101 /* Remove it from the queue */
1102 qtd_copy_status(oxu, urb->complete ?
1103 urb : ((struct oxu_murb *) urb)->main,
1104 qtd->length, token);
1105 if ((usb_pipein(qtd->urb->pipe)) &&
1106 (NULL != qtd->transfer_buffer))
1107 memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length);
1108 do_status = (urb->status == -EREMOTEIO)
1109 && usb_pipecontrol(urb->pipe);
1110
1111 if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
1112 last = list_entry(qtd->qtd_list.prev,
1113 struct ehci_qtd, qtd_list);
1114 last->hw_next = qtd->hw_next;
1115 }
1116 list_del(&qtd->qtd_list);
1117 last = qtd;
1118 }
1119
1120 /* last urb's completion might still need calling */
1121 if (likely(last != NULL)) {
1122 if (last->urb->complete == NULL) {
1123 murb = (struct oxu_murb *) last->urb;
1124 last->urb = murb->main;
1125 if (murb->last) {
1126 ehci_urb_done(oxu, last->urb);
1127 count++;
1128 }
1129 oxu_murb_free(oxu, murb);
1130 } else {
1131 ehci_urb_done(oxu, last->urb);
1132 count++;
1133 }
1134 oxu_qtd_free(oxu, last);
1135 }
1136
1137 /* restore original state; caller must unlink or relink */
1138 qh->qh_state = state;
1139
1140 /* be sure the hardware's done with the qh before refreshing
1141 * it after fault cleanup, or recovering from silicon wrongly
1142 * overlaying the dummy qtd (which reduces DMA chatter).
1143 */
1144 if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) {
1145 switch (state) {
1146 case QH_STATE_IDLE:
1147 qh_refresh(oxu, qh);
1148 break;
1149 case QH_STATE_LINKED:
1150 /* should be rare for periodic transfers,
1151 * except maybe high bandwidth ...
1152 */
1153 if ((cpu_to_le32(QH_SMASK)
1154 & qh->hw_info2) != 0) {
1155 intr_deschedule(oxu, qh);
1156 (void) qh_schedule(oxu, qh);
1157 } else
1158 unlink_async(oxu, qh);
1159 break;
1160 /* otherwise, unlink already started */
1161 }
1162 }
1163
1164 return count;
1165}
1166
1167/* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */
1168#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
1169/* ... and packet size, for any kind of endpoint descriptor */
1170#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1171
1172/* Reverse of qh_urb_transaction: free a list of TDs.
1173 * used for cleanup after errors, before HC sees an URB's TDs.
1174 */
1175static void qtd_list_free(struct oxu_hcd *oxu,
1176 struct urb *urb, struct list_head *qtd_list)
1177{
1178 struct list_head *entry, *temp;
1179
1180 list_for_each_safe(entry, temp, qtd_list) {
1181 struct ehci_qtd *qtd;
1182
1183 qtd = list_entry(entry, struct ehci_qtd, qtd_list);
1184 list_del(&qtd->qtd_list);
1185 oxu_qtd_free(oxu, qtd);
1186 }
1187}
1188
1189/* Create a list of filled qtds for this URB; won't link into qh.
1190 */
1191static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu,
1192 struct urb *urb,
1193 struct list_head *head,
1194 gfp_t flags)
1195{
1196 struct ehci_qtd *qtd, *qtd_prev;
1197 dma_addr_t buf;
1198 int len, maxpacket;
1199 int is_input;
1200 u32 token;
1201 void *transfer_buf = NULL;
1202 int ret;
1203
1204 /*
1205 * URBs map to sequences of QTDs: one logical transaction
1206 */
1207 qtd = ehci_qtd_alloc(oxu);
1208 if (unlikely(!qtd))
1209 return NULL;
1210 list_add_tail(&qtd->qtd_list, head);
1211 qtd->urb = urb;
1212
1213 token = QTD_STS_ACTIVE;
1214 token |= (EHCI_TUNE_CERR << 10);
1215 /* for split transactions, SplitXState initialized to zero */
1216
1217 len = urb->transfer_buffer_length;
1218 is_input = usb_pipein(urb->pipe);
1219 if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input)
1220 urb->transfer_buffer = phys_to_virt(urb->transfer_dma);
1221
1222 if (usb_pipecontrol(urb->pipe)) {
1223 /* SETUP pid */
1224 ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest));
1225 if (ret)
1226 goto cleanup;
1227
1228 qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest),
1229 token | (2 /* "setup" */ << 8), 8);
1230 memcpy(qtd->buffer, qtd->urb->setup_packet,
1231 sizeof(struct usb_ctrlrequest));
1232
1233 /* ... and always at least one more pid */
1234 token ^= QTD_TOGGLE;
1235 qtd_prev = qtd;
1236 qtd = ehci_qtd_alloc(oxu);
1237 if (unlikely(!qtd))
1238 goto cleanup;
1239 qtd->urb = urb;
1240 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
1241 list_add_tail(&qtd->qtd_list, head);
1242
1243 /* for zero length DATA stages, STATUS is always IN */
1244 if (len == 0)
1245 token |= (1 /* "in" */ << 8);
1246 }
1247
1248 /*
1249 * Data transfer stage: buffer setup
1250 */
1251
1252 ret = oxu_buf_alloc(oxu, qtd, len);
1253 if (ret)
1254 goto cleanup;
1255
1256 buf = qtd->buffer_dma;
1257 transfer_buf = urb->transfer_buffer;
1258
1259 if (!is_input)
1260 memcpy(qtd->buffer, qtd->urb->transfer_buffer, len);
1261
1262 if (is_input)
1263 token |= (1 /* "in" */ << 8);
1264 /* else it's already initted to "out" pid (0 << 8) */
1265
1266 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1267
1268 /*
1269 * buffer gets wrapped in one or more qtds;
1270 * last one may be "short" (including zero len)
1271 * and may serve as a control status ack
1272 */
1273 for (;;) {
1274 int this_qtd_len;
1275
1276 this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket);
1277 qtd->transfer_buffer = transfer_buf;
1278 len -= this_qtd_len;
1279 buf += this_qtd_len;
1280 transfer_buf += this_qtd_len;
1281 if (is_input)
1282 qtd->hw_alt_next = oxu->async->hw_alt_next;
1283
1284 /* qh makes control packets use qtd toggle; maybe switch it */
1285 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1286 token ^= QTD_TOGGLE;
1287
1288 if (likely(len <= 0))
1289 break;
1290
1291 qtd_prev = qtd;
1292 qtd = ehci_qtd_alloc(oxu);
1293 if (unlikely(!qtd))
1294 goto cleanup;
1295 if (likely(len > 0)) {
1296 ret = oxu_buf_alloc(oxu, qtd, len);
1297 if (ret)
1298 goto cleanup;
1299 }
1300 qtd->urb = urb;
1301 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
1302 list_add_tail(&qtd->qtd_list, head);
1303 }
1304
1305 /* unless the bulk/interrupt caller wants a chance to clean
1306 * up after short reads, hc should advance qh past this urb
1307 */
1308 if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
1309 || usb_pipecontrol(urb->pipe)))
1310 qtd->hw_alt_next = EHCI_LIST_END;
1311
1312 /*
1313 * control requests may need a terminating data "status" ack;
1314 * bulk ones may need a terminating short packet (zero length).
1315 */
1316 if (likely(urb->transfer_buffer_length != 0)) {
1317 int one_more = 0;
1318
1319 if (usb_pipecontrol(urb->pipe)) {
1320 one_more = 1;
1321 token ^= 0x0100; /* "in" <--> "out" */
1322 token |= QTD_TOGGLE; /* force DATA1 */
1323 } else if (usb_pipebulk(urb->pipe)
1324 && (urb->transfer_flags & URB_ZERO_PACKET)
1325 && !(urb->transfer_buffer_length % maxpacket)) {
1326 one_more = 1;
1327 }
1328 if (one_more) {
1329 qtd_prev = qtd;
1330 qtd = ehci_qtd_alloc(oxu);
1331 if (unlikely(!qtd))
1332 goto cleanup;
1333 qtd->urb = urb;
1334 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
1335 list_add_tail(&qtd->qtd_list, head);
1336
1337 /* never any data in such packets */
1338 qtd_fill(qtd, 0, 0, token, 0);
1339 }
1340 }
1341
1342 /* by default, enable interrupt on urb completion */
1343 qtd->hw_token |= cpu_to_le32(QTD_IOC);
1344 return head;
1345
1346cleanup:
1347 qtd_list_free(oxu, urb, head);
1348 return NULL;
1349}
1350
1351/* Each QH holds a qtd list; a QH is used for everything except iso.
1352 *
1353 * For interrupt urbs, the scheduler must set the microframe scheduling
1354 * mask(s) each time the QH gets scheduled. For highspeed, that's
1355 * just one microframe in the s-mask. For split interrupt transactions
1356 * there are additional complications: c-mask, maybe FSTNs.
1357 */
1358static struct ehci_qh *qh_make(struct oxu_hcd *oxu,
1359 struct urb *urb, gfp_t flags)
1360{
1361 struct ehci_qh *qh = oxu_qh_alloc(oxu);
1362 u32 info1 = 0, info2 = 0;
1363 int is_input, type;
1364 int maxp = 0;
1365
1366 if (!qh)
1367 return qh;
1368
1369 /*
1370 * init endpoint/device data for this QH
1371 */
1372 info1 |= usb_pipeendpoint(urb->pipe) << 8;
1373 info1 |= usb_pipedevice(urb->pipe) << 0;
1374
1375 is_input = usb_pipein(urb->pipe);
1376 type = usb_pipetype(urb->pipe);
1377 maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input);
1378
1379 /* Compute interrupt scheduling parameters just once, and save.
1380 * - allowing for high bandwidth, how many nsec/uframe are used?
1381 * - split transactions need a second CSPLIT uframe; same question
1382 * - splits also need a schedule gap (for full/low speed I/O)
1383 * - qh has a polling interval
1384 *
1385 * For control/bulk requests, the HC or TT handles these.
1386 */
1387 if (type == PIPE_INTERRUPT) {
1388 qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
1389 is_input, 0,
1390 hb_mult(maxp) * max_packet(maxp)));
1391 qh->start = NO_FRAME;
1392
1393 if (urb->dev->speed == USB_SPEED_HIGH) {
1394 qh->c_usecs = 0;
1395 qh->gap_uf = 0;
1396
1397 qh->period = urb->interval >> 3;
1398 if (qh->period == 0 && urb->interval != 1) {
1399 /* NOTE interval 2 or 4 uframes could work.
1400 * But interval 1 scheduling is simpler, and
1401 * includes high bandwidth.
1402 */
1403 dbg("intr period %d uframes, NYET!",
1404 urb->interval);
1405 goto done;
1406 }
1407 } else {
1408 struct usb_tt *tt = urb->dev->tt;
1409 int think_time;
1410
1411 /* gap is f(FS/LS transfer times) */
1412 qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
1413 is_input, 0, maxp) / (125 * 1000);
1414
1415 /* FIXME this just approximates SPLIT/CSPLIT times */
1416 if (is_input) { /* SPLIT, gap, CSPLIT+DATA */
1417 qh->c_usecs = qh->usecs + HS_USECS(0);
1418 qh->usecs = HS_USECS(1);
1419 } else { /* SPLIT+DATA, gap, CSPLIT */
1420 qh->usecs += HS_USECS(1);
1421 qh->c_usecs = HS_USECS(0);
1422 }
1423
1424 think_time = tt ? tt->think_time : 0;
1425 qh->tt_usecs = NS_TO_US(think_time +
1426 usb_calc_bus_time(urb->dev->speed,
1427 is_input, 0, max_packet(maxp)));
1428 qh->period = urb->interval;
1429 }
1430 }
1431
1432 /* support for tt scheduling, and access to toggles */
1433 qh->dev = urb->dev;
1434
1435 /* using TT? */
1436 switch (urb->dev->speed) {
1437 case USB_SPEED_LOW:
1438 info1 |= (1 << 12); /* EPS "low" */
1439 /* FALL THROUGH */
1440
1441 case USB_SPEED_FULL:
1442 /* EPS 0 means "full" */
1443 if (type != PIPE_INTERRUPT)
1444 info1 |= (EHCI_TUNE_RL_TT << 28);
1445 if (type == PIPE_CONTROL) {
1446 info1 |= (1 << 27); /* for TT */
1447 info1 |= 1 << 14; /* toggle from qtd */
1448 }
1449 info1 |= maxp << 16;
1450
1451 info2 |= (EHCI_TUNE_MULT_TT << 30);
1452 info2 |= urb->dev->ttport << 23;
1453
1454 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
1455
1456 break;
1457
1458 case USB_SPEED_HIGH: /* no TT involved */
1459 info1 |= (2 << 12); /* EPS "high" */
1460 if (type == PIPE_CONTROL) {
1461 info1 |= (EHCI_TUNE_RL_HS << 28);
1462 info1 |= 64 << 16; /* usb2 fixed maxpacket */
1463 info1 |= 1 << 14; /* toggle from qtd */
1464 info2 |= (EHCI_TUNE_MULT_HS << 30);
1465 } else if (type == PIPE_BULK) {
1466 info1 |= (EHCI_TUNE_RL_HS << 28);
1467 info1 |= 512 << 16; /* usb2 fixed maxpacket */
1468 info2 |= (EHCI_TUNE_MULT_HS << 30);
1469 } else { /* PIPE_INTERRUPT */
1470 info1 |= max_packet(maxp) << 16;
1471 info2 |= hb_mult(maxp) << 30;
1472 }
1473 break;
1474 default:
1475 dbg("bogus dev %p speed %d", urb->dev, urb->dev->speed);
1476done:
1477 qh_put(qh);
1478 return NULL;
1479 }
1480
1481 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
1482
1483 /* init as live, toggle clear, advance to dummy */
1484 qh->qh_state = QH_STATE_IDLE;
1485 qh->hw_info1 = cpu_to_le32(info1);
1486 qh->hw_info2 = cpu_to_le32(info2);
1487 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
1488 qh_refresh(oxu, qh);
1489 return qh;
1490}
1491
1492/* Move qh (and its qtds) onto async queue; maybe enable queue.
1493 */
1494static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
1495{
1496 __le32 dma = QH_NEXT(qh->qh_dma);
1497 struct ehci_qh *head;
1498
1499 /* (re)start the async schedule? */
1500 head = oxu->async;
1501 timer_action_done(oxu, TIMER_ASYNC_OFF);
1502 if (!head->qh_next.qh) {
1503 u32 cmd = readl(&oxu->regs->command);
1504
1505 if (!(cmd & CMD_ASE)) {
1506 /* in case a clear of CMD_ASE didn't take yet */
1507 (void)handshake(oxu, &oxu->regs->status,
1508 STS_ASS, 0, 150);
1509 cmd |= CMD_ASE | CMD_RUN;
1510 writel(cmd, &oxu->regs->command);
1511 oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
1512 /* posted write need not be known to HC yet ... */
1513 }
1514 }
1515
1516 /* clear halt and/or toggle; and maybe recover from silicon quirk */
1517 if (qh->qh_state == QH_STATE_IDLE)
1518 qh_refresh(oxu, qh);
1519
1520 /* splice right after start */
1521 qh->qh_next = head->qh_next;
1522 qh->hw_next = head->hw_next;
1523 wmb();
1524
1525 head->qh_next.qh = qh;
1526 head->hw_next = dma;
1527
1528 qh->qh_state = QH_STATE_LINKED;
1529 /* qtd completions reported later by interrupt */
1530}
1531
1532#define QH_ADDR_MASK cpu_to_le32(0x7f)
1533
1534/*
1535 * For control/bulk/interrupt, return QH with these TDs appended.
1536 * Allocates and initializes the QH if necessary.
1537 * Returns null if it can't allocate a QH it needs to.
1538 * If the QH has TDs (urbs) already, that's great.
1539 */
1540static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu,
1541 struct urb *urb, struct list_head *qtd_list,
1542 int epnum, void **ptr)
1543{
1544 struct ehci_qh *qh = NULL;
1545
1546 qh = (struct ehci_qh *) *ptr;
1547 if (unlikely(qh == NULL)) {
1548 /* can't sleep here, we have oxu->lock... */
1549 qh = qh_make(oxu, urb, GFP_ATOMIC);
1550 *ptr = qh;
1551 }
1552 if (likely(qh != NULL)) {
1553 struct ehci_qtd *qtd;
1554
1555 if (unlikely(list_empty(qtd_list)))
1556 qtd = NULL;
1557 else
1558 qtd = list_entry(qtd_list->next, struct ehci_qtd,
1559 qtd_list);
1560
1561 /* control qh may need patching ... */
1562 if (unlikely(epnum == 0)) {
1563
1564 /* usb_reset_device() briefly reverts to address 0 */
1565 if (usb_pipedevice(urb->pipe) == 0)
1566 qh->hw_info1 &= ~QH_ADDR_MASK;
1567 }
1568
1569 /* just one way to queue requests: swap with the dummy qtd.
1570 * only hc or qh_refresh() ever modify the overlay.
1571 */
1572 if (likely(qtd != NULL)) {
1573 struct ehci_qtd *dummy;
1574 dma_addr_t dma;
1575 __le32 token;
1576
1577 /* to avoid racing the HC, use the dummy td instead of
1578 * the first td of our list (becomes new dummy). both
1579 * tds stay deactivated until we're done, when the
1580 * HC is allowed to fetch the old dummy (4.10.2).
1581 */
1582 token = qtd->hw_token;
1583 qtd->hw_token = HALT_BIT;
1584 wmb();
1585 dummy = qh->dummy;
1586
1587 dma = dummy->qtd_dma;
1588 *dummy = *qtd;
1589 dummy->qtd_dma = dma;
1590
1591 list_del(&qtd->qtd_list);
1592 list_add(&dummy->qtd_list, qtd_list);
1593 list_splice(qtd_list, qh->qtd_list.prev);
1594
1595 ehci_qtd_init(qtd, qtd->qtd_dma);
1596 qh->dummy = qtd;
1597
1598 /* hc must see the new dummy at list end */
1599 dma = qtd->qtd_dma;
1600 qtd = list_entry(qh->qtd_list.prev,
1601 struct ehci_qtd, qtd_list);
1602 qtd->hw_next = QTD_NEXT(dma);
1603
1604 /* let the hc process these next qtds */
1605 dummy->hw_token = (token & ~(0x80));
1606 wmb();
1607 dummy->hw_token = token;
1608
1609 urb->hcpriv = qh_get(qh);
1610 }
1611 }
1612 return qh;
1613}
1614
1615static int submit_async(struct oxu_hcd *oxu, struct urb *urb,
1616 struct list_head *qtd_list, gfp_t mem_flags)
1617{
1618 struct ehci_qtd *qtd;
1619 int epnum;
1620 unsigned long flags;
1621 struct ehci_qh *qh = NULL;
1622 int rc = 0;
1623
1624 qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
1625 epnum = urb->ep->desc.bEndpointAddress;
1626
1627#ifdef OXU_URB_TRACE
1628 oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
1629 __func__, urb->dev->devpath, urb,
1630 epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
1631 urb->transfer_buffer_length,
1632 qtd, urb->ep->hcpriv);
1633#endif
1634
1635 spin_lock_irqsave(&oxu->lock, flags);
1636 if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) {
1637 rc = -ESHUTDOWN;
1638 goto done;
1639 }
1640
1641 qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
1642 if (unlikely(qh == NULL)) {
1643 rc = -ENOMEM;
1644 goto done;
1645 }
1646
1647 /* Control/bulk operations through TTs don't need scheduling,
1648 * the HC and TT handle it when the TT has a buffer ready.
1649 */
1650 if (likely(qh->qh_state == QH_STATE_IDLE))
1651 qh_link_async(oxu, qh_get(qh));
1652done:
1653 spin_unlock_irqrestore(&oxu->lock, flags);
1654 if (unlikely(qh == NULL))
1655 qtd_list_free(oxu, urb, qtd_list);
1656 return rc;
1657}
1658
1659/* The async qh for the qtds being reclaimed are now unlinked from the HC */
1660
1661static void end_unlink_async(struct oxu_hcd *oxu)
1662{
1663 struct ehci_qh *qh = oxu->reclaim;
1664 struct ehci_qh *next;
1665
1666 timer_action_done(oxu, TIMER_IAA_WATCHDOG);
1667
1668 qh->qh_state = QH_STATE_IDLE;
1669 qh->qh_next.qh = NULL;
1670 qh_put(qh); /* refcount from reclaim */
1671
1672 /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
1673 next = qh->reclaim;
1674 oxu->reclaim = next;
1675 oxu->reclaim_ready = 0;
1676 qh->reclaim = NULL;
1677
1678 qh_completions(oxu, qh);
1679
1680 if (!list_empty(&qh->qtd_list)
1681 && HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
1682 qh_link_async(oxu, qh);
1683 else {
1684 qh_put(qh); /* refcount from async list */
1685
1686 /* it's not free to turn the async schedule on/off; leave it
1687 * active but idle for a while once it empties.
1688 */
1689 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)
1690 && oxu->async->qh_next.qh == NULL)
1691 timer_action(oxu, TIMER_ASYNC_OFF);
1692 }
1693
1694 if (next) {
1695 oxu->reclaim = NULL;
1696 start_unlink_async(oxu, next);
1697 }
1698}
1699
1700/* makes sure the async qh will become idle */
1701/* caller must own oxu->lock */
1702
1703static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
1704{
1705 int cmd = readl(&oxu->regs->command);
1706 struct ehci_qh *prev;
1707
1708#ifdef DEBUG
1709 assert_spin_locked(&oxu->lock);
1710 if (oxu->reclaim || (qh->qh_state != QH_STATE_LINKED
1711 && qh->qh_state != QH_STATE_UNLINK_WAIT))
1712 BUG();
1713#endif
1714
1715 /* stop async schedule right now? */
1716 if (unlikely(qh == oxu->async)) {
1717 /* can't get here without STS_ASS set */
1718 if (oxu_to_hcd(oxu)->state != HC_STATE_HALT
1719 && !oxu->reclaim) {
1720 /* ... and CMD_IAAD clear */
1721 writel(cmd & ~CMD_ASE, &oxu->regs->command);
1722 wmb();
1723 /* handshake later, if we need to */
1724 timer_action_done(oxu, TIMER_ASYNC_OFF);
1725 }
1726 return;
1727 }
1728
1729 qh->qh_state = QH_STATE_UNLINK;
1730 oxu->reclaim = qh = qh_get(qh);
1731
1732 prev = oxu->async;
1733 while (prev->qh_next.qh != qh)
1734 prev = prev->qh_next.qh;
1735
1736 prev->hw_next = qh->hw_next;
1737 prev->qh_next = qh->qh_next;
1738 wmb();
1739
1740 if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) {
1741 /* if (unlikely(qh->reclaim != 0))
1742 * this will recurse, probably not much
1743 */
1744 end_unlink_async(oxu);
1745 return;
1746 }
1747
1748 oxu->reclaim_ready = 0;
1749 cmd |= CMD_IAAD;
1750 writel(cmd, &oxu->regs->command);
1751 (void) readl(&oxu->regs->command);
1752 timer_action(oxu, TIMER_IAA_WATCHDOG);
1753}
1754
1755static void scan_async(struct oxu_hcd *oxu)
1756{
1757 struct ehci_qh *qh;
1758 enum ehci_timer_action action = TIMER_IO_WATCHDOG;
1759
1760 if (!++(oxu->stamp))
1761 oxu->stamp++;
1762 timer_action_done(oxu, TIMER_ASYNC_SHRINK);
1763rescan:
1764 qh = oxu->async->qh_next.qh;
1765 if (likely(qh != NULL)) {
1766 do {
1767 /* clean any finished work for this qh */
1768 if (!list_empty(&qh->qtd_list)
1769 && qh->stamp != oxu->stamp) {
1770 int temp;
1771
1772 /* unlinks could happen here; completion
1773 * reporting drops the lock. rescan using
1774 * the latest schedule, but don't rescan
1775 * qhs we already finished (no looping).
1776 */
1777 qh = qh_get(qh);
1778 qh->stamp = oxu->stamp;
1779 temp = qh_completions(oxu, qh);
1780 qh_put(qh);
1781 if (temp != 0)
1782 goto rescan;
1783 }
1784
1785 /* unlink idle entries, reducing HC PCI usage as well
1786 * as HCD schedule-scanning costs. delay for any qh
1787 * we just scanned, there's a not-unusual case that it
1788 * doesn't stay idle for long.
1789 * (plus, avoids some kind of re-activation race.)
1790 */
1791 if (list_empty(&qh->qtd_list)) {
1792 if (qh->stamp == oxu->stamp)
1793 action = TIMER_ASYNC_SHRINK;
1794 else if (!oxu->reclaim
1795 && qh->qh_state == QH_STATE_LINKED)
1796 start_unlink_async(oxu, qh);
1797 }
1798
1799 qh = qh->qh_next.qh;
1800 } while (qh);
1801 }
1802 if (action == TIMER_ASYNC_SHRINK)
1803 timer_action(oxu, TIMER_ASYNC_SHRINK);
1804}
1805
1806/*
1807 * periodic_next_shadow - return "next" pointer on shadow list
1808 * @periodic: host pointer to qh/itd/sitd
1809 * @tag: hardware tag for type of this record
1810 */
1811static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic,
1812 __le32 tag)
1813{
1814 switch (tag) {
1815 default:
1816 case Q_TYPE_QH:
1817 return &periodic->qh->qh_next;
1818 }
1819}
1820
1821/* caller must hold oxu->lock */
1822static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr)
1823{
1824 union ehci_shadow *prev_p = &oxu->pshadow[frame];
1825 __le32 *hw_p = &oxu->periodic[frame];
1826 union ehci_shadow here = *prev_p;
1827
1828 /* find predecessor of "ptr"; hw and shadow lists are in sync */
1829 while (here.ptr && here.ptr != ptr) {
1830 prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p));
1831 hw_p = here.hw_next;
1832 here = *prev_p;
1833 }
1834 /* an interrupt entry (at list end) could have been shared */
1835 if (!here.ptr)
1836 return;
1837
1838 /* update shadow and hardware lists ... the old "next" pointers
1839 * from ptr may still be in use, the caller updates them.
1840 */
1841 *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p));
1842 *hw_p = *here.hw_next;
1843}
1844
1845/* how many of the uframe's 125 usecs are allocated? */
1846static unsigned short periodic_usecs(struct oxu_hcd *oxu,
1847 unsigned frame, unsigned uframe)
1848{
1849 __le32 *hw_p = &oxu->periodic[frame];
1850 union ehci_shadow *q = &oxu->pshadow[frame];
1851 unsigned usecs = 0;
1852
1853 while (q->ptr) {
1854 switch (Q_NEXT_TYPE(*hw_p)) {
1855 case Q_TYPE_QH:
1856 default:
1857 /* is it in the S-mask? */
1858 if (q->qh->hw_info2 & cpu_to_le32(1 << uframe))
1859 usecs += q->qh->usecs;
1860 /* ... or C-mask? */
1861 if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe)))
1862 usecs += q->qh->c_usecs;
1863 hw_p = &q->qh->hw_next;
1864 q = &q->qh->qh_next;
1865 break;
1866 }
1867 }
1868#ifdef DEBUG
1869 if (usecs > 100)
1870 oxu_err(oxu, "uframe %d sched overrun: %d usecs\n",
1871 frame * 8 + uframe, usecs);
1872#endif
1873 return usecs;
1874}
1875
1876static int enable_periodic(struct oxu_hcd *oxu)
1877{
1878 u32 cmd;
1879 int status;
1880
1881 /* did clearing PSE did take effect yet?
1882 * takes effect only at frame boundaries...
1883 */
1884 status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125);
1885 if (status != 0) {
1886 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
1887 usb_hc_died(oxu_to_hcd(oxu));
1888 return status;
1889 }
1890
1891 cmd = readl(&oxu->regs->command) | CMD_PSE;
1892 writel(cmd, &oxu->regs->command);
1893 /* posted write ... PSS happens later */
1894 oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
1895
1896 /* make sure ehci_work scans these */
1897 oxu->next_uframe = readl(&oxu->regs->frame_index)
1898 % (oxu->periodic_size << 3);
1899 return 0;
1900}
1901
1902static int disable_periodic(struct oxu_hcd *oxu)
1903{
1904 u32 cmd;
1905 int status;
1906
1907 /* did setting PSE not take effect yet?
1908 * takes effect only at frame boundaries...
1909 */
1910 status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125);
1911 if (status != 0) {
1912 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
1913 usb_hc_died(oxu_to_hcd(oxu));
1914 return status;
1915 }
1916
1917 cmd = readl(&oxu->regs->command) & ~CMD_PSE;
1918 writel(cmd, &oxu->regs->command);
1919 /* posted write ... */
1920
1921 oxu->next_uframe = -1;
1922 return 0;
1923}
1924
1925/* periodic schedule slots have iso tds (normal or split) first, then a
1926 * sparse tree for active interrupt transfers.
1927 *
1928 * this just links in a qh; caller guarantees uframe masks are set right.
1929 * no FSTN support (yet; oxu 0.96+)
1930 */
1931static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
1932{
1933 unsigned i;
1934 unsigned period = qh->period;
1935
1936 dev_dbg(&qh->dev->dev,
1937 "link qh%d-%04x/%p start %d [%d/%d us]\n",
1938 period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
1939 qh, qh->start, qh->usecs, qh->c_usecs);
1940
1941 /* high bandwidth, or otherwise every microframe */
1942 if (period == 0)
1943 period = 1;
1944
1945 for (i = qh->start; i < oxu->periodic_size; i += period) {
1946 union ehci_shadow *prev = &oxu->pshadow[i];
1947 __le32 *hw_p = &oxu->periodic[i];
1948 union ehci_shadow here = *prev;
1949 __le32 type = 0;
1950
1951 /* skip the iso nodes at list head */
1952 while (here.ptr) {
1953 type = Q_NEXT_TYPE(*hw_p);
1954 if (type == Q_TYPE_QH)
1955 break;
1956 prev = periodic_next_shadow(prev, type);
1957 hw_p = &here.qh->hw_next;
1958 here = *prev;
1959 }
1960
1961 /* sorting each branch by period (slow-->fast)
1962 * enables sharing interior tree nodes
1963 */
1964 while (here.ptr && qh != here.qh) {
1965 if (qh->period > here.qh->period)
1966 break;
1967 prev = &here.qh->qh_next;
1968 hw_p = &here.qh->hw_next;
1969 here = *prev;
1970 }
1971 /* link in this qh, unless some earlier pass did that */
1972 if (qh != here.qh) {
1973 qh->qh_next = here;
1974 if (here.qh)
1975 qh->hw_next = *hw_p;
1976 wmb();
1977 prev->qh = qh;
1978 *hw_p = QH_NEXT(qh->qh_dma);
1979 }
1980 }
1981 qh->qh_state = QH_STATE_LINKED;
1982 qh_get(qh);
1983
1984 /* update per-qh bandwidth for usbfs */
1985 oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period
1986 ? ((qh->usecs + qh->c_usecs) / qh->period)
1987 : (qh->usecs * 8);
1988
1989 /* maybe enable periodic schedule processing */
1990 if (!oxu->periodic_sched++)
1991 return enable_periodic(oxu);
1992
1993 return 0;
1994}
1995
1996static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
1997{
1998 unsigned i;
1999 unsigned period;
2000
2001 /* FIXME:
2002 * IF this isn't high speed
2003 * and this qh is active in the current uframe
2004 * (and overlay token SplitXstate is false?)
2005 * THEN
2006 * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore");
2007 */
2008
2009 /* high bandwidth, or otherwise part of every microframe */
2010 period = qh->period;
2011 if (period == 0)
2012 period = 1;
2013
2014 for (i = qh->start; i < oxu->periodic_size; i += period)
2015 periodic_unlink(oxu, i, qh);
2016
2017 /* update per-qh bandwidth for usbfs */
2018 oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period
2019 ? ((qh->usecs + qh->c_usecs) / qh->period)
2020 : (qh->usecs * 8);
2021
2022 dev_dbg(&qh->dev->dev,
2023 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
2024 qh->period,
2025 le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
2026 qh, qh->start, qh->usecs, qh->c_usecs);
2027
2028 /* qh->qh_next still "live" to HC */
2029 qh->qh_state = QH_STATE_UNLINK;
2030 qh->qh_next.ptr = NULL;
2031 qh_put(qh);
2032
2033 /* maybe turn off periodic schedule */
2034 oxu->periodic_sched--;
2035 if (!oxu->periodic_sched)
2036 (void) disable_periodic(oxu);
2037}
2038
2039static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
2040{
2041 unsigned wait;
2042
2043 qh_unlink_periodic(oxu, qh);
2044
2045 /* simple/paranoid: always delay, expecting the HC needs to read
2046 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
2047 * expect khubd to clean up after any CSPLITs we won't issue.
2048 * active high speed queues may need bigger delays...
2049 */
2050 if (list_empty(&qh->qtd_list)
2051 || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0)
2052 wait = 2;
2053 else
2054 wait = 55; /* worst case: 3 * 1024 */
2055
2056 udelay(wait);
2057 qh->qh_state = QH_STATE_IDLE;
2058 qh->hw_next = EHCI_LIST_END;
2059 wmb();
2060}
2061
2062static int check_period(struct oxu_hcd *oxu,
2063 unsigned frame, unsigned uframe,
2064 unsigned period, unsigned usecs)
2065{
2066 int claimed;
2067
2068 /* complete split running into next frame?
2069 * given FSTN support, we could sometimes check...
2070 */
2071 if (uframe >= 8)
2072 return 0;
2073
2074 /*
2075 * 80% periodic == 100 usec/uframe available
2076 * convert "usecs we need" to "max already claimed"
2077 */
2078 usecs = 100 - usecs;
2079
2080 /* we "know" 2 and 4 uframe intervals were rejected; so
2081 * for period 0, check _every_ microframe in the schedule.
2082 */
2083 if (unlikely(period == 0)) {
2084 do {
2085 for (uframe = 0; uframe < 7; uframe++) {
2086 claimed = periodic_usecs(oxu, frame, uframe);
2087 if (claimed > usecs)
2088 return 0;
2089 }
2090 } while ((frame += 1) < oxu->periodic_size);
2091
2092 /* just check the specified uframe, at that period */
2093 } else {
2094 do {
2095 claimed = periodic_usecs(oxu, frame, uframe);
2096 if (claimed > usecs)
2097 return 0;
2098 } while ((frame += period) < oxu->periodic_size);
2099 }
2100
2101 return 1;
2102}
2103
2104static int check_intr_schedule(struct oxu_hcd *oxu,
2105 unsigned frame, unsigned uframe,
2106 const struct ehci_qh *qh, __le32 *c_maskp)
2107{
2108 int retval = -ENOSPC;
2109
2110 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
2111 goto done;
2112
2113 if (!check_period(oxu, frame, uframe, qh->period, qh->usecs))
2114 goto done;
2115 if (!qh->c_usecs) {
2116 retval = 0;
2117 *c_maskp = 0;
2118 goto done;
2119 }
2120
2121done:
2122 return retval;
2123}
2124
2125/* "first fit" scheduling policy used the first time through,
2126 * or when the previous schedule slot can't be re-used.
2127 */
2128static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
2129{
2130 int status;
2131 unsigned uframe;
2132 __le32 c_mask;
2133 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
2134
2135 qh_refresh(oxu, qh);
2136 qh->hw_next = EHCI_LIST_END;
2137 frame = qh->start;
2138
2139 /* reuse the previous schedule slots, if we can */
2140 if (frame < qh->period) {
2141 uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK);
2142 status = check_intr_schedule(oxu, frame, --uframe,
2143 qh, &c_mask);
2144 } else {
2145 uframe = 0;
2146 c_mask = 0;
2147 status = -ENOSPC;
2148 }
2149
2150 /* else scan the schedule to find a group of slots such that all
2151 * uframes have enough periodic bandwidth available.
2152 */
2153 if (status) {
2154 /* "normal" case, uframing flexible except with splits */
2155 if (qh->period) {
2156 frame = qh->period - 1;
2157 do {
2158 for (uframe = 0; uframe < 8; uframe++) {
2159 status = check_intr_schedule(oxu,
2160 frame, uframe, qh,
2161 &c_mask);
2162 if (status == 0)
2163 break;
2164 }
2165 } while (status && frame--);
2166
2167 /* qh->period == 0 means every uframe */
2168 } else {
2169 frame = 0;
2170 status = check_intr_schedule(oxu, 0, 0, qh, &c_mask);
2171 }
2172 if (status)
2173 goto done;
2174 qh->start = frame;
2175
2176 /* reset S-frame and (maybe) C-frame masks */
2177 qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK));
2178 qh->hw_info2 |= qh->period
2179 ? cpu_to_le32(1 << uframe)
2180 : cpu_to_le32(QH_SMASK);
2181 qh->hw_info2 |= c_mask;
2182 } else
2183 oxu_dbg(oxu, "reused qh %p schedule\n", qh);
2184
2185 /* stuff into the periodic schedule */
2186 status = qh_link_periodic(oxu, qh);
2187done:
2188 return status;
2189}
2190
2191static int intr_submit(struct oxu_hcd *oxu, struct urb *urb,
2192 struct list_head *qtd_list, gfp_t mem_flags)
2193{
2194 unsigned epnum;
2195 unsigned long flags;
2196 struct ehci_qh *qh;
2197 int status = 0;
2198 struct list_head empty;
2199
2200 /* get endpoint and transfer/schedule data */
2201 epnum = urb->ep->desc.bEndpointAddress;
2202
2203 spin_lock_irqsave(&oxu->lock, flags);
2204
2205 if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) {
2206 status = -ESHUTDOWN;
2207 goto done;
2208 }
2209
2210 /* get qh and force any scheduling errors */
2211 INIT_LIST_HEAD(&empty);
2212 qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv);
2213 if (qh == NULL) {
2214 status = -ENOMEM;
2215 goto done;
2216 }
2217 if (qh->qh_state == QH_STATE_IDLE) {
2218 status = qh_schedule(oxu, qh);
2219 if (status != 0)
2220 goto done;
2221 }
2222
2223 /* then queue the urb's tds to the qh */
2224 qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
2225 BUG_ON(qh == NULL);
2226
2227 /* ... update usbfs periodic stats */
2228 oxu_to_hcd(oxu)->self.bandwidth_int_reqs++;
2229
2230done:
2231 spin_unlock_irqrestore(&oxu->lock, flags);
2232 if (status)
2233 qtd_list_free(oxu, urb, qtd_list);
2234
2235 return status;
2236}
2237
2238static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb,
2239 gfp_t mem_flags)
2240{
2241 oxu_dbg(oxu, "iso support is missing!\n");
2242 return -ENOSYS;
2243}
2244
2245static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb,
2246 gfp_t mem_flags)
2247{
2248 oxu_dbg(oxu, "split iso support is missing!\n");
2249 return -ENOSYS;
2250}
2251
2252static void scan_periodic(struct oxu_hcd *oxu)
2253{
2254 unsigned frame, clock, now_uframe, mod;
2255 unsigned modified;
2256
2257 mod = oxu->periodic_size << 3;
2258
2259 /*
2260 * When running, scan from last scan point up to "now"
2261 * else clean up by scanning everything that's left.
2262 * Touches as few pages as possible: cache-friendly.
2263 */
2264 now_uframe = oxu->next_uframe;
2265 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
2266 clock = readl(&oxu->regs->frame_index);
2267 else
2268 clock = now_uframe + mod - 1;
2269 clock %= mod;
2270
2271 for (;;) {
2272 union ehci_shadow q, *q_p;
2273 __le32 type, *hw_p;
2274 unsigned uframes;
2275
2276 /* don't scan past the live uframe */
2277 frame = now_uframe >> 3;
2278 if (frame == (clock >> 3))
2279 uframes = now_uframe & 0x07;
2280 else {
2281 /* safe to scan the whole frame at once */
2282 now_uframe |= 0x07;
2283 uframes = 8;
2284 }
2285
2286restart:
2287 /* scan each element in frame's queue for completions */
2288 q_p = &oxu->pshadow[frame];
2289 hw_p = &oxu->periodic[frame];
2290 q.ptr = q_p->ptr;
2291 type = Q_NEXT_TYPE(*hw_p);
2292 modified = 0;
2293
2294 while (q.ptr != NULL) {
2295 union ehci_shadow temp;
2296 int live;
2297
2298 live = HC_IS_RUNNING(oxu_to_hcd(oxu)->state);
2299 switch (type) {
2300 case Q_TYPE_QH:
2301 /* handle any completions */
2302 temp.qh = qh_get(q.qh);
2303 type = Q_NEXT_TYPE(q.qh->hw_next);
2304 q = q.qh->qh_next;
2305 modified = qh_completions(oxu, temp.qh);
2306 if (unlikely(list_empty(&temp.qh->qtd_list)))
2307 intr_deschedule(oxu, temp.qh);
2308 qh_put(temp.qh);
2309 break;
2310 default:
2311 dbg("corrupt type %d frame %d shadow %p",
2312 type, frame, q.ptr);
2313 q.ptr = NULL;
2314 }
2315
2316 /* assume completion callbacks modify the queue */
2317 if (unlikely(modified))
2318 goto restart;
2319 }
2320
2321 /* Stop when we catch up to the HC */
2322
2323 /* FIXME: this assumes we won't get lapped when
2324 * latencies climb; that should be rare, but...
2325 * detect it, and just go all the way around.
2326 * FLR might help detect this case, so long as latencies
2327 * don't exceed periodic_size msec (default 1.024 sec).
2328 */
2329
2330 /* FIXME: likewise assumes HC doesn't halt mid-scan */
2331
2332 if (now_uframe == clock) {
2333 unsigned now;
2334
2335 if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
2336 break;
2337 oxu->next_uframe = now_uframe;
2338 now = readl(&oxu->regs->frame_index) % mod;
2339 if (now_uframe == now)
2340 break;
2341
2342 /* rescan the rest of this frame, then ... */
2343 clock = now;
2344 } else {
2345 now_uframe++;
2346 now_uframe %= mod;
2347 }
2348 }
2349}
2350
2351/* On some systems, leaving remote wakeup enabled prevents system shutdown.
2352 * The firmware seems to think that powering off is a wakeup event!
2353 * This routine turns off remote wakeup and everything else, on all ports.
2354 */
2355static void ehci_turn_off_all_ports(struct oxu_hcd *oxu)
2356{
2357 int port = HCS_N_PORTS(oxu->hcs_params);
2358
2359 while (port--)
2360 writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
2361}
2362
2363static void ehci_port_power(struct oxu_hcd *oxu, int is_on)
2364{
2365 unsigned port;
2366
2367 if (!HCS_PPC(oxu->hcs_params))
2368 return;
2369
2370 oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down");
2371 for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; )
2372 (void) oxu_hub_control(oxu_to_hcd(oxu),
2373 is_on ? SetPortFeature : ClearPortFeature,
2374 USB_PORT_FEAT_POWER,
2375 port--, NULL, 0);
2376 msleep(20);
2377}
2378
2379/* Called from some interrupts, timers, and so on.
2380 * It calls driver completion functions, after dropping oxu->lock.
2381 */
2382static void ehci_work(struct oxu_hcd *oxu)
2383{
2384 timer_action_done(oxu, TIMER_IO_WATCHDOG);
2385 if (oxu->reclaim_ready)
2386 end_unlink_async(oxu);
2387
2388 /* another CPU may drop oxu->lock during a schedule scan while
2389 * it reports urb completions. this flag guards against bogus
2390 * attempts at re-entrant schedule scanning.
2391 */
2392 if (oxu->scanning)
2393 return;
2394 oxu->scanning = 1;
2395 scan_async(oxu);
2396 if (oxu->next_uframe != -1)
2397 scan_periodic(oxu);
2398 oxu->scanning = 0;
2399
2400 /* the IO watchdog guards against hardware or driver bugs that
2401 * misplace IRQs, and should let us run completely without IRQs.
2402 * such lossage has been observed on both VT6202 and VT8235.
2403 */
2404 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) &&
2405 (oxu->async->qh_next.ptr != NULL ||
2406 oxu->periodic_sched != 0))
2407 timer_action(oxu, TIMER_IO_WATCHDOG);
2408}
2409
2410static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
2411{
2412 /* if we need to use IAA and it's busy, defer */
2413 if (qh->qh_state == QH_STATE_LINKED
2414 && oxu->reclaim
2415 && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) {
2416 struct ehci_qh *last;
2417
2418 for (last = oxu->reclaim;
2419 last->reclaim;
2420 last = last->reclaim)
2421 continue;
2422 qh->qh_state = QH_STATE_UNLINK_WAIT;
2423 last->reclaim = qh;
2424
2425 /* bypass IAA if the hc can't care */
2426 } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim)
2427 end_unlink_async(oxu);
2428
2429 /* something else might have unlinked the qh by now */
2430 if (qh->qh_state == QH_STATE_LINKED)
2431 start_unlink_async(oxu, qh);
2432}
2433
2434/*
2435 * USB host controller methods
2436 */
2437
2438static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd)
2439{
2440 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2441 u32 status, pcd_status = 0;
2442 int bh;
2443
2444 spin_lock(&oxu->lock);
2445
2446 status = readl(&oxu->regs->status);
2447
2448 /* e.g. cardbus physical eject */
2449 if (status == ~(u32) 0) {
2450 oxu_dbg(oxu, "device removed\n");
2451 goto dead;
2452 }
2453
2454 /* Shared IRQ? */
2455 status &= INTR_MASK;
2456 if (!status || unlikely(hcd->state == HC_STATE_HALT)) {
2457 spin_unlock(&oxu->lock);
2458 return IRQ_NONE;
2459 }
2460
2461 /* clear (just) interrupts */
2462 writel(status, &oxu->regs->status);
2463 readl(&oxu->regs->command); /* unblock posted write */
2464 bh = 0;
2465
2466#ifdef OXU_VERBOSE_DEBUG
2467 /* unrequested/ignored: Frame List Rollover */
2468 dbg_status(oxu, "irq", status);
2469#endif
2470
2471 /* INT, ERR, and IAA interrupt rates can be throttled */
2472
2473 /* normal [4.15.1.2] or error [4.15.1.1] completion */
2474 if (likely((status & (STS_INT|STS_ERR)) != 0))
2475 bh = 1;
2476
2477 /* complete the unlinking of some qh [4.15.2.3] */
2478 if (status & STS_IAA) {
2479 oxu->reclaim_ready = 1;
2480 bh = 1;
2481 }
2482
2483 /* remote wakeup [4.3.1] */
2484 if (status & STS_PCD) {
2485 unsigned i = HCS_N_PORTS(oxu->hcs_params);
2486 pcd_status = status;
2487
2488 /* resume root hub? */
2489 if (!(readl(&oxu->regs->command) & CMD_RUN))
2490 usb_hcd_resume_root_hub(hcd);
2491
2492 while (i--) {
2493 int pstatus = readl(&oxu->regs->port_status[i]);
2494
2495 if (pstatus & PORT_OWNER)
2496 continue;
2497 if (!(pstatus & PORT_RESUME)
2498 || oxu->reset_done[i] != 0)
2499 continue;
2500
2501 /* start 20 msec resume signaling from this port,
2502 * and make khubd collect PORT_STAT_C_SUSPEND to
2503 * stop that signaling.
2504 */
2505 oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
2506 oxu_dbg(oxu, "port %d remote wakeup\n", i + 1);
2507 mod_timer(&hcd->rh_timer, oxu->reset_done[i]);
2508 }
2509 }
2510
2511 /* PCI errors [4.15.2.4] */
2512 if (unlikely((status & STS_FATAL) != 0)) {
2513 /* bogus "fatal" IRQs appear on some chips... why? */
2514 status = readl(&oxu->regs->status);
2515 dbg_cmd(oxu, "fatal", readl(&oxu->regs->command));
2516 dbg_status(oxu, "fatal", status);
2517 if (status & STS_HALT) {
2518 oxu_err(oxu, "fatal error\n");
2519dead:
2520 ehci_reset(oxu);
2521 writel(0, &oxu->regs->configured_flag);
2522 usb_hc_died(hcd);
2523 /* generic layer kills/unlinks all urbs, then
2524 * uses oxu_stop to clean up the rest
2525 */
2526 bh = 1;
2527 }
2528 }
2529
2530 if (bh)
2531 ehci_work(oxu);
2532 spin_unlock(&oxu->lock);
2533 if (pcd_status & STS_PCD)
2534 usb_hcd_poll_rh_status(hcd);
2535 return IRQ_HANDLED;
2536}
2537
2538static irqreturn_t oxu_irq(struct usb_hcd *hcd)
2539{
2540 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2541 int ret = IRQ_HANDLED;
2542
2543 u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS);
2544 u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET);
2545
2546 /* Disable all interrupt */
2547 oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable);
2548
2549 if ((oxu->is_otg && (status & OXU_USBOTGI)) ||
2550 (!oxu->is_otg && (status & OXU_USBSPHI)))
2551 oxu210_hcd_irq(hcd);
2552 else
2553 ret = IRQ_NONE;
2554
2555 /* Enable all interrupt back */
2556 oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable);
2557
2558 return ret;
2559}
2560
2561static void oxu_watchdog(unsigned long param)
2562{
2563 struct oxu_hcd *oxu = (struct oxu_hcd *) param;
2564 unsigned long flags;
2565
2566 spin_lock_irqsave(&oxu->lock, flags);
2567
2568 /* lost IAA irqs wedge things badly; seen with a vt8235 */
2569 if (oxu->reclaim) {
2570 u32 status = readl(&oxu->regs->status);
2571 if (status & STS_IAA) {
2572 oxu_vdbg(oxu, "lost IAA\n");
2573 writel(STS_IAA, &oxu->regs->status);
2574 oxu->reclaim_ready = 1;
2575 }
2576 }
2577
2578 /* stop async processing after it's idled a bit */
2579 if (test_bit(TIMER_ASYNC_OFF, &oxu->actions))
2580 start_unlink_async(oxu, oxu->async);
2581
2582 /* oxu could run by timer, without IRQs ... */
2583 ehci_work(oxu);
2584
2585 spin_unlock_irqrestore(&oxu->lock, flags);
2586}
2587
2588/* One-time init, only for memory state.
2589 */
2590static int oxu_hcd_init(struct usb_hcd *hcd)
2591{
2592 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2593 u32 temp;
2594 int retval;
2595 u32 hcc_params;
2596
2597 spin_lock_init(&oxu->lock);
2598
2599 init_timer(&oxu->watchdog);
2600 oxu->watchdog.function = oxu_watchdog;
2601 oxu->watchdog.data = (unsigned long) oxu;
2602
2603 /*
2604 * hw default: 1K periodic list heads, one per frame.
2605 * periodic_size can shrink by USBCMD update if hcc_params allows.
2606 */
2607 oxu->periodic_size = DEFAULT_I_TDPS;
2608 retval = ehci_mem_init(oxu, GFP_KERNEL);
2609 if (retval < 0)
2610 return retval;
2611
2612 /* controllers may cache some of the periodic schedule ... */
2613 hcc_params = readl(&oxu->caps->hcc_params);
2614 if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */
2615 oxu->i_thresh = 8;
2616 else /* N microframes cached */
2617 oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
2618
2619 oxu->reclaim = NULL;
2620 oxu->reclaim_ready = 0;
2621 oxu->next_uframe = -1;
2622
2623 /*
2624 * dedicate a qh for the async ring head, since we couldn't unlink
2625 * a 'real' qh without stopping the async schedule [4.8]. use it
2626 * as the 'reclamation list head' too.
2627 * its dummy is used in hw_alt_next of many tds, to prevent the qh
2628 * from automatically advancing to the next td after short reads.
2629 */
2630 oxu->async->qh_next.qh = NULL;
2631 oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma);
2632 oxu->async->hw_info1 = cpu_to_le32(QH_HEAD);
2633 oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT);
2634 oxu->async->hw_qtd_next = EHCI_LIST_END;
2635 oxu->async->qh_state = QH_STATE_LINKED;
2636 oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma);
2637
2638 /* clear interrupt enables, set irq latency */
2639 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
2640 log2_irq_thresh = 0;
2641 temp = 1 << (16 + log2_irq_thresh);
2642 if (HCC_CANPARK(hcc_params)) {
2643 /* HW default park == 3, on hardware that supports it (like
2644 * NVidia and ALI silicon), maximizes throughput on the async
2645 * schedule by avoiding QH fetches between transfers.
2646 *
2647 * With fast usb storage devices and NForce2, "park" seems to
2648 * make problems: throughput reduction (!), data errors...
2649 */
2650 if (park) {
2651 park = min(park, (unsigned) 3);
2652 temp |= CMD_PARK;
2653 temp |= park << 8;
2654 }
2655 oxu_dbg(oxu, "park %d\n", park);
2656 }
2657 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
2658 /* periodic schedule size can be smaller than default */
2659 temp &= ~(3 << 2);
2660 temp |= (EHCI_TUNE_FLS << 2);
2661 }
2662 oxu->command = temp;
2663
2664 return 0;
2665}
2666
2667/* Called during probe() after chip reset completes.
2668 */
2669static int oxu_reset(struct usb_hcd *hcd)
2670{
2671 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2672 int ret;
2673
2674 spin_lock_init(&oxu->mem_lock);
2675 INIT_LIST_HEAD(&oxu->urb_list);
2676 oxu->urb_len = 0;
2677
2678 /* FIMXE */
2679 hcd->self.controller->dma_mask = NULL;
2680
2681 if (oxu->is_otg) {
2682 oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET;
2683 oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \
2684 HC_LENGTH(readl(&oxu->caps->hc_capbase));
2685
2686 oxu->mem = hcd->regs + OXU_SPH_MEM;
2687 } else {
2688 oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET;
2689 oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \
2690 HC_LENGTH(readl(&oxu->caps->hc_capbase));
2691
2692 oxu->mem = hcd->regs + OXU_OTG_MEM;
2693 }
2694
2695 oxu->hcs_params = readl(&oxu->caps->hcs_params);
2696 oxu->sbrn = 0x20;
2697
2698 ret = oxu_hcd_init(hcd);
2699 if (ret)
2700 return ret;
2701
2702 return 0;
2703}
2704
2705static int oxu_run(struct usb_hcd *hcd)
2706{
2707 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2708 int retval;
2709 u32 temp, hcc_params;
2710
2711 hcd->uses_new_polling = 1;
2712
2713 /* EHCI spec section 4.1 */
2714 retval = ehci_reset(oxu);
2715 if (retval != 0) {
2716 ehci_mem_cleanup(oxu);
2717 return retval;
2718 }
2719 writel(oxu->periodic_dma, &oxu->regs->frame_list);
2720 writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
2721
2722 /* hcc_params controls whether oxu->regs->segment must (!!!)
2723 * be used; it constrains QH/ITD/SITD and QTD locations.
2724 * pci_pool consistent memory always uses segment zero.
2725 * streaming mappings for I/O buffers, like pci_map_single(),
2726 * can return segments above 4GB, if the device allows.
2727 *
2728 * NOTE: the dma mask is visible through dma_supported(), so
2729 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
2730 * Scsi_Host.highmem_io, and so forth. It's readonly to all
2731 * host side drivers though.
2732 */
2733 hcc_params = readl(&oxu->caps->hcc_params);
2734 if (HCC_64BIT_ADDR(hcc_params))
2735 writel(0, &oxu->regs->segment);
2736
2737 oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE |
2738 CMD_ASE | CMD_RESET);
2739 oxu->command |= CMD_RUN;
2740 writel(oxu->command, &oxu->regs->command);
2741 dbg_cmd(oxu, "init", oxu->command);
2742
2743 /*
2744 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
2745 * are explicitly handed to companion controller(s), so no TT is
2746 * involved with the root hub. (Except where one is integrated,
2747 * and there's no companion controller unless maybe for USB OTG.)
2748 */
2749 hcd->state = HC_STATE_RUNNING;
2750 writel(FLAG_CF, &oxu->regs->configured_flag);
2751 readl(&oxu->regs->command); /* unblock posted writes */
2752
2753 temp = HC_VERSION(readl(&oxu->caps->hc_capbase));
2754 oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n",
2755 ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f),
2756 temp >> 8, temp & 0xff, DRIVER_VERSION,
2757 ignore_oc ? ", overcurrent ignored" : "");
2758
2759 writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */
2760
2761 return 0;
2762}
2763
2764static void oxu_stop(struct usb_hcd *hcd)
2765{
2766 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2767
2768 /* Turn off port power on all root hub ports. */
2769 ehci_port_power(oxu, 0);
2770
2771 /* no more interrupts ... */
2772 del_timer_sync(&oxu->watchdog);
2773
2774 spin_lock_irq(&oxu->lock);
2775 if (HC_IS_RUNNING(hcd->state))
2776 ehci_quiesce(oxu);
2777
2778 ehci_reset(oxu);
2779 writel(0, &oxu->regs->intr_enable);
2780 spin_unlock_irq(&oxu->lock);
2781
2782 /* let companion controllers work when we aren't */
2783 writel(0, &oxu->regs->configured_flag);
2784
2785 /* root hub is shut down separately (first, when possible) */
2786 spin_lock_irq(&oxu->lock);
2787 if (oxu->async)
2788 ehci_work(oxu);
2789 spin_unlock_irq(&oxu->lock);
2790 ehci_mem_cleanup(oxu);
2791
2792 dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status));
2793}
2794
2795/* Kick in for silicon on any bus (not just pci, etc).
2796 * This forcibly disables dma and IRQs, helping kexec and other cases
2797 * where the next system software may expect clean state.
2798 */
2799static void oxu_shutdown(struct usb_hcd *hcd)
2800{
2801 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2802
2803 (void) ehci_halt(oxu);
2804 ehci_turn_off_all_ports(oxu);
2805
2806 /* make BIOS/etc use companion controller during reboot */
2807 writel(0, &oxu->regs->configured_flag);
2808
2809 /* unblock posted writes */
2810 readl(&oxu->regs->configured_flag);
2811}
2812
2813/* Non-error returns are a promise to giveback() the urb later
2814 * we drop ownership so next owner (or urb unlink) can get it
2815 *
2816 * urb + dev is in hcd.self.controller.urb_list
2817 * we're queueing TDs onto software and hardware lists
2818 *
2819 * hcd-specific init for hcpriv hasn't been done yet
2820 *
2821 * NOTE: control, bulk, and interrupt share the same code to append TDs
2822 * to a (possibly active) QH, and the same QH scanning code.
2823 */
2824static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2825 gfp_t mem_flags)
2826{
2827 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2828 struct list_head qtd_list;
2829
2830 INIT_LIST_HEAD(&qtd_list);
2831
2832 switch (usb_pipetype(urb->pipe)) {
2833 case PIPE_CONTROL:
2834 case PIPE_BULK:
2835 default:
2836 if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
2837 return -ENOMEM;
2838 return submit_async(oxu, urb, &qtd_list, mem_flags);
2839
2840 case PIPE_INTERRUPT:
2841 if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
2842 return -ENOMEM;
2843 return intr_submit(oxu, urb, &qtd_list, mem_flags);
2844
2845 case PIPE_ISOCHRONOUS:
2846 if (urb->dev->speed == USB_SPEED_HIGH)
2847 return itd_submit(oxu, urb, mem_flags);
2848 else
2849 return sitd_submit(oxu, urb, mem_flags);
2850 }
2851}
2852
2853/* This function is responsible for breaking URBs with big data size
2854 * into smaller size and processing small urbs in sequence.
2855 */
2856static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2857 gfp_t mem_flags)
2858{
2859 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2860 int num, rem;
2861 int transfer_buffer_length;
2862 void *transfer_buffer;
2863 struct urb *murb;
2864 int i, ret;
2865
2866 /* If not bulk pipe just enqueue the URB */
2867 if (!usb_pipebulk(urb->pipe))
2868 return __oxu_urb_enqueue(hcd, urb, mem_flags);
2869
2870 /* Otherwise we should verify the USB transfer buffer size! */
2871 transfer_buffer = urb->transfer_buffer;
2872 transfer_buffer_length = urb->transfer_buffer_length;
2873
2874 num = urb->transfer_buffer_length / 4096;
2875 rem = urb->transfer_buffer_length % 4096;
2876 if (rem != 0)
2877 num++;
2878
2879 /* If URB is smaller than 4096 bytes just enqueue it! */
2880 if (num == 1)
2881 return __oxu_urb_enqueue(hcd, urb, mem_flags);
2882
2883 /* Ok, we have more job to do! :) */
2884
2885 for (i = 0; i < num - 1; i++) {
2886 /* Get free micro URB poll till a free urb is received */
2887
2888 do {
2889 murb = (struct urb *) oxu_murb_alloc(oxu);
2890 if (!murb)
2891 schedule();
2892 } while (!murb);
2893
2894 /* Coping the urb */
2895 memcpy(murb, urb, sizeof(struct urb));
2896
2897 murb->transfer_buffer_length = 4096;
2898 murb->transfer_buffer = transfer_buffer + i * 4096;
2899
2900 /* Null pointer for the encodes that this is a micro urb */
2901 murb->complete = NULL;
2902
2903 ((struct oxu_murb *) murb)->main = urb;
2904 ((struct oxu_murb *) murb)->last = 0;
2905
2906 /* This loop is to guarantee urb to be processed when there's
2907 * not enough resources at a particular time by retrying.
2908 */
2909 do {
2910 ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
2911 if (ret)
2912 schedule();
2913 } while (ret);
2914 }
2915
2916 /* Last urb requires special handling */
2917
2918 /* Get free micro URB poll till a free urb is received */
2919 do {
2920 murb = (struct urb *) oxu_murb_alloc(oxu);
2921 if (!murb)
2922 schedule();
2923 } while (!murb);
2924
2925 /* Coping the urb */
2926 memcpy(murb, urb, sizeof(struct urb));
2927
2928 murb->transfer_buffer_length = rem > 0 ? rem : 4096;
2929 murb->transfer_buffer = transfer_buffer + (num - 1) * 4096;
2930
2931 /* Null pointer for the encodes that this is a micro urb */
2932 murb->complete = NULL;
2933
2934 ((struct oxu_murb *) murb)->main = urb;
2935 ((struct oxu_murb *) murb)->last = 1;
2936
2937 do {
2938 ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
2939 if (ret)
2940 schedule();
2941 } while (ret);
2942
2943 return ret;
2944}
2945
2946/* Remove from hardware lists.
2947 * Completions normally happen asynchronously
2948 */
2949static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2950{
2951 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2952 struct ehci_qh *qh;
2953 unsigned long flags;
2954
2955 spin_lock_irqsave(&oxu->lock, flags);
2956 switch (usb_pipetype(urb->pipe)) {
2957 case PIPE_CONTROL:
2958 case PIPE_BULK:
2959 default:
2960 qh = (struct ehci_qh *) urb->hcpriv;
2961 if (!qh)
2962 break;
2963 unlink_async(oxu, qh);
2964 break;
2965
2966 case PIPE_INTERRUPT:
2967 qh = (struct ehci_qh *) urb->hcpriv;
2968 if (!qh)
2969 break;
2970 switch (qh->qh_state) {
2971 case QH_STATE_LINKED:
2972 intr_deschedule(oxu, qh);
2973 /* FALL THROUGH */
2974 case QH_STATE_IDLE:
2975 qh_completions(oxu, qh);
2976 break;
2977 default:
2978 oxu_dbg(oxu, "bogus qh %p state %d\n",
2979 qh, qh->qh_state);
2980 goto done;
2981 }
2982
2983 /* reschedule QH iff another request is queued */
2984 if (!list_empty(&qh->qtd_list)
2985 && HC_IS_RUNNING(hcd->state)) {
2986 int status;
2987
2988 status = qh_schedule(oxu, qh);
2989 spin_unlock_irqrestore(&oxu->lock, flags);
2990
2991 if (status != 0) {
2992 /* shouldn't happen often, but ...
2993 * FIXME kill those tds' urbs
2994 */
2995 err("can't reschedule qh %p, err %d",
2996 qh, status);
2997 }
2998 return status;
2999 }
3000 break;
3001 }
3002done:
3003 spin_unlock_irqrestore(&oxu->lock, flags);
3004 return 0;
3005}
3006
3007/* Bulk qh holds the data toggle */
3008static void oxu_endpoint_disable(struct usb_hcd *hcd,
3009 struct usb_host_endpoint *ep)
3010{
3011 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3012 unsigned long flags;
3013 struct ehci_qh *qh, *tmp;
3014
3015 /* ASSERT: any requests/urbs are being unlinked */
3016 /* ASSERT: nobody can be submitting urbs for this any more */
3017
3018rescan:
3019 spin_lock_irqsave(&oxu->lock, flags);
3020 qh = ep->hcpriv;
3021 if (!qh)
3022 goto done;
3023
3024 /* endpoints can be iso streams. for now, we don't
3025 * accelerate iso completions ... so spin a while.
3026 */
3027 if (qh->hw_info1 == 0) {
3028 oxu_vdbg(oxu, "iso delay\n");
3029 goto idle_timeout;
3030 }
3031
3032 if (!HC_IS_RUNNING(hcd->state))
3033 qh->qh_state = QH_STATE_IDLE;
3034 switch (qh->qh_state) {
3035 case QH_STATE_LINKED:
3036 for (tmp = oxu->async->qh_next.qh;
3037 tmp && tmp != qh;
3038 tmp = tmp->qh_next.qh)
3039 continue;
3040 /* periodic qh self-unlinks on empty */
3041 if (!tmp)
3042 goto nogood;
3043 unlink_async(oxu, qh);
3044 /* FALL THROUGH */
3045 case QH_STATE_UNLINK: /* wait for hw to finish? */
3046idle_timeout:
3047 spin_unlock_irqrestore(&oxu->lock, flags);
3048 schedule_timeout_uninterruptible(1);
3049 goto rescan;
3050 case QH_STATE_IDLE: /* fully unlinked */
3051 if (list_empty(&qh->qtd_list)) {
3052 qh_put(qh);
3053 break;
3054 }
3055 /* else FALL THROUGH */
3056 default:
3057nogood:
3058 /* caller was supposed to have unlinked any requests;
3059 * that's not our job. just leak this memory.
3060 */
3061 oxu_err(oxu, "qh %p (#%02x) state %d%s\n",
3062 qh, ep->desc.bEndpointAddress, qh->qh_state,
3063 list_empty(&qh->qtd_list) ? "" : "(has tds)");
3064 break;
3065 }
3066 ep->hcpriv = NULL;
3067done:
3068 spin_unlock_irqrestore(&oxu->lock, flags);
3069}
3070
3071static int oxu_get_frame(struct usb_hcd *hcd)
3072{
3073 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3074
3075 return (readl(&oxu->regs->frame_index) >> 3) %
3076 oxu->periodic_size;
3077}
3078
3079/* Build "status change" packet (one or two bytes) from HC registers */
3080static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf)
3081{
3082 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3083 u32 temp, mask, status = 0;
3084 int ports, i, retval = 1;
3085 unsigned long flags;
3086
3087 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
3088 if (!HC_IS_RUNNING(hcd->state))
3089 return 0;
3090
3091 /* init status to no-changes */
3092 buf[0] = 0;
3093 ports = HCS_N_PORTS(oxu->hcs_params);
3094 if (ports > 7) {
3095 buf[1] = 0;
3096 retval++;
3097 }
3098
3099 /* Some boards (mostly VIA?) report bogus overcurrent indications,
3100 * causing massive log spam unless we completely ignore them. It
3101 * may be relevant that VIA VT8235 controllers, where PORT_POWER is
3102 * always set, seem to clear PORT_OCC and PORT_CSC when writing to
3103 * PORT_POWER; that's surprising, but maybe within-spec.
3104 */
3105 if (!ignore_oc)
3106 mask = PORT_CSC | PORT_PEC | PORT_OCC;
3107 else
3108 mask = PORT_CSC | PORT_PEC;
3109
3110 /* no hub change reports (bit 0) for now (power, ...) */
3111
3112 /* port N changes (bit N)? */
3113 spin_lock_irqsave(&oxu->lock, flags);
3114 for (i = 0; i < ports; i++) {
3115 temp = readl(&oxu->regs->port_status[i]);
3116
3117 /*
3118 * Return status information even for ports with OWNER set.
3119 * Otherwise khubd wouldn't see the disconnect event when a
3120 * high-speed device is switched over to the companion
3121 * controller by the user.
3122 */
3123
3124 if (!(temp & PORT_CONNECT))
3125 oxu->reset_done[i] = 0;
3126 if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 &&
3127 time_after_eq(jiffies, oxu->reset_done[i]))) {
3128 if (i < 7)
3129 buf[0] |= 1 << (i + 1);
3130 else
3131 buf[1] |= 1 << (i - 7);
3132 status = STS_PCD;
3133 }
3134 }
3135 /* FIXME autosuspend idle root hubs */
3136 spin_unlock_irqrestore(&oxu->lock, flags);
3137 return status ? retval : 0;
3138}
3139
3140/* Returns the speed of a device attached to a port on the root hub. */
3141static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu,
3142 unsigned int portsc)
3143{
3144 switch ((portsc >> 26) & 3) {
3145 case 0:
3146 return 0;
3147 case 1:
3148 return USB_PORT_STAT_LOW_SPEED;
3149 case 2:
3150 default:
3151 return USB_PORT_STAT_HIGH_SPEED;
3152 }
3153}
3154
3155#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
3156static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq,
3157 u16 wValue, u16 wIndex, char *buf, u16 wLength)
3158{
3159 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3160 int ports = HCS_N_PORTS(oxu->hcs_params);
3161 u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1];
3162 u32 temp, status;
3163 unsigned long flags;
3164 int retval = 0;
3165 unsigned selector;
3166
3167 /*
3168 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
3169 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
3170 * (track current state ourselves) ... blink for diagnostics,
3171 * power, "this is the one", etc. EHCI spec supports this.
3172 */
3173
3174 spin_lock_irqsave(&oxu->lock, flags);
3175 switch (typeReq) {
3176 case ClearHubFeature:
3177 switch (wValue) {
3178 case C_HUB_LOCAL_POWER:
3179 case C_HUB_OVER_CURRENT:
3180 /* no hub-wide feature/status flags */
3181 break;
3182 default:
3183 goto error;
3184 }
3185 break;
3186 case ClearPortFeature:
3187 if (!wIndex || wIndex > ports)
3188 goto error;
3189 wIndex--;
3190 temp = readl(status_reg);
3191
3192 /*
3193 * Even if OWNER is set, so the port is owned by the
3194 * companion controller, khubd needs to be able to clear
3195 * the port-change status bits (especially
3196 * USB_PORT_STAT_C_CONNECTION).
3197 */
3198
3199 switch (wValue) {
3200 case USB_PORT_FEAT_ENABLE:
3201 writel(temp & ~PORT_PE, status_reg);
3202 break;
3203 case USB_PORT_FEAT_C_ENABLE:
3204 writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
3205 break;
3206 case USB_PORT_FEAT_SUSPEND:
3207 if (temp & PORT_RESET)
3208 goto error;
3209 if (temp & PORT_SUSPEND) {
3210 if ((temp & PORT_PE) == 0)
3211 goto error;
3212 /* resume signaling for 20 msec */
3213 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
3214 writel(temp | PORT_RESUME, status_reg);
3215 oxu->reset_done[wIndex] = jiffies
3216 + msecs_to_jiffies(20);
3217 }
3218 break;
3219 case USB_PORT_FEAT_C_SUSPEND:
3220 /* we auto-clear this feature */
3221 break;
3222 case USB_PORT_FEAT_POWER:
3223 if (HCS_PPC(oxu->hcs_params))
3224 writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
3225 status_reg);
3226 break;
3227 case USB_PORT_FEAT_C_CONNECTION:
3228 writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
3229 break;
3230 case USB_PORT_FEAT_C_OVER_CURRENT:
3231 writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
3232 break;
3233 case USB_PORT_FEAT_C_RESET:
3234 /* GetPortStatus clears reset */
3235 break;
3236 default:
3237 goto error;
3238 }
3239 readl(&oxu->regs->command); /* unblock posted write */
3240 break;
3241 case GetHubDescriptor:
3242 ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *)
3243 buf);
3244 break;
3245 case GetHubStatus:
3246 /* no hub-wide feature/status flags */
3247 memset(buf, 0, 4);
3248 break;
3249 case GetPortStatus:
3250 if (!wIndex || wIndex > ports)
3251 goto error;
3252 wIndex--;
3253 status = 0;
3254 temp = readl(status_reg);
3255
3256 /* wPortChange bits */
3257 if (temp & PORT_CSC)
3258 status |= USB_PORT_STAT_C_CONNECTION << 16;
3259 if (temp & PORT_PEC)
3260 status |= USB_PORT_STAT_C_ENABLE << 16;
3261 if ((temp & PORT_OCC) && !ignore_oc)
3262 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3263
3264 /* whoever resumes must GetPortStatus to complete it!! */
3265 if (temp & PORT_RESUME) {
3266
3267 /* Remote Wakeup received? */
3268 if (!oxu->reset_done[wIndex]) {
3269 /* resume signaling for 20 msec */
3270 oxu->reset_done[wIndex] = jiffies
3271 + msecs_to_jiffies(20);
3272 /* check the port again */
3273 mod_timer(&oxu_to_hcd(oxu)->rh_timer,
3274 oxu->reset_done[wIndex]);
3275 }
3276
3277 /* resume completed? */
3278 else if (time_after_eq(jiffies,
3279 oxu->reset_done[wIndex])) {
3280 status |= USB_PORT_STAT_C_SUSPEND << 16;
3281 oxu->reset_done[wIndex] = 0;
3282
3283 /* stop resume signaling */
3284 temp = readl(status_reg);
3285 writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
3286 status_reg);
3287 retval = handshake(oxu, status_reg,
3288 PORT_RESUME, 0, 2000 /* 2msec */);
3289 if (retval != 0) {
3290 oxu_err(oxu,
3291 "port %d resume error %d\n",
3292 wIndex + 1, retval);
3293 goto error;
3294 }
3295 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
3296 }
3297 }
3298
3299 /* whoever resets must GetPortStatus to complete it!! */
3300 if ((temp & PORT_RESET)
3301 && time_after_eq(jiffies,
3302 oxu->reset_done[wIndex])) {
3303 status |= USB_PORT_STAT_C_RESET << 16;
3304 oxu->reset_done[wIndex] = 0;
3305
3306 /* force reset to complete */
3307 writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
3308 status_reg);
3309 /* REVISIT: some hardware needs 550+ usec to clear
3310 * this bit; seems too long to spin routinely...
3311 */
3312 retval = handshake(oxu, status_reg,
3313 PORT_RESET, 0, 750);
3314 if (retval != 0) {
3315 oxu_err(oxu, "port %d reset error %d\n",
3316 wIndex + 1, retval);
3317 goto error;
3318 }
3319
3320 /* see what we found out */
3321 temp = check_reset_complete(oxu, wIndex, status_reg,
3322 readl(status_reg));
3323 }
3324
3325 /* transfer dedicated ports to the companion hc */
3326 if ((temp & PORT_CONNECT) &&
3327 test_bit(wIndex, &oxu->companion_ports)) {
3328 temp &= ~PORT_RWC_BITS;
3329 temp |= PORT_OWNER;
3330 writel(temp, status_reg);
3331 oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1);
3332 temp = readl(status_reg);
3333 }
3334
3335 /*
3336 * Even if OWNER is set, there's no harm letting khubd
3337 * see the wPortStatus values (they should all be 0 except
3338 * for PORT_POWER anyway).
3339 */
3340
3341 if (temp & PORT_CONNECT) {
3342 status |= USB_PORT_STAT_CONNECTION;
3343 /* status may be from integrated TT */
3344 status |= oxu_port_speed(oxu, temp);
3345 }
3346 if (temp & PORT_PE)
3347 status |= USB_PORT_STAT_ENABLE;
3348 if (temp & (PORT_SUSPEND|PORT_RESUME))
3349 status |= USB_PORT_STAT_SUSPEND;
3350 if (temp & PORT_OC)
3351 status |= USB_PORT_STAT_OVERCURRENT;
3352 if (temp & PORT_RESET)
3353 status |= USB_PORT_STAT_RESET;
3354 if (temp & PORT_POWER)
3355 status |= USB_PORT_STAT_POWER;
3356
3357#ifndef OXU_VERBOSE_DEBUG
3358 if (status & ~0xffff) /* only if wPortChange is interesting */
3359#endif
3360 dbg_port(oxu, "GetStatus", wIndex + 1, temp);
3361 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
3362 break;
3363 case SetHubFeature:
3364 switch (wValue) {
3365 case C_HUB_LOCAL_POWER:
3366 case C_HUB_OVER_CURRENT:
3367 /* no hub-wide feature/status flags */
3368 break;
3369 default:
3370 goto error;
3371 }
3372 break;
3373 case SetPortFeature:
3374 selector = wIndex >> 8;
3375 wIndex &= 0xff;
3376 if (!wIndex || wIndex > ports)
3377 goto error;
3378 wIndex--;
3379 temp = readl(status_reg);
3380 if (temp & PORT_OWNER)
3381 break;
3382
3383 temp &= ~PORT_RWC_BITS;
3384 switch (wValue) {
3385 case USB_PORT_FEAT_SUSPEND:
3386 if ((temp & PORT_PE) == 0
3387 || (temp & PORT_RESET) != 0)
3388 goto error;
3389 if (device_may_wakeup(&hcd->self.root_hub->dev))
3390 temp |= PORT_WAKE_BITS;
3391 writel(temp | PORT_SUSPEND, status_reg);
3392 break;
3393 case USB_PORT_FEAT_POWER:
3394 if (HCS_PPC(oxu->hcs_params))
3395 writel(temp | PORT_POWER, status_reg);
3396 break;
3397 case USB_PORT_FEAT_RESET:
3398 if (temp & PORT_RESUME)
3399 goto error;
3400 /* line status bits may report this as low speed,
3401 * which can be fine if this root hub has a
3402 * transaction translator built in.
3403 */
3404 oxu_vdbg(oxu, "port %d reset\n", wIndex + 1);
3405 temp |= PORT_RESET;
3406 temp &= ~PORT_PE;
3407
3408 /*
3409 * caller must wait, then call GetPortStatus
3410 * usb 2.0 spec says 50 ms resets on root
3411 */
3412 oxu->reset_done[wIndex] = jiffies
3413 + msecs_to_jiffies(50);
3414 writel(temp, status_reg);
3415 break;
3416
3417 /* For downstream facing ports (these): one hub port is put
3418 * into test mode according to USB2 11.24.2.13, then the hub
3419 * must be reset (which for root hub now means rmmod+modprobe,
3420 * or else system reboot). See EHCI 2.3.9 and 4.14 for info
3421 * about the EHCI-specific stuff.
3422 */
3423 case USB_PORT_FEAT_TEST:
3424 if (!selector || selector > 5)
3425 goto error;
3426 ehci_quiesce(oxu);
3427 ehci_halt(oxu);
3428 temp |= selector << 16;
3429 writel(temp, status_reg);
3430 break;
3431
3432 default:
3433 goto error;
3434 }
3435 readl(&oxu->regs->command); /* unblock posted writes */
3436 break;
3437
3438 default:
3439error:
3440 /* "stall" on error */
3441 retval = -EPIPE;
3442 }
3443 spin_unlock_irqrestore(&oxu->lock, flags);
3444 return retval;
3445}
3446
3447#ifdef CONFIG_PM
3448
3449static int oxu_bus_suspend(struct usb_hcd *hcd)
3450{
3451 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3452 int port;
3453 int mask;
3454
3455 oxu_dbg(oxu, "suspend root hub\n");
3456
3457 if (time_before(jiffies, oxu->next_statechange))
3458 msleep(5);
3459
3460 port = HCS_N_PORTS(oxu->hcs_params);
3461 spin_lock_irq(&oxu->lock);
3462
3463 /* stop schedules, clean any completed work */
3464 if (HC_IS_RUNNING(hcd->state)) {
3465 ehci_quiesce(oxu);
3466 hcd->state = HC_STATE_QUIESCING;
3467 }
3468 oxu->command = readl(&oxu->regs->command);
3469 if (oxu->reclaim)
3470 oxu->reclaim_ready = 1;
3471 ehci_work(oxu);
3472
3473 /* Unlike other USB host controller types, EHCI doesn't have
3474 * any notion of "global" or bus-wide suspend. The driver has
3475 * to manually suspend all the active unsuspended ports, and
3476 * then manually resume them in the bus_resume() routine.
3477 */
3478 oxu->bus_suspended = 0;
3479 while (port--) {
3480 u32 __iomem *reg = &oxu->regs->port_status[port];
3481 u32 t1 = readl(reg) & ~PORT_RWC_BITS;
3482 u32 t2 = t1;
3483
3484 /* keep track of which ports we suspend */
3485 if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) &&
3486 !(t1 & PORT_SUSPEND)) {
3487 t2 |= PORT_SUSPEND;
3488 set_bit(port, &oxu->bus_suspended);
3489 }
3490
3491 /* enable remote wakeup on all ports */
3492 if (device_may_wakeup(&hcd->self.root_hub->dev))
3493 t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E;
3494 else
3495 t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E);
3496
3497 if (t1 != t2) {
3498 oxu_vdbg(oxu, "port %d, %08x -> %08x\n",
3499 port + 1, t1, t2);
3500 writel(t2, reg);
3501 }
3502 }
3503
3504 /* turn off now-idle HC */
3505 del_timer_sync(&oxu->watchdog);
3506 ehci_halt(oxu);
3507 hcd->state = HC_STATE_SUSPENDED;
3508
3509 /* allow remote wakeup */
3510 mask = INTR_MASK;
3511 if (!device_may_wakeup(&hcd->self.root_hub->dev))
3512 mask &= ~STS_PCD;
3513 writel(mask, &oxu->regs->intr_enable);
3514 readl(&oxu->regs->intr_enable);
3515
3516 oxu->next_statechange = jiffies + msecs_to_jiffies(10);
3517 spin_unlock_irq(&oxu->lock);
3518 return 0;
3519}
3520
3521/* Caller has locked the root hub, and should reset/reinit on error */
3522static int oxu_bus_resume(struct usb_hcd *hcd)
3523{
3524 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3525 u32 temp;
3526 int i;
3527
3528 if (time_before(jiffies, oxu->next_statechange))
3529 msleep(5);
3530 spin_lock_irq(&oxu->lock);
3531
3532 /* Ideally and we've got a real resume here, and no port's power
3533 * was lost. (For PCI, that means Vaux was maintained.) But we
3534 * could instead be restoring a swsusp snapshot -- so that BIOS was
3535 * the last user of the controller, not reset/pm hardware keeping
3536 * state we gave to it.
3537 */
3538 temp = readl(&oxu->regs->intr_enable);
3539 oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss");
3540
3541 /* at least some APM implementations will try to deliver
3542 * IRQs right away, so delay them until we're ready.
3543 */
3544 writel(0, &oxu->regs->intr_enable);
3545
3546 /* re-init operational registers */
3547 writel(0, &oxu->regs->segment);
3548 writel(oxu->periodic_dma, &oxu->regs->frame_list);
3549 writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
3550
3551 /* restore CMD_RUN, framelist size, and irq threshold */
3552 writel(oxu->command, &oxu->regs->command);
3553
3554 /* Some controller/firmware combinations need a delay during which
3555 * they set up the port statuses. See Bugzilla #8190. */
3556 mdelay(8);
3557
3558 /* manually resume the ports we suspended during bus_suspend() */
3559 i = HCS_N_PORTS(oxu->hcs_params);
3560 while (i--) {
3561 temp = readl(&oxu->regs->port_status[i]);
3562 temp &= ~(PORT_RWC_BITS
3563 | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E);
3564 if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
3565 oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
3566 temp |= PORT_RESUME;
3567 }
3568 writel(temp, &oxu->regs->port_status[i]);
3569 }
3570 i = HCS_N_PORTS(oxu->hcs_params);
3571 mdelay(20);
3572 while (i--) {
3573 temp = readl(&oxu->regs->port_status[i]);
3574 if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
3575 temp &= ~(PORT_RWC_BITS | PORT_RESUME);
3576 writel(temp, &oxu->regs->port_status[i]);
3577 oxu_vdbg(oxu, "resumed port %d\n", i + 1);
3578 }
3579 }
3580 (void) readl(&oxu->regs->command);
3581
3582 /* maybe re-activate the schedule(s) */
3583 temp = 0;
3584 if (oxu->async->qh_next.qh)
3585 temp |= CMD_ASE;
3586 if (oxu->periodic_sched)
3587 temp |= CMD_PSE;
3588 if (temp) {
3589 oxu->command |= temp;
3590 writel(oxu->command, &oxu->regs->command);
3591 }
3592
3593 oxu->next_statechange = jiffies + msecs_to_jiffies(5);
3594 hcd->state = HC_STATE_RUNNING;
3595
3596 /* Now we can safely re-enable irqs */
3597 writel(INTR_MASK, &oxu->regs->intr_enable);
3598
3599 spin_unlock_irq(&oxu->lock);
3600 return 0;
3601}
3602
3603#else
3604
3605static int oxu_bus_suspend(struct usb_hcd *hcd)
3606{
3607 return 0;
3608}
3609
3610static int oxu_bus_resume(struct usb_hcd *hcd)
3611{
3612 return 0;
3613}
3614
3615#endif /* CONFIG_PM */
3616
3617static const struct hc_driver oxu_hc_driver = {
3618 .description = "oxu210hp_hcd",
3619 .product_desc = "oxu210hp HCD",
3620 .hcd_priv_size = sizeof(struct oxu_hcd),
3621
3622 /*
3623 * Generic hardware linkage
3624 */
3625 .irq = oxu_irq,
3626 .flags = HCD_MEMORY | HCD_USB2,
3627
3628 /*
3629 * Basic lifecycle operations
3630 */
3631 .reset = oxu_reset,
3632 .start = oxu_run,
3633 .stop = oxu_stop,
3634 .shutdown = oxu_shutdown,
3635
3636 /*
3637 * Managing i/o requests and associated device resources
3638 */
3639 .urb_enqueue = oxu_urb_enqueue,
3640 .urb_dequeue = oxu_urb_dequeue,
3641 .endpoint_disable = oxu_endpoint_disable,
3642
3643 /*
3644 * Scheduling support
3645 */
3646 .get_frame_number = oxu_get_frame,
3647
3648 /*
3649 * Root hub support
3650 */
3651 .hub_status_data = oxu_hub_status_data,
3652 .hub_control = oxu_hub_control,
3653 .bus_suspend = oxu_bus_suspend,
3654 .bus_resume = oxu_bus_resume,
3655};
3656
3657/*
3658 * Module stuff
3659 */
3660
3661static void oxu_configuration(struct platform_device *pdev, void *base)
3662{
3663 u32 tmp;
3664
3665 /* Initialize top level registers.
3666 * First write ever
3667 */
3668 oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
3669 oxu_writel(base, OXU_SOFTRESET, OXU_SRESET);
3670 oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
3671
3672 tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL);
3673 oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040);
3674
3675 oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN |
3676 OXU_COMPARATOR | OXU_ASO_OP);
3677
3678 tmp = oxu_readl(base, OXU_CLKCTRL_SET);
3679 oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN);
3680
3681 /* Clear all top interrupt enable */
3682 oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff);
3683
3684 /* Clear all top interrupt status */
3685 oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff);
3686
3687 /* Enable all needed top interrupt except OTG SPH core */
3688 oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI);
3689}
3690
3691static int oxu_verify_id(struct platform_device *pdev, void *base)
3692{
3693 u32 id;
3694 static const char * const bo[] = {
3695 "reserved",
3696 "128-pin LQFP",
3697 "84-pin TFBGA",
3698 "reserved",
3699 };
3700
3701 /* Read controller signature register to find a match */
3702 id = oxu_readl(base, OXU_DEVICEID);
3703 dev_info(&pdev->dev, "device ID %x\n", id);
3704 if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT))
3705 return -1;
3706
3707 dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n",
3708 id >> OXU_REV_SHIFT,
3709 bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT],
3710 (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT,
3711 (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT);
3712
3713 return 0;
3714}
3715
3716static const struct hc_driver oxu_hc_driver;
3717static struct usb_hcd *oxu_create(struct platform_device *pdev,
3718 unsigned long memstart, unsigned long memlen,
3719 void *base, int irq, int otg)
3720{
3721 struct device *dev = &pdev->dev;
3722
3723 struct usb_hcd *hcd;
3724 struct oxu_hcd *oxu;
3725 int ret;
3726
3727 /* Set endian mode and host mode */
3728 oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET),
3729 OXU_USBMODE,
3730 OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS);
3731
3732 hcd = usb_create_hcd(&oxu_hc_driver, dev,
3733 otg ? "oxu210hp_otg" : "oxu210hp_sph");
3734 if (!hcd)
3735 return ERR_PTR(-ENOMEM);
3736
3737 hcd->rsrc_start = memstart;
3738 hcd->rsrc_len = memlen;
3739 hcd->regs = base;
3740 hcd->irq = irq;
3741 hcd->state = HC_STATE_HALT;
3742
3743 oxu = hcd_to_oxu(hcd);
3744 oxu->is_otg = otg;
3745
3746 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
3747 if (ret < 0)
3748 return ERR_PTR(ret);
3749
3750 return hcd;
3751}
3752
3753static int oxu_init(struct platform_device *pdev,
3754 unsigned long memstart, unsigned long memlen,
3755 void *base, int irq)
3756{
3757 struct oxu_info *info = platform_get_drvdata(pdev);
3758 struct usb_hcd *hcd;
3759 int ret;
3760
3761 /* First time configuration at start up */
3762 oxu_configuration(pdev, base);
3763
3764 ret = oxu_verify_id(pdev, base);
3765 if (ret) {
3766 dev_err(&pdev->dev, "no devices found!\n");
3767 return -ENODEV;
3768 }
3769
3770 /* Create the OTG controller */
3771 hcd = oxu_create(pdev, memstart, memlen, base, irq, 1);
3772 if (IS_ERR(hcd)) {
3773 dev_err(&pdev->dev, "cannot create OTG controller!\n");
3774 ret = PTR_ERR(hcd);
3775 goto error_create_otg;
3776 }
3777 info->hcd[0] = hcd;
3778
3779 /* Create the SPH host controller */
3780 hcd = oxu_create(pdev, memstart, memlen, base, irq, 0);
3781 if (IS_ERR(hcd)) {
3782 dev_err(&pdev->dev, "cannot create SPH controller!\n");
3783 ret = PTR_ERR(hcd);
3784 goto error_create_sph;
3785 }
3786 info->hcd[1] = hcd;
3787
3788 oxu_writel(base, OXU_CHIPIRQEN_SET,
3789 oxu_readl(base, OXU_CHIPIRQEN_SET) | 3);
3790
3791 return 0;
3792
3793error_create_sph:
3794 usb_remove_hcd(info->hcd[0]);
3795 usb_put_hcd(info->hcd[0]);
3796
3797error_create_otg:
3798 return ret;
3799}
3800
3801static int oxu_drv_probe(struct platform_device *pdev)
3802{
3803 struct resource *res;
3804 void *base;
3805 unsigned long memstart, memlen;
3806 int irq, ret;
3807 struct oxu_info *info;
3808
3809 if (usb_disabled())
3810 return -ENODEV;
3811
3812 /*
3813 * Get the platform resources
3814 */
3815 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3816 if (!res) {
3817 dev_err(&pdev->dev,
3818 "no IRQ! Check %s setup!\n", dev_name(&pdev->dev));
3819 return -ENODEV;
3820 }
3821 irq = res->start;
3822 dev_dbg(&pdev->dev, "IRQ resource %d\n", irq);
3823
3824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3825 if (!res) {
3826 dev_err(&pdev->dev, "no registers address! Check %s setup!\n",
3827 dev_name(&pdev->dev));
3828 return -ENODEV;
3829 }
3830 memstart = res->start;
3831 memlen = resource_size(res);
3832 dev_dbg(&pdev->dev, "MEM resource %lx-%lx\n", memstart, memlen);
3833 if (!request_mem_region(memstart, memlen,
3834 oxu_hc_driver.description)) {
3835 dev_dbg(&pdev->dev, "memory area already in use\n");
3836 return -EBUSY;
3837 }
3838
3839 ret = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING);
3840 if (ret) {
3841 dev_err(&pdev->dev, "error setting irq type\n");
3842 ret = -EFAULT;
3843 goto error_set_irq_type;
3844 }
3845
3846 base = ioremap(memstart, memlen);
3847 if (!base) {
3848 dev_dbg(&pdev->dev, "error mapping memory\n");
3849 ret = -EFAULT;
3850 goto error_ioremap;
3851 }
3852
3853 /* Allocate a driver data struct to hold useful info for both
3854 * SPH & OTG devices
3855 */
3856 info = kzalloc(sizeof(struct oxu_info), GFP_KERNEL);
3857 if (!info) {
3858 dev_dbg(&pdev->dev, "error allocating memory\n");
3859 ret = -EFAULT;
3860 goto error_alloc;
3861 }
3862 platform_set_drvdata(pdev, info);
3863
3864 ret = oxu_init(pdev, memstart, memlen, base, irq);
3865 if (ret < 0) {
3866 dev_dbg(&pdev->dev, "cannot init USB devices\n");
3867 goto error_init;
3868 }
3869
3870 dev_info(&pdev->dev, "devices enabled and running\n");
3871 platform_set_drvdata(pdev, info);
3872
3873 return 0;
3874
3875error_init:
3876 kfree(info);
3877 platform_set_drvdata(pdev, NULL);
3878
3879error_alloc:
3880 iounmap(base);
3881
3882error_set_irq_type:
3883error_ioremap:
3884 release_mem_region(memstart, memlen);
3885
3886 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret);
3887 return ret;
3888}
3889
3890static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd)
3891{
3892 usb_remove_hcd(hcd);
3893 usb_put_hcd(hcd);
3894}
3895
3896static int oxu_drv_remove(struct platform_device *pdev)
3897{
3898 struct oxu_info *info = platform_get_drvdata(pdev);
3899 unsigned long memstart = info->hcd[0]->rsrc_start,
3900 memlen = info->hcd[0]->rsrc_len;
3901 void *base = info->hcd[0]->regs;
3902
3903 oxu_remove(pdev, info->hcd[0]);
3904 oxu_remove(pdev, info->hcd[1]);
3905
3906 iounmap(base);
3907 release_mem_region(memstart, memlen);
3908
3909 kfree(info);
3910 platform_set_drvdata(pdev, NULL);
3911
3912 return 0;
3913}
3914
3915static void oxu_drv_shutdown(struct platform_device *pdev)
3916{
3917 oxu_drv_remove(pdev);
3918}
3919
3920#if 0
3921/* FIXME: TODO */
3922static int oxu_drv_suspend(struct device *dev)
3923{
3924 struct platform_device *pdev = to_platform_device(dev);
3925 struct usb_hcd *hcd = dev_get_drvdata(dev);
3926
3927 return 0;
3928}
3929
3930static int oxu_drv_resume(struct device *dev)
3931{
3932 struct platform_device *pdev = to_platform_device(dev);
3933 struct usb_hcd *hcd = dev_get_drvdata(dev);
3934
3935 return 0;
3936}
3937#else
3938#define oxu_drv_suspend NULL
3939#define oxu_drv_resume NULL
3940#endif
3941
3942static struct platform_driver oxu_driver = {
3943 .probe = oxu_drv_probe,
3944 .remove = oxu_drv_remove,
3945 .shutdown = oxu_drv_shutdown,
3946 .suspend = oxu_drv_suspend,
3947 .resume = oxu_drv_resume,
3948 .driver = {
3949 .name = "oxu210hp-hcd",
3950 .bus = &platform_bus_type
3951 }
3952};
3953
3954static int __init oxu_module_init(void)
3955{
3956 int retval = 0;
3957
3958 retval = platform_driver_register(&oxu_driver);
3959 if (retval < 0)
3960 return retval;
3961
3962 return retval;
3963}
3964
3965static void __exit oxu_module_cleanup(void)
3966{
3967 platform_driver_unregister(&oxu_driver);
3968}
3969
3970module_init(oxu_module_init);
3971module_exit(oxu_module_cleanup);
3972
3973MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION);
3974MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
3975MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it>
4 * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it>
5 *
6 * This code is *strongly* based on EHCI-HCD code by David Brownell since
7 * the chip is a quasi-EHCI compatible.
8 */
9
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/dmapool.h>
13#include <linux/kernel.h>
14#include <linux/delay.h>
15#include <linux/ioport.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/errno.h>
19#include <linux/timer.h>
20#include <linux/list.h>
21#include <linux/interrupt.h>
22#include <linux/usb.h>
23#include <linux/usb/hcd.h>
24#include <linux/moduleparam.h>
25#include <linux/dma-mapping.h>
26#include <linux/io.h>
27#include <linux/iopoll.h>
28
29#include <asm/irq.h>
30#include <linux/unaligned.h>
31
32#include <linux/irq.h>
33#include <linux/platform_device.h>
34
35#define DRIVER_VERSION "0.0.50"
36
37#define OXU_DEVICEID 0x00
38 #define OXU_REV_MASK 0xffff0000
39 #define OXU_REV_SHIFT 16
40 #define OXU_REV_2100 0x2100
41 #define OXU_BO_SHIFT 8
42 #define OXU_BO_MASK (0x3 << OXU_BO_SHIFT)
43 #define OXU_MAJ_REV_SHIFT 4
44 #define OXU_MAJ_REV_MASK (0xf << OXU_MAJ_REV_SHIFT)
45 #define OXU_MIN_REV_SHIFT 0
46 #define OXU_MIN_REV_MASK (0xf << OXU_MIN_REV_SHIFT)
47#define OXU_HOSTIFCONFIG 0x04
48#define OXU_SOFTRESET 0x08
49 #define OXU_SRESET (1 << 0)
50
51#define OXU_PIOBURSTREADCTRL 0x0C
52
53#define OXU_CHIPIRQSTATUS 0x10
54#define OXU_CHIPIRQEN_SET 0x14
55#define OXU_CHIPIRQEN_CLR 0x18
56 #define OXU_USBSPHLPWUI 0x00000080
57 #define OXU_USBOTGLPWUI 0x00000040
58 #define OXU_USBSPHI 0x00000002
59 #define OXU_USBOTGI 0x00000001
60
61#define OXU_CLKCTRL_SET 0x1C
62 #define OXU_SYSCLKEN 0x00000008
63 #define OXU_USBSPHCLKEN 0x00000002
64 #define OXU_USBOTGCLKEN 0x00000001
65
66#define OXU_ASO 0x68
67 #define OXU_SPHPOEN 0x00000100
68 #define OXU_OVRCCURPUPDEN 0x00000800
69 #define OXU_ASO_OP (1 << 10)
70 #define OXU_COMPARATOR 0x000004000
71
72#define OXU_USBMODE 0x1A8
73 #define OXU_VBPS 0x00000020
74 #define OXU_ES_LITTLE 0x00000000
75 #define OXU_CM_HOST_ONLY 0x00000003
76
77/*
78 * Proper EHCI structs & defines
79 */
80
81/* Magic numbers that can affect system performance */
82#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
83#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
84#define EHCI_TUNE_RL_TT 0
85#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
86#define EHCI_TUNE_MULT_TT 1
87#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
88
89struct oxu_hcd;
90
91/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
92
93/* Section 2.2 Host Controller Capability Registers */
94struct ehci_caps {
95 /* these fields are specified as 8 and 16 bit registers,
96 * but some hosts can't perform 8 or 16 bit PCI accesses.
97 */
98 u32 hc_capbase;
99#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
100#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
101 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
102#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
103#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
104#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
105#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
106#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
107#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
108#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
109
110 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
111#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
112#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
113#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
114#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
115#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
116#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
117 u8 portroute[8]; /* nibbles for routing - offset 0xC */
118} __packed;
119
120
121/* Section 2.3 Host Controller Operational Registers */
122struct ehci_regs {
123 /* USBCMD: offset 0x00 */
124 u32 command;
125/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
126#define CMD_PARK (1<<11) /* enable "park" on async qh */
127#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
128#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
129#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
130#define CMD_ASE (1<<5) /* async schedule enable */
131#define CMD_PSE (1<<4) /* periodic schedule enable */
132/* 3:2 is periodic frame list size */
133#define CMD_RESET (1<<1) /* reset HC not bus */
134#define CMD_RUN (1<<0) /* start/stop HC */
135
136 /* USBSTS: offset 0x04 */
137 u32 status;
138#define STS_ASS (1<<15) /* Async Schedule Status */
139#define STS_PSS (1<<14) /* Periodic Schedule Status */
140#define STS_RECL (1<<13) /* Reclamation */
141#define STS_HALT (1<<12) /* Not running (any reason) */
142/* some bits reserved */
143 /* these STS_* flags are also intr_enable bits (USBINTR) */
144#define STS_IAA (1<<5) /* Interrupted on async advance */
145#define STS_FATAL (1<<4) /* such as some PCI access errors */
146#define STS_FLR (1<<3) /* frame list rolled over */
147#define STS_PCD (1<<2) /* port change detect */
148#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
149#define STS_INT (1<<0) /* "normal" completion (short, ...) */
150
151#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
152
153 /* USBINTR: offset 0x08 */
154 u32 intr_enable;
155
156 /* FRINDEX: offset 0x0C */
157 u32 frame_index; /* current microframe number */
158 /* CTRLDSSEGMENT: offset 0x10 */
159 u32 segment; /* address bits 63:32 if needed */
160 /* PERIODICLISTBASE: offset 0x14 */
161 u32 frame_list; /* points to periodic list */
162 /* ASYNCLISTADDR: offset 0x18 */
163 u32 async_next; /* address of next async queue head */
164
165 u32 reserved[9];
166
167 /* CONFIGFLAG: offset 0x40 */
168 u32 configured_flag;
169#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
170
171 /* PORTSC: offset 0x44 */
172 u32 port_status[]; /* up to N_PORTS */
173/* 31:23 reserved */
174#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
175#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
176#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
177/* 19:16 for port testing */
178#define PORT_LED_OFF (0<<14)
179#define PORT_LED_AMBER (1<<14)
180#define PORT_LED_GREEN (2<<14)
181#define PORT_LED_MASK (3<<14)
182#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
183#define PORT_POWER (1<<12) /* true: has power (see PPC) */
184#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
185/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
186/* 9 reserved */
187#define PORT_RESET (1<<8) /* reset port */
188#define PORT_SUSPEND (1<<7) /* suspend port */
189#define PORT_RESUME (1<<6) /* resume it */
190#define PORT_OCC (1<<5) /* over current change */
191#define PORT_OC (1<<4) /* over current active */
192#define PORT_PEC (1<<3) /* port enable change */
193#define PORT_PE (1<<2) /* port enable */
194#define PORT_CSC (1<<1) /* connect status change */
195#define PORT_CONNECT (1<<0) /* device connected */
196#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
197} __packed;
198
199#define QTD_NEXT(dma) cpu_to_le32((u32)dma)
200
201/*
202 * EHCI Specification 0.95 Section 3.5
203 * QTD: describe data transfer components (buffer, direction, ...)
204 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
205 *
206 * These are associated only with "QH" (Queue Head) structures,
207 * used with control, bulk, and interrupt transfers.
208 */
209struct ehci_qtd {
210 /* first part defined by EHCI spec */
211 __le32 hw_next; /* see EHCI 3.5.1 */
212 __le32 hw_alt_next; /* see EHCI 3.5.2 */
213 __le32 hw_token; /* see EHCI 3.5.3 */
214#define QTD_TOGGLE (1 << 31) /* data toggle */
215#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
216#define QTD_IOC (1 << 15) /* interrupt on complete */
217#define QTD_CERR(tok) (((tok)>>10) & 0x3)
218#define QTD_PID(tok) (((tok)>>8) & 0x3)
219#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
220#define QTD_STS_HALT (1 << 6) /* halted on error */
221#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
222#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
223#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
224#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
225#define QTD_STS_STS (1 << 1) /* split transaction state */
226#define QTD_STS_PING (1 << 0) /* issue PING? */
227 __le32 hw_buf[5]; /* see EHCI 3.5.4 */
228 __le32 hw_buf_hi[5]; /* Appendix B */
229
230 /* the rest is HCD-private */
231 dma_addr_t qtd_dma; /* qtd address */
232 struct list_head qtd_list; /* sw qtd list */
233 struct urb *urb; /* qtd's urb */
234 size_t length; /* length of buffer */
235
236 u32 qtd_buffer_len;
237 void *buffer;
238 dma_addr_t buffer_dma;
239 void *transfer_buffer;
240 void *transfer_dma;
241} __aligned(32);
242
243/* mask NakCnt+T in qh->hw_alt_next */
244#define QTD_MASK cpu_to_le32 (~0x1f)
245
246#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
247
248/* Type tag from {qh, itd, sitd, fstn}->hw_next */
249#define Q_NEXT_TYPE(dma) ((dma) & cpu_to_le32 (3 << 1))
250
251/* values for that type tag */
252#define Q_TYPE_QH cpu_to_le32 (1 << 1)
253
254/* next async queue entry, or pointer to interrupt/periodic QH */
255#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
256
257/* for periodic/async schedules and qtd lists, mark end of list */
258#define EHCI_LIST_END cpu_to_le32(1) /* "null pointer" to hw */
259
260/*
261 * Entries in periodic shadow table are pointers to one of four kinds
262 * of data structure. That's dictated by the hardware; a type tag is
263 * encoded in the low bits of the hardware's periodic schedule. Use
264 * Q_NEXT_TYPE to get the tag.
265 *
266 * For entries in the async schedule, the type tag always says "qh".
267 */
268union ehci_shadow {
269 struct ehci_qh *qh; /* Q_TYPE_QH */
270 __le32 *hw_next; /* (all types) */
271 void *ptr;
272};
273
274/*
275 * EHCI Specification 0.95 Section 3.6
276 * QH: describes control/bulk/interrupt endpoints
277 * See Fig 3-7 "Queue Head Structure Layout".
278 *
279 * These appear in both the async and (for interrupt) periodic schedules.
280 */
281
282struct ehci_qh {
283 /* first part defined by EHCI spec */
284 __le32 hw_next; /* see EHCI 3.6.1 */
285 __le32 hw_info1; /* see EHCI 3.6.2 */
286#define QH_HEAD 0x00008000
287 __le32 hw_info2; /* see EHCI 3.6.2 */
288#define QH_SMASK 0x000000ff
289#define QH_CMASK 0x0000ff00
290#define QH_HUBADDR 0x007f0000
291#define QH_HUBPORT 0x3f800000
292#define QH_MULT 0xc0000000
293 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */
294
295 /* qtd overlay (hardware parts of a struct ehci_qtd) */
296 __le32 hw_qtd_next;
297 __le32 hw_alt_next;
298 __le32 hw_token;
299 __le32 hw_buf[5];
300 __le32 hw_buf_hi[5];
301
302 /* the rest is HCD-private */
303 dma_addr_t qh_dma; /* address of qh */
304 union ehci_shadow qh_next; /* ptr to qh; or periodic */
305 struct list_head qtd_list; /* sw qtd list */
306 struct ehci_qtd *dummy;
307 struct ehci_qh *reclaim; /* next to reclaim */
308
309 struct oxu_hcd *oxu;
310 struct kref kref;
311 unsigned int stamp;
312
313 u8 qh_state;
314#define QH_STATE_LINKED 1 /* HC sees this */
315#define QH_STATE_UNLINK 2 /* HC may still see this */
316#define QH_STATE_IDLE 3 /* HC doesn't see this */
317#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
318#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
319
320 /* periodic schedule info */
321 u8 usecs; /* intr bandwidth */
322 u8 gap_uf; /* uframes split/csplit gap */
323 u8 c_usecs; /* ... split completion bw */
324 u16 tt_usecs; /* tt downstream bandwidth */
325 unsigned short period; /* polling interval */
326 unsigned short start; /* where polling starts */
327#define NO_FRAME ((unsigned short)~0) /* pick new start */
328 struct usb_device *dev; /* access to TT */
329} __aligned(32);
330
331/*
332 * Proper OXU210HP structs
333 */
334
335#define OXU_OTG_CORE_OFFSET 0x00400
336#define OXU_OTG_CAP_OFFSET (OXU_OTG_CORE_OFFSET + 0x100)
337#define OXU_SPH_CORE_OFFSET 0x00800
338#define OXU_SPH_CAP_OFFSET (OXU_SPH_CORE_OFFSET + 0x100)
339
340#define OXU_OTG_MEM 0xE000
341#define OXU_SPH_MEM 0x16000
342
343/* Only how many elements & element structure are specifies here. */
344/* 2 host controllers are enabled - total size <= 28 kbytes */
345#define DEFAULT_I_TDPS 1024
346#define QHEAD_NUM 16
347#define QTD_NUM 32
348#define SITD_NUM 8
349#define MURB_NUM 8
350
351#define BUFFER_NUM 8
352#define BUFFER_SIZE 512
353
354struct oxu_info {
355 struct usb_hcd *hcd[2];
356};
357
358struct oxu_buf {
359 u8 buffer[BUFFER_SIZE];
360} __aligned(BUFFER_SIZE);
361
362struct oxu_onchip_mem {
363 struct oxu_buf db_pool[BUFFER_NUM];
364
365 u32 frame_list[DEFAULT_I_TDPS];
366 struct ehci_qh qh_pool[QHEAD_NUM];
367 struct ehci_qtd qtd_pool[QTD_NUM];
368} __aligned(4 << 10);
369
370#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
371
372struct oxu_murb {
373 struct urb urb;
374 struct urb *main;
375 u8 last;
376};
377
378struct oxu_hcd { /* one per controller */
379 unsigned int is_otg:1;
380
381 u8 qh_used[QHEAD_NUM];
382 u8 qtd_used[QTD_NUM];
383 u8 db_used[BUFFER_NUM];
384 u8 murb_used[MURB_NUM];
385
386 struct oxu_onchip_mem __iomem *mem;
387 spinlock_t mem_lock;
388
389 struct timer_list urb_timer;
390
391 struct ehci_caps __iomem *caps;
392 struct ehci_regs __iomem *regs;
393
394 u32 hcs_params; /* cached register copy */
395 spinlock_t lock;
396
397 /* async schedule support */
398 struct ehci_qh *async;
399 struct ehci_qh *reclaim;
400 unsigned int reclaim_ready:1;
401 unsigned int scanning:1;
402
403 /* periodic schedule support */
404 unsigned int periodic_size;
405 __le32 *periodic; /* hw periodic table */
406 dma_addr_t periodic_dma;
407 unsigned int i_thresh; /* uframes HC might cache */
408
409 union ehci_shadow *pshadow; /* mirror hw periodic table */
410 int next_uframe; /* scan periodic, start here */
411 unsigned int periodic_sched; /* periodic activity count */
412
413 /* per root hub port */
414 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
415 /* bit vectors (one bit per port) */
416 unsigned long bus_suspended; /* which ports were
417 * already suspended at the
418 * start of a bus suspend
419 */
420 unsigned long companion_ports;/* which ports are dedicated
421 * to the companion controller
422 */
423
424 struct timer_list watchdog;
425 unsigned long actions;
426 unsigned int stamp;
427 unsigned long next_statechange;
428 u32 command;
429
430 /* SILICON QUIRKS */
431 struct list_head urb_list; /* this is the head to urb
432 * queue that didn't get enough
433 * resources
434 */
435 struct oxu_murb *murb_pool; /* murb per split big urb */
436 unsigned int urb_len;
437
438 u8 sbrn; /* packed release number */
439};
440
441#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
442#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
443#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
444#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
445
446enum ehci_timer_action {
447 TIMER_IO_WATCHDOG,
448 TIMER_IAA_WATCHDOG,
449 TIMER_ASYNC_SHRINK,
450 TIMER_ASYNC_OFF,
451};
452
453/*
454 * Main defines
455 */
456
457#define oxu_dbg(oxu, fmt, args...) \
458 dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
459#define oxu_err(oxu, fmt, args...) \
460 dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
461#define oxu_info(oxu, fmt, args...) \
462 dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
463
464#ifdef CONFIG_DYNAMIC_DEBUG
465#define DEBUG
466#endif
467
468static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu)
469{
470 return container_of((void *) oxu, struct usb_hcd, hcd_priv);
471}
472
473static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd)
474{
475 return (struct oxu_hcd *) (hcd->hcd_priv);
476}
477
478/*
479 * Debug stuff
480 */
481
482#undef OXU_URB_TRACE
483#undef OXU_VERBOSE_DEBUG
484
485#ifdef OXU_VERBOSE_DEBUG
486#define oxu_vdbg oxu_dbg
487#else
488#define oxu_vdbg(oxu, fmt, args...) /* Nop */
489#endif
490
491#ifdef DEBUG
492
493static int __attribute__((__unused__))
494dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
495{
496 return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
497 label, label[0] ? " " : "", status,
498 (status & STS_ASS) ? " Async" : "",
499 (status & STS_PSS) ? " Periodic" : "",
500 (status & STS_RECL) ? " Recl" : "",
501 (status & STS_HALT) ? " Halt" : "",
502 (status & STS_IAA) ? " IAA" : "",
503 (status & STS_FATAL) ? " FATAL" : "",
504 (status & STS_FLR) ? " FLR" : "",
505 (status & STS_PCD) ? " PCD" : "",
506 (status & STS_ERR) ? " ERR" : "",
507 (status & STS_INT) ? " INT" : ""
508 );
509}
510
511static int __attribute__((__unused__))
512dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
513{
514 return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
515 label, label[0] ? " " : "", enable,
516 (enable & STS_IAA) ? " IAA" : "",
517 (enable & STS_FATAL) ? " FATAL" : "",
518 (enable & STS_FLR) ? " FLR" : "",
519 (enable & STS_PCD) ? " PCD" : "",
520 (enable & STS_ERR) ? " ERR" : "",
521 (enable & STS_INT) ? " INT" : ""
522 );
523}
524
525static const char *const fls_strings[] =
526 { "1024", "512", "256", "??" };
527
528static int dbg_command_buf(char *buf, unsigned len,
529 const char *label, u32 command)
530{
531 return scnprintf(buf, len,
532 "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
533 label, label[0] ? " " : "", command,
534 (command & CMD_PARK) ? "park" : "(park)",
535 CMD_PARK_CNT(command),
536 (command >> 16) & 0x3f,
537 (command & CMD_LRESET) ? " LReset" : "",
538 (command & CMD_IAAD) ? " IAAD" : "",
539 (command & CMD_ASE) ? " Async" : "",
540 (command & CMD_PSE) ? " Periodic" : "",
541 fls_strings[(command >> 2) & 0x3],
542 (command & CMD_RESET) ? " Reset" : "",
543 (command & CMD_RUN) ? "RUN" : "HALT"
544 );
545}
546
547static int dbg_port_buf(char *buf, unsigned len, const char *label,
548 int port, u32 status)
549{
550 char *sig;
551
552 /* signaling state */
553 switch (status & (3 << 10)) {
554 case 0 << 10:
555 sig = "se0";
556 break;
557 case 1 << 10:
558 sig = "k"; /* low speed */
559 break;
560 case 2 << 10:
561 sig = "j";
562 break;
563 default:
564 sig = "?";
565 break;
566 }
567
568 return scnprintf(buf, len,
569 "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
570 label, label[0] ? " " : "", port, status,
571 (status & PORT_POWER) ? " POWER" : "",
572 (status & PORT_OWNER) ? " OWNER" : "",
573 sig,
574 (status & PORT_RESET) ? " RESET" : "",
575 (status & PORT_SUSPEND) ? " SUSPEND" : "",
576 (status & PORT_RESUME) ? " RESUME" : "",
577 (status & PORT_OCC) ? " OCC" : "",
578 (status & PORT_OC) ? " OC" : "",
579 (status & PORT_PEC) ? " PEC" : "",
580 (status & PORT_PE) ? " PE" : "",
581 (status & PORT_CSC) ? " CSC" : "",
582 (status & PORT_CONNECT) ? " CONNECT" : ""
583 );
584}
585
586#else
587
588static inline int __attribute__((__unused__))
589dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
590{ return 0; }
591
592static inline int __attribute__((__unused__))
593dbg_command_buf(char *buf, unsigned len, const char *label, u32 command)
594{ return 0; }
595
596static inline int __attribute__((__unused__))
597dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
598{ return 0; }
599
600static inline int __attribute__((__unused__))
601dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status)
602{ return 0; }
603
604#endif /* DEBUG */
605
606/* functions have the "wrong" filename when they're output... */
607#define dbg_status(oxu, label, status) { \
608 char _buf[80]; \
609 dbg_status_buf(_buf, sizeof _buf, label, status); \
610 oxu_dbg(oxu, "%s\n", _buf); \
611}
612
613#define dbg_cmd(oxu, label, command) { \
614 char _buf[80]; \
615 dbg_command_buf(_buf, sizeof _buf, label, command); \
616 oxu_dbg(oxu, "%s\n", _buf); \
617}
618
619#define dbg_port(oxu, label, port, status) { \
620 char _buf[80]; \
621 dbg_port_buf(_buf, sizeof _buf, label, port, status); \
622 oxu_dbg(oxu, "%s\n", _buf); \
623}
624
625/*
626 * Module parameters
627 */
628
629/* Initial IRQ latency: faster than hw default */
630static int log2_irq_thresh; /* 0 to 6 */
631module_param(log2_irq_thresh, int, S_IRUGO);
632MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
633
634/* Initial park setting: slower than hw default */
635static unsigned park;
636module_param(park, uint, S_IRUGO);
637MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
638
639/* For flakey hardware, ignore overcurrent indicators */
640static bool ignore_oc;
641module_param(ignore_oc, bool, S_IRUGO);
642MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications");
643
644
645static void ehci_work(struct oxu_hcd *oxu);
646static int oxu_hub_control(struct usb_hcd *hcd,
647 u16 typeReq, u16 wValue, u16 wIndex,
648 char *buf, u16 wLength);
649
650/*
651 * Local functions
652 */
653
654/* Low level read/write registers functions */
655static inline u32 oxu_readl(void __iomem *base, u32 reg)
656{
657 return readl(base + reg);
658}
659
660static inline void oxu_writel(void __iomem *base, u32 reg, u32 val)
661{
662 writel(val, base + reg);
663}
664
665static inline void timer_action_done(struct oxu_hcd *oxu,
666 enum ehci_timer_action action)
667{
668 clear_bit(action, &oxu->actions);
669}
670
671static inline void timer_action(struct oxu_hcd *oxu,
672 enum ehci_timer_action action)
673{
674 if (!test_and_set_bit(action, &oxu->actions)) {
675 unsigned long t;
676
677 switch (action) {
678 case TIMER_IAA_WATCHDOG:
679 t = EHCI_IAA_JIFFIES;
680 break;
681 case TIMER_IO_WATCHDOG:
682 t = EHCI_IO_JIFFIES;
683 break;
684 case TIMER_ASYNC_OFF:
685 t = EHCI_ASYNC_JIFFIES;
686 break;
687 case TIMER_ASYNC_SHRINK:
688 default:
689 t = EHCI_SHRINK_JIFFIES;
690 break;
691 }
692 t += jiffies;
693 /* all timings except IAA watchdog can be overridden.
694 * async queue SHRINK often precedes IAA. while it's ready
695 * to go OFF neither can matter, and afterwards the IO
696 * watchdog stops unless there's still periodic traffic.
697 */
698 if (action != TIMER_IAA_WATCHDOG
699 && t > oxu->watchdog.expires
700 && timer_pending(&oxu->watchdog))
701 return;
702 mod_timer(&oxu->watchdog, t);
703 }
704}
705
706/*
707 * handshake - spin reading hc until handshake completes or fails
708 * @ptr: address of hc register to be read
709 * @mask: bits to look at in result of read
710 * @done: value of those bits when handshake succeeds
711 * @usec: timeout in microseconds
712 *
713 * Returns negative errno, or zero on success
714 *
715 * Success happens when the "mask" bits have the specified value (hardware
716 * handshake done). There are two failure modes: "usec" have passed (major
717 * hardware flakeout), or the register reads as all-ones (hardware removed).
718 *
719 * That last failure should_only happen in cases like physical cardbus eject
720 * before driver shutdown. But it also seems to be caused by bugs in cardbus
721 * bridge shutdown: shutting down the bridge before the devices using it.
722 */
723static int handshake(struct oxu_hcd *oxu, void __iomem *ptr,
724 u32 mask, u32 done, int usec)
725{
726 u32 result;
727 int ret;
728
729 ret = readl_poll_timeout_atomic(ptr, result,
730 ((result & mask) == done ||
731 result == U32_MAX),
732 1, usec);
733 if (result == U32_MAX) /* card removed */
734 return -ENODEV;
735
736 return ret;
737}
738
739/* Force HC to halt state from unknown (EHCI spec section 2.3) */
740static int ehci_halt(struct oxu_hcd *oxu)
741{
742 u32 temp = readl(&oxu->regs->status);
743
744 /* disable any irqs left enabled by previous code */
745 writel(0, &oxu->regs->intr_enable);
746
747 if ((temp & STS_HALT) != 0)
748 return 0;
749
750 temp = readl(&oxu->regs->command);
751 temp &= ~CMD_RUN;
752 writel(temp, &oxu->regs->command);
753 return handshake(oxu, &oxu->regs->status,
754 STS_HALT, STS_HALT, 16 * 125);
755}
756
757/* Put TDI/ARC silicon into EHCI mode */
758static void tdi_reset(struct oxu_hcd *oxu)
759{
760 u32 __iomem *reg_ptr;
761 u32 tmp;
762
763 reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68);
764 tmp = readl(reg_ptr);
765 tmp |= 0x3;
766 writel(tmp, reg_ptr);
767}
768
769/* Reset a non-running (STS_HALT == 1) controller */
770static int ehci_reset(struct oxu_hcd *oxu)
771{
772 int retval;
773 u32 command = readl(&oxu->regs->command);
774
775 command |= CMD_RESET;
776 dbg_cmd(oxu, "reset", command);
777 writel(command, &oxu->regs->command);
778 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
779 oxu->next_statechange = jiffies;
780 retval = handshake(oxu, &oxu->regs->command,
781 CMD_RESET, 0, 250 * 1000);
782
783 if (retval)
784 return retval;
785
786 tdi_reset(oxu);
787
788 return retval;
789}
790
791/* Idle the controller (from running) */
792static void ehci_quiesce(struct oxu_hcd *oxu)
793{
794 u32 temp;
795
796#ifdef DEBUG
797 BUG_ON(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state));
798#endif
799
800 /* wait for any schedule enables/disables to take effect */
801 temp = readl(&oxu->regs->command) << 10;
802 temp &= STS_ASS | STS_PSS;
803 if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
804 temp, 16 * 125) != 0) {
805 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
806 return;
807 }
808
809 /* then disable anything that's still active */
810 temp = readl(&oxu->regs->command);
811 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
812 writel(temp, &oxu->regs->command);
813
814 /* hardware can take 16 microframes to turn off ... */
815 if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
816 0, 16 * 125) != 0) {
817 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
818 return;
819 }
820}
821
822static int check_reset_complete(struct oxu_hcd *oxu, int index,
823 u32 __iomem *status_reg, int port_status)
824{
825 if (!(port_status & PORT_CONNECT)) {
826 oxu->reset_done[index] = 0;
827 return port_status;
828 }
829
830 /* if reset finished and it's still not enabled -- handoff */
831 if (!(port_status & PORT_PE)) {
832 oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n",
833 index+1);
834 return port_status;
835 } else
836 oxu_dbg(oxu, "port %d high speed\n", index + 1);
837
838 return port_status;
839}
840
841static void ehci_hub_descriptor(struct oxu_hcd *oxu,
842 struct usb_hub_descriptor *desc)
843{
844 int ports = HCS_N_PORTS(oxu->hcs_params);
845 u16 temp;
846
847 desc->bDescriptorType = USB_DT_HUB;
848 desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */
849 desc->bHubContrCurrent = 0;
850
851 desc->bNbrPorts = ports;
852 temp = 1 + (ports / 8);
853 desc->bDescLength = 7 + 2 * temp;
854
855 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
856 memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
857 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
858
859 temp = HUB_CHAR_INDV_PORT_OCPM; /* per-port overcurrent reporting */
860 if (HCS_PPC(oxu->hcs_params))
861 temp |= HUB_CHAR_INDV_PORT_LPSM; /* per-port power control */
862 else
863 temp |= HUB_CHAR_NO_LPSM; /* no power switching */
864 desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp);
865}
866
867
868/* Allocate an OXU210HP on-chip memory data buffer
869 *
870 * An on-chip memory data buffer is required for each OXU210HP USB transfer.
871 * Each transfer descriptor has one or more on-chip memory data buffers.
872 *
873 * Data buffers are allocated from a fix sized pool of data blocks.
874 * To minimise fragmentation and give reasonable memory utlisation,
875 * data buffers are allocated with sizes the power of 2 multiples of
876 * the block size, starting on an address a multiple of the allocated size.
877 *
878 * FIXME: callers of this function require a buffer to be allocated for
879 * len=0. This is a waste of on-chip memory and should be fix. Then this
880 * function should be changed to not allocate a buffer for len=0.
881 */
882static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len)
883{
884 int n_blocks; /* minium blocks needed to hold len */
885 int a_blocks; /* blocks allocated */
886 int i, j;
887
888 /* Don't allocate bigger than supported */
889 if (len > BUFFER_SIZE * BUFFER_NUM) {
890 oxu_err(oxu, "buffer too big (%d)\n", len);
891 return -ENOMEM;
892 }
893
894 spin_lock(&oxu->mem_lock);
895
896 /* Number of blocks needed to hold len */
897 n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE;
898
899 /* Round the number of blocks up to the power of 2 */
900 for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1)
901 ;
902
903 /* Find a suitable available data buffer */
904 for (i = 0; i < BUFFER_NUM;
905 i += max_t(int, a_blocks, oxu->db_used[i])) {
906
907 /* Check all the required blocks are available */
908 for (j = 0; j < a_blocks; j++)
909 if (oxu->db_used[i + j])
910 break;
911
912 if (j != a_blocks)
913 continue;
914
915 /* Allocate blocks found! */
916 qtd->buffer = (void *) &oxu->mem->db_pool[i];
917 qtd->buffer_dma = virt_to_phys(qtd->buffer);
918
919 qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks;
920 oxu->db_used[i] = a_blocks;
921
922 spin_unlock(&oxu->mem_lock);
923
924 return 0;
925 }
926
927 /* Failed */
928
929 spin_unlock(&oxu->mem_lock);
930
931 return -ENOMEM;
932}
933
934static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
935{
936 int index;
937
938 spin_lock(&oxu->mem_lock);
939
940 index = (qtd->buffer - (void *) &oxu->mem->db_pool[0])
941 / BUFFER_SIZE;
942 oxu->db_used[index] = 0;
943 qtd->qtd_buffer_len = 0;
944 qtd->buffer_dma = 0;
945 qtd->buffer = NULL;
946
947 spin_unlock(&oxu->mem_lock);
948}
949
950static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma)
951{
952 memset(qtd, 0, sizeof *qtd);
953 qtd->qtd_dma = dma;
954 qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
955 qtd->hw_next = EHCI_LIST_END;
956 qtd->hw_alt_next = EHCI_LIST_END;
957 INIT_LIST_HEAD(&qtd->qtd_list);
958}
959
960static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
961{
962 int index;
963
964 if (qtd->buffer)
965 oxu_buf_free(oxu, qtd);
966
967 spin_lock(&oxu->mem_lock);
968
969 index = qtd - &oxu->mem->qtd_pool[0];
970 oxu->qtd_used[index] = 0;
971
972 spin_unlock(&oxu->mem_lock);
973}
974
975static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu)
976{
977 int i;
978 struct ehci_qtd *qtd = NULL;
979
980 spin_lock(&oxu->mem_lock);
981
982 for (i = 0; i < QTD_NUM; i++)
983 if (!oxu->qtd_used[i])
984 break;
985
986 if (i < QTD_NUM) {
987 qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i];
988 memset(qtd, 0, sizeof *qtd);
989
990 qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
991 qtd->hw_next = EHCI_LIST_END;
992 qtd->hw_alt_next = EHCI_LIST_END;
993 INIT_LIST_HEAD(&qtd->qtd_list);
994
995 qtd->qtd_dma = virt_to_phys(qtd);
996
997 oxu->qtd_used[i] = 1;
998 }
999
1000 spin_unlock(&oxu->mem_lock);
1001
1002 return qtd;
1003}
1004
1005static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh)
1006{
1007 int index;
1008
1009 spin_lock(&oxu->mem_lock);
1010
1011 index = qh - &oxu->mem->qh_pool[0];
1012 oxu->qh_used[index] = 0;
1013
1014 spin_unlock(&oxu->mem_lock);
1015}
1016
1017static void qh_destroy(struct kref *kref)
1018{
1019 struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
1020 struct oxu_hcd *oxu = qh->oxu;
1021
1022 /* clean qtds first, and know this is not linked */
1023 if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
1024 oxu_dbg(oxu, "unused qh not empty!\n");
1025 BUG();
1026 }
1027 if (qh->dummy)
1028 oxu_qtd_free(oxu, qh->dummy);
1029 oxu_qh_free(oxu, qh);
1030}
1031
1032static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu)
1033{
1034 int i;
1035 struct ehci_qh *qh = NULL;
1036
1037 spin_lock(&oxu->mem_lock);
1038
1039 for (i = 0; i < QHEAD_NUM; i++)
1040 if (!oxu->qh_used[i])
1041 break;
1042
1043 if (i < QHEAD_NUM) {
1044 qh = (struct ehci_qh *) &oxu->mem->qh_pool[i];
1045 memset(qh, 0, sizeof *qh);
1046
1047 kref_init(&qh->kref);
1048 qh->oxu = oxu;
1049 qh->qh_dma = virt_to_phys(qh);
1050 INIT_LIST_HEAD(&qh->qtd_list);
1051
1052 /* dummy td enables safe urb queuing */
1053 qh->dummy = ehci_qtd_alloc(oxu);
1054 if (qh->dummy == NULL) {
1055 oxu_dbg(oxu, "no dummy td\n");
1056 oxu->qh_used[i] = 0;
1057 qh = NULL;
1058 goto unlock;
1059 }
1060
1061 oxu->qh_used[i] = 1;
1062 }
1063unlock:
1064 spin_unlock(&oxu->mem_lock);
1065
1066 return qh;
1067}
1068
1069/* to share a qh (cpu threads, or hc) */
1070static inline struct ehci_qh *qh_get(struct ehci_qh *qh)
1071{
1072 kref_get(&qh->kref);
1073 return qh;
1074}
1075
1076static inline void qh_put(struct ehci_qh *qh)
1077{
1078 kref_put(&qh->kref, qh_destroy);
1079}
1080
1081static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb)
1082{
1083 int index;
1084
1085 spin_lock(&oxu->mem_lock);
1086
1087 index = murb - &oxu->murb_pool[0];
1088 oxu->murb_used[index] = 0;
1089
1090 spin_unlock(&oxu->mem_lock);
1091}
1092
1093static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu)
1094
1095{
1096 int i;
1097 struct oxu_murb *murb = NULL;
1098
1099 spin_lock(&oxu->mem_lock);
1100
1101 for (i = 0; i < MURB_NUM; i++)
1102 if (!oxu->murb_used[i])
1103 break;
1104
1105 if (i < MURB_NUM) {
1106 murb = &(oxu->murb_pool)[i];
1107
1108 oxu->murb_used[i] = 1;
1109 }
1110
1111 spin_unlock(&oxu->mem_lock);
1112
1113 return murb;
1114}
1115
1116/* The queue heads and transfer descriptors are managed from pools tied
1117 * to each of the "per device" structures.
1118 * This is the initialisation and cleanup code.
1119 */
1120static void ehci_mem_cleanup(struct oxu_hcd *oxu)
1121{
1122 kfree(oxu->murb_pool);
1123 oxu->murb_pool = NULL;
1124
1125 if (oxu->async)
1126 qh_put(oxu->async);
1127 oxu->async = NULL;
1128
1129 del_timer(&oxu->urb_timer);
1130
1131 oxu->periodic = NULL;
1132
1133 /* shadow periodic table */
1134 kfree(oxu->pshadow);
1135 oxu->pshadow = NULL;
1136}
1137
1138/* Remember to add cleanup code (above) if you add anything here.
1139 */
1140static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags)
1141{
1142 int i;
1143
1144 for (i = 0; i < oxu->periodic_size; i++)
1145 oxu->mem->frame_list[i] = EHCI_LIST_END;
1146 for (i = 0; i < QHEAD_NUM; i++)
1147 oxu->qh_used[i] = 0;
1148 for (i = 0; i < QTD_NUM; i++)
1149 oxu->qtd_used[i] = 0;
1150
1151 oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags);
1152 if (!oxu->murb_pool)
1153 goto fail;
1154
1155 for (i = 0; i < MURB_NUM; i++)
1156 oxu->murb_used[i] = 0;
1157
1158 oxu->async = oxu_qh_alloc(oxu);
1159 if (!oxu->async)
1160 goto fail;
1161
1162 oxu->periodic = (__le32 *) &oxu->mem->frame_list;
1163 oxu->periodic_dma = virt_to_phys(oxu->periodic);
1164
1165 for (i = 0; i < oxu->periodic_size; i++)
1166 oxu->periodic[i] = EHCI_LIST_END;
1167
1168 /* software shadow of hardware table */
1169 oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags);
1170 if (oxu->pshadow != NULL)
1171 return 0;
1172
1173fail:
1174 oxu_dbg(oxu, "couldn't init memory\n");
1175 ehci_mem_cleanup(oxu);
1176 return -ENOMEM;
1177}
1178
1179/* Fill a qtd, returning how much of the buffer we were able to queue up.
1180 */
1181static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len,
1182 int token, int maxpacket)
1183{
1184 int i, count;
1185 u64 addr = buf;
1186
1187 /* one buffer entry per 4K ... first might be short or unaligned */
1188 qtd->hw_buf[0] = cpu_to_le32((u32)addr);
1189 qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32));
1190 count = 0x1000 - (buf & 0x0fff); /* rest of that page */
1191 if (likely(len < count)) /* ... iff needed */
1192 count = len;
1193 else {
1194 buf += 0x1000;
1195 buf &= ~0x0fff;
1196
1197 /* per-qtd limit: from 16K to 20K (best alignment) */
1198 for (i = 1; count < len && i < 5; i++) {
1199 addr = buf;
1200 qtd->hw_buf[i] = cpu_to_le32((u32)addr);
1201 qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32));
1202 buf += 0x1000;
1203 if ((count + 0x1000) < len)
1204 count += 0x1000;
1205 else
1206 count = len;
1207 }
1208
1209 /* short packets may only terminate transfers */
1210 if (count != len)
1211 count -= (count % maxpacket);
1212 }
1213 qtd->hw_token = cpu_to_le32((count << 16) | token);
1214 qtd->length = count;
1215
1216 return count;
1217}
1218
1219static inline void qh_update(struct oxu_hcd *oxu,
1220 struct ehci_qh *qh, struct ehci_qtd *qtd)
1221{
1222 /* writes to an active overlay are unsafe */
1223 BUG_ON(qh->qh_state != QH_STATE_IDLE);
1224
1225 qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma);
1226 qh->hw_alt_next = EHCI_LIST_END;
1227
1228 /* Except for control endpoints, we make hardware maintain data
1229 * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
1230 * and set the pseudo-toggle in udev. Only usb_clear_halt() will
1231 * ever clear it.
1232 */
1233 if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) {
1234 unsigned is_out, epnum;
1235
1236 is_out = !(qtd->hw_token & cpu_to_le32(1 << 8));
1237 epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f;
1238 if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
1239 qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE);
1240 usb_settoggle(qh->dev, epnum, is_out, 1);
1241 }
1242 }
1243
1244 /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
1245 wmb();
1246 qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING);
1247}
1248
1249/* If it weren't for a common silicon quirk (writing the dummy into the qh
1250 * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
1251 * recovery (including urb dequeue) would need software changes to a QH...
1252 */
1253static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh)
1254{
1255 struct ehci_qtd *qtd;
1256
1257 if (list_empty(&qh->qtd_list))
1258 qtd = qh->dummy;
1259 else {
1260 qtd = list_entry(qh->qtd_list.next,
1261 struct ehci_qtd, qtd_list);
1262 /* first qtd may already be partially processed */
1263 if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current)
1264 qtd = NULL;
1265 }
1266
1267 if (qtd)
1268 qh_update(oxu, qh, qtd);
1269}
1270
1271static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb,
1272 size_t length, u32 token)
1273{
1274 /* count IN/OUT bytes, not SETUP (even short packets) */
1275 if (likely(QTD_PID(token) != 2))
1276 urb->actual_length += length - QTD_LENGTH(token);
1277
1278 /* don't modify error codes */
1279 if (unlikely(urb->status != -EINPROGRESS))
1280 return;
1281
1282 /* force cleanup after short read; not always an error */
1283 if (unlikely(IS_SHORT_READ(token)))
1284 urb->status = -EREMOTEIO;
1285
1286 /* serious "can't proceed" faults reported by the hardware */
1287 if (token & QTD_STS_HALT) {
1288 if (token & QTD_STS_BABBLE) {
1289 /* FIXME "must" disable babbling device's port too */
1290 urb->status = -EOVERFLOW;
1291 } else if (token & QTD_STS_MMF) {
1292 /* fs/ls interrupt xfer missed the complete-split */
1293 urb->status = -EPROTO;
1294 } else if (token & QTD_STS_DBE) {
1295 urb->status = (QTD_PID(token) == 1) /* IN ? */
1296 ? -ENOSR /* hc couldn't read data */
1297 : -ECOMM; /* hc couldn't write data */
1298 } else if (token & QTD_STS_XACT) {
1299 /* timeout, bad crc, wrong PID, etc; retried */
1300 if (QTD_CERR(token))
1301 urb->status = -EPIPE;
1302 else {
1303 oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n",
1304 urb->dev->devpath,
1305 usb_pipeendpoint(urb->pipe),
1306 usb_pipein(urb->pipe) ? "in" : "out");
1307 urb->status = -EPROTO;
1308 }
1309 /* CERR nonzero + no errors + halt --> stall */
1310 } else if (QTD_CERR(token))
1311 urb->status = -EPIPE;
1312 else /* unknown */
1313 urb->status = -EPROTO;
1314
1315 oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n",
1316 usb_pipedevice(urb->pipe),
1317 usb_pipeendpoint(urb->pipe),
1318 usb_pipein(urb->pipe) ? "in" : "out",
1319 token, urb->status);
1320 }
1321}
1322
1323static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb)
1324__releases(oxu->lock)
1325__acquires(oxu->lock)
1326{
1327 if (likely(urb->hcpriv != NULL)) {
1328 struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv;
1329
1330 /* S-mask in a QH means it's an interrupt urb */
1331 if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) {
1332
1333 /* ... update hc-wide periodic stats (for usbfs) */
1334 oxu_to_hcd(oxu)->self.bandwidth_int_reqs--;
1335 }
1336 qh_put(qh);
1337 }
1338
1339 urb->hcpriv = NULL;
1340 switch (urb->status) {
1341 case -EINPROGRESS: /* success */
1342 urb->status = 0;
1343 break;
1344 default: /* fault */
1345 break;
1346 case -EREMOTEIO: /* fault or normal */
1347 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
1348 urb->status = 0;
1349 break;
1350 case -ECONNRESET: /* canceled */
1351 case -ENOENT:
1352 break;
1353 }
1354
1355#ifdef OXU_URB_TRACE
1356 oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n",
1357 __func__, urb->dev->devpath, urb,
1358 usb_pipeendpoint(urb->pipe),
1359 usb_pipein(urb->pipe) ? "in" : "out",
1360 urb->status,
1361 urb->actual_length, urb->transfer_buffer_length);
1362#endif
1363
1364 /* complete() can reenter this HCD */
1365 spin_unlock(&oxu->lock);
1366 usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status);
1367 spin_lock(&oxu->lock);
1368}
1369
1370static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
1371static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
1372
1373static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
1374static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
1375
1376#define HALT_BIT cpu_to_le32(QTD_STS_HALT)
1377
1378/* Process and free completed qtds for a qh, returning URBs to drivers.
1379 * Chases up to qh->hw_current. Returns number of completions called,
1380 * indicating how much "real" work we did.
1381 */
1382static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh)
1383{
1384 struct ehci_qtd *last = NULL, *end = qh->dummy;
1385 struct ehci_qtd *qtd, *tmp;
1386 int stopped;
1387 unsigned count = 0;
1388 int do_status = 0;
1389 u8 state;
1390 struct oxu_murb *murb = NULL;
1391
1392 if (unlikely(list_empty(&qh->qtd_list)))
1393 return count;
1394
1395 /* completions (or tasks on other cpus) must never clobber HALT
1396 * till we've gone through and cleaned everything up, even when
1397 * they add urbs to this qh's queue or mark them for unlinking.
1398 *
1399 * NOTE: unlinking expects to be done in queue order.
1400 */
1401 state = qh->qh_state;
1402 qh->qh_state = QH_STATE_COMPLETING;
1403 stopped = (state == QH_STATE_IDLE);
1404
1405 /* remove de-activated QTDs from front of queue.
1406 * after faults (including short reads), cleanup this urb
1407 * then let the queue advance.
1408 * if queue is stopped, handles unlinks.
1409 */
1410 list_for_each_entry_safe(qtd, tmp, &qh->qtd_list, qtd_list) {
1411 struct urb *urb;
1412 u32 token = 0;
1413
1414 urb = qtd->urb;
1415
1416 /* Clean up any state from previous QTD ...*/
1417 if (last) {
1418 if (likely(last->urb != urb)) {
1419 if (last->urb->complete == NULL) {
1420 murb = (struct oxu_murb *) last->urb;
1421 last->urb = murb->main;
1422 if (murb->last) {
1423 ehci_urb_done(oxu, last->urb);
1424 count++;
1425 }
1426 oxu_murb_free(oxu, murb);
1427 } else {
1428 ehci_urb_done(oxu, last->urb);
1429 count++;
1430 }
1431 }
1432 oxu_qtd_free(oxu, last);
1433 last = NULL;
1434 }
1435
1436 /* ignore urbs submitted during completions we reported */
1437 if (qtd == end)
1438 break;
1439
1440 /* hardware copies qtd out of qh overlay */
1441 rmb();
1442 token = le32_to_cpu(qtd->hw_token);
1443
1444 /* always clean up qtds the hc de-activated */
1445 if ((token & QTD_STS_ACTIVE) == 0) {
1446
1447 if ((token & QTD_STS_HALT) != 0) {
1448 stopped = 1;
1449
1450 /* magic dummy for some short reads; qh won't advance.
1451 * that silicon quirk can kick in with this dummy too.
1452 */
1453 } else if (IS_SHORT_READ(token) &&
1454 !(qtd->hw_alt_next & EHCI_LIST_END)) {
1455 stopped = 1;
1456 goto halt;
1457 }
1458
1459 /* stop scanning when we reach qtds the hc is using */
1460 } else if (likely(!stopped &&
1461 HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) {
1462 break;
1463
1464 } else {
1465 stopped = 1;
1466
1467 if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)))
1468 urb->status = -ESHUTDOWN;
1469
1470 /* ignore active urbs unless some previous qtd
1471 * for the urb faulted (including short read) or
1472 * its urb was canceled. we may patch qh or qtds.
1473 */
1474 if (likely(urb->status == -EINPROGRESS))
1475 continue;
1476
1477 /* issue status after short control reads */
1478 if (unlikely(do_status != 0)
1479 && QTD_PID(token) == 0 /* OUT */) {
1480 do_status = 0;
1481 continue;
1482 }
1483
1484 /* token in overlay may be most current */
1485 if (state == QH_STATE_IDLE
1486 && cpu_to_le32(qtd->qtd_dma)
1487 == qh->hw_current)
1488 token = le32_to_cpu(qh->hw_token);
1489
1490 /* force halt for unlinked or blocked qh, so we'll
1491 * patch the qh later and so that completions can't
1492 * activate it while we "know" it's stopped.
1493 */
1494 if ((HALT_BIT & qh->hw_token) == 0) {
1495halt:
1496 qh->hw_token |= HALT_BIT;
1497 wmb();
1498 }
1499 }
1500
1501 /* Remove it from the queue */
1502 qtd_copy_status(oxu, urb->complete ?
1503 urb : ((struct oxu_murb *) urb)->main,
1504 qtd->length, token);
1505 if ((usb_pipein(qtd->urb->pipe)) &&
1506 (NULL != qtd->transfer_buffer))
1507 memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length);
1508 do_status = (urb->status == -EREMOTEIO)
1509 && usb_pipecontrol(urb->pipe);
1510
1511 if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
1512 last = list_entry(qtd->qtd_list.prev,
1513 struct ehci_qtd, qtd_list);
1514 last->hw_next = qtd->hw_next;
1515 }
1516 list_del(&qtd->qtd_list);
1517 last = qtd;
1518 }
1519
1520 /* last urb's completion might still need calling */
1521 if (likely(last != NULL)) {
1522 if (last->urb->complete == NULL) {
1523 murb = (struct oxu_murb *) last->urb;
1524 last->urb = murb->main;
1525 if (murb->last) {
1526 ehci_urb_done(oxu, last->urb);
1527 count++;
1528 }
1529 oxu_murb_free(oxu, murb);
1530 } else {
1531 ehci_urb_done(oxu, last->urb);
1532 count++;
1533 }
1534 oxu_qtd_free(oxu, last);
1535 }
1536
1537 /* restore original state; caller must unlink or relink */
1538 qh->qh_state = state;
1539
1540 /* be sure the hardware's done with the qh before refreshing
1541 * it after fault cleanup, or recovering from silicon wrongly
1542 * overlaying the dummy qtd (which reduces DMA chatter).
1543 */
1544 if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) {
1545 switch (state) {
1546 case QH_STATE_IDLE:
1547 qh_refresh(oxu, qh);
1548 break;
1549 case QH_STATE_LINKED:
1550 /* should be rare for periodic transfers,
1551 * except maybe high bandwidth ...
1552 */
1553 if ((cpu_to_le32(QH_SMASK)
1554 & qh->hw_info2) != 0) {
1555 intr_deschedule(oxu, qh);
1556 (void) qh_schedule(oxu, qh);
1557 } else
1558 unlink_async(oxu, qh);
1559 break;
1560 /* otherwise, unlink already started */
1561 }
1562 }
1563
1564 return count;
1565}
1566
1567/* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */
1568#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
1569/* ... and packet size, for any kind of endpoint descriptor */
1570#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1571
1572/* Reverse of qh_urb_transaction: free a list of TDs.
1573 * used for cleanup after errors, before HC sees an URB's TDs.
1574 */
1575static void qtd_list_free(struct oxu_hcd *oxu,
1576 struct urb *urb, struct list_head *head)
1577{
1578 struct ehci_qtd *qtd, *temp;
1579
1580 list_for_each_entry_safe(qtd, temp, head, qtd_list) {
1581 list_del(&qtd->qtd_list);
1582 oxu_qtd_free(oxu, qtd);
1583 }
1584}
1585
1586/* Create a list of filled qtds for this URB; won't link into qh.
1587 */
1588static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu,
1589 struct urb *urb,
1590 struct list_head *head,
1591 gfp_t flags)
1592{
1593 struct ehci_qtd *qtd, *qtd_prev;
1594 dma_addr_t buf;
1595 int len, maxpacket;
1596 int is_input;
1597 u32 token;
1598 void *transfer_buf = NULL;
1599 int ret;
1600
1601 /*
1602 * URBs map to sequences of QTDs: one logical transaction
1603 */
1604 qtd = ehci_qtd_alloc(oxu);
1605 if (unlikely(!qtd))
1606 return NULL;
1607 list_add_tail(&qtd->qtd_list, head);
1608 qtd->urb = urb;
1609
1610 token = QTD_STS_ACTIVE;
1611 token |= (EHCI_TUNE_CERR << 10);
1612 /* for split transactions, SplitXState initialized to zero */
1613
1614 len = urb->transfer_buffer_length;
1615 is_input = usb_pipein(urb->pipe);
1616 if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input)
1617 urb->transfer_buffer = phys_to_virt(urb->transfer_dma);
1618
1619 if (usb_pipecontrol(urb->pipe)) {
1620 /* SETUP pid */
1621 ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest));
1622 if (ret)
1623 goto cleanup;
1624
1625 qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest),
1626 token | (2 /* "setup" */ << 8), 8);
1627 memcpy(qtd->buffer, qtd->urb->setup_packet,
1628 sizeof(struct usb_ctrlrequest));
1629
1630 /* ... and always at least one more pid */
1631 token ^= QTD_TOGGLE;
1632 qtd_prev = qtd;
1633 qtd = ehci_qtd_alloc(oxu);
1634 if (unlikely(!qtd))
1635 goto cleanup;
1636 qtd->urb = urb;
1637 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
1638 list_add_tail(&qtd->qtd_list, head);
1639
1640 /* for zero length DATA stages, STATUS is always IN */
1641 if (len == 0)
1642 token |= (1 /* "in" */ << 8);
1643 }
1644
1645 /*
1646 * Data transfer stage: buffer setup
1647 */
1648
1649 ret = oxu_buf_alloc(oxu, qtd, len);
1650 if (ret)
1651 goto cleanup;
1652
1653 buf = qtd->buffer_dma;
1654 transfer_buf = urb->transfer_buffer;
1655
1656 if (!is_input)
1657 memcpy(qtd->buffer, qtd->urb->transfer_buffer, len);
1658
1659 if (is_input)
1660 token |= (1 /* "in" */ << 8);
1661 /* else it's already initted to "out" pid (0 << 8) */
1662
1663 maxpacket = usb_maxpacket(urb->dev, urb->pipe);
1664
1665 /*
1666 * buffer gets wrapped in one or more qtds;
1667 * last one may be "short" (including zero len)
1668 * and may serve as a control status ack
1669 */
1670 for (;;) {
1671 int this_qtd_len;
1672
1673 this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket);
1674 qtd->transfer_buffer = transfer_buf;
1675 len -= this_qtd_len;
1676 buf += this_qtd_len;
1677 transfer_buf += this_qtd_len;
1678 if (is_input)
1679 qtd->hw_alt_next = oxu->async->hw_alt_next;
1680
1681 /* qh makes control packets use qtd toggle; maybe switch it */
1682 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1683 token ^= QTD_TOGGLE;
1684
1685 if (likely(len <= 0))
1686 break;
1687
1688 qtd_prev = qtd;
1689 qtd = ehci_qtd_alloc(oxu);
1690 if (unlikely(!qtd))
1691 goto cleanup;
1692 if (likely(len > 0)) {
1693 ret = oxu_buf_alloc(oxu, qtd, len);
1694 if (ret)
1695 goto cleanup;
1696 }
1697 qtd->urb = urb;
1698 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
1699 list_add_tail(&qtd->qtd_list, head);
1700 }
1701
1702 /* unless the bulk/interrupt caller wants a chance to clean
1703 * up after short reads, hc should advance qh past this urb
1704 */
1705 if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
1706 || usb_pipecontrol(urb->pipe)))
1707 qtd->hw_alt_next = EHCI_LIST_END;
1708
1709 /*
1710 * control requests may need a terminating data "status" ack;
1711 * bulk ones may need a terminating short packet (zero length).
1712 */
1713 if (likely(urb->transfer_buffer_length != 0)) {
1714 int one_more = 0;
1715
1716 if (usb_pipecontrol(urb->pipe)) {
1717 one_more = 1;
1718 token ^= 0x0100; /* "in" <--> "out" */
1719 token |= QTD_TOGGLE; /* force DATA1 */
1720 } else if (usb_pipebulk(urb->pipe)
1721 && (urb->transfer_flags & URB_ZERO_PACKET)
1722 && !(urb->transfer_buffer_length % maxpacket)) {
1723 one_more = 1;
1724 }
1725 if (one_more) {
1726 qtd_prev = qtd;
1727 qtd = ehci_qtd_alloc(oxu);
1728 if (unlikely(!qtd))
1729 goto cleanup;
1730 qtd->urb = urb;
1731 qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
1732 list_add_tail(&qtd->qtd_list, head);
1733
1734 /* never any data in such packets */
1735 qtd_fill(qtd, 0, 0, token, 0);
1736 }
1737 }
1738
1739 /* by default, enable interrupt on urb completion */
1740 qtd->hw_token |= cpu_to_le32(QTD_IOC);
1741 return head;
1742
1743cleanup:
1744 qtd_list_free(oxu, urb, head);
1745 return NULL;
1746}
1747
1748/* Each QH holds a qtd list; a QH is used for everything except iso.
1749 *
1750 * For interrupt urbs, the scheduler must set the microframe scheduling
1751 * mask(s) each time the QH gets scheduled. For highspeed, that's
1752 * just one microframe in the s-mask. For split interrupt transactions
1753 * there are additional complications: c-mask, maybe FSTNs.
1754 */
1755static struct ehci_qh *qh_make(struct oxu_hcd *oxu,
1756 struct urb *urb, gfp_t flags)
1757{
1758 struct ehci_qh *qh = oxu_qh_alloc(oxu);
1759 u32 info1 = 0, info2 = 0;
1760 int is_input, type;
1761 int maxp = 0;
1762
1763 if (!qh)
1764 return qh;
1765
1766 /*
1767 * init endpoint/device data for this QH
1768 */
1769 info1 |= usb_pipeendpoint(urb->pipe) << 8;
1770 info1 |= usb_pipedevice(urb->pipe) << 0;
1771
1772 is_input = usb_pipein(urb->pipe);
1773 type = usb_pipetype(urb->pipe);
1774 maxp = usb_maxpacket(urb->dev, urb->pipe);
1775
1776 /* Compute interrupt scheduling parameters just once, and save.
1777 * - allowing for high bandwidth, how many nsec/uframe are used?
1778 * - split transactions need a second CSPLIT uframe; same question
1779 * - splits also need a schedule gap (for full/low speed I/O)
1780 * - qh has a polling interval
1781 *
1782 * For control/bulk requests, the HC or TT handles these.
1783 */
1784 if (type == PIPE_INTERRUPT) {
1785 qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
1786 is_input, 0,
1787 hb_mult(maxp) * max_packet(maxp)));
1788 qh->start = NO_FRAME;
1789
1790 if (urb->dev->speed == USB_SPEED_HIGH) {
1791 qh->c_usecs = 0;
1792 qh->gap_uf = 0;
1793
1794 qh->period = urb->interval >> 3;
1795 if (qh->period == 0 && urb->interval != 1) {
1796 /* NOTE interval 2 or 4 uframes could work.
1797 * But interval 1 scheduling is simpler, and
1798 * includes high bandwidth.
1799 */
1800 oxu_dbg(oxu, "intr period %d uframes, NYET!\n",
1801 urb->interval);
1802 goto done;
1803 }
1804 } else {
1805 struct usb_tt *tt = urb->dev->tt;
1806 int think_time;
1807
1808 /* gap is f(FS/LS transfer times) */
1809 qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
1810 is_input, 0, maxp) / (125 * 1000);
1811
1812 /* FIXME this just approximates SPLIT/CSPLIT times */
1813 if (is_input) { /* SPLIT, gap, CSPLIT+DATA */
1814 qh->c_usecs = qh->usecs + HS_USECS(0);
1815 qh->usecs = HS_USECS(1);
1816 } else { /* SPLIT+DATA, gap, CSPLIT */
1817 qh->usecs += HS_USECS(1);
1818 qh->c_usecs = HS_USECS(0);
1819 }
1820
1821 think_time = tt ? tt->think_time : 0;
1822 qh->tt_usecs = NS_TO_US(think_time +
1823 usb_calc_bus_time(urb->dev->speed,
1824 is_input, 0, max_packet(maxp)));
1825 qh->period = urb->interval;
1826 }
1827 }
1828
1829 /* support for tt scheduling, and access to toggles */
1830 qh->dev = urb->dev;
1831
1832 /* using TT? */
1833 switch (urb->dev->speed) {
1834 case USB_SPEED_LOW:
1835 info1 |= (1 << 12); /* EPS "low" */
1836 fallthrough;
1837
1838 case USB_SPEED_FULL:
1839 /* EPS 0 means "full" */
1840 if (type != PIPE_INTERRUPT)
1841 info1 |= (EHCI_TUNE_RL_TT << 28);
1842 if (type == PIPE_CONTROL) {
1843 info1 |= (1 << 27); /* for TT */
1844 info1 |= 1 << 14; /* toggle from qtd */
1845 }
1846 info1 |= maxp << 16;
1847
1848 info2 |= (EHCI_TUNE_MULT_TT << 30);
1849 info2 |= urb->dev->ttport << 23;
1850
1851 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
1852
1853 break;
1854
1855 case USB_SPEED_HIGH: /* no TT involved */
1856 info1 |= (2 << 12); /* EPS "high" */
1857 if (type == PIPE_CONTROL) {
1858 info1 |= (EHCI_TUNE_RL_HS << 28);
1859 info1 |= 64 << 16; /* usb2 fixed maxpacket */
1860 info1 |= 1 << 14; /* toggle from qtd */
1861 info2 |= (EHCI_TUNE_MULT_HS << 30);
1862 } else if (type == PIPE_BULK) {
1863 info1 |= (EHCI_TUNE_RL_HS << 28);
1864 info1 |= 512 << 16; /* usb2 fixed maxpacket */
1865 info2 |= (EHCI_TUNE_MULT_HS << 30);
1866 } else { /* PIPE_INTERRUPT */
1867 info1 |= max_packet(maxp) << 16;
1868 info2 |= hb_mult(maxp) << 30;
1869 }
1870 break;
1871 default:
1872 oxu_dbg(oxu, "bogus dev %p speed %d\n", urb->dev, urb->dev->speed);
1873done:
1874 qh_put(qh);
1875 return NULL;
1876 }
1877
1878 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
1879
1880 /* init as live, toggle clear, advance to dummy */
1881 qh->qh_state = QH_STATE_IDLE;
1882 qh->hw_info1 = cpu_to_le32(info1);
1883 qh->hw_info2 = cpu_to_le32(info2);
1884 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
1885 qh_refresh(oxu, qh);
1886 return qh;
1887}
1888
1889/* Move qh (and its qtds) onto async queue; maybe enable queue.
1890 */
1891static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
1892{
1893 __le32 dma = QH_NEXT(qh->qh_dma);
1894 struct ehci_qh *head;
1895
1896 /* (re)start the async schedule? */
1897 head = oxu->async;
1898 timer_action_done(oxu, TIMER_ASYNC_OFF);
1899 if (!head->qh_next.qh) {
1900 u32 cmd = readl(&oxu->regs->command);
1901
1902 if (!(cmd & CMD_ASE)) {
1903 /* in case a clear of CMD_ASE didn't take yet */
1904 (void)handshake(oxu, &oxu->regs->status,
1905 STS_ASS, 0, 150);
1906 cmd |= CMD_ASE | CMD_RUN;
1907 writel(cmd, &oxu->regs->command);
1908 oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
1909 /* posted write need not be known to HC yet ... */
1910 }
1911 }
1912
1913 /* clear halt and/or toggle; and maybe recover from silicon quirk */
1914 if (qh->qh_state == QH_STATE_IDLE)
1915 qh_refresh(oxu, qh);
1916
1917 /* splice right after start */
1918 qh->qh_next = head->qh_next;
1919 qh->hw_next = head->hw_next;
1920 wmb();
1921
1922 head->qh_next.qh = qh;
1923 head->hw_next = dma;
1924
1925 qh->qh_state = QH_STATE_LINKED;
1926 /* qtd completions reported later by interrupt */
1927}
1928
1929#define QH_ADDR_MASK cpu_to_le32(0x7f)
1930
1931/*
1932 * For control/bulk/interrupt, return QH with these TDs appended.
1933 * Allocates and initializes the QH if necessary.
1934 * Returns null if it can't allocate a QH it needs to.
1935 * If the QH has TDs (urbs) already, that's great.
1936 */
1937static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu,
1938 struct urb *urb, struct list_head *qtd_list,
1939 int epnum, void **ptr)
1940{
1941 struct ehci_qh *qh = NULL;
1942
1943 qh = (struct ehci_qh *) *ptr;
1944 if (unlikely(qh == NULL)) {
1945 /* can't sleep here, we have oxu->lock... */
1946 qh = qh_make(oxu, urb, GFP_ATOMIC);
1947 *ptr = qh;
1948 }
1949 if (likely(qh != NULL)) {
1950 struct ehci_qtd *qtd;
1951
1952 if (unlikely(list_empty(qtd_list)))
1953 qtd = NULL;
1954 else
1955 qtd = list_entry(qtd_list->next, struct ehci_qtd,
1956 qtd_list);
1957
1958 /* control qh may need patching ... */
1959 if (unlikely(epnum == 0)) {
1960
1961 /* usb_reset_device() briefly reverts to address 0 */
1962 if (usb_pipedevice(urb->pipe) == 0)
1963 qh->hw_info1 &= ~QH_ADDR_MASK;
1964 }
1965
1966 /* just one way to queue requests: swap with the dummy qtd.
1967 * only hc or qh_refresh() ever modify the overlay.
1968 */
1969 if (likely(qtd != NULL)) {
1970 struct ehci_qtd *dummy;
1971 dma_addr_t dma;
1972 __le32 token;
1973
1974 /* to avoid racing the HC, use the dummy td instead of
1975 * the first td of our list (becomes new dummy). both
1976 * tds stay deactivated until we're done, when the
1977 * HC is allowed to fetch the old dummy (4.10.2).
1978 */
1979 token = qtd->hw_token;
1980 qtd->hw_token = HALT_BIT;
1981 wmb();
1982 dummy = qh->dummy;
1983
1984 dma = dummy->qtd_dma;
1985 *dummy = *qtd;
1986 dummy->qtd_dma = dma;
1987
1988 list_del(&qtd->qtd_list);
1989 list_add(&dummy->qtd_list, qtd_list);
1990 list_splice(qtd_list, qh->qtd_list.prev);
1991
1992 ehci_qtd_init(qtd, qtd->qtd_dma);
1993 qh->dummy = qtd;
1994
1995 /* hc must see the new dummy at list end */
1996 dma = qtd->qtd_dma;
1997 qtd = list_entry(qh->qtd_list.prev,
1998 struct ehci_qtd, qtd_list);
1999 qtd->hw_next = QTD_NEXT(dma);
2000
2001 /* let the hc process these next qtds */
2002 dummy->hw_token = (token & ~(0x80));
2003 wmb();
2004 dummy->hw_token = token;
2005
2006 urb->hcpriv = qh_get(qh);
2007 }
2008 }
2009 return qh;
2010}
2011
2012static int submit_async(struct oxu_hcd *oxu, struct urb *urb,
2013 struct list_head *qtd_list, gfp_t mem_flags)
2014{
2015 int epnum = urb->ep->desc.bEndpointAddress;
2016 unsigned long flags;
2017 struct ehci_qh *qh = NULL;
2018 int rc = 0;
2019#ifdef OXU_URB_TRACE
2020 struct ehci_qtd *qtd;
2021
2022 qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
2023
2024 oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
2025 __func__, urb->dev->devpath, urb,
2026 epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
2027 urb->transfer_buffer_length,
2028 qtd, urb->ep->hcpriv);
2029#endif
2030
2031 spin_lock_irqsave(&oxu->lock, flags);
2032 if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) {
2033 rc = -ESHUTDOWN;
2034 goto done;
2035 }
2036
2037 qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
2038 if (unlikely(qh == NULL)) {
2039 rc = -ENOMEM;
2040 goto done;
2041 }
2042
2043 /* Control/bulk operations through TTs don't need scheduling,
2044 * the HC and TT handle it when the TT has a buffer ready.
2045 */
2046 if (likely(qh->qh_state == QH_STATE_IDLE))
2047 qh_link_async(oxu, qh_get(qh));
2048done:
2049 spin_unlock_irqrestore(&oxu->lock, flags);
2050 if (unlikely(qh == NULL))
2051 qtd_list_free(oxu, urb, qtd_list);
2052 return rc;
2053}
2054
2055/* The async qh for the qtds being reclaimed are now unlinked from the HC */
2056
2057static void end_unlink_async(struct oxu_hcd *oxu)
2058{
2059 struct ehci_qh *qh = oxu->reclaim;
2060 struct ehci_qh *next;
2061
2062 timer_action_done(oxu, TIMER_IAA_WATCHDOG);
2063
2064 qh->qh_state = QH_STATE_IDLE;
2065 qh->qh_next.qh = NULL;
2066 qh_put(qh); /* refcount from reclaim */
2067
2068 /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
2069 next = qh->reclaim;
2070 oxu->reclaim = next;
2071 oxu->reclaim_ready = 0;
2072 qh->reclaim = NULL;
2073
2074 qh_completions(oxu, qh);
2075
2076 if (!list_empty(&qh->qtd_list)
2077 && HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
2078 qh_link_async(oxu, qh);
2079 else {
2080 qh_put(qh); /* refcount from async list */
2081
2082 /* it's not free to turn the async schedule on/off; leave it
2083 * active but idle for a while once it empties.
2084 */
2085 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)
2086 && oxu->async->qh_next.qh == NULL)
2087 timer_action(oxu, TIMER_ASYNC_OFF);
2088 }
2089
2090 if (next) {
2091 oxu->reclaim = NULL;
2092 start_unlink_async(oxu, next);
2093 }
2094}
2095
2096/* makes sure the async qh will become idle */
2097/* caller must own oxu->lock */
2098
2099static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
2100{
2101 int cmd = readl(&oxu->regs->command);
2102 struct ehci_qh *prev;
2103
2104#ifdef DEBUG
2105 assert_spin_locked(&oxu->lock);
2106 BUG_ON(oxu->reclaim || (qh->qh_state != QH_STATE_LINKED
2107 && qh->qh_state != QH_STATE_UNLINK_WAIT));
2108#endif
2109
2110 /* stop async schedule right now? */
2111 if (unlikely(qh == oxu->async)) {
2112 /* can't get here without STS_ASS set */
2113 if (oxu_to_hcd(oxu)->state != HC_STATE_HALT
2114 && !oxu->reclaim) {
2115 /* ... and CMD_IAAD clear */
2116 writel(cmd & ~CMD_ASE, &oxu->regs->command);
2117 wmb();
2118 /* handshake later, if we need to */
2119 timer_action_done(oxu, TIMER_ASYNC_OFF);
2120 }
2121 return;
2122 }
2123
2124 qh->qh_state = QH_STATE_UNLINK;
2125 oxu->reclaim = qh = qh_get(qh);
2126
2127 prev = oxu->async;
2128 while (prev->qh_next.qh != qh)
2129 prev = prev->qh_next.qh;
2130
2131 prev->hw_next = qh->hw_next;
2132 prev->qh_next = qh->qh_next;
2133 wmb();
2134
2135 if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) {
2136 /* if (unlikely(qh->reclaim != 0))
2137 * this will recurse, probably not much
2138 */
2139 end_unlink_async(oxu);
2140 return;
2141 }
2142
2143 oxu->reclaim_ready = 0;
2144 cmd |= CMD_IAAD;
2145 writel(cmd, &oxu->regs->command);
2146 (void) readl(&oxu->regs->command);
2147 timer_action(oxu, TIMER_IAA_WATCHDOG);
2148}
2149
2150static void scan_async(struct oxu_hcd *oxu)
2151{
2152 struct ehci_qh *qh;
2153 enum ehci_timer_action action = TIMER_IO_WATCHDOG;
2154
2155 if (!++(oxu->stamp))
2156 oxu->stamp++;
2157 timer_action_done(oxu, TIMER_ASYNC_SHRINK);
2158rescan:
2159 qh = oxu->async->qh_next.qh;
2160 if (likely(qh != NULL)) {
2161 do {
2162 /* clean any finished work for this qh */
2163 if (!list_empty(&qh->qtd_list)
2164 && qh->stamp != oxu->stamp) {
2165 int temp;
2166
2167 /* unlinks could happen here; completion
2168 * reporting drops the lock. rescan using
2169 * the latest schedule, but don't rescan
2170 * qhs we already finished (no looping).
2171 */
2172 qh = qh_get(qh);
2173 qh->stamp = oxu->stamp;
2174 temp = qh_completions(oxu, qh);
2175 qh_put(qh);
2176 if (temp != 0)
2177 goto rescan;
2178 }
2179
2180 /* unlink idle entries, reducing HC PCI usage as well
2181 * as HCD schedule-scanning costs. delay for any qh
2182 * we just scanned, there's a not-unusual case that it
2183 * doesn't stay idle for long.
2184 * (plus, avoids some kind of re-activation race.)
2185 */
2186 if (list_empty(&qh->qtd_list)) {
2187 if (qh->stamp == oxu->stamp)
2188 action = TIMER_ASYNC_SHRINK;
2189 else if (!oxu->reclaim
2190 && qh->qh_state == QH_STATE_LINKED)
2191 start_unlink_async(oxu, qh);
2192 }
2193
2194 qh = qh->qh_next.qh;
2195 } while (qh);
2196 }
2197 if (action == TIMER_ASYNC_SHRINK)
2198 timer_action(oxu, TIMER_ASYNC_SHRINK);
2199}
2200
2201/*
2202 * periodic_next_shadow - return "next" pointer on shadow list
2203 * @periodic: host pointer to qh/itd/sitd
2204 * @tag: hardware tag for type of this record
2205 */
2206static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic,
2207 __le32 tag)
2208{
2209 switch (tag) {
2210 default:
2211 case Q_TYPE_QH:
2212 return &periodic->qh->qh_next;
2213 }
2214}
2215
2216/* caller must hold oxu->lock */
2217static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr)
2218{
2219 union ehci_shadow *prev_p = &oxu->pshadow[frame];
2220 __le32 *hw_p = &oxu->periodic[frame];
2221 union ehci_shadow here = *prev_p;
2222
2223 /* find predecessor of "ptr"; hw and shadow lists are in sync */
2224 while (here.ptr && here.ptr != ptr) {
2225 prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p));
2226 hw_p = here.hw_next;
2227 here = *prev_p;
2228 }
2229 /* an interrupt entry (at list end) could have been shared */
2230 if (!here.ptr)
2231 return;
2232
2233 /* update shadow and hardware lists ... the old "next" pointers
2234 * from ptr may still be in use, the caller updates them.
2235 */
2236 *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p));
2237 *hw_p = *here.hw_next;
2238}
2239
2240/* how many of the uframe's 125 usecs are allocated? */
2241static unsigned short periodic_usecs(struct oxu_hcd *oxu,
2242 unsigned frame, unsigned uframe)
2243{
2244 __le32 *hw_p = &oxu->periodic[frame];
2245 union ehci_shadow *q = &oxu->pshadow[frame];
2246 unsigned usecs = 0;
2247
2248 while (q->ptr) {
2249 switch (Q_NEXT_TYPE(*hw_p)) {
2250 case Q_TYPE_QH:
2251 default:
2252 /* is it in the S-mask? */
2253 if (q->qh->hw_info2 & cpu_to_le32(1 << uframe))
2254 usecs += q->qh->usecs;
2255 /* ... or C-mask? */
2256 if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe)))
2257 usecs += q->qh->c_usecs;
2258 hw_p = &q->qh->hw_next;
2259 q = &q->qh->qh_next;
2260 break;
2261 }
2262 }
2263#ifdef DEBUG
2264 if (usecs > 100)
2265 oxu_err(oxu, "uframe %d sched overrun: %d usecs\n",
2266 frame * 8 + uframe, usecs);
2267#endif
2268 return usecs;
2269}
2270
2271static int enable_periodic(struct oxu_hcd *oxu)
2272{
2273 u32 cmd;
2274 int status;
2275
2276 /* did clearing PSE did take effect yet?
2277 * takes effect only at frame boundaries...
2278 */
2279 status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125);
2280 if (status != 0) {
2281 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
2282 usb_hc_died(oxu_to_hcd(oxu));
2283 return status;
2284 }
2285
2286 cmd = readl(&oxu->regs->command) | CMD_PSE;
2287 writel(cmd, &oxu->regs->command);
2288 /* posted write ... PSS happens later */
2289 oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
2290
2291 /* make sure ehci_work scans these */
2292 oxu->next_uframe = readl(&oxu->regs->frame_index)
2293 % (oxu->periodic_size << 3);
2294 return 0;
2295}
2296
2297static int disable_periodic(struct oxu_hcd *oxu)
2298{
2299 u32 cmd;
2300 int status;
2301
2302 /* did setting PSE not take effect yet?
2303 * takes effect only at frame boundaries...
2304 */
2305 status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125);
2306 if (status != 0) {
2307 oxu_to_hcd(oxu)->state = HC_STATE_HALT;
2308 usb_hc_died(oxu_to_hcd(oxu));
2309 return status;
2310 }
2311
2312 cmd = readl(&oxu->regs->command) & ~CMD_PSE;
2313 writel(cmd, &oxu->regs->command);
2314 /* posted write ... */
2315
2316 oxu->next_uframe = -1;
2317 return 0;
2318}
2319
2320/* periodic schedule slots have iso tds (normal or split) first, then a
2321 * sparse tree for active interrupt transfers.
2322 *
2323 * this just links in a qh; caller guarantees uframe masks are set right.
2324 * no FSTN support (yet; oxu 0.96+)
2325 */
2326static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
2327{
2328 unsigned i;
2329 unsigned period = qh->period;
2330
2331 dev_dbg(&qh->dev->dev,
2332 "link qh%d-%04x/%p start %d [%d/%d us]\n",
2333 period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
2334 qh, qh->start, qh->usecs, qh->c_usecs);
2335
2336 /* high bandwidth, or otherwise every microframe */
2337 if (period == 0)
2338 period = 1;
2339
2340 for (i = qh->start; i < oxu->periodic_size; i += period) {
2341 union ehci_shadow *prev = &oxu->pshadow[i];
2342 __le32 *hw_p = &oxu->periodic[i];
2343 union ehci_shadow here = *prev;
2344 __le32 type = 0;
2345
2346 /* skip the iso nodes at list head */
2347 while (here.ptr) {
2348 type = Q_NEXT_TYPE(*hw_p);
2349 if (type == Q_TYPE_QH)
2350 break;
2351 prev = periodic_next_shadow(prev, type);
2352 hw_p = &here.qh->hw_next;
2353 here = *prev;
2354 }
2355
2356 /* sorting each branch by period (slow-->fast)
2357 * enables sharing interior tree nodes
2358 */
2359 while (here.ptr && qh != here.qh) {
2360 if (qh->period > here.qh->period)
2361 break;
2362 prev = &here.qh->qh_next;
2363 hw_p = &here.qh->hw_next;
2364 here = *prev;
2365 }
2366 /* link in this qh, unless some earlier pass did that */
2367 if (qh != here.qh) {
2368 qh->qh_next = here;
2369 if (here.qh)
2370 qh->hw_next = *hw_p;
2371 wmb();
2372 prev->qh = qh;
2373 *hw_p = QH_NEXT(qh->qh_dma);
2374 }
2375 }
2376 qh->qh_state = QH_STATE_LINKED;
2377 qh_get(qh);
2378
2379 /* update per-qh bandwidth for usbfs */
2380 oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period
2381 ? ((qh->usecs + qh->c_usecs) / qh->period)
2382 : (qh->usecs * 8);
2383
2384 /* maybe enable periodic schedule processing */
2385 if (!oxu->periodic_sched++)
2386 return enable_periodic(oxu);
2387
2388 return 0;
2389}
2390
2391static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
2392{
2393 unsigned i;
2394 unsigned period;
2395
2396 /* FIXME:
2397 * IF this isn't high speed
2398 * and this qh is active in the current uframe
2399 * (and overlay token SplitXstate is false?)
2400 * THEN
2401 * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore");
2402 */
2403
2404 /* high bandwidth, or otherwise part of every microframe */
2405 period = qh->period;
2406 if (period == 0)
2407 period = 1;
2408
2409 for (i = qh->start; i < oxu->periodic_size; i += period)
2410 periodic_unlink(oxu, i, qh);
2411
2412 /* update per-qh bandwidth for usbfs */
2413 oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period
2414 ? ((qh->usecs + qh->c_usecs) / qh->period)
2415 : (qh->usecs * 8);
2416
2417 dev_dbg(&qh->dev->dev,
2418 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
2419 qh->period,
2420 le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
2421 qh, qh->start, qh->usecs, qh->c_usecs);
2422
2423 /* qh->qh_next still "live" to HC */
2424 qh->qh_state = QH_STATE_UNLINK;
2425 qh->qh_next.ptr = NULL;
2426 qh_put(qh);
2427
2428 /* maybe turn off periodic schedule */
2429 oxu->periodic_sched--;
2430 if (!oxu->periodic_sched)
2431 (void) disable_periodic(oxu);
2432}
2433
2434static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
2435{
2436 unsigned wait;
2437
2438 qh_unlink_periodic(oxu, qh);
2439
2440 /* simple/paranoid: always delay, expecting the HC needs to read
2441 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
2442 * expect hub_wq to clean up after any CSPLITs we won't issue.
2443 * active high speed queues may need bigger delays...
2444 */
2445 if (list_empty(&qh->qtd_list)
2446 || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0)
2447 wait = 2;
2448 else
2449 wait = 55; /* worst case: 3 * 1024 */
2450
2451 udelay(wait);
2452 qh->qh_state = QH_STATE_IDLE;
2453 qh->hw_next = EHCI_LIST_END;
2454 wmb();
2455}
2456
2457static int check_period(struct oxu_hcd *oxu,
2458 unsigned frame, unsigned uframe,
2459 unsigned period, unsigned usecs)
2460{
2461 int claimed;
2462
2463 /* complete split running into next frame?
2464 * given FSTN support, we could sometimes check...
2465 */
2466 if (uframe >= 8)
2467 return 0;
2468
2469 /*
2470 * 80% periodic == 100 usec/uframe available
2471 * convert "usecs we need" to "max already claimed"
2472 */
2473 usecs = 100 - usecs;
2474
2475 /* we "know" 2 and 4 uframe intervals were rejected; so
2476 * for period 0, check _every_ microframe in the schedule.
2477 */
2478 if (unlikely(period == 0)) {
2479 do {
2480 for (uframe = 0; uframe < 7; uframe++) {
2481 claimed = periodic_usecs(oxu, frame, uframe);
2482 if (claimed > usecs)
2483 return 0;
2484 }
2485 } while ((frame += 1) < oxu->periodic_size);
2486
2487 /* just check the specified uframe, at that period */
2488 } else {
2489 do {
2490 claimed = periodic_usecs(oxu, frame, uframe);
2491 if (claimed > usecs)
2492 return 0;
2493 } while ((frame += period) < oxu->periodic_size);
2494 }
2495
2496 return 1;
2497}
2498
2499static int check_intr_schedule(struct oxu_hcd *oxu,
2500 unsigned frame, unsigned uframe,
2501 const struct ehci_qh *qh, __le32 *c_maskp)
2502{
2503 int retval = -ENOSPC;
2504
2505 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
2506 goto done;
2507
2508 if (!check_period(oxu, frame, uframe, qh->period, qh->usecs))
2509 goto done;
2510 if (!qh->c_usecs) {
2511 retval = 0;
2512 *c_maskp = 0;
2513 goto done;
2514 }
2515
2516done:
2517 return retval;
2518}
2519
2520/* "first fit" scheduling policy used the first time through,
2521 * or when the previous schedule slot can't be re-used.
2522 */
2523static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
2524{
2525 int status;
2526 unsigned uframe;
2527 __le32 c_mask;
2528 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
2529
2530 qh_refresh(oxu, qh);
2531 qh->hw_next = EHCI_LIST_END;
2532 frame = qh->start;
2533
2534 /* reuse the previous schedule slots, if we can */
2535 if (frame < qh->period) {
2536 uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK);
2537 status = check_intr_schedule(oxu, frame, --uframe,
2538 qh, &c_mask);
2539 } else {
2540 uframe = 0;
2541 c_mask = 0;
2542 status = -ENOSPC;
2543 }
2544
2545 /* else scan the schedule to find a group of slots such that all
2546 * uframes have enough periodic bandwidth available.
2547 */
2548 if (status) {
2549 /* "normal" case, uframing flexible except with splits */
2550 if (qh->period) {
2551 frame = qh->period - 1;
2552 do {
2553 for (uframe = 0; uframe < 8; uframe++) {
2554 status = check_intr_schedule(oxu,
2555 frame, uframe, qh,
2556 &c_mask);
2557 if (status == 0)
2558 break;
2559 }
2560 } while (status && frame--);
2561
2562 /* qh->period == 0 means every uframe */
2563 } else {
2564 frame = 0;
2565 status = check_intr_schedule(oxu, 0, 0, qh, &c_mask);
2566 }
2567 if (status)
2568 goto done;
2569 qh->start = frame;
2570
2571 /* reset S-frame and (maybe) C-frame masks */
2572 qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK));
2573 qh->hw_info2 |= qh->period
2574 ? cpu_to_le32(1 << uframe)
2575 : cpu_to_le32(QH_SMASK);
2576 qh->hw_info2 |= c_mask;
2577 } else
2578 oxu_dbg(oxu, "reused qh %p schedule\n", qh);
2579
2580 /* stuff into the periodic schedule */
2581 status = qh_link_periodic(oxu, qh);
2582done:
2583 return status;
2584}
2585
2586static int intr_submit(struct oxu_hcd *oxu, struct urb *urb,
2587 struct list_head *qtd_list, gfp_t mem_flags)
2588{
2589 unsigned epnum;
2590 unsigned long flags;
2591 struct ehci_qh *qh;
2592 int status = 0;
2593 struct list_head empty;
2594
2595 /* get endpoint and transfer/schedule data */
2596 epnum = urb->ep->desc.bEndpointAddress;
2597
2598 spin_lock_irqsave(&oxu->lock, flags);
2599
2600 if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) {
2601 status = -ESHUTDOWN;
2602 goto done;
2603 }
2604
2605 /* get qh and force any scheduling errors */
2606 INIT_LIST_HEAD(&empty);
2607 qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv);
2608 if (qh == NULL) {
2609 status = -ENOMEM;
2610 goto done;
2611 }
2612 if (qh->qh_state == QH_STATE_IDLE) {
2613 status = qh_schedule(oxu, qh);
2614 if (status != 0)
2615 goto done;
2616 }
2617
2618 /* then queue the urb's tds to the qh */
2619 qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
2620 BUG_ON(qh == NULL);
2621
2622 /* ... update usbfs periodic stats */
2623 oxu_to_hcd(oxu)->self.bandwidth_int_reqs++;
2624
2625done:
2626 spin_unlock_irqrestore(&oxu->lock, flags);
2627 if (status)
2628 qtd_list_free(oxu, urb, qtd_list);
2629
2630 return status;
2631}
2632
2633static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb,
2634 gfp_t mem_flags)
2635{
2636 oxu_dbg(oxu, "iso support is missing!\n");
2637 return -ENOSYS;
2638}
2639
2640static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb,
2641 gfp_t mem_flags)
2642{
2643 oxu_dbg(oxu, "split iso support is missing!\n");
2644 return -ENOSYS;
2645}
2646
2647static void scan_periodic(struct oxu_hcd *oxu)
2648{
2649 unsigned frame, clock, now_uframe, mod;
2650 unsigned modified;
2651
2652 mod = oxu->periodic_size << 3;
2653
2654 /*
2655 * When running, scan from last scan point up to "now"
2656 * else clean up by scanning everything that's left.
2657 * Touches as few pages as possible: cache-friendly.
2658 */
2659 now_uframe = oxu->next_uframe;
2660 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
2661 clock = readl(&oxu->regs->frame_index);
2662 else
2663 clock = now_uframe + mod - 1;
2664 clock %= mod;
2665
2666 for (;;) {
2667 union ehci_shadow q, *q_p;
2668 __le32 type, *hw_p;
2669
2670 /* don't scan past the live uframe */
2671 frame = now_uframe >> 3;
2672 if (frame != (clock >> 3)) {
2673 /* safe to scan the whole frame at once */
2674 now_uframe |= 0x07;
2675 }
2676
2677restart:
2678 /* scan each element in frame's queue for completions */
2679 q_p = &oxu->pshadow[frame];
2680 hw_p = &oxu->periodic[frame];
2681 q.ptr = q_p->ptr;
2682 type = Q_NEXT_TYPE(*hw_p);
2683 modified = 0;
2684
2685 while (q.ptr != NULL) {
2686 union ehci_shadow temp;
2687
2688 switch (type) {
2689 case Q_TYPE_QH:
2690 /* handle any completions */
2691 temp.qh = qh_get(q.qh);
2692 type = Q_NEXT_TYPE(q.qh->hw_next);
2693 q = q.qh->qh_next;
2694 modified = qh_completions(oxu, temp.qh);
2695 if (unlikely(list_empty(&temp.qh->qtd_list)))
2696 intr_deschedule(oxu, temp.qh);
2697 qh_put(temp.qh);
2698 break;
2699 default:
2700 oxu_dbg(oxu, "corrupt type %d frame %d shadow %p\n",
2701 type, frame, q.ptr);
2702 q.ptr = NULL;
2703 }
2704
2705 /* assume completion callbacks modify the queue */
2706 if (unlikely(modified))
2707 goto restart;
2708 }
2709
2710 /* Stop when we catch up to the HC */
2711
2712 /* FIXME: this assumes we won't get lapped when
2713 * latencies climb; that should be rare, but...
2714 * detect it, and just go all the way around.
2715 * FLR might help detect this case, so long as latencies
2716 * don't exceed periodic_size msec (default 1.024 sec).
2717 */
2718
2719 /* FIXME: likewise assumes HC doesn't halt mid-scan */
2720
2721 if (now_uframe == clock) {
2722 unsigned now;
2723
2724 if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
2725 break;
2726 oxu->next_uframe = now_uframe;
2727 now = readl(&oxu->regs->frame_index) % mod;
2728 if (now_uframe == now)
2729 break;
2730
2731 /* rescan the rest of this frame, then ... */
2732 clock = now;
2733 } else {
2734 now_uframe++;
2735 now_uframe %= mod;
2736 }
2737 }
2738}
2739
2740/* On some systems, leaving remote wakeup enabled prevents system shutdown.
2741 * The firmware seems to think that powering off is a wakeup event!
2742 * This routine turns off remote wakeup and everything else, on all ports.
2743 */
2744static void ehci_turn_off_all_ports(struct oxu_hcd *oxu)
2745{
2746 int port = HCS_N_PORTS(oxu->hcs_params);
2747
2748 while (port--)
2749 writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
2750}
2751
2752static void ehci_port_power(struct oxu_hcd *oxu, int is_on)
2753{
2754 unsigned port;
2755
2756 if (!HCS_PPC(oxu->hcs_params))
2757 return;
2758
2759 oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down");
2760 for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; ) {
2761 if (is_on)
2762 oxu_hub_control(oxu_to_hcd(oxu), SetPortFeature,
2763 USB_PORT_FEAT_POWER, port--, NULL, 0);
2764 else
2765 oxu_hub_control(oxu_to_hcd(oxu), ClearPortFeature,
2766 USB_PORT_FEAT_POWER, port--, NULL, 0);
2767 }
2768
2769 msleep(20);
2770}
2771
2772/* Called from some interrupts, timers, and so on.
2773 * It calls driver completion functions, after dropping oxu->lock.
2774 */
2775static void ehci_work(struct oxu_hcd *oxu)
2776{
2777 timer_action_done(oxu, TIMER_IO_WATCHDOG);
2778 if (oxu->reclaim_ready)
2779 end_unlink_async(oxu);
2780
2781 /* another CPU may drop oxu->lock during a schedule scan while
2782 * it reports urb completions. this flag guards against bogus
2783 * attempts at re-entrant schedule scanning.
2784 */
2785 if (oxu->scanning)
2786 return;
2787 oxu->scanning = 1;
2788 scan_async(oxu);
2789 if (oxu->next_uframe != -1)
2790 scan_periodic(oxu);
2791 oxu->scanning = 0;
2792
2793 /* the IO watchdog guards against hardware or driver bugs that
2794 * misplace IRQs, and should let us run completely without IRQs.
2795 * such lossage has been observed on both VT6202 and VT8235.
2796 */
2797 if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) &&
2798 (oxu->async->qh_next.ptr != NULL ||
2799 oxu->periodic_sched != 0))
2800 timer_action(oxu, TIMER_IO_WATCHDOG);
2801}
2802
2803static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
2804{
2805 /* if we need to use IAA and it's busy, defer */
2806 if (qh->qh_state == QH_STATE_LINKED
2807 && oxu->reclaim
2808 && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) {
2809 struct ehci_qh *last;
2810
2811 for (last = oxu->reclaim;
2812 last->reclaim;
2813 last = last->reclaim)
2814 continue;
2815 qh->qh_state = QH_STATE_UNLINK_WAIT;
2816 last->reclaim = qh;
2817
2818 /* bypass IAA if the hc can't care */
2819 } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim)
2820 end_unlink_async(oxu);
2821
2822 /* something else might have unlinked the qh by now */
2823 if (qh->qh_state == QH_STATE_LINKED)
2824 start_unlink_async(oxu, qh);
2825}
2826
2827/*
2828 * USB host controller methods
2829 */
2830
2831static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd)
2832{
2833 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2834 u32 status, pcd_status = 0;
2835 int bh;
2836
2837 spin_lock(&oxu->lock);
2838
2839 status = readl(&oxu->regs->status);
2840
2841 /* e.g. cardbus physical eject */
2842 if (status == ~(u32) 0) {
2843 oxu_dbg(oxu, "device removed\n");
2844 goto dead;
2845 }
2846
2847 /* Shared IRQ? */
2848 status &= INTR_MASK;
2849 if (!status || unlikely(hcd->state == HC_STATE_HALT)) {
2850 spin_unlock(&oxu->lock);
2851 return IRQ_NONE;
2852 }
2853
2854 /* clear (just) interrupts */
2855 writel(status, &oxu->regs->status);
2856 readl(&oxu->regs->command); /* unblock posted write */
2857 bh = 0;
2858
2859#ifdef OXU_VERBOSE_DEBUG
2860 /* unrequested/ignored: Frame List Rollover */
2861 dbg_status(oxu, "irq", status);
2862#endif
2863
2864 /* INT, ERR, and IAA interrupt rates can be throttled */
2865
2866 /* normal [4.15.1.2] or error [4.15.1.1] completion */
2867 if (likely((status & (STS_INT|STS_ERR)) != 0))
2868 bh = 1;
2869
2870 /* complete the unlinking of some qh [4.15.2.3] */
2871 if (status & STS_IAA) {
2872 oxu->reclaim_ready = 1;
2873 bh = 1;
2874 }
2875
2876 /* remote wakeup [4.3.1] */
2877 if (status & STS_PCD) {
2878 unsigned i = HCS_N_PORTS(oxu->hcs_params);
2879 pcd_status = status;
2880
2881 /* resume root hub? */
2882 if (!(readl(&oxu->regs->command) & CMD_RUN))
2883 usb_hcd_resume_root_hub(hcd);
2884
2885 while (i--) {
2886 int pstatus = readl(&oxu->regs->port_status[i]);
2887
2888 if (pstatus & PORT_OWNER)
2889 continue;
2890 if (!(pstatus & PORT_RESUME)
2891 || oxu->reset_done[i] != 0)
2892 continue;
2893
2894 /* start USB_RESUME_TIMEOUT resume signaling from this
2895 * port, and make hub_wq collect PORT_STAT_C_SUSPEND to
2896 * stop that signaling.
2897 */
2898 oxu->reset_done[i] = jiffies +
2899 msecs_to_jiffies(USB_RESUME_TIMEOUT);
2900 oxu_dbg(oxu, "port %d remote wakeup\n", i + 1);
2901 mod_timer(&hcd->rh_timer, oxu->reset_done[i]);
2902 }
2903 }
2904
2905 /* PCI errors [4.15.2.4] */
2906 if (unlikely((status & STS_FATAL) != 0)) {
2907 /* bogus "fatal" IRQs appear on some chips... why? */
2908 status = readl(&oxu->regs->status);
2909 dbg_cmd(oxu, "fatal", readl(&oxu->regs->command));
2910 dbg_status(oxu, "fatal", status);
2911 if (status & STS_HALT) {
2912 oxu_err(oxu, "fatal error\n");
2913dead:
2914 ehci_reset(oxu);
2915 writel(0, &oxu->regs->configured_flag);
2916 usb_hc_died(hcd);
2917 /* generic layer kills/unlinks all urbs, then
2918 * uses oxu_stop to clean up the rest
2919 */
2920 bh = 1;
2921 }
2922 }
2923
2924 if (bh)
2925 ehci_work(oxu);
2926 spin_unlock(&oxu->lock);
2927 if (pcd_status & STS_PCD)
2928 usb_hcd_poll_rh_status(hcd);
2929 return IRQ_HANDLED;
2930}
2931
2932static irqreturn_t oxu_irq(struct usb_hcd *hcd)
2933{
2934 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2935 int ret = IRQ_HANDLED;
2936
2937 u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS);
2938 u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET);
2939
2940 /* Disable all interrupt */
2941 oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable);
2942
2943 if ((oxu->is_otg && (status & OXU_USBOTGI)) ||
2944 (!oxu->is_otg && (status & OXU_USBSPHI)))
2945 oxu210_hcd_irq(hcd);
2946 else
2947 ret = IRQ_NONE;
2948
2949 /* Enable all interrupt back */
2950 oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable);
2951
2952 return ret;
2953}
2954
2955static void oxu_watchdog(struct timer_list *t)
2956{
2957 struct oxu_hcd *oxu = from_timer(oxu, t, watchdog);
2958 unsigned long flags;
2959
2960 spin_lock_irqsave(&oxu->lock, flags);
2961
2962 /* lost IAA irqs wedge things badly; seen with a vt8235 */
2963 if (oxu->reclaim) {
2964 u32 status = readl(&oxu->regs->status);
2965 if (status & STS_IAA) {
2966 oxu_vdbg(oxu, "lost IAA\n");
2967 writel(STS_IAA, &oxu->regs->status);
2968 oxu->reclaim_ready = 1;
2969 }
2970 }
2971
2972 /* stop async processing after it's idled a bit */
2973 if (test_bit(TIMER_ASYNC_OFF, &oxu->actions))
2974 start_unlink_async(oxu, oxu->async);
2975
2976 /* oxu could run by timer, without IRQs ... */
2977 ehci_work(oxu);
2978
2979 spin_unlock_irqrestore(&oxu->lock, flags);
2980}
2981
2982/* One-time init, only for memory state.
2983 */
2984static int oxu_hcd_init(struct usb_hcd *hcd)
2985{
2986 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
2987 u32 temp;
2988 int retval;
2989 u32 hcc_params;
2990
2991 spin_lock_init(&oxu->lock);
2992
2993 timer_setup(&oxu->watchdog, oxu_watchdog, 0);
2994
2995 /*
2996 * hw default: 1K periodic list heads, one per frame.
2997 * periodic_size can shrink by USBCMD update if hcc_params allows.
2998 */
2999 oxu->periodic_size = DEFAULT_I_TDPS;
3000 retval = ehci_mem_init(oxu, GFP_KERNEL);
3001 if (retval < 0)
3002 return retval;
3003
3004 /* controllers may cache some of the periodic schedule ... */
3005 hcc_params = readl(&oxu->caps->hcc_params);
3006 if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */
3007 oxu->i_thresh = 8;
3008 else /* N microframes cached */
3009 oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
3010
3011 oxu->reclaim = NULL;
3012 oxu->reclaim_ready = 0;
3013 oxu->next_uframe = -1;
3014
3015 /*
3016 * dedicate a qh for the async ring head, since we couldn't unlink
3017 * a 'real' qh without stopping the async schedule [4.8]. use it
3018 * as the 'reclamation list head' too.
3019 * its dummy is used in hw_alt_next of many tds, to prevent the qh
3020 * from automatically advancing to the next td after short reads.
3021 */
3022 oxu->async->qh_next.qh = NULL;
3023 oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma);
3024 oxu->async->hw_info1 = cpu_to_le32(QH_HEAD);
3025 oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT);
3026 oxu->async->hw_qtd_next = EHCI_LIST_END;
3027 oxu->async->qh_state = QH_STATE_LINKED;
3028 oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma);
3029
3030 /* clear interrupt enables, set irq latency */
3031 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
3032 log2_irq_thresh = 0;
3033 temp = 1 << (16 + log2_irq_thresh);
3034 if (HCC_CANPARK(hcc_params)) {
3035 /* HW default park == 3, on hardware that supports it (like
3036 * NVidia and ALI silicon), maximizes throughput on the async
3037 * schedule by avoiding QH fetches between transfers.
3038 *
3039 * With fast usb storage devices and NForce2, "park" seems to
3040 * make problems: throughput reduction (!), data errors...
3041 */
3042 if (park) {
3043 park = min_t(unsigned int, park, 3);
3044 temp |= CMD_PARK;
3045 temp |= park << 8;
3046 }
3047 oxu_dbg(oxu, "park %d\n", park);
3048 }
3049 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
3050 /* periodic schedule size can be smaller than default */
3051 temp &= ~(3 << 2);
3052 temp |= (EHCI_TUNE_FLS << 2);
3053 }
3054 oxu->command = temp;
3055
3056 return 0;
3057}
3058
3059/* Called during probe() after chip reset completes.
3060 */
3061static int oxu_reset(struct usb_hcd *hcd)
3062{
3063 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3064
3065 spin_lock_init(&oxu->mem_lock);
3066 INIT_LIST_HEAD(&oxu->urb_list);
3067 oxu->urb_len = 0;
3068
3069 if (oxu->is_otg) {
3070 oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET;
3071 oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \
3072 HC_LENGTH(readl(&oxu->caps->hc_capbase));
3073
3074 oxu->mem = hcd->regs + OXU_SPH_MEM;
3075 } else {
3076 oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET;
3077 oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \
3078 HC_LENGTH(readl(&oxu->caps->hc_capbase));
3079
3080 oxu->mem = hcd->regs + OXU_OTG_MEM;
3081 }
3082
3083 oxu->hcs_params = readl(&oxu->caps->hcs_params);
3084 oxu->sbrn = 0x20;
3085
3086 return oxu_hcd_init(hcd);
3087}
3088
3089static int oxu_run(struct usb_hcd *hcd)
3090{
3091 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3092 int retval;
3093 u32 temp, hcc_params;
3094
3095 hcd->uses_new_polling = 1;
3096
3097 /* EHCI spec section 4.1 */
3098 retval = ehci_reset(oxu);
3099 if (retval != 0) {
3100 ehci_mem_cleanup(oxu);
3101 return retval;
3102 }
3103 writel(oxu->periodic_dma, &oxu->regs->frame_list);
3104 writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
3105
3106 /* hcc_params controls whether oxu->regs->segment must (!!!)
3107 * be used; it constrains QH/ITD/SITD and QTD locations.
3108 * dma_pool consistent memory always uses segment zero.
3109 * streaming mappings for I/O buffers, like dma_map_single(),
3110 * can return segments above 4GB, if the device allows.
3111 *
3112 * NOTE: the dma mask is visible through dev->dma_mask, so
3113 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
3114 * Scsi_Host.highmem_io, and so forth. It's readonly to all
3115 * host side drivers though.
3116 */
3117 hcc_params = readl(&oxu->caps->hcc_params);
3118 if (HCC_64BIT_ADDR(hcc_params))
3119 writel(0, &oxu->regs->segment);
3120
3121 oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE |
3122 CMD_ASE | CMD_RESET);
3123 oxu->command |= CMD_RUN;
3124 writel(oxu->command, &oxu->regs->command);
3125 dbg_cmd(oxu, "init", oxu->command);
3126
3127 /*
3128 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
3129 * are explicitly handed to companion controller(s), so no TT is
3130 * involved with the root hub. (Except where one is integrated,
3131 * and there's no companion controller unless maybe for USB OTG.)
3132 */
3133 hcd->state = HC_STATE_RUNNING;
3134 writel(FLAG_CF, &oxu->regs->configured_flag);
3135 readl(&oxu->regs->command); /* unblock posted writes */
3136
3137 temp = HC_VERSION(readl(&oxu->caps->hc_capbase));
3138 oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n",
3139 ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f),
3140 temp >> 8, temp & 0xff, DRIVER_VERSION,
3141 ignore_oc ? ", overcurrent ignored" : "");
3142
3143 writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */
3144
3145 return 0;
3146}
3147
3148static void oxu_stop(struct usb_hcd *hcd)
3149{
3150 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3151
3152 /* Turn off port power on all root hub ports. */
3153 ehci_port_power(oxu, 0);
3154
3155 /* no more interrupts ... */
3156 del_timer_sync(&oxu->watchdog);
3157
3158 spin_lock_irq(&oxu->lock);
3159 if (HC_IS_RUNNING(hcd->state))
3160 ehci_quiesce(oxu);
3161
3162 ehci_reset(oxu);
3163 writel(0, &oxu->regs->intr_enable);
3164 spin_unlock_irq(&oxu->lock);
3165
3166 /* let companion controllers work when we aren't */
3167 writel(0, &oxu->regs->configured_flag);
3168
3169 /* root hub is shut down separately (first, when possible) */
3170 spin_lock_irq(&oxu->lock);
3171 if (oxu->async)
3172 ehci_work(oxu);
3173 spin_unlock_irq(&oxu->lock);
3174 ehci_mem_cleanup(oxu);
3175
3176 dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status));
3177}
3178
3179/* Kick in for silicon on any bus (not just pci, etc).
3180 * This forcibly disables dma and IRQs, helping kexec and other cases
3181 * where the next system software may expect clean state.
3182 */
3183static void oxu_shutdown(struct usb_hcd *hcd)
3184{
3185 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3186
3187 (void) ehci_halt(oxu);
3188 ehci_turn_off_all_ports(oxu);
3189
3190 /* make BIOS/etc use companion controller during reboot */
3191 writel(0, &oxu->regs->configured_flag);
3192
3193 /* unblock posted writes */
3194 readl(&oxu->regs->configured_flag);
3195}
3196
3197/* Non-error returns are a promise to giveback() the urb later
3198 * we drop ownership so next owner (or urb unlink) can get it
3199 *
3200 * urb + dev is in hcd.self.controller.urb_list
3201 * we're queueing TDs onto software and hardware lists
3202 *
3203 * hcd-specific init for hcpriv hasn't been done yet
3204 *
3205 * NOTE: control, bulk, and interrupt share the same code to append TDs
3206 * to a (possibly active) QH, and the same QH scanning code.
3207 */
3208static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
3209 gfp_t mem_flags)
3210{
3211 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3212 struct list_head qtd_list;
3213
3214 INIT_LIST_HEAD(&qtd_list);
3215
3216 switch (usb_pipetype(urb->pipe)) {
3217 case PIPE_CONTROL:
3218 case PIPE_BULK:
3219 default:
3220 if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
3221 return -ENOMEM;
3222 return submit_async(oxu, urb, &qtd_list, mem_flags);
3223
3224 case PIPE_INTERRUPT:
3225 if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
3226 return -ENOMEM;
3227 return intr_submit(oxu, urb, &qtd_list, mem_flags);
3228
3229 case PIPE_ISOCHRONOUS:
3230 if (urb->dev->speed == USB_SPEED_HIGH)
3231 return itd_submit(oxu, urb, mem_flags);
3232 else
3233 return sitd_submit(oxu, urb, mem_flags);
3234 }
3235}
3236
3237/* This function is responsible for breaking URBs with big data size
3238 * into smaller size and processing small urbs in sequence.
3239 */
3240static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
3241 gfp_t mem_flags)
3242{
3243 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3244 int num, rem;
3245 void *transfer_buffer;
3246 struct urb *murb;
3247 int i, ret;
3248
3249 /* If not bulk pipe just enqueue the URB */
3250 if (!usb_pipebulk(urb->pipe))
3251 return __oxu_urb_enqueue(hcd, urb, mem_flags);
3252
3253 /* Otherwise we should verify the USB transfer buffer size! */
3254 transfer_buffer = urb->transfer_buffer;
3255
3256 num = urb->transfer_buffer_length / 4096;
3257 rem = urb->transfer_buffer_length % 4096;
3258 if (rem != 0)
3259 num++;
3260
3261 /* If URB is smaller than 4096 bytes just enqueue it! */
3262 if (num == 1)
3263 return __oxu_urb_enqueue(hcd, urb, mem_flags);
3264
3265 /* Ok, we have more job to do! :) */
3266
3267 for (i = 0; i < num - 1; i++) {
3268 /* Get free micro URB poll till a free urb is received */
3269
3270 do {
3271 murb = (struct urb *) oxu_murb_alloc(oxu);
3272 if (!murb)
3273 schedule();
3274 } while (!murb);
3275
3276 /* Coping the urb */
3277 memcpy(murb, urb, sizeof(struct urb));
3278
3279 murb->transfer_buffer_length = 4096;
3280 murb->transfer_buffer = transfer_buffer + i * 4096;
3281
3282 /* Null pointer for the encodes that this is a micro urb */
3283 murb->complete = NULL;
3284
3285 ((struct oxu_murb *) murb)->main = urb;
3286 ((struct oxu_murb *) murb)->last = 0;
3287
3288 /* This loop is to guarantee urb to be processed when there's
3289 * not enough resources at a particular time by retrying.
3290 */
3291 do {
3292 ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
3293 if (ret)
3294 schedule();
3295 } while (ret);
3296 }
3297
3298 /* Last urb requires special handling */
3299
3300 /* Get free micro URB poll till a free urb is received */
3301 do {
3302 murb = (struct urb *) oxu_murb_alloc(oxu);
3303 if (!murb)
3304 schedule();
3305 } while (!murb);
3306
3307 /* Coping the urb */
3308 memcpy(murb, urb, sizeof(struct urb));
3309
3310 murb->transfer_buffer_length = rem > 0 ? rem : 4096;
3311 murb->transfer_buffer = transfer_buffer + (num - 1) * 4096;
3312
3313 /* Null pointer for the encodes that this is a micro urb */
3314 murb->complete = NULL;
3315
3316 ((struct oxu_murb *) murb)->main = urb;
3317 ((struct oxu_murb *) murb)->last = 1;
3318
3319 do {
3320 ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
3321 if (ret)
3322 schedule();
3323 } while (ret);
3324
3325 return ret;
3326}
3327
3328/* Remove from hardware lists.
3329 * Completions normally happen asynchronously
3330 */
3331static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
3332{
3333 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3334 struct ehci_qh *qh;
3335 unsigned long flags;
3336
3337 spin_lock_irqsave(&oxu->lock, flags);
3338 switch (usb_pipetype(urb->pipe)) {
3339 case PIPE_CONTROL:
3340 case PIPE_BULK:
3341 default:
3342 qh = (struct ehci_qh *) urb->hcpriv;
3343 if (!qh)
3344 break;
3345 unlink_async(oxu, qh);
3346 break;
3347
3348 case PIPE_INTERRUPT:
3349 qh = (struct ehci_qh *) urb->hcpriv;
3350 if (!qh)
3351 break;
3352 switch (qh->qh_state) {
3353 case QH_STATE_LINKED:
3354 intr_deschedule(oxu, qh);
3355 fallthrough;
3356 case QH_STATE_IDLE:
3357 qh_completions(oxu, qh);
3358 break;
3359 default:
3360 oxu_dbg(oxu, "bogus qh %p state %d\n",
3361 qh, qh->qh_state);
3362 goto done;
3363 }
3364
3365 /* reschedule QH iff another request is queued */
3366 if (!list_empty(&qh->qtd_list)
3367 && HC_IS_RUNNING(hcd->state)) {
3368 int status;
3369
3370 status = qh_schedule(oxu, qh);
3371 spin_unlock_irqrestore(&oxu->lock, flags);
3372
3373 if (status != 0) {
3374 /* shouldn't happen often, but ...
3375 * FIXME kill those tds' urbs
3376 */
3377 dev_err(hcd->self.controller,
3378 "can't reschedule qh %p, err %d\n", qh,
3379 status);
3380 }
3381 return status;
3382 }
3383 break;
3384 }
3385done:
3386 spin_unlock_irqrestore(&oxu->lock, flags);
3387 return 0;
3388}
3389
3390/* Bulk qh holds the data toggle */
3391static void oxu_endpoint_disable(struct usb_hcd *hcd,
3392 struct usb_host_endpoint *ep)
3393{
3394 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3395 unsigned long flags;
3396 struct ehci_qh *qh, *tmp;
3397
3398 /* ASSERT: any requests/urbs are being unlinked */
3399 /* ASSERT: nobody can be submitting urbs for this any more */
3400
3401rescan:
3402 spin_lock_irqsave(&oxu->lock, flags);
3403 qh = ep->hcpriv;
3404 if (!qh)
3405 goto done;
3406
3407 /* endpoints can be iso streams. for now, we don't
3408 * accelerate iso completions ... so spin a while.
3409 */
3410 if (qh->hw_info1 == 0) {
3411 oxu_vdbg(oxu, "iso delay\n");
3412 goto idle_timeout;
3413 }
3414
3415 if (!HC_IS_RUNNING(hcd->state))
3416 qh->qh_state = QH_STATE_IDLE;
3417 switch (qh->qh_state) {
3418 case QH_STATE_LINKED:
3419 for (tmp = oxu->async->qh_next.qh;
3420 tmp && tmp != qh;
3421 tmp = tmp->qh_next.qh)
3422 continue;
3423 /* periodic qh self-unlinks on empty */
3424 if (!tmp)
3425 goto nogood;
3426 unlink_async(oxu, qh);
3427 fallthrough;
3428 case QH_STATE_UNLINK: /* wait for hw to finish? */
3429idle_timeout:
3430 spin_unlock_irqrestore(&oxu->lock, flags);
3431 schedule_timeout_uninterruptible(1);
3432 goto rescan;
3433 case QH_STATE_IDLE: /* fully unlinked */
3434 if (list_empty(&qh->qtd_list)) {
3435 qh_put(qh);
3436 break;
3437 }
3438 fallthrough;
3439 default:
3440nogood:
3441 /* caller was supposed to have unlinked any requests;
3442 * that's not our job. just leak this memory.
3443 */
3444 oxu_err(oxu, "qh %p (#%02x) state %d%s\n",
3445 qh, ep->desc.bEndpointAddress, qh->qh_state,
3446 list_empty(&qh->qtd_list) ? "" : "(has tds)");
3447 break;
3448 }
3449 ep->hcpriv = NULL;
3450done:
3451 spin_unlock_irqrestore(&oxu->lock, flags);
3452}
3453
3454static int oxu_get_frame(struct usb_hcd *hcd)
3455{
3456 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3457
3458 return (readl(&oxu->regs->frame_index) >> 3) %
3459 oxu->periodic_size;
3460}
3461
3462/* Build "status change" packet (one or two bytes) from HC registers */
3463static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf)
3464{
3465 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3466 u32 temp, mask, status = 0;
3467 int ports, i, retval = 1;
3468 unsigned long flags;
3469
3470 /* if !PM, root hub timers won't get shut down ... */
3471 if (!HC_IS_RUNNING(hcd->state))
3472 return 0;
3473
3474 /* init status to no-changes */
3475 buf[0] = 0;
3476 ports = HCS_N_PORTS(oxu->hcs_params);
3477 if (ports > 7) {
3478 buf[1] = 0;
3479 retval++;
3480 }
3481
3482 /* Some boards (mostly VIA?) report bogus overcurrent indications,
3483 * causing massive log spam unless we completely ignore them. It
3484 * may be relevant that VIA VT8235 controllers, where PORT_POWER is
3485 * always set, seem to clear PORT_OCC and PORT_CSC when writing to
3486 * PORT_POWER; that's surprising, but maybe within-spec.
3487 */
3488 if (!ignore_oc)
3489 mask = PORT_CSC | PORT_PEC | PORT_OCC;
3490 else
3491 mask = PORT_CSC | PORT_PEC;
3492
3493 /* no hub change reports (bit 0) for now (power, ...) */
3494
3495 /* port N changes (bit N)? */
3496 spin_lock_irqsave(&oxu->lock, flags);
3497 for (i = 0; i < ports; i++) {
3498 temp = readl(&oxu->regs->port_status[i]);
3499
3500 /*
3501 * Return status information even for ports with OWNER set.
3502 * Otherwise hub_wq wouldn't see the disconnect event when a
3503 * high-speed device is switched over to the companion
3504 * controller by the user.
3505 */
3506
3507 if (!(temp & PORT_CONNECT))
3508 oxu->reset_done[i] = 0;
3509 if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 &&
3510 time_after_eq(jiffies, oxu->reset_done[i]))) {
3511 if (i < 7)
3512 buf[0] |= 1 << (i + 1);
3513 else
3514 buf[1] |= 1 << (i - 7);
3515 status = STS_PCD;
3516 }
3517 }
3518 /* FIXME autosuspend idle root hubs */
3519 spin_unlock_irqrestore(&oxu->lock, flags);
3520 return status ? retval : 0;
3521}
3522
3523/* Returns the speed of a device attached to a port on the root hub. */
3524static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu,
3525 unsigned int portsc)
3526{
3527 switch ((portsc >> 26) & 3) {
3528 case 0:
3529 return 0;
3530 case 1:
3531 return USB_PORT_STAT_LOW_SPEED;
3532 case 2:
3533 default:
3534 return USB_PORT_STAT_HIGH_SPEED;
3535 }
3536}
3537
3538#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
3539static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq,
3540 u16 wValue, u16 wIndex, char *buf, u16 wLength)
3541{
3542 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3543 int ports = HCS_N_PORTS(oxu->hcs_params);
3544 u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1];
3545 u32 temp, status;
3546 unsigned long flags;
3547 int retval = 0;
3548 unsigned selector;
3549
3550 /*
3551 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
3552 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
3553 * (track current state ourselves) ... blink for diagnostics,
3554 * power, "this is the one", etc. EHCI spec supports this.
3555 */
3556
3557 spin_lock_irqsave(&oxu->lock, flags);
3558 switch (typeReq) {
3559 case ClearHubFeature:
3560 switch (wValue) {
3561 case C_HUB_LOCAL_POWER:
3562 case C_HUB_OVER_CURRENT:
3563 /* no hub-wide feature/status flags */
3564 break;
3565 default:
3566 goto error;
3567 }
3568 break;
3569 case ClearPortFeature:
3570 if (!wIndex || wIndex > ports)
3571 goto error;
3572 wIndex--;
3573 temp = readl(status_reg);
3574
3575 /*
3576 * Even if OWNER is set, so the port is owned by the
3577 * companion controller, hub_wq needs to be able to clear
3578 * the port-change status bits (especially
3579 * USB_PORT_STAT_C_CONNECTION).
3580 */
3581
3582 switch (wValue) {
3583 case USB_PORT_FEAT_ENABLE:
3584 writel(temp & ~PORT_PE, status_reg);
3585 break;
3586 case USB_PORT_FEAT_C_ENABLE:
3587 writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
3588 break;
3589 case USB_PORT_FEAT_SUSPEND:
3590 if (temp & PORT_RESET)
3591 goto error;
3592 if (temp & PORT_SUSPEND) {
3593 if ((temp & PORT_PE) == 0)
3594 goto error;
3595 /* resume signaling for 20 msec */
3596 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
3597 writel(temp | PORT_RESUME, status_reg);
3598 oxu->reset_done[wIndex] = jiffies
3599 + msecs_to_jiffies(20);
3600 }
3601 break;
3602 case USB_PORT_FEAT_C_SUSPEND:
3603 /* we auto-clear this feature */
3604 break;
3605 case USB_PORT_FEAT_POWER:
3606 if (HCS_PPC(oxu->hcs_params))
3607 writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
3608 status_reg);
3609 break;
3610 case USB_PORT_FEAT_C_CONNECTION:
3611 writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
3612 break;
3613 case USB_PORT_FEAT_C_OVER_CURRENT:
3614 writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
3615 break;
3616 case USB_PORT_FEAT_C_RESET:
3617 /* GetPortStatus clears reset */
3618 break;
3619 default:
3620 goto error;
3621 }
3622 readl(&oxu->regs->command); /* unblock posted write */
3623 break;
3624 case GetHubDescriptor:
3625 ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *)
3626 buf);
3627 break;
3628 case GetHubStatus:
3629 /* no hub-wide feature/status flags */
3630 memset(buf, 0, 4);
3631 break;
3632 case GetPortStatus:
3633 if (!wIndex || wIndex > ports)
3634 goto error;
3635 wIndex--;
3636 status = 0;
3637 temp = readl(status_reg);
3638
3639 /* wPortChange bits */
3640 if (temp & PORT_CSC)
3641 status |= USB_PORT_STAT_C_CONNECTION << 16;
3642 if (temp & PORT_PEC)
3643 status |= USB_PORT_STAT_C_ENABLE << 16;
3644 if ((temp & PORT_OCC) && !ignore_oc)
3645 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3646
3647 /* whoever resumes must GetPortStatus to complete it!! */
3648 if (temp & PORT_RESUME) {
3649
3650 /* Remote Wakeup received? */
3651 if (!oxu->reset_done[wIndex]) {
3652 /* resume signaling for 20 msec */
3653 oxu->reset_done[wIndex] = jiffies
3654 + msecs_to_jiffies(20);
3655 /* check the port again */
3656 mod_timer(&oxu_to_hcd(oxu)->rh_timer,
3657 oxu->reset_done[wIndex]);
3658 }
3659
3660 /* resume completed? */
3661 else if (time_after_eq(jiffies,
3662 oxu->reset_done[wIndex])) {
3663 status |= USB_PORT_STAT_C_SUSPEND << 16;
3664 oxu->reset_done[wIndex] = 0;
3665
3666 /* stop resume signaling */
3667 temp = readl(status_reg);
3668 writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
3669 status_reg);
3670 retval = handshake(oxu, status_reg,
3671 PORT_RESUME, 0, 2000 /* 2msec */);
3672 if (retval != 0) {
3673 oxu_err(oxu,
3674 "port %d resume error %d\n",
3675 wIndex + 1, retval);
3676 goto error;
3677 }
3678 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
3679 }
3680 }
3681
3682 /* whoever resets must GetPortStatus to complete it!! */
3683 if ((temp & PORT_RESET)
3684 && time_after_eq(jiffies,
3685 oxu->reset_done[wIndex])) {
3686 status |= USB_PORT_STAT_C_RESET << 16;
3687 oxu->reset_done[wIndex] = 0;
3688
3689 /* force reset to complete */
3690 writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
3691 status_reg);
3692 /* REVISIT: some hardware needs 550+ usec to clear
3693 * this bit; seems too long to spin routinely...
3694 */
3695 retval = handshake(oxu, status_reg,
3696 PORT_RESET, 0, 750);
3697 if (retval != 0) {
3698 oxu_err(oxu, "port %d reset error %d\n",
3699 wIndex + 1, retval);
3700 goto error;
3701 }
3702
3703 /* see what we found out */
3704 temp = check_reset_complete(oxu, wIndex, status_reg,
3705 readl(status_reg));
3706 }
3707
3708 /* transfer dedicated ports to the companion hc */
3709 if ((temp & PORT_CONNECT) &&
3710 test_bit(wIndex, &oxu->companion_ports)) {
3711 temp &= ~PORT_RWC_BITS;
3712 temp |= PORT_OWNER;
3713 writel(temp, status_reg);
3714 oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1);
3715 temp = readl(status_reg);
3716 }
3717
3718 /*
3719 * Even if OWNER is set, there's no harm letting hub_wq
3720 * see the wPortStatus values (they should all be 0 except
3721 * for PORT_POWER anyway).
3722 */
3723
3724 if (temp & PORT_CONNECT) {
3725 status |= USB_PORT_STAT_CONNECTION;
3726 /* status may be from integrated TT */
3727 status |= oxu_port_speed(oxu, temp);
3728 }
3729 if (temp & PORT_PE)
3730 status |= USB_PORT_STAT_ENABLE;
3731 if (temp & (PORT_SUSPEND|PORT_RESUME))
3732 status |= USB_PORT_STAT_SUSPEND;
3733 if (temp & PORT_OC)
3734 status |= USB_PORT_STAT_OVERCURRENT;
3735 if (temp & PORT_RESET)
3736 status |= USB_PORT_STAT_RESET;
3737 if (temp & PORT_POWER)
3738 status |= USB_PORT_STAT_POWER;
3739
3740#ifndef OXU_VERBOSE_DEBUG
3741 if (status & ~0xffff) /* only if wPortChange is interesting */
3742#endif
3743 dbg_port(oxu, "GetStatus", wIndex + 1, temp);
3744 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
3745 break;
3746 case SetHubFeature:
3747 switch (wValue) {
3748 case C_HUB_LOCAL_POWER:
3749 case C_HUB_OVER_CURRENT:
3750 /* no hub-wide feature/status flags */
3751 break;
3752 default:
3753 goto error;
3754 }
3755 break;
3756 case SetPortFeature:
3757 selector = wIndex >> 8;
3758 wIndex &= 0xff;
3759 if (!wIndex || wIndex > ports)
3760 goto error;
3761 wIndex--;
3762 temp = readl(status_reg);
3763 if (temp & PORT_OWNER)
3764 break;
3765
3766 temp &= ~PORT_RWC_BITS;
3767 switch (wValue) {
3768 case USB_PORT_FEAT_SUSPEND:
3769 if ((temp & PORT_PE) == 0
3770 || (temp & PORT_RESET) != 0)
3771 goto error;
3772 if (device_may_wakeup(&hcd->self.root_hub->dev))
3773 temp |= PORT_WAKE_BITS;
3774 writel(temp | PORT_SUSPEND, status_reg);
3775 break;
3776 case USB_PORT_FEAT_POWER:
3777 if (HCS_PPC(oxu->hcs_params))
3778 writel(temp | PORT_POWER, status_reg);
3779 break;
3780 case USB_PORT_FEAT_RESET:
3781 if (temp & PORT_RESUME)
3782 goto error;
3783 /* line status bits may report this as low speed,
3784 * which can be fine if this root hub has a
3785 * transaction translator built in.
3786 */
3787 oxu_vdbg(oxu, "port %d reset\n", wIndex + 1);
3788 temp |= PORT_RESET;
3789 temp &= ~PORT_PE;
3790
3791 /*
3792 * caller must wait, then call GetPortStatus
3793 * usb 2.0 spec says 50 ms resets on root
3794 */
3795 oxu->reset_done[wIndex] = jiffies
3796 + msecs_to_jiffies(50);
3797 writel(temp, status_reg);
3798 break;
3799
3800 /* For downstream facing ports (these): one hub port is put
3801 * into test mode according to USB2 11.24.2.13, then the hub
3802 * must be reset (which for root hub now means rmmod+modprobe,
3803 * or else system reboot). See EHCI 2.3.9 and 4.14 for info
3804 * about the EHCI-specific stuff.
3805 */
3806 case USB_PORT_FEAT_TEST:
3807 if (!selector || selector > 5)
3808 goto error;
3809 ehci_quiesce(oxu);
3810 ehci_halt(oxu);
3811 temp |= selector << 16;
3812 writel(temp, status_reg);
3813 break;
3814
3815 default:
3816 goto error;
3817 }
3818 readl(&oxu->regs->command); /* unblock posted writes */
3819 break;
3820
3821 default:
3822error:
3823 /* "stall" on error */
3824 retval = -EPIPE;
3825 }
3826 spin_unlock_irqrestore(&oxu->lock, flags);
3827 return retval;
3828}
3829
3830#ifdef CONFIG_PM
3831
3832static int oxu_bus_suspend(struct usb_hcd *hcd)
3833{
3834 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3835 int port;
3836 int mask;
3837
3838 oxu_dbg(oxu, "suspend root hub\n");
3839
3840 if (time_before(jiffies, oxu->next_statechange))
3841 msleep(5);
3842
3843 port = HCS_N_PORTS(oxu->hcs_params);
3844 spin_lock_irq(&oxu->lock);
3845
3846 /* stop schedules, clean any completed work */
3847 if (HC_IS_RUNNING(hcd->state)) {
3848 ehci_quiesce(oxu);
3849 hcd->state = HC_STATE_QUIESCING;
3850 }
3851 oxu->command = readl(&oxu->regs->command);
3852 if (oxu->reclaim)
3853 oxu->reclaim_ready = 1;
3854 ehci_work(oxu);
3855
3856 /* Unlike other USB host controller types, EHCI doesn't have
3857 * any notion of "global" or bus-wide suspend. The driver has
3858 * to manually suspend all the active unsuspended ports, and
3859 * then manually resume them in the bus_resume() routine.
3860 */
3861 oxu->bus_suspended = 0;
3862 while (port--) {
3863 u32 __iomem *reg = &oxu->regs->port_status[port];
3864 u32 t1 = readl(reg) & ~PORT_RWC_BITS;
3865 u32 t2 = t1;
3866
3867 /* keep track of which ports we suspend */
3868 if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) &&
3869 !(t1 & PORT_SUSPEND)) {
3870 t2 |= PORT_SUSPEND;
3871 set_bit(port, &oxu->bus_suspended);
3872 }
3873
3874 /* enable remote wakeup on all ports */
3875 if (device_may_wakeup(&hcd->self.root_hub->dev))
3876 t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E;
3877 else
3878 t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E);
3879
3880 if (t1 != t2) {
3881 oxu_vdbg(oxu, "port %d, %08x -> %08x\n",
3882 port + 1, t1, t2);
3883 writel(t2, reg);
3884 }
3885 }
3886
3887 spin_unlock_irq(&oxu->lock);
3888 /* turn off now-idle HC */
3889 del_timer_sync(&oxu->watchdog);
3890 spin_lock_irq(&oxu->lock);
3891 ehci_halt(oxu);
3892 hcd->state = HC_STATE_SUSPENDED;
3893
3894 /* allow remote wakeup */
3895 mask = INTR_MASK;
3896 if (!device_may_wakeup(&hcd->self.root_hub->dev))
3897 mask &= ~STS_PCD;
3898 writel(mask, &oxu->regs->intr_enable);
3899 readl(&oxu->regs->intr_enable);
3900
3901 oxu->next_statechange = jiffies + msecs_to_jiffies(10);
3902 spin_unlock_irq(&oxu->lock);
3903 return 0;
3904}
3905
3906/* Caller has locked the root hub, and should reset/reinit on error */
3907static int oxu_bus_resume(struct usb_hcd *hcd)
3908{
3909 struct oxu_hcd *oxu = hcd_to_oxu(hcd);
3910 u32 temp;
3911 int i;
3912
3913 if (time_before(jiffies, oxu->next_statechange))
3914 msleep(5);
3915 spin_lock_irq(&oxu->lock);
3916
3917 /* Ideally and we've got a real resume here, and no port's power
3918 * was lost. (For PCI, that means Vaux was maintained.) But we
3919 * could instead be restoring a swsusp snapshot -- so that BIOS was
3920 * the last user of the controller, not reset/pm hardware keeping
3921 * state we gave to it.
3922 */
3923 temp = readl(&oxu->regs->intr_enable);
3924 oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss");
3925
3926 /* at least some APM implementations will try to deliver
3927 * IRQs right away, so delay them until we're ready.
3928 */
3929 writel(0, &oxu->regs->intr_enable);
3930
3931 /* re-init operational registers */
3932 writel(0, &oxu->regs->segment);
3933 writel(oxu->periodic_dma, &oxu->regs->frame_list);
3934 writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
3935
3936 /* restore CMD_RUN, framelist size, and irq threshold */
3937 writel(oxu->command, &oxu->regs->command);
3938
3939 /* Some controller/firmware combinations need a delay during which
3940 * they set up the port statuses. See Bugzilla #8190. */
3941 mdelay(8);
3942
3943 /* manually resume the ports we suspended during bus_suspend() */
3944 i = HCS_N_PORTS(oxu->hcs_params);
3945 while (i--) {
3946 temp = readl(&oxu->regs->port_status[i]);
3947 temp &= ~(PORT_RWC_BITS
3948 | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E);
3949 if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
3950 oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
3951 temp |= PORT_RESUME;
3952 }
3953 writel(temp, &oxu->regs->port_status[i]);
3954 }
3955 i = HCS_N_PORTS(oxu->hcs_params);
3956 mdelay(20);
3957 while (i--) {
3958 temp = readl(&oxu->regs->port_status[i]);
3959 if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
3960 temp &= ~(PORT_RWC_BITS | PORT_RESUME);
3961 writel(temp, &oxu->regs->port_status[i]);
3962 oxu_vdbg(oxu, "resumed port %d\n", i + 1);
3963 }
3964 }
3965 (void) readl(&oxu->regs->command);
3966
3967 /* maybe re-activate the schedule(s) */
3968 temp = 0;
3969 if (oxu->async->qh_next.qh)
3970 temp |= CMD_ASE;
3971 if (oxu->periodic_sched)
3972 temp |= CMD_PSE;
3973 if (temp) {
3974 oxu->command |= temp;
3975 writel(oxu->command, &oxu->regs->command);
3976 }
3977
3978 oxu->next_statechange = jiffies + msecs_to_jiffies(5);
3979 hcd->state = HC_STATE_RUNNING;
3980
3981 /* Now we can safely re-enable irqs */
3982 writel(INTR_MASK, &oxu->regs->intr_enable);
3983
3984 spin_unlock_irq(&oxu->lock);
3985 return 0;
3986}
3987
3988#else
3989
3990static int oxu_bus_suspend(struct usb_hcd *hcd)
3991{
3992 return 0;
3993}
3994
3995static int oxu_bus_resume(struct usb_hcd *hcd)
3996{
3997 return 0;
3998}
3999
4000#endif /* CONFIG_PM */
4001
4002static const struct hc_driver oxu_hc_driver = {
4003 .description = "oxu210hp_hcd",
4004 .product_desc = "oxu210hp HCD",
4005 .hcd_priv_size = sizeof(struct oxu_hcd),
4006
4007 /*
4008 * Generic hardware linkage
4009 */
4010 .irq = oxu_irq,
4011 .flags = HCD_MEMORY | HCD_USB2,
4012
4013 /*
4014 * Basic lifecycle operations
4015 */
4016 .reset = oxu_reset,
4017 .start = oxu_run,
4018 .stop = oxu_stop,
4019 .shutdown = oxu_shutdown,
4020
4021 /*
4022 * Managing i/o requests and associated device resources
4023 */
4024 .urb_enqueue = oxu_urb_enqueue,
4025 .urb_dequeue = oxu_urb_dequeue,
4026 .endpoint_disable = oxu_endpoint_disable,
4027
4028 /*
4029 * Scheduling support
4030 */
4031 .get_frame_number = oxu_get_frame,
4032
4033 /*
4034 * Root hub support
4035 */
4036 .hub_status_data = oxu_hub_status_data,
4037 .hub_control = oxu_hub_control,
4038 .bus_suspend = oxu_bus_suspend,
4039 .bus_resume = oxu_bus_resume,
4040};
4041
4042/*
4043 * Module stuff
4044 */
4045
4046static void oxu_configuration(struct platform_device *pdev, void __iomem *base)
4047{
4048 u32 tmp;
4049
4050 /* Initialize top level registers.
4051 * First write ever
4052 */
4053 oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
4054 oxu_writel(base, OXU_SOFTRESET, OXU_SRESET);
4055 oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
4056
4057 tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL);
4058 oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040);
4059
4060 oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN |
4061 OXU_COMPARATOR | OXU_ASO_OP);
4062
4063 tmp = oxu_readl(base, OXU_CLKCTRL_SET);
4064 oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN);
4065
4066 /* Clear all top interrupt enable */
4067 oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff);
4068
4069 /* Clear all top interrupt status */
4070 oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff);
4071
4072 /* Enable all needed top interrupt except OTG SPH core */
4073 oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI);
4074}
4075
4076static int oxu_verify_id(struct platform_device *pdev, void __iomem *base)
4077{
4078 u32 id;
4079 static const char * const bo[] = {
4080 "reserved",
4081 "128-pin LQFP",
4082 "84-pin TFBGA",
4083 "reserved",
4084 };
4085
4086 /* Read controller signature register to find a match */
4087 id = oxu_readl(base, OXU_DEVICEID);
4088 dev_info(&pdev->dev, "device ID %x\n", id);
4089 if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT))
4090 return -1;
4091
4092 dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n",
4093 id >> OXU_REV_SHIFT,
4094 bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT],
4095 (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT,
4096 (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT);
4097
4098 return 0;
4099}
4100
4101static const struct hc_driver oxu_hc_driver;
4102static struct usb_hcd *oxu_create(struct platform_device *pdev,
4103 unsigned long memstart, unsigned long memlen,
4104 void __iomem *base, int irq, int otg)
4105{
4106 struct device *dev = &pdev->dev;
4107
4108 struct usb_hcd *hcd;
4109 struct oxu_hcd *oxu;
4110 int ret;
4111
4112 /* Set endian mode and host mode */
4113 oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET),
4114 OXU_USBMODE,
4115 OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS);
4116
4117 hcd = usb_create_hcd(&oxu_hc_driver, dev,
4118 otg ? "oxu210hp_otg" : "oxu210hp_sph");
4119 if (!hcd)
4120 return ERR_PTR(-ENOMEM);
4121
4122 hcd->rsrc_start = memstart;
4123 hcd->rsrc_len = memlen;
4124 hcd->regs = base;
4125 hcd->irq = irq;
4126 hcd->state = HC_STATE_HALT;
4127
4128 oxu = hcd_to_oxu(hcd);
4129 oxu->is_otg = otg;
4130
4131 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
4132 if (ret < 0) {
4133 usb_put_hcd(hcd);
4134 return ERR_PTR(ret);
4135 }
4136
4137 device_wakeup_enable(hcd->self.controller);
4138 return hcd;
4139}
4140
4141static int oxu_init(struct platform_device *pdev,
4142 unsigned long memstart, unsigned long memlen,
4143 void __iomem *base, int irq)
4144{
4145 struct oxu_info *info = platform_get_drvdata(pdev);
4146 struct usb_hcd *hcd;
4147 int ret;
4148
4149 /* First time configuration at start up */
4150 oxu_configuration(pdev, base);
4151
4152 ret = oxu_verify_id(pdev, base);
4153 if (ret) {
4154 dev_err(&pdev->dev, "no devices found!\n");
4155 return -ENODEV;
4156 }
4157
4158 /* Create the OTG controller */
4159 hcd = oxu_create(pdev, memstart, memlen, base, irq, 1);
4160 if (IS_ERR(hcd)) {
4161 dev_err(&pdev->dev, "cannot create OTG controller!\n");
4162 ret = PTR_ERR(hcd);
4163 goto error_create_otg;
4164 }
4165 info->hcd[0] = hcd;
4166
4167 /* Create the SPH host controller */
4168 hcd = oxu_create(pdev, memstart, memlen, base, irq, 0);
4169 if (IS_ERR(hcd)) {
4170 dev_err(&pdev->dev, "cannot create SPH controller!\n");
4171 ret = PTR_ERR(hcd);
4172 goto error_create_sph;
4173 }
4174 info->hcd[1] = hcd;
4175
4176 oxu_writel(base, OXU_CHIPIRQEN_SET,
4177 oxu_readl(base, OXU_CHIPIRQEN_SET) | 3);
4178
4179 return 0;
4180
4181error_create_sph:
4182 usb_remove_hcd(info->hcd[0]);
4183 usb_put_hcd(info->hcd[0]);
4184
4185error_create_otg:
4186 return ret;
4187}
4188
4189static int oxu_drv_probe(struct platform_device *pdev)
4190{
4191 struct resource *res;
4192 void __iomem *base;
4193 unsigned long memstart, memlen;
4194 int irq, ret;
4195 struct oxu_info *info;
4196
4197 if (usb_disabled())
4198 return -ENODEV;
4199
4200 /*
4201 * Get the platform resources
4202 */
4203 irq = platform_get_irq(pdev, 0);
4204 if (irq < 0)
4205 return irq;
4206 dev_dbg(&pdev->dev, "IRQ resource %d\n", irq);
4207
4208 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
4209 if (IS_ERR(base)) {
4210 ret = PTR_ERR(base);
4211 goto error;
4212 }
4213 memstart = res->start;
4214 memlen = resource_size(res);
4215
4216 ret = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING);
4217 if (ret) {
4218 dev_err(&pdev->dev, "error setting irq type\n");
4219 ret = -EFAULT;
4220 goto error;
4221 }
4222
4223 /* Allocate a driver data struct to hold useful info for both
4224 * SPH & OTG devices
4225 */
4226 info = devm_kzalloc(&pdev->dev, sizeof(struct oxu_info), GFP_KERNEL);
4227 if (!info) {
4228 ret = -EFAULT;
4229 goto error;
4230 }
4231 platform_set_drvdata(pdev, info);
4232
4233 ret = oxu_init(pdev, memstart, memlen, base, irq);
4234 if (ret < 0) {
4235 dev_dbg(&pdev->dev, "cannot init USB devices\n");
4236 goto error;
4237 }
4238
4239 dev_info(&pdev->dev, "devices enabled and running\n");
4240 platform_set_drvdata(pdev, info);
4241
4242 return 0;
4243
4244error:
4245 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret);
4246 return ret;
4247}
4248
4249static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd)
4250{
4251 usb_remove_hcd(hcd);
4252 usb_put_hcd(hcd);
4253}
4254
4255static void oxu_drv_remove(struct platform_device *pdev)
4256{
4257 struct oxu_info *info = platform_get_drvdata(pdev);
4258
4259 oxu_remove(pdev, info->hcd[0]);
4260 oxu_remove(pdev, info->hcd[1]);
4261}
4262
4263static void oxu_drv_shutdown(struct platform_device *pdev)
4264{
4265 oxu_drv_remove(pdev);
4266}
4267
4268#if 0
4269/* FIXME: TODO */
4270static int oxu_drv_suspend(struct device *dev)
4271{
4272 struct platform_device *pdev = to_platform_device(dev);
4273 struct usb_hcd *hcd = dev_get_drvdata(dev);
4274
4275 return 0;
4276}
4277
4278static int oxu_drv_resume(struct device *dev)
4279{
4280 struct platform_device *pdev = to_platform_device(dev);
4281 struct usb_hcd *hcd = dev_get_drvdata(dev);
4282
4283 return 0;
4284}
4285#else
4286#define oxu_drv_suspend NULL
4287#define oxu_drv_resume NULL
4288#endif
4289
4290static struct platform_driver oxu_driver = {
4291 .probe = oxu_drv_probe,
4292 .remove = oxu_drv_remove,
4293 .shutdown = oxu_drv_shutdown,
4294 .suspend = oxu_drv_suspend,
4295 .resume = oxu_drv_resume,
4296 .driver = {
4297 .name = "oxu210hp-hcd",
4298 .bus = &platform_bus_type
4299 }
4300};
4301
4302module_platform_driver(oxu_driver);
4303
4304MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION);
4305MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
4306MODULE_LICENSE("GPL");