Loading...
1/*
2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
3 *
4 * Copyright (c) 2000-2004 by David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef CONFIG_PCI
22#error "This file is PCI bus glue. CONFIG_PCI must be defined."
23#endif
24
25/* defined here to avoid adding to pci_ids.h for single instance use */
26#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
27
28/*-------------------------------------------------------------------------*/
29
30/* called after powerup, by probe or system-pm "wakeup" */
31static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
32{
33 int retval;
34
35 /* we expect static quirk code to handle the "extended capabilities"
36 * (currently just BIOS handoff) allowed starting with EHCI 0.96
37 */
38
39 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
40 retval = pci_set_mwi(pdev);
41 if (!retval)
42 ehci_dbg(ehci, "MWI active\n");
43
44 return 0;
45}
46
47/* called during probe() after chip reset completes */
48static int ehci_pci_setup(struct usb_hcd *hcd)
49{
50 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
51 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
52 struct pci_dev *p_smbus;
53 u8 rev;
54 u32 temp;
55 int retval;
56
57 switch (pdev->vendor) {
58 case PCI_VENDOR_ID_TOSHIBA_2:
59 /* celleb's companion chip */
60 if (pdev->device == 0x01b5) {
61#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
62 ehci->big_endian_mmio = 1;
63#else
64 ehci_warn(ehci,
65 "unsupported big endian Toshiba quirk\n");
66#endif
67 }
68 break;
69 }
70
71 ehci->caps = hcd->regs;
72 ehci->regs = hcd->regs +
73 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
74
75 dbg_hcs_params(ehci, "reset");
76 dbg_hcc_params(ehci, "reset");
77
78 /* ehci_init() causes memory for DMA transfers to be
79 * allocated. Thus, any vendor-specific workarounds based on
80 * limiting the type of memory used for DMA transfers must
81 * happen before ehci_init() is called. */
82 switch (pdev->vendor) {
83 case PCI_VENDOR_ID_NVIDIA:
84 /* NVidia reports that certain chips don't handle
85 * QH, ITD, or SITD addresses above 2GB. (But TD,
86 * data buffer, and periodic schedule are normal.)
87 */
88 switch (pdev->device) {
89 case 0x003c: /* MCP04 */
90 case 0x005b: /* CK804 */
91 case 0x00d8: /* CK8 */
92 case 0x00e8: /* CK8S */
93 if (pci_set_consistent_dma_mask(pdev,
94 DMA_BIT_MASK(31)) < 0)
95 ehci_warn(ehci, "can't enable NVidia "
96 "workaround for >2GB RAM\n");
97 break;
98 }
99 break;
100 }
101
102 /* cache this readonly data; minimize chip reads */
103 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
104
105 retval = ehci_halt(ehci);
106 if (retval)
107 return retval;
108
109 if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
110 (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
111 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
112 * read/write memory space which does not belong to it when
113 * there is NULL pointer with T-bit set to 1 in the frame list
114 * table. To avoid the issue, the frame list link pointer
115 * should always contain a valid pointer to a inactive qh.
116 */
117 ehci->use_dummy_qh = 1;
118 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
119 "dummy qh workaround\n");
120 }
121
122 /* data structure init */
123 retval = ehci_init(hcd);
124 if (retval)
125 return retval;
126
127 switch (pdev->vendor) {
128 case PCI_VENDOR_ID_NEC:
129 ehci->need_io_watchdog = 0;
130 break;
131 case PCI_VENDOR_ID_INTEL:
132 ehci->need_io_watchdog = 0;
133 ehci->fs_i_thresh = 1;
134 if (pdev->device == 0x27cc) {
135 ehci->broken_periodic = 1;
136 ehci_info(ehci, "using broken periodic workaround\n");
137 }
138 if (pdev->device == 0x0806 || pdev->device == 0x0811
139 || pdev->device == 0x0829) {
140 ehci_info(ehci, "disable lpm for langwell/penwell\n");
141 ehci->has_lpm = 0;
142 }
143 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
144 hcd->has_tt = 1;
145 tdi_reset(ehci);
146 }
147 break;
148 case PCI_VENDOR_ID_TDI:
149 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
150 hcd->has_tt = 1;
151 tdi_reset(ehci);
152 }
153 break;
154 case PCI_VENDOR_ID_AMD:
155 /* AMD PLL quirk */
156 if (usb_amd_find_chipset_info())
157 ehci->amd_pll_fix = 1;
158 /* AMD8111 EHCI doesn't work, according to AMD errata */
159 if (pdev->device == 0x7463) {
160 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
161 retval = -EIO;
162 goto done;
163 }
164 break;
165 case PCI_VENDOR_ID_NVIDIA:
166 switch (pdev->device) {
167 /* Some NForce2 chips have problems with selective suspend;
168 * fixed in newer silicon.
169 */
170 case 0x0068:
171 if (pdev->revision < 0xa4)
172 ehci->no_selective_suspend = 1;
173 break;
174
175 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
176 * fetching device descriptors unless LPM is disabled.
177 * There are also intermittent problems enumerating
178 * devices with PPCD enabled.
179 */
180 case 0x0d9d:
181 ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
182 ehci->has_lpm = 0;
183 ehci->has_ppcd = 0;
184 ehci->command &= ~CMD_PPCEE;
185 break;
186 }
187 break;
188 case PCI_VENDOR_ID_VIA:
189 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
190 u8 tmp;
191
192 /* The VT6212 defaults to a 1 usec EHCI sleep time which
193 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
194 * that sleep time use the conventional 10 usec.
195 */
196 pci_read_config_byte(pdev, 0x4b, &tmp);
197 if (tmp & 0x20)
198 break;
199 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
200 }
201 break;
202 case PCI_VENDOR_ID_ATI:
203 /* AMD PLL quirk */
204 if (usb_amd_find_chipset_info())
205 ehci->amd_pll_fix = 1;
206 /* SB600 and old version of SB700 have a bug in EHCI controller,
207 * which causes usb devices lose response in some cases.
208 */
209 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
210 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
211 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
212 NULL);
213 if (!p_smbus)
214 break;
215 rev = p_smbus->revision;
216 if ((pdev->device == 0x4386) || (rev == 0x3a)
217 || (rev == 0x3b)) {
218 u8 tmp;
219 ehci_info(ehci, "applying AMD SB600/SB700 USB "
220 "freeze workaround\n");
221 pci_read_config_byte(pdev, 0x53, &tmp);
222 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
223 }
224 pci_dev_put(p_smbus);
225 }
226 break;
227 }
228
229 /* optional debug port, normally in the first BAR */
230 temp = pci_find_capability(pdev, 0x0a);
231 if (temp) {
232 pci_read_config_dword(pdev, temp, &temp);
233 temp >>= 16;
234 if ((temp & (3 << 13)) == (1 << 13)) {
235 temp &= 0x1fff;
236 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
237 temp = ehci_readl(ehci, &ehci->debug->control);
238 ehci_info(ehci, "debug port %d%s\n",
239 HCS_DEBUG_PORT(ehci->hcs_params),
240 (temp & DBGP_ENABLED)
241 ? " IN USE"
242 : "");
243 if (!(temp & DBGP_ENABLED))
244 ehci->debug = NULL;
245 }
246 }
247
248 ehci_reset(ehci);
249
250 /* at least the Genesys GL880S needs fixup here */
251 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
252 temp &= 0x0f;
253 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
254 ehci_dbg(ehci, "bogus port configuration: "
255 "cc=%d x pcc=%d < ports=%d\n",
256 HCS_N_CC(ehci->hcs_params),
257 HCS_N_PCC(ehci->hcs_params),
258 HCS_N_PORTS(ehci->hcs_params));
259
260 switch (pdev->vendor) {
261 case 0x17a0: /* GENESYS */
262 /* GL880S: should be PORTS=2 */
263 temp |= (ehci->hcs_params & ~0xf);
264 ehci->hcs_params = temp;
265 break;
266 case PCI_VENDOR_ID_NVIDIA:
267 /* NF4: should be PCC=10 */
268 break;
269 }
270 }
271
272 /* Serial Bus Release Number is at PCI 0x60 offset */
273 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
274
275 /* Keep this around for a while just in case some EHCI
276 * implementation uses legacy PCI PM support. This test
277 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
278 * been triggered by then.
279 */
280 if (!device_can_wakeup(&pdev->dev)) {
281 u16 port_wake;
282
283 pci_read_config_word(pdev, 0x62, &port_wake);
284 if (port_wake & 0x0001) {
285 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
286 device_set_wakeup_capable(&pdev->dev, 1);
287 }
288 }
289
290#ifdef CONFIG_USB_SUSPEND
291 /* REVISIT: the controller works fine for wakeup iff the root hub
292 * itself is "globally" suspended, but usbcore currently doesn't
293 * understand such things.
294 *
295 * System suspend currently expects to be able to suspend the entire
296 * device tree, device-at-a-time. If we failed selective suspend
297 * reports, system suspend would fail; so the root hub code must claim
298 * success. That's lying to usbcore, and it matters for runtime
299 * PM scenarios with selective suspend and remote wakeup...
300 */
301 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
302 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
303#endif
304
305 ehci_port_power(ehci, 1);
306 retval = ehci_pci_reinit(ehci, pdev);
307done:
308 return retval;
309}
310
311/*-------------------------------------------------------------------------*/
312
313#ifdef CONFIG_PM
314
315/* suspend/resume, section 4.3 */
316
317/* These routines rely on the PCI bus glue
318 * to handle powerdown and wakeup, and currently also on
319 * transceivers that don't need any software attention to set up
320 * the right sort of wakeup.
321 * Also they depend on separate root hub suspend/resume.
322 */
323
324static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
325{
326 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
327 unsigned long flags;
328 int rc = 0;
329
330 if (time_before(jiffies, ehci->next_statechange))
331 msleep(10);
332
333 /* Root hub was already suspended. Disable irq emission and
334 * mark HW unaccessible. The PM and USB cores make sure that
335 * the root hub is either suspended or stopped.
336 */
337 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
338 spin_lock_irqsave (&ehci->lock, flags);
339 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
340 (void)ehci_readl(ehci, &ehci->regs->intr_enable);
341
342 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
343 spin_unlock_irqrestore (&ehci->lock, flags);
344
345 // could save FLADJ in case of Vaux power loss
346 // ... we'd only use it to handle clock skew
347
348 return rc;
349}
350
351static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
352{
353 return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
354 pdev->vendor == PCI_VENDOR_ID_INTEL &&
355 pdev->device == 0x1E26;
356}
357
358static void ehci_enable_xhci_companion(void)
359{
360 struct pci_dev *companion = NULL;
361
362 /* The xHCI and EHCI controllers are not on the same PCI slot */
363 for_each_pci_dev(companion) {
364 if (!usb_is_intel_switchable_xhci(companion))
365 continue;
366 usb_enable_xhci_ports(companion);
367 return;
368 }
369}
370
371static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
372{
373 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
374 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
375
376 /* The BIOS on systems with the Intel Panther Point chipset may or may
377 * not support xHCI natively. That means that during system resume, it
378 * may switch the ports back to EHCI so that users can use their
379 * keyboard to select a kernel from GRUB after resume from hibernate.
380 *
381 * The BIOS is supposed to remember whether the OS had xHCI ports
382 * enabled before resume, and switch the ports back to xHCI when the
383 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
384 * writers.
385 *
386 * Unconditionally switch the ports back to xHCI after a system resume.
387 * We can't tell whether the EHCI or xHCI controller will be resumed
388 * first, so we have to do the port switchover in both drivers. Writing
389 * a '1' to the port switchover registers should have no effect if the
390 * port was already switched over.
391 */
392 if (usb_is_intel_switchable_ehci(pdev))
393 ehci_enable_xhci_companion();
394
395 // maybe restore FLADJ
396
397 if (time_before(jiffies, ehci->next_statechange))
398 msleep(100);
399
400 /* Mark hardware accessible again as we are out of D3 state by now */
401 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
402
403 /* If CF is still set and we aren't resuming from hibernation
404 * then we maintained PCI Vaux power.
405 * Just undo the effect of ehci_pci_suspend().
406 */
407 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
408 !hibernated) {
409 int mask = INTR_MASK;
410
411 ehci_prepare_ports_for_controller_resume(ehci);
412 if (!hcd->self.root_hub->do_remote_wakeup)
413 mask &= ~STS_PCD;
414 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
415 ehci_readl(ehci, &ehci->regs->intr_enable);
416 return 0;
417 }
418
419 usb_root_hub_lost_power(hcd->self.root_hub);
420
421 /* Else reset, to cope with power loss or flush-to-storage
422 * style "resume" having let BIOS kick in during reboot.
423 */
424 (void) ehci_halt(ehci);
425 (void) ehci_reset(ehci);
426 (void) ehci_pci_reinit(ehci, pdev);
427
428 /* emptying the schedule aborts any urbs */
429 spin_lock_irq(&ehci->lock);
430 if (ehci->reclaim)
431 end_unlink_async(ehci);
432 ehci_work(ehci);
433 spin_unlock_irq(&ehci->lock);
434
435 ehci_writel(ehci, ehci->command, &ehci->regs->command);
436 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
437 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
438
439 /* here we "know" root ports should always stay powered */
440 ehci_port_power(ehci, 1);
441
442 hcd->state = HC_STATE_SUSPENDED;
443 return 0;
444}
445#endif
446
447static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
448{
449 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
450 int rc = 0;
451
452 if (!udev->parent) /* udev is root hub itself, impossible */
453 rc = -1;
454 /* we only support lpm device connected to root hub yet */
455 if (ehci->has_lpm && !udev->parent->parent) {
456 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
457 if (!rc)
458 rc = ehci_lpm_check(ehci, udev->portnum);
459 }
460 return rc;
461}
462
463static const struct hc_driver ehci_pci_hc_driver = {
464 .description = hcd_name,
465 .product_desc = "EHCI Host Controller",
466 .hcd_priv_size = sizeof(struct ehci_hcd),
467
468 /*
469 * generic hardware linkage
470 */
471 .irq = ehci_irq,
472 .flags = HCD_MEMORY | HCD_USB2,
473
474 /*
475 * basic lifecycle operations
476 */
477 .reset = ehci_pci_setup,
478 .start = ehci_run,
479#ifdef CONFIG_PM
480 .pci_suspend = ehci_pci_suspend,
481 .pci_resume = ehci_pci_resume,
482#endif
483 .stop = ehci_stop,
484 .shutdown = ehci_shutdown,
485
486 /*
487 * managing i/o requests and associated device resources
488 */
489 .urb_enqueue = ehci_urb_enqueue,
490 .urb_dequeue = ehci_urb_dequeue,
491 .endpoint_disable = ehci_endpoint_disable,
492 .endpoint_reset = ehci_endpoint_reset,
493
494 /*
495 * scheduling support
496 */
497 .get_frame_number = ehci_get_frame,
498
499 /*
500 * root hub support
501 */
502 .hub_status_data = ehci_hub_status_data,
503 .hub_control = ehci_hub_control,
504 .bus_suspend = ehci_bus_suspend,
505 .bus_resume = ehci_bus_resume,
506 .relinquish_port = ehci_relinquish_port,
507 .port_handed_over = ehci_port_handed_over,
508
509 /*
510 * call back when device connected and addressed
511 */
512 .update_device = ehci_update_device,
513
514 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
515};
516
517/*-------------------------------------------------------------------------*/
518
519/* PCI driver selection metadata; PCI hotplugging uses this */
520static const struct pci_device_id pci_ids [] = { {
521 /* handle any USB 2.0 EHCI controller */
522 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
523 .driver_data = (unsigned long) &ehci_pci_hc_driver,
524 },
525 { /* end: all zeroes */ }
526};
527MODULE_DEVICE_TABLE(pci, pci_ids);
528
529/* pci driver glue; this is a "new style" PCI driver module */
530static struct pci_driver ehci_pci_driver = {
531 .name = (char *) hcd_name,
532 .id_table = pci_ids,
533
534 .probe = usb_hcd_pci_probe,
535 .remove = usb_hcd_pci_remove,
536 .shutdown = usb_hcd_pci_shutdown,
537
538#ifdef CONFIG_PM_SLEEP
539 .driver = {
540 .pm = &usb_hcd_pci_pm_ops
541 },
542#endif
543};
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4 *
5 * Copyright (c) 2000-2004 by David Brownell
6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/usb.h>
12#include <linux/usb/hcd.h>
13
14#include "ehci.h"
15#include "pci-quirks.h"
16
17#define DRIVER_DESC "EHCI PCI platform driver"
18
19static const char hcd_name[] = "ehci-pci";
20
21/* defined here to avoid adding to pci_ids.h for single instance use */
22#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
23
24#define PCI_VENDOR_ID_ASPEED 0x1a03
25#define PCI_DEVICE_ID_ASPEED_EHCI 0x2603
26
27/*-------------------------------------------------------------------------*/
28#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
29static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
30{
31 return pdev->vendor == PCI_VENDOR_ID_INTEL &&
32 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
33}
34
35/*
36 * This is the list of PCI IDs for the devices that have EHCI USB class and
37 * specific drivers for that. One of the example is a ChipIdea device installed
38 * on some Intel MID platforms.
39 */
40static const struct pci_device_id bypass_pci_id_table[] = {
41 /* ChipIdea on Intel MID platform */
42 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
43 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
44 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
45 {}
46};
47
48static inline bool is_bypassed_id(struct pci_dev *pdev)
49{
50 return !!pci_match_id(bypass_pci_id_table, pdev);
51}
52
53/*
54 * 0x84 is the offset of in/out threshold register,
55 * and it is the same offset as the register of 'hostpc'.
56 */
57#define intel_quark_x1000_insnreg01 hostpc
58
59/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
60#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
61
62/* called after powerup, by probe or system-pm "wakeup" */
63static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
64{
65 int retval;
66
67 /* we expect static quirk code to handle the "extended capabilities"
68 * (currently just BIOS handoff) allowed starting with EHCI 0.96
69 */
70
71 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
72 retval = pci_set_mwi(pdev);
73 if (!retval)
74 ehci_dbg(ehci, "MWI active\n");
75
76 /* Reset the threshold limit */
77 if (is_intel_quark_x1000(pdev)) {
78 /*
79 * For the Intel QUARK X1000, raise the I/O threshold to the
80 * maximum usable value in order to improve performance.
81 */
82 ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
83 ehci->regs->intel_quark_x1000_insnreg01);
84 }
85
86 return 0;
87}
88
89/* called during probe() after chip reset completes */
90static int ehci_pci_setup(struct usb_hcd *hcd)
91{
92 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
93 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
94 u32 temp;
95 int retval;
96
97 ehci->caps = hcd->regs;
98
99 /*
100 * ehci_init() causes memory for DMA transfers to be
101 * allocated. Thus, any vendor-specific workarounds based on
102 * limiting the type of memory used for DMA transfers must
103 * happen before ehci_setup() is called.
104 *
105 * Most other workarounds can be done either before or after
106 * init and reset; they are located here too.
107 */
108 switch (pdev->vendor) {
109 case PCI_VENDOR_ID_TOSHIBA_2:
110 /* celleb's companion chip */
111 if (pdev->device == 0x01b5) {
112#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
113 ehci->big_endian_mmio = 1;
114#else
115 ehci_warn(ehci,
116 "unsupported big endian Toshiba quirk\n");
117#endif
118 }
119 break;
120 case PCI_VENDOR_ID_NVIDIA:
121 /* NVidia reports that certain chips don't handle
122 * QH, ITD, or SITD addresses above 2GB. (But TD,
123 * data buffer, and periodic schedule are normal.)
124 */
125 switch (pdev->device) {
126 case 0x003c: /* MCP04 */
127 case 0x005b: /* CK804 */
128 case 0x00d8: /* CK8 */
129 case 0x00e8: /* CK8S */
130 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31)) < 0)
131 ehci_warn(ehci, "can't enable NVidia "
132 "workaround for >2GB RAM\n");
133 break;
134
135 /* Some NForce2 chips have problems with selective suspend;
136 * fixed in newer silicon.
137 */
138 case 0x0068:
139 if (pdev->revision < 0xa4)
140 ehci->no_selective_suspend = 1;
141 break;
142 }
143 break;
144 case PCI_VENDOR_ID_INTEL:
145 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
146 hcd->has_tt = 1;
147 break;
148 case PCI_VENDOR_ID_TDI:
149 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
150 hcd->has_tt = 1;
151 break;
152 case PCI_VENDOR_ID_AMD:
153 /* AMD PLL quirk */
154 if (usb_amd_quirk_pll_check())
155 ehci->amd_pll_fix = 1;
156 /* AMD8111 EHCI doesn't work, according to AMD errata */
157 if (pdev->device == 0x7463) {
158 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
159 retval = -EIO;
160 goto done;
161 }
162
163 /*
164 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
165 * read/write memory space which does not belong to it when
166 * there is NULL pointer with T-bit set to 1 in the frame list
167 * table. To avoid the issue, the frame list link pointer
168 * should always contain a valid pointer to a inactive qh.
169 */
170 if (pdev->device == 0x7808) {
171 ehci->use_dummy_qh = 1;
172 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
173 }
174 break;
175 case PCI_VENDOR_ID_VIA:
176 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
177 u8 tmp;
178
179 /* The VT6212 defaults to a 1 usec EHCI sleep time which
180 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
181 * that sleep time use the conventional 10 usec.
182 */
183 pci_read_config_byte(pdev, 0x4b, &tmp);
184 if (tmp & 0x20)
185 break;
186 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
187 }
188 break;
189 case PCI_VENDOR_ID_ATI:
190 /* AMD PLL quirk */
191 if (usb_amd_quirk_pll_check())
192 ehci->amd_pll_fix = 1;
193
194 /*
195 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
196 * read/write memory space which does not belong to it when
197 * there is NULL pointer with T-bit set to 1 in the frame list
198 * table. To avoid the issue, the frame list link pointer
199 * should always contain a valid pointer to a inactive qh.
200 */
201 if (pdev->device == 0x4396) {
202 ehci->use_dummy_qh = 1;
203 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
204 }
205 /* SB600 and old version of SB700 have a bug in EHCI controller,
206 * which causes usb devices lose response in some cases.
207 */
208 if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
209 usb_amd_hang_symptom_quirk()) {
210 u8 tmp;
211 ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
212 pci_read_config_byte(pdev, 0x53, &tmp);
213 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
214 }
215 break;
216 case PCI_VENDOR_ID_NETMOS:
217 /* MosChip frame-index-register bug */
218 ehci_info(ehci, "applying MosChip frame-index workaround\n");
219 ehci->frame_index_bug = 1;
220 break;
221 case PCI_VENDOR_ID_HUAWEI:
222 /* Synopsys HC bug */
223 if (pdev->device == 0xa239) {
224 ehci_info(ehci, "applying Synopsys HC workaround\n");
225 ehci->has_synopsys_hc_bug = 1;
226 }
227 break;
228 case PCI_VENDOR_ID_ASPEED:
229 if (pdev->device == PCI_DEVICE_ID_ASPEED_EHCI) {
230 ehci_info(ehci, "applying Aspeed HC workaround\n");
231 ehci->is_aspeed = 1;
232 }
233 break;
234 case PCI_VENDOR_ID_ZHAOXIN:
235 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x90)
236 ehci->zx_wakeup_clear_needed = 1;
237 break;
238 }
239
240 /* optional debug port, normally in the first BAR */
241 temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
242 if (temp) {
243 pci_read_config_dword(pdev, temp, &temp);
244 temp >>= 16;
245 if (((temp >> 13) & 7) == 1) {
246 u32 hcs_params = ehci_readl(ehci,
247 &ehci->caps->hcs_params);
248
249 temp &= 0x1fff;
250 ehci->debug = hcd->regs + temp;
251 temp = ehci_readl(ehci, &ehci->debug->control);
252 ehci_info(ehci, "debug port %d%s\n",
253 HCS_DEBUG_PORT(hcs_params),
254 (temp & DBGP_ENABLED) ? " IN USE" : "");
255 if (!(temp & DBGP_ENABLED))
256 ehci->debug = NULL;
257 }
258 }
259
260 retval = ehci_setup(hcd);
261 if (retval)
262 return retval;
263
264 /* These workarounds need to be applied after ehci_setup() */
265 switch (pdev->vendor) {
266 case PCI_VENDOR_ID_NEC:
267 case PCI_VENDOR_ID_INTEL:
268 case PCI_VENDOR_ID_AMD:
269 ehci->need_io_watchdog = 0;
270 break;
271 case PCI_VENDOR_ID_NVIDIA:
272 switch (pdev->device) {
273 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
274 * fetching device descriptors unless LPM is disabled.
275 * There are also intermittent problems enumerating
276 * devices with PPCD enabled.
277 */
278 case 0x0d9d:
279 ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
280 ehci->has_ppcd = 0;
281 ehci->command &= ~CMD_PPCEE;
282 break;
283 }
284 break;
285 }
286
287 /* at least the Genesys GL880S needs fixup here */
288 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
289 temp &= 0x0f;
290 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
291 ehci_dbg(ehci, "bogus port configuration: "
292 "cc=%d x pcc=%d < ports=%d\n",
293 HCS_N_CC(ehci->hcs_params),
294 HCS_N_PCC(ehci->hcs_params),
295 HCS_N_PORTS(ehci->hcs_params));
296
297 switch (pdev->vendor) {
298 case 0x17a0: /* GENESYS */
299 /* GL880S: should be PORTS=2 */
300 temp |= (ehci->hcs_params & ~0xf);
301 ehci->hcs_params = temp;
302 break;
303 case PCI_VENDOR_ID_NVIDIA:
304 /* NF4: should be PCC=10 */
305 break;
306 }
307 }
308
309 /* Serial Bus Release Number is at PCI 0x60 offset */
310 if (pdev->vendor == PCI_VENDOR_ID_STMICRO
311 && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
312 ; /* ConneXT has no sbrn register */
313 else if (pdev->vendor == PCI_VENDOR_ID_HUAWEI
314 && pdev->device == 0xa239)
315 ; /* HUAWEI Kunpeng920 USB EHCI has no sbrn register */
316 else
317 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
318
319 /* Keep this around for a while just in case some EHCI
320 * implementation uses legacy PCI PM support. This test
321 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
322 * been triggered by then.
323 */
324 if (!device_can_wakeup(&pdev->dev)) {
325 u16 port_wake;
326
327 pci_read_config_word(pdev, 0x62, &port_wake);
328 if (port_wake & 0x0001) {
329 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
330 device_set_wakeup_capable(&pdev->dev, 1);
331 }
332 }
333
334#ifdef CONFIG_PM
335 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
336 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
337#endif
338
339 retval = ehci_pci_reinit(ehci, pdev);
340done:
341 return retval;
342}
343
344/*-------------------------------------------------------------------------*/
345
346#ifdef CONFIG_PM
347
348/* suspend/resume, section 4.3 */
349
350/* These routines rely on the PCI bus glue
351 * to handle powerdown and wakeup, and currently also on
352 * transceivers that don't need any software attention to set up
353 * the right sort of wakeup.
354 * Also they depend on separate root hub suspend/resume.
355 */
356
357static int ehci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
358{
359 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
360 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
361 bool hibernated = (msg.event == PM_EVENT_RESTORE);
362
363 if (ehci_resume(hcd, hibernated) != 0)
364 (void) ehci_pci_reinit(ehci, pdev);
365 return 0;
366}
367
368#else
369
370#define ehci_suspend NULL
371#define ehci_pci_resume NULL
372#endif /* CONFIG_PM */
373
374static struct hc_driver __read_mostly ehci_pci_hc_driver;
375
376static const struct ehci_driver_overrides pci_overrides __initconst = {
377 .reset = ehci_pci_setup,
378};
379
380/*-------------------------------------------------------------------------*/
381
382static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
383{
384 if (is_bypassed_id(pdev))
385 return -ENODEV;
386 return usb_hcd_pci_probe(pdev, &ehci_pci_hc_driver);
387}
388
389static void ehci_pci_remove(struct pci_dev *pdev)
390{
391 pci_clear_mwi(pdev);
392 usb_hcd_pci_remove(pdev);
393}
394
395/* PCI driver selection metadata; PCI hotplugging uses this */
396static const struct pci_device_id pci_ids [] = { {
397 /* handle any USB 2.0 EHCI controller */
398 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
399 }, {
400 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
401 },
402 { /* end: all zeroes */ }
403};
404MODULE_DEVICE_TABLE(pci, pci_ids);
405
406/* pci driver glue; this is a "new style" PCI driver module */
407static struct pci_driver ehci_pci_driver = {
408 .name = hcd_name,
409 .id_table = pci_ids,
410
411 .probe = ehci_pci_probe,
412 .remove = ehci_pci_remove,
413 .shutdown = usb_hcd_pci_shutdown,
414
415 .driver = {
416#ifdef CONFIG_PM
417 .pm = &usb_hcd_pci_pm_ops,
418#endif
419 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
420 },
421};
422
423static int __init ehci_pci_init(void)
424{
425 if (usb_disabled())
426 return -ENODEV;
427
428 ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
429
430 /* Entries for the PCI suspend/resume callbacks are special */
431 ehci_pci_hc_driver.pci_suspend = ehci_suspend;
432 ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
433
434 return pci_register_driver(&ehci_pci_driver);
435}
436module_init(ehci_pci_init);
437
438static void __exit ehci_pci_cleanup(void)
439{
440 pci_unregister_driver(&ehci_pci_driver);
441}
442module_exit(ehci_pci_cleanup);
443
444MODULE_DESCRIPTION(DRIVER_DESC);
445MODULE_AUTHOR("David Brownell");
446MODULE_AUTHOR("Alan Stern");
447MODULE_LICENSE("GPL");