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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright 2017-2023 Broadcom Inc. All rights reserved.
4 */
5#ifndef MPI30_CNFG_H
6#define MPI30_CNFG_H 1
7#define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00)
8#define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01)
9#define MPI3_CONFIG_PAGETYPE_IOC (0x02)
10#define MPI3_CONFIG_PAGETYPE_DRIVER (0x03)
11#define MPI3_CONFIG_PAGETYPE_SECURITY (0x04)
12#define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11)
13#define MPI3_CONFIG_PAGETYPE_DEVICE (0x12)
14#define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20)
15#define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21)
16#define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23)
17#define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24)
18#define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30)
19#define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31)
20#define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33)
21#define MPI3_CONFIG_PAGEATTR_MASK (0xf0)
22#define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00)
23#define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10)
24#define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20)
25#define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00)
26#define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01)
27#define MPI3_CONFIG_ACTION_READ_CURRENT (0x02)
28#define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03)
29#define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04)
30#define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05)
31#define MPI3_DEVICE_PGAD_FORM_MASK (0xf0000000)
32#define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
33#define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000)
34#define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000ffff)
35#define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xf0000000)
36#define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
37#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000)
38#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000)
39#define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00ff0000)
40#define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
41#define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000ffff)
42#define MPI3_SAS_PHY_PGAD_FORM_MASK (0xf0000000)
43#define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
44#define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000ff)
45#define MPI3_SASPORT_PGAD_FORM_MASK (0xf0000000)
46#define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
47#define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
48#define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000ff)
49#define MPI3_ENCLOS_PGAD_FORM_MASK (0xf0000000)
50#define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
51#define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
52#define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000ffff)
53#define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xf0000000)
54#define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
55#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000)
56#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000)
57#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00ff0000)
58#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16)
59#define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000ffff)
60#define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xf0000000)
61#define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000)
62#define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000)
63#define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000ff)
64#define MPI3_SECURITY_PGAD_FORM_MASK (0xf0000000)
65#define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000)
66#define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000)
67#define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000ff00)
68#define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8)
69#define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000ff)
70#define MPI3_INSTANCE_PGAD_INSTANCE_MASK (0x0000ffff)
71struct mpi3_config_request {
72 __le16 host_tag;
73 u8 ioc_use_only02;
74 u8 function;
75 __le16 ioc_use_only04;
76 u8 ioc_use_only06;
77 u8 msg_flags;
78 __le16 change_count;
79 u8 proxy_ioc_number;
80 u8 reserved0b;
81 u8 page_version;
82 u8 page_number;
83 u8 page_type;
84 u8 action;
85 __le32 page_address;
86 __le16 page_length;
87 __le16 reserved16;
88 __le32 reserved18[2];
89 union mpi3_sge_union sgl;
90};
91
92struct mpi3_config_page_header {
93 u8 page_version;
94 u8 reserved01;
95 u8 page_number;
96 u8 page_attribute;
97 __le16 page_length;
98 u8 page_type;
99 u8 reserved07;
100};
101
102#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xf0)
103#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4)
104#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0f)
105#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0)
106#define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
107#define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
108#define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
109#define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
110#define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
111#define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
112#define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
113#define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08)
114#define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09)
115#define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0a)
116#define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0b)
117#define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0c)
118#define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
119#define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
120#define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
121#define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000f)
122#define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
123#define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
124#define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
125#define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
126#define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
127#define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
128#define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
129#define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
130#define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
131#define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009)
132#define MPI3_SAS_PHYINFO_STATUS_MASK (0xc0000000)
133#define MPI3_SAS_PHYINFO_STATUS_SHIFT (30)
134#define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000)
135#define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000)
136#define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000)
137#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
138#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000)
139#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000)
140#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000)
141#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000)
142#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26)
143#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000)
144#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25)
145#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000)
146#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24)
147#define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
148#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000)
149#define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
150#define MPI3_SAS_PHYINFO_REASON_MASK (0x000f0000)
151#define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
152#define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
153#define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
154#define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
155#define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
156#define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
157#define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
158#define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
159#define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
160#define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000)
161#define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
162#define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
163#define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
164#define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000f00)
165#define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8)
166#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000f0)
167#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000)
168#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010)
169#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020)
170#define MPI3_SAS_PRATE_MAX_RATE_MASK (0xf0)
171#define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
172#define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80)
173#define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90)
174#define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xa0)
175#define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xb0)
176#define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xc0)
177#define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0f)
178#define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
179#define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08)
180#define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09)
181#define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0a)
182#define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0b)
183#define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0c)
184#define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xf0)
185#define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80)
186#define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90)
187#define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xa0)
188#define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xb0)
189#define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xc0)
190#define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0f)
191#define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08)
192#define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09)
193#define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0a)
194#define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0b)
195#define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0c)
196#define MPI3_SLOT_INVALID (0xffff)
197#define MPI3_SLOT_INDEX_INVALID (0xffff)
198#define MPI3_LINK_CHANGE_COUNT_INVALID (0xffff)
199#define MPI3_RATE_CHANGE_COUNT_INVALID (0xffff)
200#define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0)
201#define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1)
202#define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2)
203#define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3)
204#define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000)
205#define MPI3_MFGPAGE_DEVID_SAS4116 (0x00a5)
206#define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00b3)
207#define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00b4)
208#define MPI3_MFGPAGE_DEVID_SAS5116_MPI_MGMT (0x00b5)
209#define MPI3_MFGPAGE_DEVID_SAS5116_NVME_MGMT (0x00b6)
210#define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00b8)
211#define MPI3_MFGPAGE_DEVID_SAS5248_MPI (0x00f0)
212#define MPI3_MFGPAGE_DEVID_SAS5248_MPI_NS (0x00f1)
213#define MPI3_MFGPAGE_DEVID_SAS5248_PCIE_SWITCH (0x00f2)
214struct mpi3_man_page0 {
215 struct mpi3_config_page_header header;
216 u8 chip_revision[8];
217 u8 chip_name[32];
218 u8 board_name[32];
219 u8 board_assembly[32];
220 u8 board_tracer_number[32];
221 __le32 board_power;
222 __le32 reserved94;
223 __le32 reserved98;
224 u8 oem;
225 u8 profile_identifier;
226 __le16 flags;
227 u8 board_mfg_day;
228 u8 board_mfg_month;
229 __le16 board_mfg_year;
230 u8 board_rework_day;
231 u8 board_rework_month;
232 __le16 board_rework_year;
233 u8 board_revision[8];
234 u8 e_pack_fru[16];
235 u8 product_name[256];
236};
237
238#define MPI3_MAN0_PAGEVERSION (0x00)
239#define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002)
240#define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001)
241#define MPI3_MAN1_VPD_SIZE (512)
242struct mpi3_man_page1 {
243 struct mpi3_config_page_header header;
244 __le32 reserved08[2];
245 u8 vpd[MPI3_MAN1_VPD_SIZE];
246};
247
248#define MPI3_MAN1_PAGEVERSION (0x00)
249struct mpi3_man_page2 {
250 struct mpi3_config_page_header header;
251 u8 flags;
252 u8 reserved09[3];
253 __le32 reserved0c[3];
254 u8 oem_board_tracer_number[32];
255};
256#define MPI3_MAN2_PAGEVERSION (0x00)
257#define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01)
258struct mpi3_man5_phy_entry {
259 __le64 ioc_wwid;
260 __le64 device_name;
261 __le64 sata_wwid;
262};
263
264#ifndef MPI3_MAN5_PHY_MAX
265#define MPI3_MAN5_PHY_MAX (1)
266#endif
267struct mpi3_man_page5 {
268 struct mpi3_config_page_header header;
269 u8 num_phys;
270 u8 reserved09[3];
271 __le32 reserved0c;
272 struct mpi3_man5_phy_entry phy[MPI3_MAN5_PHY_MAX];
273};
274
275#define MPI3_MAN5_PAGEVERSION (0x00)
276struct mpi3_man6_gpio_entry {
277 u8 function_code;
278 u8 function_flags;
279 __le16 flags;
280 u8 param1;
281 u8 param2;
282 __le16 reserved06;
283 __le32 param3;
284};
285
286#define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00)
287#define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01)
288#define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02)
289#define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03)
290#define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04)
291#define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05)
292#define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06)
293#define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07)
294#define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08)
295#define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0a)
296#define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0b)
297#define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0c)
298#define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0d)
299#define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0e)
300#define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0f)
301#define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10)
302#define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11)
303#define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12)
304#define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13)
305#define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14)
306#define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15)
307#define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16)
308#define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17)
309#define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18)
310#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01)
311#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00)
312#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01)
313#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xf0)
314#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00)
315#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10)
316#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20)
317#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02)
318#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01)
319#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00)
320#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01)
321#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00)
322#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01)
323#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00)
324#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01)
325#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02)
326#define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00)
327#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100)
328#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100)
329#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000)
330#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00c0)
331#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000)
332#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040)
333#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080)
334#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00c0)
335#define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030)
336#define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4)
337#define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008)
338#define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004)
339#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003)
340#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000)
341#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001)
342#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002)
343#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003)
344#ifndef MPI3_MAN6_GPIO_MAX
345#define MPI3_MAN6_GPIO_MAX (1)
346#endif
347struct mpi3_man_page6 {
348 struct mpi3_config_page_header header;
349 __le16 flags;
350 __le16 reserved0a;
351 u8 num_gpio;
352 u8 reserved0d[3];
353 struct mpi3_man6_gpio_entry gpio[MPI3_MAN6_GPIO_MAX];
354};
355
356#define MPI3_MAN6_PAGEVERSION (0x00)
357#define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001)
358struct mpi3_man7_receptacle_info {
359 __le32 name[4];
360 u8 location;
361 u8 connector_type;
362 u8 ped_clk;
363 u8 connector_id;
364 __le32 reserved14;
365};
366
367#define MPI3_MAN7_LOCATION_UNKNOWN (0x00)
368#define MPI3_MAN7_LOCATION_INTERNAL (0x01)
369#define MPI3_MAN7_LOCATION_EXTERNAL (0x02)
370#define MPI3_MAN7_LOCATION_VIRTUAL (0x03)
371#define MPI3_MAN7_LOCATION_HOST (0x04)
372#define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00)
373#define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10)
374#define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00)
375#define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10)
376#define MPI3_MAN7_PEDCLK_ID_MASK (0x0f)
377#ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX
378#define MPI3_MAN7_RECEPTACLE_INFO_MAX (1)
379#endif
380struct mpi3_man_page7 {
381 struct mpi3_config_page_header header;
382 __le32 flags;
383 u8 num_receptacles;
384 u8 reserved0d[3];
385 __le32 enclosure_name[4];
386 struct mpi3_man7_receptacle_info receptacle_info[MPI3_MAN7_RECEPTACLE_INFO_MAX];
387};
388
389#define MPI3_MAN7_PAGEVERSION (0x00)
390#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01)
391#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00)
392#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01)
393struct mpi3_man8_phy_info {
394 u8 receptacle_id;
395 u8 connector_lane;
396 __le16 reserved02;
397 __le16 slotx1;
398 __le16 slotx2;
399 __le16 slotx4;
400 __le16 reserved0a;
401 __le32 reserved0c;
402};
403
404#define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xff)
405#define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xff)
406#ifndef MPI3_MAN8_PHY_INFO_MAX
407#define MPI3_MAN8_PHY_INFO_MAX (1)
408#endif
409struct mpi3_man_page8 {
410 struct mpi3_config_page_header header;
411 __le32 reserved08;
412 u8 num_phys;
413 u8 reserved0d[3];
414 struct mpi3_man8_phy_info phy_info[MPI3_MAN8_PHY_INFO_MAX];
415};
416
417#define MPI3_MAN8_PAGEVERSION (0x00)
418struct mpi3_man9_rsrc_entry {
419 __le32 maximum;
420 __le32 decrement;
421 __le32 minimum;
422 __le32 actual;
423};
424
425enum mpi3_man9_resources {
426 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0,
427 MPI3_MAN9_RSRC_TARGET_CMDS = 1,
428 MPI3_MAN9_RSRC_RESERVED02 = 2,
429 MPI3_MAN9_RSRC_NVME = 3,
430 MPI3_MAN9_RSRC_INITIATORS = 4,
431 MPI3_MAN9_RSRC_VDS = 5,
432 MPI3_MAN9_RSRC_ENCLOSURES = 6,
433 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7,
434 MPI3_MAN9_RSRC_EXPANDERS = 8,
435 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9,
436 MPI3_MAN9_RSRC_RESERVED10 = 10,
437 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11,
438 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12,
439 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13,
440 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14,
441 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15,
442 MPI3_MAN9_RSRC_NUM_RESOURCES
443};
444
445#define MPI3_MAN9_MIN_OUTSTANDING_REQS (1)
446#define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000)
447#define MPI3_MAN9_MIN_TARGET_CMDS (0)
448#define MPI3_MAN9_MAX_TARGET_CMDS (65535)
449#define MPI3_MAN9_MIN_NVME_TARGETS (0)
450#define MPI3_MAN9_MIN_INITIATORS (0)
451#define MPI3_MAN9_MIN_VDS (0)
452#define MPI3_MAN9_MIN_ENCLOSURES (1)
453#define MPI3_MAN9_MAX_ENCLOSURES (65535)
454#define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0)
455#define MPI3_MAN9_MIN_EXPANDERS (0)
456#define MPI3_MAN9_MAX_EXPANDERS (65535)
457#define MPI3_MAN9_MIN_PCIE_SWITCHES (0)
458#define MPI3_MAN9_MIN_HOST_PD_DRIVES (0)
459#define MPI3_MAN9_ADV_HOST_PD_DRIVES (0)
460#define MPI3_MAN9_RAID_PD_DRIVES (0)
461#define MPI3_MAN9_DRIVER_DIAG_BUFFER (0)
462#define MPI3_MAN9_MIN_NAMESPACE_COUNT (1)
463#define MPI3_MAN9_MIN_EXPANDERS (0)
464#define MPI3_MAN9_MAX_EXPANDERS (65535)
465struct mpi3_man_page9 {
466 struct mpi3_config_page_header header;
467 u8 num_resources;
468 u8 reserved09;
469 __le16 reserved0a;
470 __le32 reserved0c;
471 __le32 reserved10;
472 __le32 reserved14;
473 __le32 reserved18;
474 __le32 reserved1c;
475 struct mpi3_man9_rsrc_entry resource[MPI3_MAN9_RSRC_NUM_RESOURCES];
476};
477
478#define MPI3_MAN9_PAGEVERSION (0x00)
479struct mpi3_man10_istwi_ctrlr_entry {
480 __le16 target_address;
481 __le16 flags;
482 u8 scl_low_override;
483 u8 scl_high_override;
484 __le16 reserved06;
485};
486
487#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000c)
488#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100K (0x0000)
489#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400K (0x0004)
490#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002)
491#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001)
492#ifndef MPI3_MAN10_ISTWI_CTRLR_MAX
493#define MPI3_MAN10_ISTWI_CTRLR_MAX (1)
494#endif
495struct mpi3_man_page10 {
496 struct mpi3_config_page_header header;
497 __le32 reserved08;
498 u8 num_istwi_ctrl;
499 u8 reserved0d[3];
500 struct mpi3_man10_istwi_ctrlr_entry istwi_controller[MPI3_MAN10_ISTWI_CTRLR_MAX];
501};
502
503#define MPI3_MAN10_PAGEVERSION (0x00)
504struct mpi3_man11_mux_device_format {
505 u8 max_channel;
506 u8 reserved01[3];
507 __le32 reserved04;
508};
509
510struct mpi3_man11_temp_sensor_device_format {
511 u8 type;
512 u8 reserved01[3];
513 u8 temp_channel[4];
514};
515
516#define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00)
517#define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01)
518#define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02)
519#define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03)
520#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xe0)
521#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5)
522#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01)
523struct mpi3_man11_seeprom_device_format {
524 u8 size;
525 u8 page_write_size;
526 __le16 reserved02;
527 __le32 reserved04;
528};
529
530#define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01)
531#define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02)
532#define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03)
533#define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04)
534#define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05)
535#define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06)
536#define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07)
537#define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08)
538struct mpi3_man11_ddr_spd_device_format {
539 u8 channel;
540 u8 reserved01[3];
541 __le32 reserved04;
542};
543
544struct mpi3_man11_cable_mgmt_device_format {
545 u8 type;
546 u8 receptacle_id;
547 __le16 reserved02;
548 __le32 reserved04;
549};
550
551#define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00)
552struct mpi3_man11_bkplane_spec_ubm_format {
553 __le16 flags;
554 __le16 reserved02;
555};
556
557#define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200)
558#define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100)
559#define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00f0)
560#define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4)
561#define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f)
562#define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0)
563struct mpi3_man11_bkplane_spec_non_ubm_format {
564 __le16 flags;
565 u8 reserved02;
566 u8 type;
567};
568
569#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xf000)
570#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12)
571#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200)
572#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00c0)
573#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000)
574#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040)
575#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080)
576#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030)
577#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000)
578#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010)
579#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000f)
580#define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0)
581#define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00)
582union mpi3_man11_bkplane_spec_format {
583 struct mpi3_man11_bkplane_spec_ubm_format ubm;
584 struct mpi3_man11_bkplane_spec_non_ubm_format non_ubm;
585};
586
587struct mpi3_man11_bkplane_mgmt_device_format {
588 u8 type;
589 u8 receptacle_id;
590 u8 reset_info;
591 u8 reserved03;
592 union mpi3_man11_bkplane_spec_format backplane_mgmt_specific;
593};
594
595#define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00)
596#define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01)
597#define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xf0)
598#define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4)
599#define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0f)
600#define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0)
601struct mpi3_man11_gas_gauge_device_format {
602 u8 type;
603 u8 reserved01[3];
604 __le32 reserved04;
605};
606
607#define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00)
608struct mpi3_man11_mgmt_ctrlr_device_format {
609 __le32 reserved00;
610 __le32 reserved04;
611};
612struct mpi3_man11_board_fan_device_format {
613 u8 flags;
614 u8 reserved01;
615 u8 min_fan_speed;
616 u8 max_fan_speed;
617 __le32 reserved04;
618};
619#define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07)
620#define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00)
621union mpi3_man11_device_specific_format {
622 struct mpi3_man11_mux_device_format mux;
623 struct mpi3_man11_temp_sensor_device_format temp_sensor;
624 struct mpi3_man11_seeprom_device_format seeprom;
625 struct mpi3_man11_ddr_spd_device_format ddr_spd;
626 struct mpi3_man11_cable_mgmt_device_format cable_mgmt;
627 struct mpi3_man11_bkplane_mgmt_device_format bkplane_mgmt;
628 struct mpi3_man11_gas_gauge_device_format gas_gauge;
629 struct mpi3_man11_mgmt_ctrlr_device_format mgmt_controller;
630 struct mpi3_man11_board_fan_device_format board_fan;
631 __le32 words[2];
632};
633struct mpi3_man11_istwi_device_format {
634 u8 device_type;
635 u8 controller;
636 u8 reserved02;
637 u8 flags;
638 __le16 device_address;
639 u8 mux_channel;
640 u8 mux_index;
641 union mpi3_man11_device_specific_format device_specific;
642};
643
644#define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00)
645#define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01)
646#define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02)
647#define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03)
648#define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04)
649#define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05)
650#define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06)
651#define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07)
652#define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08)
653#define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01)
654#ifndef MPI3_MAN11_ISTWI_DEVICE_MAX
655#define MPI3_MAN11_ISTWI_DEVICE_MAX (1)
656#endif
657struct mpi3_man_page11 {
658 struct mpi3_config_page_header header;
659 __le32 reserved08;
660 u8 num_istwi_dev;
661 u8 reserved0d[3];
662 struct mpi3_man11_istwi_device_format istwi_device[MPI3_MAN11_ISTWI_DEVICE_MAX];
663};
664
665#define MPI3_MAN11_PAGEVERSION (0x00)
666#ifndef MPI3_MAN12_NUM_SGPIO_MAX
667#define MPI3_MAN12_NUM_SGPIO_MAX (1)
668#endif
669struct mpi3_man12_sgpio_info {
670 u8 slot_count;
671 u8 reserved01[3];
672 __le32 reserved04;
673 u8 phy_order[32];
674};
675
676struct mpi3_man_page12 {
677 struct mpi3_config_page_header header;
678 __le32 flags;
679 __le32 s_clock_freq;
680 __le32 activity_modulation;
681 u8 num_sgpio;
682 u8 reserved15[3];
683 __le32 reserved18;
684 __le32 reserved1c;
685 __le32 pattern[8];
686 struct mpi3_man12_sgpio_info sgpio_info[MPI3_MAN12_NUM_SGPIO_MAX];
687};
688
689#define MPI3_MAN12_PAGEVERSION (0x00)
690#define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400)
691#define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200)
692#define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100)
693#define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004)
694#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002)
695#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000)
696#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002)
697#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001)
698#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000)
699#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001)
700#define MPI3_MAN12_SIO_CLK_FREQ_MIN (32)
701#define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000)
702#define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000f000)
703#define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12)
704#define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000f00)
705#define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8)
706#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000f0)
707#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4)
708#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000f)
709#define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0)
710#define MPI3_MAN12_PATTERN_RATE_MASK (0xe0000000)
711#define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000)
712#define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000)
713#define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000)
714#define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000)
715#define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000)
716#define MPI3_MAN12_PATTERN_RATE_20_HZ (0xa0000000)
717#define MPI3_MAN12_PATTERN_RATE_40_HZ (0xc0000000)
718#define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1f000000)
719#define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24)
720#define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00ffffff)
721#define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0)
722#ifndef MPI3_MAN13_NUM_TRANSLATION_MAX
723#define MPI3_MAN13_NUM_TRANSLATION_MAX (1)
724#endif
725struct mpi3_man13_translation_info {
726 __le32 slot_status;
727 __le32 mask;
728 u8 activity;
729 u8 locate;
730 u8 error;
731 u8 reserved0b;
732};
733
734#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000)
735#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000)
736#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000)
737#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000)
738#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000)
739#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000)
740#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000)
741#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000)
742#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000)
743#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000)
744#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000)
745#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000)
746#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800)
747#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400)
748#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200)
749#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100)
750#define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040)
751#define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00)
752#define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01)
753#define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02)
754#define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03)
755#define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04)
756#define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05)
757#define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06)
758#define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07)
759#define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08)
760#define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09)
761#define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0a)
762#define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0b)
763struct mpi3_man_page13 {
764 struct mpi3_config_page_header header;
765 u8 num_trans;
766 u8 reserved09[3];
767 __le32 reserved0c;
768 struct mpi3_man13_translation_info translation[MPI3_MAN13_NUM_TRANSLATION_MAX];
769};
770
771#define MPI3_MAN13_PAGEVERSION (0x00)
772struct mpi3_man_page14 {
773 struct mpi3_config_page_header header;
774 __le32 reserved08;
775 u8 num_slot_groups;
776 u8 num_slots;
777 __le16 max_cert_chain_length;
778 __le32 sealed_slots;
779 __le32 populated_slots;
780 __le32 mgmt_pt_updatable_slots;
781};
782#define MPI3_MAN14_PAGEVERSION (0x00)
783#define MPI3_MAN14_NUMSLOTS_MAX (32)
784#ifndef MPI3_MAN15_VERSION_RECORD_MAX
785#define MPI3_MAN15_VERSION_RECORD_MAX 1
786#endif
787struct mpi3_man15_version_record {
788 __le16 spdm_version;
789 __le16 reserved02;
790};
791
792struct mpi3_man_page15 {
793 struct mpi3_config_page_header header;
794 u8 num_version_records;
795 u8 reserved09[3];
796 __le32 reserved0c;
797 struct mpi3_man15_version_record version_record[MPI3_MAN15_VERSION_RECORD_MAX];
798};
799
800#define MPI3_MAN15_PAGEVERSION (0x00)
801#ifndef MPI3_MAN16_CERT_ALGO_MAX
802#define MPI3_MAN16_CERT_ALGO_MAX 1
803#endif
804struct mpi3_man16_certificate_algorithm {
805 u8 slot_group;
806 u8 reserved01[3];
807 __le32 base_asym_algo;
808 __le32 base_hash_algo;
809 __le32 reserved0c[3];
810};
811
812struct mpi3_man_page16 {
813 struct mpi3_config_page_header header;
814 __le32 reserved08;
815 u8 num_cert_algos;
816 u8 reserved0d[3];
817 struct mpi3_man16_certificate_algorithm certificate_algorithm[MPI3_MAN16_CERT_ALGO_MAX];
818};
819
820#define MPI3_MAN16_PAGEVERSION (0x00)
821#ifndef MPI3_MAN17_HASH_ALGORITHM_MAX
822#define MPI3_MAN17_HASH_ALGORITHM_MAX 1
823#endif
824struct mpi3_man17_hash_algorithm {
825 u8 meas_specification;
826 u8 reserved01[3];
827 __le32 measurement_hash_algo;
828 __le32 reserved08[2];
829};
830
831struct mpi3_man_page17 {
832 struct mpi3_config_page_header header;
833 __le32 reserved08;
834 u8 num_hash_algos;
835 u8 reserved0d[3];
836 struct mpi3_man17_hash_algorithm hash_algorithm[MPI3_MAN17_HASH_ALGORITHM_MAX];
837};
838
839#define MPI3_MAN17_PAGEVERSION (0x00)
840struct mpi3_man_page20 {
841 struct mpi3_config_page_header header;
842 __le32 reserved08;
843 __le32 nonpremium_features;
844 u8 allowed_personalities;
845 u8 reserved11[3];
846};
847
848#define MPI3_MAN20_PAGEVERSION (0x00)
849#define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02)
850#define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02)
851#define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00)
852#define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01)
853#define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01)
854#define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00)
855#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01)
856#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00)
857#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01)
858struct mpi3_man_page21 {
859 struct mpi3_config_page_header header;
860 __le32 reserved08;
861 __le32 flags;
862};
863
864#define MPI3_MAN21_PAGEVERSION (0x00)
865#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060)
866#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000)
867#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020)
868#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040)
869#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008)
870#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000)
871#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008)
872#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001)
873#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000)
874#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001)
875#ifndef MPI3_MAN_PROD_SPECIFIC_MAX
876#define MPI3_MAN_PROD_SPECIFIC_MAX (1)
877#endif
878struct mpi3_man_page_product_specific {
879 struct mpi3_config_page_header header;
880 __le32 product_specific_info[MPI3_MAN_PROD_SPECIFIC_MAX];
881};
882
883struct mpi3_io_unit_page0 {
884 struct mpi3_config_page_header header;
885 __le64 unique_value;
886 __le32 nvdata_version_default;
887 __le32 nvdata_version_persistent;
888};
889
890#define MPI3_IOUNIT0_PAGEVERSION (0x00)
891struct mpi3_io_unit_page1 {
892 struct mpi3_config_page_header header;
893 __le32 flags;
894 u8 dmd_io_delay;
895 u8 dmd_report_pcie;
896 u8 dmd_report_sata;
897 u8 dmd_report_sas;
898};
899
900#define MPI3_IOUNIT1_PAGEVERSION (0x00)
901#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030)
902#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000)
903#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010)
904#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020)
905#define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008)
906#define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004)
907#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003)
908#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000)
909#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001)
910#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002)
911#define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7f)
912#define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80)
913#ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX
914#define MPI3_IO_UNIT2_GPIO_VAL_MAX (1)
915#endif
916struct mpi3_io_unit_page2 {
917 struct mpi3_config_page_header header;
918 u8 gpio_count;
919 u8 reserved09[3];
920 __le16 gpio_val[MPI3_IO_UNIT2_GPIO_VAL_MAX];
921};
922
923#define MPI3_IOUNIT2_PAGEVERSION (0x00)
924#define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xfffc)
925#define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2)
926#define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001)
927#define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000)
928#define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001)
929struct mpi3_io_unit3_sensor {
930 __le16 flags;
931 u8 threshold_margin;
932 u8 reserved03;
933 __le16 threshold[3];
934 __le16 reserved0a;
935 __le32 reserved0c;
936 __le32 reserved10;
937 __le32 reserved14;
938};
939
940#define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010)
941#define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008)
942#define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004)
943#define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002)
944#define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001)
945#ifndef MPI3_IO_UNIT3_SENSOR_MAX
946#define MPI3_IO_UNIT3_SENSOR_MAX (1)
947#endif
948struct mpi3_io_unit_page3 {
949 struct mpi3_config_page_header header;
950 __le32 reserved08;
951 u8 num_sensors;
952 u8 nominal_poll_interval;
953 u8 warning_poll_interval;
954 u8 reserved0f;
955 struct mpi3_io_unit3_sensor sensor[MPI3_IO_UNIT3_SENSOR_MAX];
956};
957
958#define MPI3_IOUNIT3_PAGEVERSION (0x00)
959struct mpi3_io_unit4_sensor {
960 __le16 current_temperature;
961 __le16 reserved02;
962 u8 flags;
963 u8 reserved05[3];
964 __le16 istwi_index;
965 u8 channel;
966 u8 reserved0b;
967 __le32 reserved0c;
968};
969
970#define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xe0)
971#define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5)
972#define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01)
973#define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xffff)
974#define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xff)
975#ifndef MPI3_IO_UNIT4_SENSOR_MAX
976#define MPI3_IO_UNIT4_SENSOR_MAX (1)
977#endif
978struct mpi3_io_unit_page4 {
979 struct mpi3_config_page_header header;
980 __le32 reserved08;
981 u8 num_sensors;
982 u8 reserved0d[3];
983 struct mpi3_io_unit4_sensor sensor[MPI3_IO_UNIT4_SENSOR_MAX];
984};
985
986#define MPI3_IOUNIT4_PAGEVERSION (0x00)
987struct mpi3_io_unit5_spinup_group {
988 u8 max_target_spinup;
989 u8 spinup_delay;
990 u8 spinup_flags;
991 u8 reserved03;
992};
993
994#define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01)
995#ifndef MPI3_IO_UNIT5_PHY_MAX
996#define MPI3_IO_UNIT5_PHY_MAX (4)
997#endif
998struct mpi3_io_unit_page5 {
999 struct mpi3_config_page_header header;
1000 struct mpi3_io_unit5_spinup_group spinup_group_parameters[4];
1001 __le32 reserved18;
1002 __le32 reserved1c;
1003 __le16 device_shutdown;
1004 __le16 reserved22;
1005 u8 pcie_device_wait_time;
1006 u8 sata_device_wait_time;
1007 u8 spinup_encl_drive_count;
1008 u8 spinup_encl_delay;
1009 u8 num_phys;
1010 u8 pe_initial_spinup_delay;
1011 u8 topology_stable_time;
1012 u8 flags;
1013 u8 phy[MPI3_IO_UNIT5_PHY_MAX];
1014};
1015
1016#define MPI3_IOUNIT5_PAGEVERSION (0x00)
1017#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00)
1018#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01)
1019#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02)
1020#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02)
1021#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03)
1022#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03)
1023#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300)
1024#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8)
1025#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00c0)
1026#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6)
1027#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030)
1028#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4)
1029#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000c)
1030#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2)
1031#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003)
1032#define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0)
1033#define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0c)
1034#define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00)
1035#define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04)
1036#define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08)
1037#define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0c)
1038#define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02)
1039#define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01)
1040#define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03)
1041struct mpi3_io_unit_page6 {
1042 struct mpi3_config_page_header header;
1043 __le32 board_power_requirement;
1044 __le32 pci_slot_power_allocation;
1045 u8 flags;
1046 u8 reserved11[3];
1047};
1048
1049#define MPI3_IOUNIT6_PAGEVERSION (0x00)
1050#define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01)
1051#ifndef MPI3_IOUNIT8_DIGEST_MAX
1052#define MPI3_IOUNIT8_DIGEST_MAX (1)
1053#endif
1054union mpi3_iounit8_digest {
1055 __le32 dword[16];
1056 __le16 word[32];
1057 u8 byte[64];
1058};
1059
1060struct mpi3_io_unit_page8 {
1061 struct mpi3_config_page_header header;
1062 u8 sb_mode;
1063 u8 sb_state;
1064 __le16 reserved0a;
1065 u8 num_slots;
1066 u8 slots_available;
1067 u8 current_key_encryption_algo;
1068 u8 key_digest_hash_algo;
1069 union mpi3_version_union current_svn;
1070 __le32 reserved14;
1071 __le32 current_key[128];
1072 union mpi3_iounit8_digest digest[MPI3_IOUNIT8_DIGEST_MAX];
1073};
1074
1075#define MPI3_IOUNIT8_PAGEVERSION (0x00)
1076#define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04)
1077#define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02)
1078#define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01)
1079#define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04)
1080#define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02)
1081#define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01)
1082#define MPI3_IOUNIT8_SBMODE_CURRENT_KEY_IOUNIT17 (0x10)
1083#define MPI3_IOUNIT8_SBMODE_HARD_SECURE_RECERTIFIED (0x08)
1084struct mpi3_io_unit_page9 {
1085 struct mpi3_config_page_header header;
1086 __le32 flags;
1087 __le16 first_device;
1088 __le16 reserved0e;
1089};
1090
1091#define MPI3_IOUNIT9_PAGEVERSION (0x00)
1092#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006)
1093#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1)
1094#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000)
1095#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002)
1096#define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004)
1097#define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001)
1098#define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xffff)
1099#define MPI3_IOUNIT9_FIRSTDEVICE_IN_DRIVER_PAGE_0 (0xfffe)
1100
1101struct mpi3_io_unit_page10 {
1102 struct mpi3_config_page_header header;
1103 u8 flags;
1104 u8 reserved09[3];
1105 __le32 silicon_id;
1106 u8 fw_version_minor;
1107 u8 fw_version_major;
1108 u8 hw_version_minor;
1109 u8 hw_version_major;
1110 u8 part_number[16];
1111};
1112#define MPI3_IOUNIT10_PAGEVERSION (0x00)
1113#define MPI3_IOUNIT10_FLAGS_VALID (0x01)
1114#define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02)
1115#define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00)
1116#define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02)
1117#define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80)
1118#ifndef MPI3_IOUNIT11_PROFILE_MAX
1119#define MPI3_IOUNIT11_PROFILE_MAX (1)
1120#endif
1121struct mpi3_iounit11_profile {
1122 u8 profile_identifier;
1123 u8 reserved01[3];
1124 __le16 max_vds;
1125 __le16 max_host_pds;
1126 __le16 max_adv_host_pds;
1127 __le16 max_raid_pds;
1128 __le16 max_nvme;
1129 __le16 max_outstanding_requests;
1130 __le16 subsystem_id;
1131 __le16 reserved12;
1132 __le32 reserved14[2];
1133};
1134struct mpi3_io_unit_page11 {
1135 struct mpi3_config_page_header header;
1136 __le32 reserved08;
1137 u8 num_profiles;
1138 u8 current_profile_identifier;
1139 __le16 reserved0e;
1140 struct mpi3_iounit11_profile profile[MPI3_IOUNIT11_PROFILE_MAX];
1141};
1142#define MPI3_IOUNIT11_PAGEVERSION (0x00)
1143#ifndef MPI3_IOUNIT12_BUCKET_MAX
1144#define MPI3_IOUNIT12_BUCKET_MAX (1)
1145#endif
1146struct mpi3_iounit12_bucket {
1147 u8 coalescing_depth;
1148 u8 coalescing_timeout;
1149 __le16 io_count_low_boundary;
1150 __le32 reserved04;
1151};
1152struct mpi3_io_unit_page12 {
1153 struct mpi3_config_page_header header;
1154 __le32 flags;
1155 __le32 reserved0c[4];
1156 u8 num_buckets;
1157 u8 reserved1d[3];
1158 struct mpi3_iounit12_bucket bucket[MPI3_IOUNIT12_BUCKET_MAX];
1159};
1160#define MPI3_IOUNIT12_PAGEVERSION (0x00)
1161#define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300)
1162#define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8)
1163#define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000)
1164#define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100)
1165#define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200)
1166#define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300)
1167#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003)
1168#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000)
1169#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001)
1170#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002)
1171#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003)
1172#ifndef MPI3_IOUNIT13_FUNC_MAX
1173#define MPI3_IOUNIT13_FUNC_MAX (1)
1174#endif
1175struct mpi3_iounit13_allowed_function {
1176 __le16 sub_function;
1177 u8 function_code;
1178 u8 function_flags;
1179};
1180#define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04)
1181#define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02)
1182#define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01)
1183struct mpi3_io_unit_page13 {
1184 struct mpi3_config_page_header header;
1185 __le16 flags;
1186 __le16 reserved0a;
1187 u8 num_allowed_functions;
1188 u8 reserved0d[3];
1189 struct mpi3_iounit13_allowed_function allowed_function[MPI3_IOUNIT13_FUNC_MAX];
1190};
1191#define MPI3_IOUNIT13_PAGEVERSION (0x00)
1192#define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002)
1193#define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001)
1194#ifndef MPI3_IOUNIT14_MD_MAX
1195#define MPI3_IOUNIT14_MD_MAX (1)
1196#endif
1197struct mpi3_iounit14_pagemetadata {
1198 u8 page_type;
1199 u8 page_number;
1200 u8 reserved02;
1201 u8 page_flags;
1202};
1203#define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02)
1204#define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01)
1205struct mpi3_io_unit_page14 {
1206 struct mpi3_config_page_header header;
1207 u8 flags;
1208 u8 reserved09[3];
1209 u8 num_pages;
1210 u8 reserved0d[3];
1211 struct mpi3_iounit14_pagemetadata page_metadata[MPI3_IOUNIT14_MD_MAX];
1212};
1213#define MPI3_IOUNIT14_PAGEVERSION (0x00)
1214#define MPI3_IOUNIT14_FLAGS_READONLY (0x01)
1215#ifndef MPI3_IOUNIT15_PBD_MAX
1216#define MPI3_IOUNIT15_PBD_MAX (1)
1217#endif
1218struct mpi3_io_unit_page15 {
1219 struct mpi3_config_page_header header;
1220 u8 flags;
1221 u8 reserved09[3];
1222 __le32 reserved0c;
1223 u8 power_budgeting_capability;
1224 u8 reserved11[3];
1225 u8 num_power_budget_data;
1226 u8 reserved15[3];
1227 __le32 power_budget_data[MPI3_IOUNIT15_PBD_MAX];
1228};
1229#define MPI3_IOUNIT15_PAGEVERSION (0x00)
1230#define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04)
1231#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03)
1232#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00)
1233#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01)
1234#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02)
1235#define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00)
1236
1237struct mpi3_io_unit_page17 {
1238 struct mpi3_config_page_header header;
1239 u8 num_instances;
1240 u8 instance;
1241 __le16 reserved0a;
1242 __le32 reserved0c[4];
1243 __le16 key_length;
1244 u8 encryption_algorithm;
1245 u8 reserved1f;
1246 __le32 current_key[];
1247};
1248#define MPI3_IOUNIT17_PAGEVERSION (0x00)
1249struct mpi3_ioc_page0 {
1250 struct mpi3_config_page_header header;
1251 __le32 reserved08;
1252 __le16 vendor_id;
1253 __le16 device_id;
1254 u8 revision_id;
1255 u8 reserved11[3];
1256 __le32 class_code;
1257 __le16 subsystem_vendor_id;
1258 __le16 subsystem_id;
1259};
1260
1261#define MPI3_IOC0_PAGEVERSION (0x00)
1262struct mpi3_ioc_page1 {
1263 struct mpi3_config_page_header header;
1264 __le32 coalescing_timeout;
1265 u8 coalescing_depth;
1266 u8 obsolete;
1267 __le16 reserved0e;
1268};
1269#define MPI3_IOC1_PAGEVERSION (0x00)
1270#ifndef MPI3_IOC2_EVENTMASK_WORDS
1271#define MPI3_IOC2_EVENTMASK_WORDS (4)
1272#endif
1273struct mpi3_ioc_page2 {
1274 struct mpi3_config_page_header header;
1275 __le32 reserved08;
1276 __le16 sas_broadcast_primitive_masks;
1277 __le16 sas_notify_primitive_masks;
1278 __le32 event_masks[MPI3_IOC2_EVENTMASK_WORDS];
1279};
1280
1281#define MPI3_IOC2_PAGEVERSION (0x00)
1282#define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010)
1283#define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008)
1284#define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004)
1285#define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002)
1286#define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001)
1287struct mpi3_allowed_cmd_scsi {
1288 __le16 service_action;
1289 u8 operation_code;
1290 u8 command_flags;
1291};
1292
1293struct mpi3_allowed_cmd_ata {
1294 u8 subcommand;
1295 u8 reserved01;
1296 u8 command;
1297 u8 command_flags;
1298};
1299
1300struct mpi3_allowed_cmd_nvme {
1301 u8 reserved00;
1302 u8 nvme_cmd_flags;
1303 u8 op_code;
1304 u8 command_flags;
1305};
1306
1307#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80)
1308#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00)
1309#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80)
1310#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3f)
1311#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00)
1312union mpi3_allowed_cmd {
1313 struct mpi3_allowed_cmd_scsi scsi;
1314 struct mpi3_allowed_cmd_ata ata;
1315 struct mpi3_allowed_cmd_nvme nvme;
1316};
1317
1318#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20)
1319#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10)
1320#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08)
1321#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04)
1322#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02)
1323#define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01)
1324#ifndef MPI3_ALLOWED_CMDS_MAX
1325#define MPI3_ALLOWED_CMDS_MAX (1)
1326#endif
1327struct mpi3_driver_page0 {
1328 struct mpi3_config_page_header header;
1329 __le32 bsd_options;
1330 u8 ssu_timeout;
1331 u8 io_timeout;
1332 u8 tur_retries;
1333 u8 tur_interval;
1334 u8 reserved10;
1335 u8 security_key_timeout;
1336 __le16 first_device;
1337 __le32 reserved14;
1338 __le32 reserved18;
1339};
1340#define MPI3_DRIVER0_PAGEVERSION (0x00)
1341#define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020)
1342#define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010)
1343#define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008)
1344#define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004)
1345#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003)
1346#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000)
1347#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001)
1348#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002)
1349#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE1 (0x0000)
1350#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE2 (0xffff)
1351struct mpi3_driver_page1 {
1352 struct mpi3_config_page_header header;
1353 __le32 flags;
1354 u8 time_stamp_update;
1355 u8 reserved0d[3];
1356 __le16 host_diag_trace_max_size;
1357 __le16 host_diag_trace_min_size;
1358 __le16 host_diag_trace_decrement_size;
1359 __le16 reserved16;
1360 __le16 host_diag_fw_max_size;
1361 __le16 host_diag_fw_min_size;
1362 __le16 host_diag_fw_decrement_size;
1363 __le16 reserved1e;
1364 __le16 host_diag_driver_max_size;
1365 __le16 host_diag_driver_min_size;
1366 __le16 host_diag_driver_decrement_size;
1367 __le16 reserved26;
1368};
1369
1370#define MPI3_DRIVER1_PAGEVERSION (0x00)
1371#ifndef MPI3_DRIVER2_TRIGGER_MAX
1372#define MPI3_DRIVER2_TRIGGER_MAX (1)
1373#endif
1374struct mpi3_driver2_trigger_event {
1375 u8 type;
1376 u8 flags;
1377 u8 reserved02;
1378 u8 event;
1379 __le32 reserved04[3];
1380};
1381
1382struct mpi3_driver2_trigger_scsi_sense {
1383 u8 type;
1384 u8 flags;
1385 __le16 reserved02;
1386 u8 ascq;
1387 u8 asc;
1388 u8 sense_key;
1389 u8 reserved07;
1390 __le32 reserved08[2];
1391};
1392
1393#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xff)
1394#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xff)
1395#define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xff)
1396struct mpi3_driver2_trigger_reply {
1397 u8 type;
1398 u8 flags;
1399 __le16 ioc_status;
1400 __le32 ioc_log_info;
1401 __le32 ioc_log_info_mask;
1402 __le32 reserved0c;
1403};
1404
1405#define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xffff)
1406union mpi3_driver2_trigger_element {
1407 struct mpi3_driver2_trigger_event event;
1408 struct mpi3_driver2_trigger_scsi_sense scsi_sense;
1409 struct mpi3_driver2_trigger_reply reply;
1410};
1411
1412#define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00)
1413#define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01)
1414#define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02)
1415#define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02)
1416#define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01)
1417struct mpi3_driver_page2 {
1418 struct mpi3_config_page_header header;
1419 __le64 global_trigger;
1420 __le32 reserved10[3];
1421 u8 num_triggers;
1422 u8 reserved1d[3];
1423 union mpi3_driver2_trigger_element trigger[MPI3_DRIVER2_TRIGGER_MAX];
1424};
1425
1426#define MPI3_DRIVER2_PAGEVERSION (0x00)
1427#define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL)
1428#define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL)
1429#define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL)
1430#define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL)
1431#define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL)
1432#define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL)
1433#define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL)
1434struct mpi3_driver_page10 {
1435 struct mpi3_config_page_header header;
1436 __le16 flags;
1437 __le16 reserved0a;
1438 u8 num_allowed_commands;
1439 u8 reserved0d[3];
1440 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX];
1441};
1442
1443#define MPI3_DRIVER10_PAGEVERSION (0x00)
1444struct mpi3_driver_page20 {
1445 struct mpi3_config_page_header header;
1446 __le16 flags;
1447 __le16 reserved0a;
1448 u8 num_allowed_commands;
1449 u8 reserved0d[3];
1450 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX];
1451};
1452
1453#define MPI3_DRIVER20_PAGEVERSION (0x00)
1454struct mpi3_driver_page30 {
1455 struct mpi3_config_page_header header;
1456 __le16 flags;
1457 __le16 reserved0a;
1458 u8 num_allowed_commands;
1459 u8 reserved0d[3];
1460 union mpi3_allowed_cmd allowed_command[MPI3_ALLOWED_CMDS_MAX];
1461};
1462
1463#define MPI3_DRIVER30_PAGEVERSION (0x00)
1464union mpi3_security_mac {
1465 __le32 dword[16];
1466 __le16 word[32];
1467 u8 byte[64];
1468};
1469
1470union mpi3_security_nonce {
1471 __le32 dword[16];
1472 __le16 word[32];
1473 u8 byte[64];
1474};
1475
1476union mpi3_security_root_digest {
1477 __le32 dword[16];
1478 __le16 word[32];
1479 u8 byte[64];
1480};
1481
1482union mpi3_security0_cert_chain {
1483 __le32 dword[1024];
1484 __le16 word[2048];
1485 u8 byte[4096];
1486};
1487
1488struct mpi3_security_page0 {
1489 struct mpi3_config_page_header header;
1490 u8 slot_num_group;
1491 u8 slot_num;
1492 __le16 cert_chain_length;
1493 u8 cert_chain_flags;
1494 u8 reserved0d[3];
1495 __le32 base_asym_algo;
1496 __le32 base_hash_algo;
1497 __le32 reserved18[4];
1498 union mpi3_security_mac mac;
1499 union mpi3_security_nonce nonce;
1500 union mpi3_security0_cert_chain certificate_chain;
1501};
1502
1503#define MPI3_SECURITY0_PAGEVERSION (0x00)
1504#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0e)
1505#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00)
1506#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02)
1507#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04)
1508#define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01)
1509#ifndef MPI3_SECURITY1_KEY_RECORD_MAX
1510#define MPI3_SECURITY1_KEY_RECORD_MAX 1
1511#endif
1512#ifndef MPI3_SECURITY1_PAD_MAX
1513#define MPI3_SECURITY1_PAD_MAX 4
1514#endif
1515union mpi3_security1_key_data {
1516 __le32 dword[128];
1517 __le16 word[256];
1518 u8 byte[512];
1519};
1520
1521struct mpi3_security1_key_record {
1522 u8 flags;
1523 u8 consumer;
1524 __le16 key_data_size;
1525 __le32 additional_key_data;
1526 __le32 reserved08[2];
1527 union mpi3_security1_key_data key_data;
1528};
1529
1530#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1f)
1531#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00)
1532#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01)
1533#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02)
1534#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03)
1535#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04)
1536#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00)
1537#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01)
1538#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02)
1539#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03)
1540#define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04)
1541struct mpi3_security_page1 {
1542 struct mpi3_config_page_header header;
1543 __le32 reserved08[2];
1544 union mpi3_security_mac mac;
1545 union mpi3_security_nonce nonce;
1546 u8 num_keys;
1547 u8 reserved91[3];
1548 __le32 reserved94[3];
1549 struct mpi3_security1_key_record key_record[MPI3_SECURITY1_KEY_RECORD_MAX];
1550 u8 pad[MPI3_SECURITY1_PAD_MAX];
1551};
1552
1553#define MPI3_SECURITY1_PAGEVERSION (0x00)
1554#ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX
1555#define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1
1556#endif
1557struct mpi3_security2_trusted_root {
1558 u8 level;
1559 u8 hash_algorithm;
1560 __le16 trusted_root_flags;
1561 __le32 reserved04[3];
1562 union mpi3_security_root_digest root_digest;
1563};
1564#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006)
1565#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1)
1566#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000)
1567#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002)
1568#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001)
1569struct mpi3_security_page2 {
1570 struct mpi3_config_page_header header;
1571 __le32 reserved08[2];
1572 union mpi3_security_mac mac;
1573 union mpi3_security_nonce nonce;
1574 __le32 reserved90[3];
1575 u8 num_roots;
1576 u8 reserved9d[3];
1577 struct mpi3_security2_trusted_root trusted_root[MPI3_SECURITY2_TRUSTED_ROOT_MAX];
1578};
1579#define MPI3_SECURITY2_PAGEVERSION (0x00)
1580struct mpi3_sas_io_unit0_phy_data {
1581 u8 io_unit_port;
1582 u8 port_flags;
1583 u8 phy_flags;
1584 u8 negotiated_link_rate;
1585 __le16 controller_phy_device_info;
1586 __le16 reserved06;
1587 __le16 attached_dev_handle;
1588 __le16 controller_dev_handle;
1589 __le32 discovery_status;
1590 __le32 reserved10;
1591};
1592
1593struct mpi3_sas_io_unit_page0 {
1594 struct mpi3_config_page_header header;
1595 __le32 reserved08;
1596 u8 num_phys;
1597 u8 init_status;
1598 __le16 reserved0e;
1599 struct mpi3_sas_io_unit0_phy_data phy_data[];
1600};
1601
1602#define MPI3_SASIOUNIT0_PAGEVERSION (0x00)
1603#define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00)
1604#define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01)
1605#define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02)
1606#define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04)
1607#define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05)
1608#define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06)
1609#define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xf0)
1610#define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xff)
1611#define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08)
1612#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03)
1613#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00)
1614#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01)
1615#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02)
1616#define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
1617#define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
1618#define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1619#define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02)
1620#define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01)
1621struct mpi3_sas_io_unit1_phy_data {
1622 u8 io_unit_port;
1623 u8 port_flags;
1624 u8 phy_flags;
1625 u8 max_min_link_rate;
1626 __le16 controller_phy_device_info;
1627 __le16 max_target_port_connect_time;
1628 __le32 reserved08;
1629};
1630
1631struct mpi3_sas_io_unit_page1 {
1632 struct mpi3_config_page_header header;
1633 __le16 control_flags;
1634 __le16 sas_narrow_max_queue_depth;
1635 __le16 additional_control_flags;
1636 __le16 sas_wide_max_queue_depth;
1637 u8 num_phys;
1638 u8 sata_max_q_depth;
1639 __le16 reserved12;
1640 struct mpi3_sas_io_unit1_phy_data phy_data[];
1641};
1642
1643#define MPI3_SASIOUNIT1_PAGEVERSION (0x00)
1644#define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000)
1645#define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1646#define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1647#define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1648#define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1649#define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1650#define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1651#define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1652#define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1653#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001)
1654#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000)
1655#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001)
1656#define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100)
1657#define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1658#define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1659#define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1660#define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1661#define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1662#define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1663#define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1664#define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1665#define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1666#define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40)
1667#define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20)
1668#define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1669#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xf0)
1670#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4)
1671#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xa0)
1672#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xb0)
1673#define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xc0)
1674#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0f)
1675#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0a)
1676#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0b)
1677#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0c)
1678struct mpi3_sas_io_unit2_phy_pm_settings {
1679 u8 control_flags;
1680 u8 reserved01;
1681 __le16 inactivity_timer_exponent;
1682 u8 sata_partial_timeout;
1683 u8 reserved05;
1684 u8 sata_slumber_timeout;
1685 u8 reserved07;
1686 u8 sas_partial_timeout;
1687 u8 reserved09;
1688 u8 sas_slumber_timeout;
1689 u8 reserved0b;
1690};
1691
1692#ifndef MPI3_SAS_IO_UNIT2_PHY_MAX
1693#define MPI3_SAS_IO_UNIT2_PHY_MAX (1)
1694#endif
1695struct mpi3_sas_io_unit_page2 {
1696 struct mpi3_config_page_header header;
1697 u8 num_phys;
1698 u8 reserved09[3];
1699 __le32 reserved0c;
1700 struct mpi3_sas_io_unit2_phy_pm_settings sas_phy_power_management_settings[MPI3_SAS_IO_UNIT2_PHY_MAX];
1701};
1702
1703#define MPI3_SASIOUNIT2_PAGEVERSION (0x00)
1704#define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08)
1705#define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04)
1706#define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02)
1707#define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01)
1708#define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000)
1709#define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12)
1710#define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700)
1711#define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8)
1712#define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070)
1713#define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4)
1714#define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007)
1715#define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0)
1716#define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7)
1717#define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6)
1718#define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5)
1719#define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4)
1720#define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3)
1721#define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2)
1722#define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1)
1723#define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0)
1724struct mpi3_sas_io_unit_page3 {
1725 struct mpi3_config_page_header header;
1726 __le32 reserved08;
1727 __le32 power_management_capabilities;
1728};
1729
1730#define MPI3_SASIOUNIT3_PAGEVERSION (0x00)
1731#define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
1732#define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
1733#define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
1734#define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
1735#define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
1736#define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
1737#define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
1738#define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
1739struct mpi3_sas_expander_page0 {
1740 struct mpi3_config_page_header header;
1741 u8 io_unit_port;
1742 u8 report_gen_length;
1743 __le16 enclosure_handle;
1744 __le32 reserved0c;
1745 __le64 sas_address;
1746 __le32 discovery_status;
1747 __le16 dev_handle;
1748 __le16 parent_dev_handle;
1749 __le16 expander_change_count;
1750 __le16 expander_route_indexes;
1751 u8 num_phys;
1752 u8 sas_level;
1753 __le16 flags;
1754 __le16 stp_bus_inactivity_time_limit;
1755 __le16 stp_max_connect_time_limit;
1756 __le16 stp_smp_nexus_loss_time;
1757 __le16 max_num_routed_sas_addresses;
1758 __le64 active_zone_manager_sas_address;
1759 __le16 zone_lock_inactivity_limit;
1760 __le16 reserved3a;
1761 u8 time_to_reduced_func;
1762 u8 initial_time_to_reduced_func;
1763 u8 max_reduced_func_time;
1764 u8 exp_status;
1765};
1766
1767#define MPI3_SASEXPANDER0_PAGEVERSION (0x00)
1768#define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
1769#define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
1770#define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
1771#define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
1772#define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
1773#define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
1774#define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
1775#define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
1776#define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
1777#define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
1778#define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
1779#define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02)
1780#define MPI3_SASEXPANDER0_ES_RESPONDING (0x03)
1781#define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04)
1782struct mpi3_sas_expander_page1 {
1783 struct mpi3_config_page_header header;
1784 u8 io_unit_port;
1785 u8 reserved09[3];
1786 u8 num_phys;
1787 u8 phy;
1788 __le16 num_table_entries_programmed;
1789 u8 programmed_link_rate;
1790 u8 hw_link_rate;
1791 __le16 attached_dev_handle;
1792 __le32 phy_info;
1793 __le16 attached_device_info;
1794 __le16 reserved1a;
1795 __le16 expander_dev_handle;
1796 u8 change_count;
1797 u8 negotiated_link_rate;
1798 u8 phy_identifier;
1799 u8 attached_phy_identifier;
1800 u8 reserved22;
1801 u8 discovery_info;
1802 __le32 attached_phy_info;
1803 u8 zone_group;
1804 u8 self_config_status;
1805 __le16 reserved2a;
1806 __le16 slot;
1807 __le16 slot_index;
1808};
1809
1810#define MPI3_SASEXPANDER1_PAGEVERSION (0x00)
1811#define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
1812#define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
1813#define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
1814#ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS
1815#define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1)
1816#endif
1817struct mpi3_sasexpander2_phy_element {
1818 u8 link_change_count;
1819 u8 reserved01;
1820 __le16 rate_change_count;
1821 __le32 reserved04;
1822};
1823
1824struct mpi3_sas_expander_page2 {
1825 struct mpi3_config_page_header header;
1826 u8 num_phys;
1827 u8 reserved09;
1828 __le16 dev_handle;
1829 __le32 reserved0c;
1830 struct mpi3_sasexpander2_phy_element phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS];
1831};
1832
1833#define MPI3_SASEXPANDER2_PAGEVERSION (0x00)
1834struct mpi3_sas_port_page0 {
1835 struct mpi3_config_page_header header;
1836 u8 port_number;
1837 u8 reserved09;
1838 u8 port_width;
1839 u8 reserved0b;
1840 u8 zone_group;
1841 u8 reserved0d[3];
1842 __le64 sas_address;
1843 __le16 device_info;
1844 __le16 reserved1a;
1845 __le32 reserved1c;
1846};
1847
1848#define MPI3_SASPORT0_PAGEVERSION (0x00)
1849struct mpi3_sas_phy_page0 {
1850 struct mpi3_config_page_header header;
1851 __le16 owner_dev_handle;
1852 __le16 reserved0a;
1853 __le16 attached_dev_handle;
1854 u8 attached_phy_identifier;
1855 u8 reserved0f;
1856 __le32 attached_phy_info;
1857 u8 programmed_link_rate;
1858 u8 hw_link_rate;
1859 u8 change_count;
1860 u8 flags;
1861 __le32 phy_info;
1862 u8 negotiated_link_rate;
1863 u8 reserved1d[3];
1864 __le16 slot;
1865 __le16 slot_index;
1866};
1867
1868#define MPI3_SASPHY0_PAGEVERSION (0x00)
1869#define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
1870struct mpi3_sas_phy_page1 {
1871 struct mpi3_config_page_header header;
1872 __le32 reserved08;
1873 __le32 invalid_dword_count;
1874 __le32 running_disparity_error_count;
1875 __le32 loss_dword_synch_count;
1876 __le32 phy_reset_problem_count;
1877};
1878
1879#define MPI3_SASPHY1_PAGEVERSION (0x00)
1880struct mpi3_sas_phy2_phy_event {
1881 u8 phy_event_code;
1882 u8 reserved01[3];
1883 __le32 phy_event_info;
1884};
1885
1886#ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX
1887#define MPI3_SAS_PHY2_PHY_EVENT_MAX (1)
1888#endif
1889struct mpi3_sas_phy_page2 {
1890 struct mpi3_config_page_header header;
1891 __le32 reserved08;
1892 u8 num_phy_events;
1893 u8 reserved0d[3];
1894 struct mpi3_sas_phy2_phy_event phy_event[MPI3_SAS_PHY2_PHY_EVENT_MAX];
1895};
1896
1897#define MPI3_SASPHY2_PAGEVERSION (0x00)
1898struct mpi3_sas_phy3_phy_event_config {
1899 u8 phy_event_code;
1900 u8 reserved01[3];
1901 u8 counter_type;
1902 u8 threshold_window;
1903 u8 time_units;
1904 u8 reserved07;
1905 __le32 event_threshold;
1906 __le16 threshold_flags;
1907 __le16 reserved0e;
1908};
1909
1910#define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
1911#define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
1912#define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
1913#define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
1914#define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
1915#define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
1916#define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
1917#define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07)
1918#define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08)
1919#define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
1920#define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
1921#define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
1922#define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
1923#define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
1924#define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
1925#define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
1926#define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
1927#define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
1928#define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
1929#define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2a)
1930#define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2b)
1931#define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2c)
1932#define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2d)
1933#define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2e)
1934#define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2f)
1935#define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
1936#define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
1937#define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
1938#define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
1939#define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
1940#define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
1941#define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
1942#define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
1943#define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
1944#define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
1945#define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
1946#define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
1947#define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xd0)
1948#define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xd1)
1949#define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xd2)
1950#define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xd3)
1951#define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xd4)
1952#define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xd5)
1953#define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xd6)
1954#define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xd7)
1955#define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xd8)
1956#define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xd9)
1957#define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xda)
1958#define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xdb)
1959#define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xdc)
1960#define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
1961#define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
1962#define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
1963#define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
1964#define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
1965#define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
1966#define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
1967#define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002)
1968#define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
1969#ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX
1970#define MPI3_SAS_PHY3_PHY_EVENT_MAX (1)
1971#endif
1972struct mpi3_sas_phy_page3 {
1973 struct mpi3_config_page_header header;
1974 __le32 reserved08;
1975 u8 num_phy_events;
1976 u8 reserved0d[3];
1977 struct mpi3_sas_phy3_phy_event_config phy_event_config[MPI3_SAS_PHY3_PHY_EVENT_MAX];
1978};
1979
1980#define MPI3_SASPHY3_PAGEVERSION (0x00)
1981struct mpi3_sas_phy_page4 {
1982 struct mpi3_config_page_header header;
1983 u8 reserved08[3];
1984 u8 flags;
1985 u8 initial_frame[28];
1986};
1987
1988#define MPI3_SASPHY4_PAGEVERSION (0x00)
1989#define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02)
1990#define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01)
1991#define MPI3_PCIE_LINK_RETIMERS_MASK (0x30)
1992#define MPI3_PCIE_LINK_RETIMERS_SHIFT (4)
1993#define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0f)
1994#define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00)
1995#define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01)
1996#define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02)
1997#define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03)
1998#define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04)
1999#define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05)
2000#define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06)
2001#define MPI3_PCIE_ASPM_ENABLE_NONE (0x0)
2002#define MPI3_PCIE_ASPM_ENABLE_L0S (0x1)
2003#define MPI3_PCIE_ASPM_ENABLE_L1 (0x2)
2004#define MPI3_PCIE_ASPM_ENABLE_L0S_L1 (0x3)
2005#define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0)
2006#define MPI3_PCIE_ASPM_SUPPORT_L0S (0x1)
2007#define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2)
2008#define MPI3_PCIE_ASPM_SUPPORT_L0S_L1 (0x3)
2009struct mpi3_pcie_io_unit0_phy_data {
2010 u8 link;
2011 u8 link_flags;
2012 u8 phy_flags;
2013 u8 negotiated_link_rate;
2014 __le16 attached_dev_handle;
2015 __le16 controller_dev_handle;
2016 __le32 enumeration_status;
2017 u8 io_unit_port;
2018 u8 reserved0d[3];
2019};
2020
2021#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10)
2022#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00)
2023#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10)
2024#define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08)
2025#define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2026#define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01)
2027#define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000)
2028#define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000)
2029#define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000)
2030#define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000)
2031#ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX
2032#define MPI3_PCIE_IO_UNIT0_PHY_MAX (1)
2033#endif
2034struct mpi3_pcie_io_unit_page0 {
2035 struct mpi3_config_page_header header;
2036 __le32 reserved08;
2037 u8 num_phys;
2038 u8 init_status;
2039 u8 aspm;
2040 u8 reserved0f;
2041 struct mpi3_pcie_io_unit0_phy_data phy_data[MPI3_PCIE_IO_UNIT0_PHY_MAX];
2042};
2043
2044#define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00)
2045#define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00)
2046#define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01)
2047#define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02)
2048#define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03)
2049#define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04)
2050#define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05)
2051#define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06)
2052#define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07)
2053#define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08)
2054#define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xf0)
2055#define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xff)
2056#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xc0)
2057#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6)
2058#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30)
2059#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4)
2060#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0c)
2061#define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2)
2062#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03)
2063#define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0)
2064struct mpi3_pcie_io_unit1_phy_data {
2065 u8 link;
2066 u8 link_flags;
2067 u8 phy_flags;
2068 u8 max_min_link_rate;
2069 __le32 reserved04;
2070 __le32 reserved08;
2071};
2072
2073#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03)
2074#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00)
2075#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01)
2076#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02)
2077#define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2078#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xf0)
2079#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4)
2080#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20)
2081#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30)
2082#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40)
2083#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50)
2084#define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60)
2085#ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX
2086#define MPI3_PCIE_IO_UNIT1_PHY_MAX (1)
2087#endif
2088struct mpi3_pcie_io_unit_page1 {
2089 struct mpi3_config_page_header header;
2090 __le32 control_flags;
2091 __le32 reserved0c;
2092 u8 num_phys;
2093 u8 reserved11;
2094 u8 aspm;
2095 u8 reserved13;
2096 struct mpi3_pcie_io_unit1_phy_data phy_data[MPI3_PCIE_IO_UNIT1_PHY_MAX];
2097};
2098
2099#define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00)
2100#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xe0000000)
2101#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000)
2102#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000)
2103#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000)
2104#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000)
2105#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1c000000)
2106#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000)
2107#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT (0x04000000)
2108#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT (0x08000000)
2109#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0c000000)
2110#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080)
2111#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040)
2112#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030)
2113#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4)
2114#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000)
2115#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010)
2116#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020)
2117#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000f)
2118#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000)
2119#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002)
2120#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003)
2121#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004)
2122#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005)
2123#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006)
2124#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0c)
2125#define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2)
2126#define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03)
2127#define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0)
2128struct mpi3_pcie_io_unit_page2 {
2129 struct mpi3_config_page_header header;
2130 __le16 nvme_max_q_dx1;
2131 __le16 nvme_max_q_dx2;
2132 u8 nvme_abort_to;
2133 u8 reserved0d;
2134 __le16 nvme_max_q_dx4;
2135};
2136
2137#define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00)
2138#define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0)
2139#define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1)
2140#define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2)
2141#define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3)
2142#define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4)
2143#define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5)
2144struct mpi3_pcie_io_unit3_error {
2145 __le16 threshold_count;
2146 __le16 reserved02;
2147};
2148
2149struct mpi3_pcie_io_unit_page3 {
2150 struct mpi3_config_page_header header;
2151 u8 threshold_window;
2152 u8 threshold_action;
2153 u8 escalation_count;
2154 u8 escalation_action;
2155 u8 num_errors;
2156 u8 reserved0d[3];
2157 struct mpi3_pcie_io_unit3_error error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX];
2158};
2159
2160#define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00)
2161#define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00)
2162#define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01)
2163#define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02)
2164#define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03)
2165struct mpi3_pcie_switch_page0 {
2166 struct mpi3_config_page_header header;
2167 u8 io_unit_port;
2168 u8 switch_status;
2169 u8 reserved0a[2];
2170 __le16 dev_handle;
2171 __le16 parent_dev_handle;
2172 u8 num_ports;
2173 u8 pcie_level;
2174 __le16 reserved12;
2175 __le32 reserved14;
2176 __le32 reserved18;
2177 __le32 reserved1c;
2178};
2179
2180#define MPI3_PCIESWITCH0_PAGEVERSION (0x00)
2181#define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02)
2182#define MPI3_PCIESWITCH0_SS_RESPONDING (0x03)
2183#define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04)
2184struct mpi3_pcie_switch_page1 {
2185 struct mpi3_config_page_header header;
2186 u8 io_unit_port;
2187 u8 flags;
2188 __le16 reserved0a;
2189 u8 num_ports;
2190 u8 port_num;
2191 __le16 attached_dev_handle;
2192 __le16 switch_dev_handle;
2193 u8 negotiated_port_width;
2194 u8 negotiated_link_rate;
2195 __le16 slot;
2196 __le16 slot_index;
2197 __le32 reserved18;
2198};
2199
2200#define MPI3_PCIESWITCH1_PAGEVERSION (0x00)
2201#define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0c)
2202#define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2)
2203#define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03)
2204#define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0)
2205#ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS
2206#define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1)
2207#endif
2208struct mpi3_pcieswitch2_port_element {
2209 __le16 link_change_count;
2210 __le16 rate_change_count;
2211 __le32 reserved04;
2212};
2213
2214struct mpi3_pcie_switch_page2 {
2215 struct mpi3_config_page_header header;
2216 u8 num_ports;
2217 u8 reserved09;
2218 __le16 dev_handle;
2219 __le32 reserved0c;
2220 struct mpi3_pcieswitch2_port_element port[MPI3_PCIESWITCH2_MAX_NUM_PORTS];
2221};
2222
2223#define MPI3_PCIESWITCH2_PAGEVERSION (0x00)
2224struct mpi3_pcie_link_page0 {
2225 struct mpi3_config_page_header header;
2226 u8 link;
2227 u8 reserved09[3];
2228 __le32 reserved0c;
2229 __le32 receiver_error_count;
2230 __le32 recovery_count;
2231 __le32 corr_error_msg_count;
2232 __le32 non_fatal_error_msg_count;
2233 __le32 fatal_error_msg_count;
2234 __le32 non_fatal_error_count;
2235 __le32 fatal_error_count;
2236 __le32 bad_dllp_count;
2237 __le32 bad_tlp_count;
2238};
2239
2240#define MPI3_PCIELINK0_PAGEVERSION (0x00)
2241struct mpi3_enclosure_page0 {
2242 struct mpi3_config_page_header header;
2243 __le64 enclosure_logical_id;
2244 __le16 flags;
2245 __le16 enclosure_handle;
2246 __le16 num_slots;
2247 __le16 reserved16;
2248 u8 io_unit_port;
2249 u8 enclosure_level;
2250 __le16 sep_dev_handle;
2251 u8 chassis_slot;
2252 u8 reserved1d[3];
2253};
2254
2255#define MPI3_ENCLOSURE0_PAGEVERSION (0x00)
2256#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xc000)
2257#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000)
2258#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000)
2259#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000)
2260#define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
2261#define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010)
2262#define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000)
2263#define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010)
2264#define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000f)
2265#define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2266#define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2267#define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002)
2268#define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00)
2269#define MPI3_DEVICE_DEVFORM_PCIE (0x01)
2270#define MPI3_DEVICE_DEVFORM_VD (0x02)
2271struct mpi3_device0_sas_sata_format {
2272 __le64 sas_address;
2273 __le16 flags;
2274 __le16 device_info;
2275 u8 phy_num;
2276 u8 attached_phy_identifier;
2277 u8 max_port_connections;
2278 u8 zone_group;
2279};
2280
2281#define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400)
2282#define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200)
2283#define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100)
2284#define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080)
2285#define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040)
2286#define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020)
2287#define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010)
2288#define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008)
2289#define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004)
2290#define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002)
2291#define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001)
2292struct mpi3_device0_pcie_format {
2293 u8 supported_link_rates;
2294 u8 max_port_width;
2295 u8 negotiated_port_width;
2296 u8 negotiated_link_rate;
2297 u8 port_num;
2298 u8 controller_reset_to;
2299 __le16 device_info;
2300 __le32 maximum_data_transfer_size;
2301 __le32 capabilities;
2302 __le16 noiob;
2303 u8 nvme_abort_to;
2304 u8 page_size;
2305 __le16 shutdown_latency;
2306 u8 recovery_info;
2307 u8 reserved17;
2308};
2309
2310#define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10)
2311#define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08)
2312#define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04)
2313#define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02)
2314#define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01)
2315#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007)
2316#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000)
2317#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001)
2318#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002)
2319#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003)
2320#define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030)
2321#define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4)
2322#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00c0)
2323#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6)
2324#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000)
2325#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040)
2326#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080)
2327#define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00c0)
2328#define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020)
2329#define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010)
2330#define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008)
2331#define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004)
2332#define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000)
2333#define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002)
2334#define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001)
2335#define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000c0)
2336#define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6)
2337#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xe0)
2338#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00)
2339#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20)
2340#define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1f)
2341#define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00)
2342#define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01)
2343#define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02)
2344#define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03)
2345#define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04)
2346#define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05)
2347struct mpi3_device0_vd_format {
2348 u8 vd_state;
2349 u8 raid_level;
2350 __le16 device_info;
2351 __le16 flags;
2352 __le16 io_throttle_group;
2353 __le16 io_throttle_group_low;
2354 __le16 io_throttle_group_high;
2355 __le32 reserved0c;
2356};
2357#define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00)
2358#define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01)
2359#define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02)
2360#define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03)
2361#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0)
2362#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1)
2363#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5)
2364#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6)
2365#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10)
2366#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50)
2367#define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60)
2368#define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010)
2369#define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008)
2370#define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004)
2371#define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002)
2372#define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001)
2373#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xf000)
2374#define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12)
2375#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_MASK (0x0003)
2376#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_HDD (0x0000)
2377#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SSD (0x0001)
2378#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_NO_GUIDANCE (0x0002)
2379union mpi3_device0_dev_spec_format {
2380 struct mpi3_device0_sas_sata_format sas_sata_format;
2381 struct mpi3_device0_pcie_format pcie_format;
2382 struct mpi3_device0_vd_format vd_format;
2383};
2384
2385struct mpi3_device_page0 {
2386 struct mpi3_config_page_header header;
2387 __le16 dev_handle;
2388 __le16 parent_dev_handle;
2389 __le16 slot;
2390 __le16 enclosure_handle;
2391 __le64 wwid;
2392 __le16 persistent_id;
2393 u8 io_unit_port;
2394 u8 access_status;
2395 __le16 flags;
2396 __le16 reserved1e;
2397 __le16 slot_index;
2398 __le16 queue_depth;
2399 u8 reserved24[3];
2400 u8 device_form;
2401 union mpi3_device0_dev_spec_format device_specific;
2402};
2403
2404#define MPI3_DEVICE0_PAGEVERSION (0x00)
2405#define MPI3_DEVICE0_PARENT_INVALID (0xffff)
2406#define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000)
2407#define MPI3_DEVICE0_WWID_INVALID (0xffffffffffffffff)
2408#define MPI3_DEVICE0_PERSISTENTID_INVALID (0xffff)
2409#define MPI3_DEVICE0_IOUNITPORT_INVALID (0xff)
2410#define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2411#define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01)
2412#define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02)
2413#define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03)
2414#define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04)
2415#define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05)
2416#define MPI3_DEVICE0_ASTATUS_PREPARE (0x06)
2417#define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07)
2418#define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0f)
2419#define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10)
2420#define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11)
2421#define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12)
2422#define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1f)
2423#define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20)
2424#define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21)
2425#define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22)
2426#define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23)
2427#define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24)
2428#define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25)
2429#define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26)
2430#define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27)
2431#define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28)
2432#define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29)
2433#define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2f)
2434#define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30)
2435#define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31)
2436#define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32)
2437#define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33)
2438#define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34)
2439#define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3f)
2440#define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40)
2441#define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41)
2442#define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42)
2443#define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43)
2444#define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44)
2445#define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45)
2446#define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46)
2447#define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47)
2448#define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48)
2449#define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49)
2450#define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4a)
2451#define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4b)
2452#define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4c)
2453#define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4d)
2454#define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4e)
2455#define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4f)
2456#define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50)
2457#define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51)
2458#define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52)
2459#define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5f)
2460#define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80)
2461#define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8f)
2462#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xe000)
2463#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000)
2464#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000)
2465#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000)
2466#define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080)
2467#define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010)
2468#define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008)
2469#define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004)
2470#define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002)
2471#define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2472#define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000)
2473struct mpi3_device1_sas_sata_format {
2474 __le32 reserved00;
2475};
2476struct mpi3_device1_pcie_format {
2477 __le16 vendor_id;
2478 __le16 device_id;
2479 __le16 subsystem_vendor_id;
2480 __le16 subsystem_id;
2481 __le32 reserved08;
2482 u8 revision_id;
2483 u8 reserved0d;
2484 __le16 pci_parameters;
2485};
2486
2487#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0)
2488#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1)
2489#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2)
2490#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3)
2491#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4)
2492#define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5)
2493#define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01c0)
2494#define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6)
2495#define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038)
2496#define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3)
2497#define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007)
2498#define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0)
2499struct mpi3_device1_vd_format {
2500 __le32 reserved00;
2501};
2502
2503union mpi3_device1_dev_spec_format {
2504 struct mpi3_device1_sas_sata_format sas_sata_format;
2505 struct mpi3_device1_pcie_format pcie_format;
2506 struct mpi3_device1_vd_format vd_format;
2507};
2508
2509struct mpi3_device_page1 {
2510 struct mpi3_config_page_header header;
2511 __le16 dev_handle;
2512 __le16 reserved0a;
2513 __le16 link_change_count;
2514 __le16 rate_change_count;
2515 __le16 tm_count;
2516 __le16 reserved12;
2517 __le32 reserved14[10];
2518 u8 reserved3c[3];
2519 u8 device_form;
2520 union mpi3_device1_dev_spec_format device_specific;
2521};
2522
2523#define MPI3_DEVICE1_PAGEVERSION (0x00)
2524#define MPI3_DEVICE1_COUNTER_MAX (0xfffe)
2525#define MPI3_DEVICE1_COUNTER_INVALID (0xffff)
2526#endif