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1/*
2 * NCR 5380 defines
3 *
4 * Copyright 1993, Drew Eckhardt
5 * Visionary Computing
6 * (Unix consulting and custom programming)
7 * drew@colorado.edu
8 * +1 (303) 666-5836
9 *
10 * DISTRIBUTION RELEASE 7
11 *
12 * For more information, please consult
13 *
14 * NCR 5380 Family
15 * SCSI Protocol Controller
16 * Databook
17 * NCR Microelectronics
18 * 1635 Aeroplaza Drive
19 * Colorado Springs, CO 80916
20 * 1+ (719) 578-3400
21 * 1+ (800) 334-5454
22 */
23
24/*
25 * $Log: NCR5380.h,v $
26 */
27
28#ifndef NCR5380_H
29#define NCR5380_H
30
31#include <linux/interrupt.h>
32
33#ifdef AUTOSENSE
34#include <scsi/scsi_eh.h>
35#endif
36
37#define NCR5380_PUBLIC_RELEASE 7
38#define NCR53C400_PUBLIC_RELEASE 2
39
40#define NDEBUG_ARBITRATION 0x1
41#define NDEBUG_AUTOSENSE 0x2
42#define NDEBUG_DMA 0x4
43#define NDEBUG_HANDSHAKE 0x8
44#define NDEBUG_INFORMATION 0x10
45#define NDEBUG_INIT 0x20
46#define NDEBUG_INTR 0x40
47#define NDEBUG_LINKED 0x80
48#define NDEBUG_MAIN 0x100
49#define NDEBUG_NO_DATAOUT 0x200
50#define NDEBUG_NO_WRITE 0x400
51#define NDEBUG_PIO 0x800
52#define NDEBUG_PSEUDO_DMA 0x1000
53#define NDEBUG_QUEUES 0x2000
54#define NDEBUG_RESELECTION 0x4000
55#define NDEBUG_SELECTION 0x8000
56#define NDEBUG_USLEEP 0x10000
57#define NDEBUG_LAST_BYTE_SENT 0x20000
58#define NDEBUG_RESTART_SELECT 0x40000
59#define NDEBUG_EXTENDED 0x80000
60#define NDEBUG_C400_PREAD 0x100000
61#define NDEBUG_C400_PWRITE 0x200000
62#define NDEBUG_LISTS 0x400000
63
64#define NDEBUG_ANY 0xFFFFFFFFUL
65
66/*
67 * The contents of the OUTPUT DATA register are asserted on the bus when
68 * either arbitration is occurring or the phase-indicating signals (
69 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
70 * bit in the INITIATOR COMMAND register is set.
71 */
72
73#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
74#define CURRENT_SCSI_DATA_REG 0 /* ro same */
75
76#define INITIATOR_COMMAND_REG 1 /* rw */
77#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
78#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
79#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
80#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
81#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
82#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
83#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
84#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
85#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
86#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
87
88#ifdef DIFFERENTIAL
89#define ICR_BASE ICR_DIFF_ENABLE
90#else
91#define ICR_BASE 0
92#endif
93
94#define MODE_REG 2
95/*
96 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
97 * transfer, causing the chip to hog the bus. You probably don't want
98 * this.
99 */
100#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
101#define MR_TARGET 0x40 /* rw target mode */
102#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
103#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
104#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
105#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
106#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
107#define MR_ARBITRATE 0x01 /* rw start arbitration */
108
109#ifdef PARITY
110#define MR_BASE MR_ENABLE_PAR_CHECK
111#else
112#define MR_BASE 0
113#endif
114
115#define TARGET_COMMAND_REG 3
116#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
117#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
118#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
119#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
120#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
121
122#define STATUS_REG 4 /* ro */
123/*
124 * Note : a set bit indicates an active signal, driven by us or another
125 * device.
126 */
127#define SR_RST 0x80
128#define SR_BSY 0x40
129#define SR_REQ 0x20
130#define SR_MSG 0x10
131#define SR_CD 0x08
132#define SR_IO 0x04
133#define SR_SEL 0x02
134#define SR_DBP 0x01
135
136/*
137 * Setting a bit in this register will cause an interrupt to be generated when
138 * BSY is false and SEL true and this bit is asserted on the bus.
139 */
140#define SELECT_ENABLE_REG 4 /* wo */
141
142#define BUS_AND_STATUS_REG 5 /* ro */
143#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
144#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
145#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
146#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
147#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
148#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
149#define BASR_ATN 0x02 /* ro BUS status */
150#define BASR_ACK 0x01 /* ro BUS status */
151
152/* Write any value to this register to start a DMA send */
153#define START_DMA_SEND_REG 5 /* wo */
154
155/*
156 * Used in DMA transfer mode, data is latched from the SCSI bus on
157 * the falling edge of REQ (ini) or ACK (tgt)
158 */
159#define INPUT_DATA_REG 6 /* ro */
160
161/* Write any value to this register to start a DMA receive */
162#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
163
164/* Read this register to clear interrupt conditions */
165#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
166
167/* Write any value to this register to start an ini mode DMA receive */
168#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
169
170#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
171
172#define CSR_RESET 0x80 /* wo Resets 53c400 */
173#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
174#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
175#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
176#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
177#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
178#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
179#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
180#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
181
182#if 0
183#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
184#else
185#define CSR_BASE CSR_53C80_INTR
186#endif
187
188/* Number of 128-byte blocks to be transferred */
189#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
190
191/* Resume transfer after disconnect */
192#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
193
194/* Access to host buffer stack */
195#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
196
197
198/* Note : PHASE_* macros are based on the values of the STATUS register */
199#define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
200
201#define PHASE_DATAOUT 0
202#define PHASE_DATAIN SR_IO
203#define PHASE_CMDOUT SR_CD
204#define PHASE_STATIN (SR_CD | SR_IO)
205#define PHASE_MSGOUT (SR_MSG | SR_CD)
206#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
207#define PHASE_UNKNOWN 0xff
208
209/*
210 * Convert status register phase to something we can use to set phase in
211 * the target register so we can get phase mismatch interrupts on DMA
212 * transfers.
213 */
214
215#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
216
217/*
218 * The internal should_disconnect() function returns these based on the
219 * expected length of a disconnect if a device supports disconnect/
220 * reconnect.
221 */
222
223#define DISCONNECT_NONE 0
224#define DISCONNECT_TIME_TO_DATA 1
225#define DISCONNECT_LONG 2
226
227/*
228 * These are "special" values for the tag parameter passed to NCR5380_select.
229 */
230
231#define TAG_NEXT -1 /* Use next free tag */
232#define TAG_NONE -2 /*
233 * Establish I_T_L nexus instead of I_T_L_Q
234 * even on SCSI-II devices.
235 */
236
237/*
238 * These are "special" values for the irq and dma_channel fields of the
239 * Scsi_Host structure
240 */
241
242#define SCSI_IRQ_NONE 255
243#define DMA_NONE 255
244#define IRQ_AUTO 254
245#define DMA_AUTO 254
246#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
247
248#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
249#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
250#define FLAG_NCR53C400 4 /* NCR53c400 */
251#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
252#define FLAG_DTC3181E 16 /* DTC3181E */
253
254#ifndef ASM
255struct NCR5380_hostdata {
256 NCR5380_implementation_fields; /* implementation specific */
257 struct Scsi_Host *host; /* Host backpointer */
258 unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
259 unsigned char targets_present; /* targets we have connected
260 to, so we can call a select
261 failure a retryable condition */
262 volatile unsigned char busy[8]; /* index = target, bit = lun */
263#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
264 volatile int dma_len; /* requested length of DMA */
265#endif
266 volatile unsigned char last_message; /* last message OUT */
267 volatile Scsi_Cmnd *connected; /* currently connected command */
268 volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
269 volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
270 volatile int restart_select; /* we have disconnected,
271 used to restart
272 NCR5380_select() */
273 volatile unsigned aborted:1; /* flag, says aborted */
274 int flags;
275 unsigned long time_expires; /* in jiffies, set prior to sleeping */
276 int select_time; /* timer in select for target response */
277 volatile Scsi_Cmnd *selecting;
278 struct delayed_work coroutine; /* our co-routine */
279#ifdef NCR5380_STATS
280 unsigned timebase; /* Base for time calcs */
281 long time_read[8]; /* time to do reads */
282 long time_write[8]; /* time to do writes */
283 unsigned long bytes_read[8]; /* bytes read */
284 unsigned long bytes_write[8]; /* bytes written */
285 unsigned pendingr;
286 unsigned pendingw;
287#endif
288#ifdef AUTOSENSE
289 struct scsi_eh_save ses;
290#endif
291};
292
293#ifdef __KERNEL__
294
295#define dprintk(a,b) do {} while(0)
296#define NCR5380_dprint(a,b) do {} while(0)
297#define NCR5380_dprint_phase(a,b) do {} while(0)
298
299#if defined(AUTOPROBE_IRQ)
300static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
301#endif
302static int NCR5380_init(struct Scsi_Host *instance, int flags);
303static void NCR5380_exit(struct Scsi_Host *instance);
304static void NCR5380_information_transfer(struct Scsi_Host *instance);
305#ifndef DONT_USE_INTR
306static irqreturn_t NCR5380_intr(int irq, void *dev_id);
307#endif
308static void NCR5380_main(struct work_struct *work);
309static void __maybe_unused NCR5380_print_options(struct Scsi_Host *instance);
310#ifdef NDEBUG
311static void NCR5380_print_phase(struct Scsi_Host *instance);
312static void NCR5380_print(struct Scsi_Host *instance);
313#endif
314static int NCR5380_abort(Scsi_Cmnd * cmd);
315static int NCR5380_bus_reset(Scsi_Cmnd * cmd);
316static int NCR5380_queue_command(struct Scsi_Host *, struct scsi_cmnd *);
317static int __maybe_unused NCR5380_proc_info(struct Scsi_Host *instance,
318 char *buffer, char **start, off_t offset, int length, int inout);
319
320static void NCR5380_reselect(struct Scsi_Host *instance);
321static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag);
322#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
323static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
324#endif
325static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
326
327#if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
328
329#if defined(i386) || defined(__alpha__)
330
331/**
332 * NCR5380_pc_dma_setup - setup ISA DMA
333 * @instance: adapter to set up
334 * @ptr: block to transfer (virtual address)
335 * @count: number of bytes to transfer
336 * @mode: DMA controller mode to use
337 *
338 * Program the DMA controller ready to perform an ISA DMA transfer
339 * on this chip.
340 *
341 * Locks: takes and releases the ISA DMA lock.
342 */
343
344static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
345{
346 unsigned limit;
347 unsigned long bus_addr = virt_to_bus(ptr);
348 unsigned long flags;
349
350 if (instance->dma_channel <= 3) {
351 if (count > 65536)
352 count = 65536;
353 limit = 65536 - (bus_addr & 0xFFFF);
354 } else {
355 if (count > 65536 * 2)
356 count = 65536 * 2;
357 limit = 65536 * 2 - (bus_addr & 0x1FFFF);
358 }
359
360 if (count > limit)
361 count = limit;
362
363 if ((count & 1) || (bus_addr & 1))
364 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
365
366 flags=claim_dma_lock();
367 disable_dma(instance->dma_channel);
368 clear_dma_ff(instance->dma_channel);
369 set_dma_addr(instance->dma_channel, bus_addr);
370 set_dma_count(instance->dma_channel, count);
371 set_dma_mode(instance->dma_channel, mode);
372 enable_dma(instance->dma_channel);
373 release_dma_lock(flags);
374
375 return count;
376}
377
378/**
379 * NCR5380_pc_dma_write_setup - setup ISA DMA write
380 * @instance: adapter to set up
381 * @ptr: block to transfer (virtual address)
382 * @count: number of bytes to transfer
383 *
384 * Program the DMA controller ready to perform an ISA DMA write to the
385 * SCSI controller.
386 *
387 * Locks: called routines take and release the ISA DMA lock.
388 */
389
390static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
391{
392 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
393}
394
395/**
396 * NCR5380_pc_dma_read_setup - setup ISA DMA read
397 * @instance: adapter to set up
398 * @ptr: block to transfer (virtual address)
399 * @count: number of bytes to transfer
400 *
401 * Program the DMA controller ready to perform an ISA DMA read from the
402 * SCSI controller.
403 *
404 * Locks: called routines take and release the ISA DMA lock.
405 */
406
407static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
408{
409 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
410}
411
412/**
413 * NCR5380_pc_dma_residual - return bytes left
414 * @instance: adapter
415 *
416 * Reports the number of bytes left over after the DMA was terminated.
417 *
418 * Locks: takes and releases the ISA DMA lock.
419 */
420
421static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
422{
423 unsigned long flags;
424 int tmp;
425
426 flags = claim_dma_lock();
427 clear_dma_ff(instance->dma_channel);
428 tmp = get_dma_residue(instance->dma_channel);
429 release_dma_lock(flags);
430
431 return tmp;
432}
433#endif /* defined(i386) || defined(__alpha__) */
434#endif /* defined(REAL_DMA) */
435#endif /* __KERNEL__ */
436#endif /* ndef ASM */
437#endif /* NCR5380_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * NCR 5380 defines
4 *
5 * Copyright 1993, Drew Eckhardt
6 * Visionary Computing
7 * (Unix consulting and custom programming)
8 * drew@colorado.edu
9 * +1 (303) 666-5836
10 *
11 * For more information, please consult
12 *
13 * NCR 5380 Family
14 * SCSI Protocol Controller
15 * Databook
16 * NCR Microelectronics
17 * 1635 Aeroplaza Drive
18 * Colorado Springs, CO 80916
19 * 1+ (719) 578-3400
20 * 1+ (800) 334-5454
21 */
22
23#ifndef NCR5380_H
24#define NCR5380_H
25
26#include <linux/delay.h>
27#include <linux/interrupt.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <scsi/scsi_dbg.h>
31#include <scsi/scsi_eh.h>
32#include <scsi/scsi_transport_spi.h>
33
34#define NDEBUG_ARBITRATION 0x1
35#define NDEBUG_AUTOSENSE 0x2
36#define NDEBUG_DMA 0x4
37#define NDEBUG_HANDSHAKE 0x8
38#define NDEBUG_INFORMATION 0x10
39#define NDEBUG_INIT 0x20
40#define NDEBUG_INTR 0x40
41#define NDEBUG_LINKED 0x80
42#define NDEBUG_MAIN 0x100
43#define NDEBUG_NO_DATAOUT 0x200
44#define NDEBUG_NO_WRITE 0x400
45#define NDEBUG_PIO 0x800
46#define NDEBUG_PSEUDO_DMA 0x1000
47#define NDEBUG_QUEUES 0x2000
48#define NDEBUG_RESELECTION 0x4000
49#define NDEBUG_SELECTION 0x8000
50#define NDEBUG_USLEEP 0x10000
51#define NDEBUG_LAST_BYTE_SENT 0x20000
52#define NDEBUG_RESTART_SELECT 0x40000
53#define NDEBUG_EXTENDED 0x80000
54#define NDEBUG_C400_PREAD 0x100000
55#define NDEBUG_C400_PWRITE 0x200000
56#define NDEBUG_LISTS 0x400000
57#define NDEBUG_ABORT 0x800000
58#define NDEBUG_TAGS 0x1000000
59#define NDEBUG_MERGING 0x2000000
60
61#define NDEBUG_ANY 0xFFFFFFFFUL
62
63/*
64 * The contents of the OUTPUT DATA register are asserted on the bus when
65 * either arbitration is occurring or the phase-indicating signals (
66 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
67 * bit in the INITIATOR COMMAND register is set.
68 */
69
70#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
71#define CURRENT_SCSI_DATA_REG 0 /* ro same */
72
73#define INITIATOR_COMMAND_REG 1 /* rw */
74#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
75#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
76#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
77#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
78#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
79#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
80#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
81#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
82#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
83#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
84
85#define ICR_BASE 0
86
87#define MODE_REG 2
88/*
89 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
90 * transfer, causing the chip to hog the bus. You probably don't want
91 * this.
92 */
93#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
94#define MR_TARGET 0x40 /* rw target mode */
95#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
96#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
97#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
98#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
99#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
100#define MR_ARBITRATE 0x01 /* rw start arbitration */
101
102#define MR_BASE 0
103
104#define TARGET_COMMAND_REG 3
105#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
106#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
107#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
108#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
109#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
110
111#define STATUS_REG 4 /* ro */
112/*
113 * Note : a set bit indicates an active signal, driven by us or another
114 * device.
115 */
116#define SR_RST 0x80
117#define SR_BSY 0x40
118#define SR_REQ 0x20
119#define SR_MSG 0x10
120#define SR_CD 0x08
121#define SR_IO 0x04
122#define SR_SEL 0x02
123#define SR_DBP 0x01
124
125/*
126 * Setting a bit in this register will cause an interrupt to be generated when
127 * BSY is false and SEL true and this bit is asserted on the bus.
128 */
129#define SELECT_ENABLE_REG 4 /* wo */
130
131#define BUS_AND_STATUS_REG 5 /* ro */
132#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
133#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
134#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
135#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
136#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
137#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
138#define BASR_ATN 0x02 /* ro BUS status */
139#define BASR_ACK 0x01 /* ro BUS status */
140
141/* Write any value to this register to start a DMA send */
142#define START_DMA_SEND_REG 5 /* wo */
143
144/*
145 * Used in DMA transfer mode, data is latched from the SCSI bus on
146 * the falling edge of REQ (ini) or ACK (tgt)
147 */
148#define INPUT_DATA_REG 6 /* ro */
149
150/* Write any value to this register to start a DMA receive */
151#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
152
153/* Read this register to clear interrupt conditions */
154#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
155
156/* Write any value to this register to start an ini mode DMA receive */
157#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
158
159/* NCR 53C400(A) Control Status Register bits: */
160#define CSR_RESET 0x80 /* wo Resets 53c400 */
161#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
162#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
163#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
164#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
165#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
166#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
167#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
168#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
169
170#define CSR_BASE CSR_53C80_INTR
171
172/* Note : PHASE_* macros are based on the values of the STATUS register */
173#define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
174
175#define PHASE_DATAOUT 0
176#define PHASE_DATAIN SR_IO
177#define PHASE_CMDOUT SR_CD
178#define PHASE_STATIN (SR_CD | SR_IO)
179#define PHASE_MSGOUT (SR_MSG | SR_CD)
180#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
181#define PHASE_UNKNOWN 0xff
182
183/*
184 * Convert status register phase to something we can use to set phase in
185 * the target register so we can get phase mismatch interrupts on DMA
186 * transfers.
187 */
188
189#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
190
191#ifndef NO_IRQ
192#define NO_IRQ 0
193#endif
194
195#define FLAG_DMA_FIXUP 1 /* Use DMA errata workarounds */
196#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
197#define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */
198#define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */
199
200struct NCR5380_hostdata {
201 NCR5380_implementation_fields; /* Board-specific data */
202 u8 __iomem *io; /* Remapped 5380 address */
203 u8 __iomem *pdma_io; /* Remapped PDMA address */
204 unsigned long poll_loops; /* Register polling limit */
205 spinlock_t lock; /* Protects this struct */
206 struct scsi_cmnd *connected; /* Currently connected cmnd */
207 struct list_head disconnected; /* Waiting for reconnect */
208 struct Scsi_Host *host; /* SCSI host backpointer */
209 struct workqueue_struct *work_q; /* SCSI host work queue */
210 struct work_struct main_task; /* Work item for main loop */
211 int flags; /* Board-specific quirks */
212 int dma_len; /* Requested length of DMA */
213 int read_overruns; /* Transfer size reduction for DMA erratum */
214 unsigned long io_port; /* Device IO port */
215 unsigned long base; /* Device base address */
216 struct list_head unissued; /* Waiting to be issued */
217 struct scsi_cmnd *selecting; /* Cmnd to be connected */
218 struct list_head autosense; /* Priority cmnd queue */
219 struct scsi_cmnd *sensing; /* Cmnd needing autosense */
220 struct scsi_eh_save ses; /* Cmnd state saved for EH */
221 unsigned char busy[8]; /* Index = target, bit = lun */
222 unsigned char id_mask; /* 1 << Host ID */
223 unsigned char id_higher_mask; /* All bits above id_mask */
224 unsigned char last_message; /* Last Message Out */
225 unsigned long region_size; /* Size of address/port range */
226 char info[168]; /* Host banner message */
227};
228
229struct NCR5380_cmd {
230 char *ptr;
231 int this_residual;
232 struct scatterlist *buffer;
233 int status;
234 int phase;
235 struct list_head list;
236};
237
238#define NCR5380_PIO_CHUNK_SIZE 256
239
240/* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */
241#define NCR5380_REG_POLL_TIME 10
242
243static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr)
244{
245 return ((struct scsi_cmnd *)ncmd_ptr) - 1;
246}
247
248static inline struct NCR5380_cmd *NCR5380_to_ncmd(struct scsi_cmnd *cmd)
249{
250 return scsi_cmd_priv(cmd);
251}
252
253#ifndef NDEBUG
254#define NDEBUG (0)
255#endif
256
257#define dprintk(flg, fmt, ...) \
258 do { if ((NDEBUG) & (flg)) \
259 printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
260
261#define dsprintk(flg, host, fmt, ...) \
262 do { if ((NDEBUG) & (flg)) \
263 shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
264 } while (0)
265
266#if NDEBUG
267#define NCR5380_dprint(flg, arg) \
268 do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
269#define NCR5380_dprint_phase(flg, arg) \
270 do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
271static void NCR5380_print_phase(struct Scsi_Host *instance);
272static void NCR5380_print(struct Scsi_Host *instance);
273#else
274#define NCR5380_dprint(flg, arg) do {} while (0)
275#define NCR5380_dprint_phase(flg, arg) do {} while (0)
276#endif
277
278static int NCR5380_init(struct Scsi_Host *instance, int flags);
279static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
280static void NCR5380_exit(struct Scsi_Host *instance);
281static void NCR5380_information_transfer(struct Scsi_Host *instance);
282static irqreturn_t NCR5380_intr(int irq, void *dev_id);
283static void NCR5380_main(struct work_struct *work);
284static const char *NCR5380_info(struct Scsi_Host *instance);
285static void NCR5380_reselect(struct Scsi_Host *instance);
286static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *);
287static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
288static void NCR5380_transfer_pio(struct Scsi_Host *instance,
289 unsigned char *phase, int *count,
290 unsigned char **data, unsigned int can_sleep);
291static int NCR5380_poll_politely2(struct NCR5380_hostdata *,
292 unsigned int, u8, u8,
293 unsigned int, u8, u8, unsigned long);
294
295static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata,
296 unsigned int reg, u8 bit, u8 val,
297 unsigned long wait)
298{
299 if ((NCR5380_read(reg) & bit) == val)
300 return 0;
301
302 return NCR5380_poll_politely2(hostdata, reg, bit, val,
303 reg, bit, val, wait);
304}
305
306static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *,
307 struct scsi_cmnd *);
308static int NCR5380_dma_send_setup(struct NCR5380_hostdata *,
309 unsigned char *, int);
310static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *,
311 unsigned char *, int);
312static int NCR5380_dma_residual(struct NCR5380_hostdata *);
313
314static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata,
315 struct scsi_cmnd *cmd)
316{
317 return 0;
318}
319
320static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata,
321 unsigned char *data, int count)
322{
323 return 0;
324}
325
326static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata)
327{
328 return 0;
329}
330
331#endif /* NCR5380_H */