Loading...
Note: File does not exist in v3.1.
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Intel Core SoC Power Management Controller Header File
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 * All Rights Reserved.
7 *
8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com>
10 */
11
12#ifndef PMC_CORE_H
13#define PMC_CORE_H
14
15#include <linux/acpi.h>
16#include <linux/bits.h>
17#include <linux/platform_device.h>
18
19struct telem_endpoint;
20
21#define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0)
22
23#define PMC_BASE_ADDR_DEFAULT 0xFE000000
24#define MAX_NUM_PMC 3
25#define S0IX_BLK_SIZE 4
26
27/* Sunrise Point Power Management Controller PCI Device ID */
28#define SPT_PMC_PCI_DEVICE_ID 0x9d21
29#define SPT_PMC_BASE_ADDR_OFFSET 0x48
30#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
31#define SPT_PMC_PM_CFG_OFFSET 0x18
32#define SPT_PMC_PM_STS_OFFSET 0x1c
33#define SPT_PMC_MTPMC_OFFSET 0x20
34#define SPT_PMC_MFPMC_OFFSET 0x38
35#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
36#define SPT_PMC_VRIC1_OFFSET 0x31c
37#define SPT_PMC_MPHY_CORE_STS_0 0x1143
38#define SPT_PMC_MPHY_CORE_STS_1 0x1142
39#define SPT_PMC_MPHY_COM_STS_0 0x1155
40#define SPT_PMC_MMIO_REG_LEN 0x1000
41#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68
42#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
43#define MTPMC_MASK 0xffff0000
44#define PPFEAR_MAX_NUM_ENTRIES 12
45#define SPT_PPFEAR_NUM_ENTRIES 5
46#define SPT_PMC_READ_DISABLE_BIT 0x16
47#define SPT_PMC_MSG_FULL_STS_BIT 0x18
48#define NUM_RETRIES 100
49#define SPT_NUM_IP_IGN_ALLOWED 17
50
51#define SPT_PMC_LTR_CUR_PLT 0x350
52#define SPT_PMC_LTR_CUR_ASLT 0x354
53#define SPT_PMC_LTR_SPA 0x360
54#define SPT_PMC_LTR_SPB 0x364
55#define SPT_PMC_LTR_SATA 0x368
56#define SPT_PMC_LTR_GBE 0x36C
57#define SPT_PMC_LTR_XHCI 0x370
58#define SPT_PMC_LTR_RESERVED 0x374
59#define SPT_PMC_LTR_ME 0x378
60#define SPT_PMC_LTR_EVA 0x37C
61#define SPT_PMC_LTR_SPC 0x380
62#define SPT_PMC_LTR_AZ 0x384
63#define SPT_PMC_LTR_LPSS 0x38C
64#define SPT_PMC_LTR_CAM 0x390
65#define SPT_PMC_LTR_SPD 0x394
66#define SPT_PMC_LTR_SPE 0x398
67#define SPT_PMC_LTR_ESPI 0x39C
68#define SPT_PMC_LTR_SCC 0x3A0
69#define SPT_PMC_LTR_ISH 0x3A4
70
71/* Sunrise Point: PGD PFET Enable Ack Status Registers */
72enum ppfear_regs {
73 SPT_PMC_XRAM_PPFEAR0A = 0x590,
74 SPT_PMC_XRAM_PPFEAR0B,
75 SPT_PMC_XRAM_PPFEAR0C,
76 SPT_PMC_XRAM_PPFEAR0D,
77 SPT_PMC_XRAM_PPFEAR1A,
78};
79
80#define SPT_PMC_BIT_PMC BIT(0)
81#define SPT_PMC_BIT_OPI BIT(1)
82#define SPT_PMC_BIT_SPI BIT(2)
83#define SPT_PMC_BIT_XHCI BIT(3)
84#define SPT_PMC_BIT_SPA BIT(4)
85#define SPT_PMC_BIT_SPB BIT(5)
86#define SPT_PMC_BIT_SPC BIT(6)
87#define SPT_PMC_BIT_GBE BIT(7)
88
89#define SPT_PMC_BIT_SATA BIT(0)
90#define SPT_PMC_BIT_HDA_PGD0 BIT(1)
91#define SPT_PMC_BIT_HDA_PGD1 BIT(2)
92#define SPT_PMC_BIT_HDA_PGD2 BIT(3)
93#define SPT_PMC_BIT_HDA_PGD3 BIT(4)
94#define SPT_PMC_BIT_RSVD_0B BIT(5)
95#define SPT_PMC_BIT_LPSS BIT(6)
96#define SPT_PMC_BIT_LPC BIT(7)
97
98#define SPT_PMC_BIT_SMB BIT(0)
99#define SPT_PMC_BIT_ISH BIT(1)
100#define SPT_PMC_BIT_P2SB BIT(2)
101#define SPT_PMC_BIT_DFX BIT(3)
102#define SPT_PMC_BIT_SCC BIT(4)
103#define SPT_PMC_BIT_RSVD_0C BIT(5)
104#define SPT_PMC_BIT_FUSE BIT(6)
105#define SPT_PMC_BIT_CAMREA BIT(7)
106
107#define SPT_PMC_BIT_RSVD_0D BIT(0)
108#define SPT_PMC_BIT_USB3_OTG BIT(1)
109#define SPT_PMC_BIT_EXI BIT(2)
110#define SPT_PMC_BIT_CSE BIT(3)
111#define SPT_PMC_BIT_CSME_KVM BIT(4)
112#define SPT_PMC_BIT_CSME_PMT BIT(5)
113#define SPT_PMC_BIT_CSME_CLINK BIT(6)
114#define SPT_PMC_BIT_CSME_PTIO BIT(7)
115
116#define SPT_PMC_BIT_CSME_USBR BIT(0)
117#define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
118#define SPT_PMC_BIT_CSME_SMT BIT(2)
119#define SPT_PMC_BIT_RSVD_1A BIT(3)
120#define SPT_PMC_BIT_CSME_SMS2 BIT(4)
121#define SPT_PMC_BIT_CSME_SMS1 BIT(5)
122#define SPT_PMC_BIT_CSME_RTC BIT(6)
123#define SPT_PMC_BIT_CSME_PSF BIT(7)
124
125#define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
126#define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
127#define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
128#define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
129#define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
130#define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
131#define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
132#define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
133
134#define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
135#define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
136#define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
137#define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
138#define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
139#define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
140#define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
141#define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
142
143#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
144#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
145#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
146#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
147
148#define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
149#define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
150
151/* Cannonlake Power Management Controller register offsets */
152#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
153#define CNP_PMC_PM_CFG_OFFSET 0x1818
154#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
155#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
156/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
157#define CNP_PMC_HOST_PPFEAR0A 0x1D90
158
159#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
160
161#define CNP_PMC_MMIO_REG_LEN 0x2000
162#define CNP_PPFEAR_NUM_ENTRIES 8
163#define CNP_PMC_READ_DISABLE_BIT 22
164#define CNP_NUM_IP_IGN_ALLOWED 19
165#define CNP_PMC_LTR_CUR_PLT 0x1B50
166#define CNP_PMC_LTR_CUR_ASLT 0x1B54
167#define CNP_PMC_LTR_SPA 0x1B60
168#define CNP_PMC_LTR_SPB 0x1B64
169#define CNP_PMC_LTR_SATA 0x1B68
170#define CNP_PMC_LTR_GBE 0x1B6C
171#define CNP_PMC_LTR_XHCI 0x1B70
172#define CNP_PMC_LTR_RESERVED 0x1B74
173#define CNP_PMC_LTR_ME 0x1B78
174#define CNP_PMC_LTR_EVA 0x1B7C
175#define CNP_PMC_LTR_SPC 0x1B80
176#define CNP_PMC_LTR_AZ 0x1B84
177#define CNP_PMC_LTR_LPSS 0x1B8C
178#define CNP_PMC_LTR_CAM 0x1B90
179#define CNP_PMC_LTR_SPD 0x1B94
180#define CNP_PMC_LTR_SPE 0x1B98
181#define CNP_PMC_LTR_ESPI 0x1B9C
182#define CNP_PMC_LTR_SCC 0x1BA0
183#define CNP_PMC_LTR_ISH 0x1BA4
184#define CNP_PMC_LTR_CNV 0x1BF0
185#define CNP_PMC_LTR_EMMC 0x1BF4
186#define CNP_PMC_LTR_UFSX2 0x1BF8
187
188#define LTR_DECODED_VAL GENMASK(9, 0)
189#define LTR_DECODED_SCALE GENMASK(12, 10)
190#define LTR_REQ_SNOOP BIT(15)
191#define LTR_REQ_NONSNOOP BIT(31)
192
193#define ICL_PPFEAR_NUM_ENTRIES 9
194#define ICL_NUM_IP_IGN_ALLOWED 20
195#define ICL_PMC_LTR_WIGIG 0x1BFC
196#define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64
197
198#define LPM_MAX_NUM_MODES 8
199#define LPM_DEFAULT_PRI { 7, 6, 2, 5, 4, 1, 3, 0 }
200
201#define GET_X2_COUNTER(v) ((v) >> 1)
202#define LPM_STS_LATCH_MODE BIT(31)
203
204#define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A
205#define TGL_PMC_LTR_THC0 0x1C04
206#define TGL_PMC_LTR_THC1 0x1C08
207#define TGL_NUM_IP_IGN_ALLOWED 23
208#define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */
209
210#define ADL_PMC_LTR_SPF 0x1C00
211#define ADL_NUM_IP_IGN_ALLOWED 23
212#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098
213
214/*
215 * Tigerlake Power Management Controller register offsets
216 */
217#define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34
218#define TGL_LPM_EN_OFFSET 0x1C78
219#define TGL_LPM_RESIDENCY_OFFSET 0x1C80
220
221/* Tigerlake Low Power Mode debug registers */
222#define TGL_LPM_STATUS_OFFSET 0x1C3C
223#define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C
224#define TGL_LPM_PRI_OFFSET 0x1C7C
225#define TGL_LPM_NUM_MAPS 6
226
227/* Tigerlake PSON residency register */
228#define TGL_PSON_RESIDENCY_OFFSET 0x18f8
229#define TGL_PSON_RES_COUNTER_STEP 0x7A
230
231/* Extended Test Mode Register 3 (CNL and later) */
232#define ETR3_OFFSET 0x1048
233#define ETR3_CF9GR BIT(20)
234#define ETR3_CF9LOCK BIT(31)
235
236/* Extended Test Mode Register LPM bits (TGL and later */
237#define ETR3_CLEAR_LPM_EVENTS BIT(28)
238
239/* Alder Lake Power Management Controller register offsets */
240#define ADL_LPM_EN_OFFSET 0x179C
241#define ADL_LPM_RESIDENCY_OFFSET 0x17A4
242#define ADL_LPM_NUM_MODES 2
243#define ADL_LPM_NUM_MAPS 14
244
245/* Alder Lake Low Power Mode debug registers */
246#define ADL_LPM_STATUS_OFFSET 0x170C
247#define ADL_LPM_PRI_OFFSET 0x17A0
248#define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704
249#define ADL_LPM_LIVE_STATUS_OFFSET 0x1764
250
251/* Meteor Lake Power Management Controller register offsets */
252#define MTL_LPM_EN_OFFSET 0x1798
253#define MTL_LPM_RESIDENCY_OFFSET 0x17A0
254
255/* Meteor Lake Low Power Mode debug registers */
256#define MTL_LPM_PRI_OFFSET 0x179C
257#define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8
258#define MTL_LPM_STATUS_OFFSET 0x1700
259#define MTL_LPM_LIVE_STATUS_OFFSET 0x175C
260#define MTL_PMC_LTR_IOE_PMC 0x1C0C
261#define MTL_PMC_LTR_ESE 0x1BAC
262#define MTL_PMC_LTR_RESERVED 0x1BA4
263#define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4
264#define MTL_SOCM_NUM_IP_IGN_ALLOWED 25
265#define MTL_SOC_PMC_MMIO_REG_LEN 0x2708
266#define MTL_PMC_LTR_SPG 0x1B74
267#define ARL_SOCS_PMC_LTR_RESERVED 0x1B88
268#define ARL_SOCS_NUM_IP_IGN_ALLOWED 26
269#define ARL_PMC_LTR_DMI3 0x1BE4
270#define ARL_PCH_PMC_MMIO_REG_LEN 0x2720
271
272/* Meteor Lake PGD PFET Enable Ack Status */
273#define MTL_SOCM_PPFEAR_NUM_ENTRIES 8
274#define MTL_IOE_PPFEAR_NUM_ENTRIES 10
275#define ARL_SOCS_PPFEAR_NUM_ENTRIES 9
276
277/* Die C6 from PUNIT telemetry */
278#define MTL_PMT_DMU_DIE_C6_OFFSET 15
279#define MTL_PMT_DMU_GUID 0x1A067102
280#define ARL_PMT_DMU_GUID 0x1A06A000
281
282#define LNL_PMC_MMIO_REG_LEN 0x2708
283#define LNL_PMC_LTR_OSSE 0x1B88
284#define LNL_NUM_IP_IGN_ALLOWED 27
285#define LNL_PPFEAR_NUM_ENTRIES 12
286#define LNL_S0IX_BLOCKER_OFFSET 0x2004
287
288extern const char *pmc_lpm_modes[];
289
290struct pmc_bit_map {
291 const char *name;
292 u32 bit_mask;
293 u8 blk;
294};
295
296/**
297 * struct pmc_reg_map - Structure used to define parameter unique to a
298 PCH family
299 * @pfear_sts: Maps name of IP block to PPFEAR* bit
300 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
301 * @pll_sts: Maps name of PLL to corresponding bit status
302 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
303 * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets
304 * @s0ix_blocker_maps: Maps name of IP block to S0ix blocker counter
305 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
306 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
307 * @regmap_length: Length of memory to map from PWRMBASE address to access
308 * @ppfear0_offset: PWRMBASE offset to read PPFEAR*
309 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
310 * PPFEAR
311 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register
312 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
313 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
314 * @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter
315 *
316 * Each PCH has unique set of register offsets and bit indexes. This structure
317 * captures them to have a common implementation.
318 */
319struct pmc_reg_map {
320 const struct pmc_bit_map **pfear_sts;
321 const struct pmc_bit_map *mphy_sts;
322 const struct pmc_bit_map *pll_sts;
323 const struct pmc_bit_map **slps0_dbg_maps;
324 const struct pmc_bit_map *ltr_show_sts;
325 const struct pmc_bit_map *msr_sts;
326 const struct pmc_bit_map **lpm_sts;
327 const struct pmc_bit_map **s0ix_blocker_maps;
328 const u32 slp_s0_offset;
329 const int slp_s0_res_counter_step;
330 const u32 ltr_ignore_offset;
331 const int regmap_length;
332 const u32 ppfear0_offset;
333 const int ppfear_buckets;
334 const u32 pm_cfg_offset;
335 const int pm_read_disable_bit;
336 const u32 slps0_dbg_offset;
337 const u32 ltr_ignore_max;
338 const u32 pm_vric1_offset;
339 const u32 s0ix_blocker_offset;
340 /* Low Power Mode registers */
341 const int lpm_num_maps;
342 const int lpm_num_modes;
343 const int lpm_res_counter_step_x2;
344 const u32 lpm_sts_latch_en_offset;
345 const u32 lpm_en_offset;
346 const u32 lpm_priority_offset;
347 const u32 lpm_residency_offset;
348 const u32 lpm_status_offset;
349 const u32 lpm_live_status_offset;
350 const u32 etr3_offset;
351 const u8 *lpm_reg_index;
352 const u32 pson_residency_offset;
353 const u32 pson_residency_counter_step;
354};
355
356/**
357 * struct pmc_info - Structure to keep pmc info
358 * @devid: device id of the pmc device
359 * @map: pointer to a pmc_reg_map struct that contains platform
360 * specific attributes
361 */
362struct pmc_info {
363 u32 guid;
364 u16 devid;
365 const struct pmc_reg_map *map;
366};
367
368/**
369 * struct pmc - pmc private info structure
370 * @base_addr: contains pmc base address
371 * @regbase: pointer to io-remapped memory location
372 * @map: pointer to pmc_reg_map struct that contains platform
373 * specific attributes
374 * @lpm_req_regs: List of substate requirements
375 * @ltr_ign: Holds LTR ignore data while suspended
376 *
377 * pmc contains info about one power management controller device.
378 */
379struct pmc {
380 u64 base_addr;
381 void __iomem *regbase;
382 const struct pmc_reg_map *map;
383 u32 *lpm_req_regs;
384 u32 ltr_ign;
385};
386
387/**
388 * struct pmc_dev - pmc device structure
389 * @devs: pointer to an array of pmc pointers
390 * @pdev: pointer to platform_device struct
391 * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM
392 * @crystal_freq: crystal frequency from cpuid
393 * @dbgfs_dir: path to debugfs interface
394 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
395 * used to read MPHY PG and PLL status are available
396 * @mutex_lock: mutex to complete one transcation
397 * @pkgc_res_cnt: Array of PKGC residency counters
398 * @num_of_pkgc: Number of PKGC
399 * @s0ix_counter: S0ix residency (step adjusted)
400 * @num_lpm_modes: Count of enabled modes
401 * @lpm_en_modes: Array of enabled modes from lowest to highest priority
402 * @suspend: Function to perform platform specific suspend
403 * @resume: Function to perform platform specific resume
404 *
405 * pmc_dev contains info about power management controller device.
406 */
407struct pmc_dev {
408 struct pmc *pmcs[MAX_NUM_PMC];
409 struct dentry *dbgfs_dir;
410 struct platform_device *pdev;
411 struct pci_dev *ssram_pcidev;
412 unsigned int crystal_freq;
413 int pmc_xram_read_bit;
414 struct mutex lock; /* generic mutex lock for PMC Core */
415
416 u64 s0ix_counter;
417 int num_lpm_modes;
418 int lpm_en_modes[LPM_MAX_NUM_MODES];
419 void (*suspend)(struct pmc_dev *pmcdev);
420 int (*resume)(struct pmc_dev *pmcdev);
421
422 u64 *pkgc_res_cnt;
423 u8 num_of_pkgc;
424
425 bool has_die_c6;
426 u32 die_c6_offset;
427 struct telem_endpoint *punit_ep;
428 struct pmc_info *regmap_list;
429};
430
431enum pmc_index {
432 PMC_IDX_MAIN,
433 PMC_IDX_SOC = PMC_IDX_MAIN,
434 PMC_IDX_IOE,
435 PMC_IDX_PCH,
436 PMC_IDX_MAX
437};
438
439extern const struct pmc_bit_map msr_map[];
440extern const struct pmc_bit_map spt_pll_map[];
441extern const struct pmc_bit_map spt_mphy_map[];
442extern const struct pmc_bit_map spt_pfear_map[];
443extern const struct pmc_bit_map *ext_spt_pfear_map[];
444extern const struct pmc_bit_map spt_ltr_show_map[];
445extern const struct pmc_reg_map spt_reg_map;
446extern const struct pmc_bit_map cnp_pfear_map[];
447extern const struct pmc_bit_map *ext_cnp_pfear_map[];
448extern const struct pmc_bit_map cnp_slps0_dbg0_map[];
449extern const struct pmc_bit_map cnp_slps0_dbg1_map[];
450extern const struct pmc_bit_map cnp_slps0_dbg2_map[];
451extern const struct pmc_bit_map *cnp_slps0_dbg_maps[];
452extern const struct pmc_bit_map cnp_ltr_show_map[];
453extern const struct pmc_reg_map cnp_reg_map;
454extern const struct pmc_bit_map icl_pfear_map[];
455extern const struct pmc_bit_map *ext_icl_pfear_map[];
456extern const struct pmc_reg_map icl_reg_map;
457extern const struct pmc_bit_map tgl_pfear_map[];
458extern const struct pmc_bit_map *ext_tgl_pfear_map[];
459extern const struct pmc_bit_map tgl_clocksource_status_map[];
460extern const struct pmc_bit_map tgl_power_gating_status_map[];
461extern const struct pmc_bit_map tgl_d3_status_map[];
462extern const struct pmc_bit_map tgl_vnn_req_status_map[];
463extern const struct pmc_bit_map tgl_vnn_misc_status_map[];
464extern const struct pmc_bit_map tgl_signal_status_map[];
465extern const struct pmc_bit_map *tgl_lpm_maps[];
466extern const struct pmc_reg_map tgl_reg_map;
467extern const struct pmc_reg_map tgl_h_reg_map;
468extern const struct pmc_bit_map adl_pfear_map[];
469extern const struct pmc_bit_map *ext_adl_pfear_map[];
470extern const struct pmc_bit_map adl_ltr_show_map[];
471extern const struct pmc_bit_map adl_clocksource_status_map[];
472extern const struct pmc_bit_map adl_power_gating_status_0_map[];
473extern const struct pmc_bit_map adl_power_gating_status_1_map[];
474extern const struct pmc_bit_map adl_power_gating_status_2_map[];
475extern const struct pmc_bit_map adl_d3_status_0_map[];
476extern const struct pmc_bit_map adl_d3_status_1_map[];
477extern const struct pmc_bit_map adl_d3_status_2_map[];
478extern const struct pmc_bit_map adl_d3_status_3_map[];
479extern const struct pmc_bit_map adl_vnn_req_status_0_map[];
480extern const struct pmc_bit_map adl_vnn_req_status_1_map[];
481extern const struct pmc_bit_map adl_vnn_req_status_2_map[];
482extern const struct pmc_bit_map adl_vnn_req_status_3_map[];
483extern const struct pmc_bit_map adl_vnn_misc_status_map[];
484extern const struct pmc_bit_map *adl_lpm_maps[];
485extern const struct pmc_reg_map adl_reg_map;
486extern const struct pmc_bit_map mtl_socm_pfear_map[];
487extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[];
488extern const struct pmc_bit_map mtl_socm_ltr_show_map[];
489extern const struct pmc_bit_map mtl_socm_clocksource_status_map[];
490extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[];
491extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[];
492extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[];
493extern const struct pmc_bit_map mtl_socm_d3_status_0_map[];
494extern const struct pmc_bit_map mtl_socm_d3_status_1_map[];
495extern const struct pmc_bit_map mtl_socm_d3_status_2_map[];
496extern const struct pmc_bit_map mtl_socm_d3_status_3_map[];
497extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[];
498extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[];
499extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[];
500extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[];
501extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[];
502extern const struct pmc_bit_map mtl_socm_signal_status_map[];
503extern const struct pmc_bit_map *mtl_socm_lpm_maps[];
504extern const struct pmc_reg_map mtl_socm_reg_map;
505extern const struct pmc_bit_map mtl_ioep_pfear_map[];
506extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[];
507extern const struct pmc_bit_map mtl_ioep_ltr_show_map[];
508extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[];
509extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[];
510extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[];
511extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[];
512extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[];
513extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[];
514extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[];
515extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[];
516extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[];
517extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[];
518extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[];
519extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[];
520extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[];
521extern const struct pmc_bit_map *mtl_ioep_lpm_maps[];
522extern const struct pmc_reg_map mtl_ioep_reg_map;
523extern const struct pmc_bit_map mtl_ioem_pfear_map[];
524extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[];
525extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[];
526extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[];
527extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
528extern const struct pmc_reg_map mtl_ioem_reg_map;
529extern const struct pmc_reg_map lnl_socm_reg_map;
530
531/* LNL */
532extern const struct pmc_bit_map lnl_ltr_show_map[];
533extern const struct pmc_bit_map lnl_clocksource_status_map[];
534extern const struct pmc_bit_map lnl_power_gating_status_0_map[];
535extern const struct pmc_bit_map lnl_power_gating_status_1_map[];
536extern const struct pmc_bit_map lnl_power_gating_status_2_map[];
537extern const struct pmc_bit_map lnl_d3_status_0_map[];
538extern const struct pmc_bit_map lnl_d3_status_1_map[];
539extern const struct pmc_bit_map lnl_d3_status_2_map[];
540extern const struct pmc_bit_map lnl_d3_status_3_map[];
541extern const struct pmc_bit_map lnl_vnn_req_status_0_map[];
542extern const struct pmc_bit_map lnl_vnn_req_status_1_map[];
543extern const struct pmc_bit_map lnl_vnn_req_status_2_map[];
544extern const struct pmc_bit_map lnl_vnn_req_status_3_map[];
545extern const struct pmc_bit_map lnl_vnn_misc_status_map[];
546extern const struct pmc_bit_map *lnl_lpm_maps[];
547extern const struct pmc_bit_map *lnl_blk_maps[];
548extern const struct pmc_bit_map lnl_pfear_map[];
549extern const struct pmc_bit_map *ext_lnl_pfear_map[];
550extern const struct pmc_bit_map lnl_signal_status_map[];
551
552/* ARL */
553extern const struct pmc_bit_map arl_socs_ltr_show_map[];
554extern const struct pmc_bit_map arl_socs_clocksource_status_map[];
555extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[];
556extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[];
557extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[];
558extern const struct pmc_bit_map arl_socs_d3_status_2_map[];
559extern const struct pmc_bit_map arl_socs_d3_status_3_map[];
560extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[];
561extern const struct pmc_bit_map *arl_socs_lpm_maps[];
562extern const struct pmc_bit_map arl_socs_pfear_map[];
563extern const struct pmc_bit_map *ext_arl_socs_pfear_map[];
564extern const struct pmc_reg_map arl_socs_reg_map;
565extern const struct pmc_bit_map arl_pchs_ltr_show_map[];
566extern const struct pmc_bit_map arl_pchs_clocksource_status_map[];
567extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[];
568extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[];
569extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[];
570extern const struct pmc_bit_map arl_pchs_d3_status_0_map[];
571extern const struct pmc_bit_map arl_pchs_d3_status_1_map[];
572extern const struct pmc_bit_map arl_pchs_d3_status_2_map[];
573extern const struct pmc_bit_map arl_pchs_d3_status_3_map[];
574extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[];
575extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[];
576extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[];
577extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[];
578extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[];
579extern const struct pmc_bit_map arl_pchs_signal_status_map[];
580extern const struct pmc_bit_map *arl_pchs_lpm_maps[];
581extern const struct pmc_reg_map arl_pchs_reg_map;
582
583extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
584extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);
585int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
586
587int pmc_core_resume_common(struct pmc_dev *pmcdev);
588int get_primary_reg_base(struct pmc *pmc);
589extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev);
590extern void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid);
591extern void pmc_core_set_device_d3(unsigned int device);
592
593extern int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func);
594
595int spt_core_init(struct pmc_dev *pmcdev);
596int cnp_core_init(struct pmc_dev *pmcdev);
597int icl_core_init(struct pmc_dev *pmcdev);
598int tgl_core_init(struct pmc_dev *pmcdev);
599int tgl_l_core_init(struct pmc_dev *pmcdev);
600int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp);
601int adl_core_init(struct pmc_dev *pmcdev);
602int mtl_core_init(struct pmc_dev *pmcdev);
603int arl_core_init(struct pmc_dev *pmcdev);
604int lnl_core_init(struct pmc_dev *pmcdev);
605
606void cnl_suspend(struct pmc_dev *pmcdev);
607int cnl_resume(struct pmc_dev *pmcdev);
608
609#define pmc_for_each_mode(mode, pmcdev) \
610 for (unsigned int __i = 0, __cond; \
611 __cond = __i < (pmcdev)->num_lpm_modes, \
612 __cond && ((mode) = (pmcdev)->lpm_en_modes[__i]), \
613 __cond; \
614 __i++)
615
616#define DEFINE_PMC_CORE_ATTR_WRITE(__name) \
617static int __name ## _open(struct inode *inode, struct file *file) \
618{ \
619 return single_open(file, __name ## _show, inode->i_private); \
620} \
621 \
622static const struct file_operations __name ## _fops = { \
623 .owner = THIS_MODULE, \
624 .open = __name ## _open, \
625 .read = seq_read, \
626 .write = __name ## _write, \
627 .release = single_release, \
628}
629
630#endif /* PMC_CORE_H */