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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Samsung Exynos5 SoC series USB DRD PHY driver
4 *
5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
6 *
7 * Copyright (C) 2014 Samsung Electronics Co., Ltd.
8 * Author: Vivek Gautam <gautam.vivek@samsung.com>
9 */
10
11#include <linux/bitfield.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/iopoll.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/mutex.h>
22#include <linux/mfd/syscon.h>
23#include <linux/regmap.h>
24#include <linux/regulator/consumer.h>
25#include <linux/soc/samsung/exynos-regs-pmu.h>
26
27/* Exynos USB PHY registers */
28#define EXYNOS5_FSEL_9MHZ6 0x0
29#define EXYNOS5_FSEL_10MHZ 0x1
30#define EXYNOS5_FSEL_12MHZ 0x2
31#define EXYNOS5_FSEL_19MHZ2 0x3
32#define EXYNOS5_FSEL_20MHZ 0x4
33#define EXYNOS5_FSEL_24MHZ 0x5
34#define EXYNOS5_FSEL_26MHZ 0x6
35#define EXYNOS5_FSEL_50MHZ 0x7
36
37/* Exynos5: USB 3.0 DRD PHY registers */
38#define EXYNOS5_DRD_LINKSYSTEM 0x04
39#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
40#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
41#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
42
43#define EXYNOS5_DRD_PHYUTMI 0x08
44#define PHYUTMI_OTGDISABLE BIT(6)
45#define PHYUTMI_FORCESUSPEND BIT(1)
46#define PHYUTMI_FORCESLEEP BIT(0)
47
48#define EXYNOS5_DRD_PHYPIPE 0x0c
49
50#define EXYNOS5_DRD_PHYCLKRST 0x10
51#define PHYCLKRST_EN_UTMISUSPEND BIT(31)
52#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
53#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
54#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
55#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
56#define PHYCLKRST_SSC_EN BIT(20)
57#define PHYCLKRST_REF_SSP_EN BIT(19)
58#define PHYCLKRST_REF_CLKDIV2 BIT(18)
59#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
60#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
61#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
62#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
63#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
64#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
65#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
66#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
67#define PHYCLKRST_FSEL(_x) ((_x) << 5)
68#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
69#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
70#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
71#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
72#define PHYCLKRST_RETENABLEN BIT(4)
73#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
74#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
75#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
76#define PHYCLKRST_PORTRESET BIT(1)
77#define PHYCLKRST_COMMONONN BIT(0)
78
79#define EXYNOS5_DRD_PHYREG0 0x14
80#define PHYREG0_SSC_REF_CLK_SEL BIT(21)
81#define PHYREG0_SSC_RANGE BIT(20)
82#define PHYREG0_CR_WRITE BIT(19)
83#define PHYREG0_CR_READ BIT(18)
84#define PHYREG0_CR_DATA_IN(_x) ((_x) << 2)
85#define PHYREG0_CR_CAP_DATA BIT(1)
86#define PHYREG0_CR_CAP_ADDR BIT(0)
87
88#define EXYNOS5_DRD_PHYREG1 0x18
89#define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1)
90#define PHYREG1_CR_ACK BIT(0)
91
92#define EXYNOS5_DRD_PHYPARAM0 0x1c
93#define PHYPARAM0_REF_USE_PAD BIT(31)
94#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
95#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
96
97#define EXYNOS5_DRD_PHYPARAM1 0x20
98#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
99#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
100
101#define EXYNOS5_DRD_PHYTERM 0x24
102
103#define EXYNOS5_DRD_PHYTEST 0x28
104#define PHYTEST_POWERDOWN_SSP BIT(3)
105#define PHYTEST_POWERDOWN_HSP BIT(2)
106
107#define EXYNOS5_DRD_PHYADP 0x2c
108
109#define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
110#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
111
112#define EXYNOS5_DRD_PHYRESUME 0x34
113
114#define EXYNOS5_DRD_LINKPORT 0x44
115
116/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
117#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15)
118#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13)
119#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13)
120#define LOSLEVEL_OVRD_IN_EN (0x1 << 10)
121#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0)
122
123#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12)
124#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13)
125#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13)
126
127#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010)
128#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4)
129#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4)
130#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4)
131#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4)
132#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4)
133#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4)
134
135/* Exynos850: USB DRD PHY registers */
136#define EXYNOS850_DRD_LINKCTRL 0x04
137#define LINKCTRL_FORCE_RXELECIDLE BIT(18)
138#define LINKCTRL_FORCE_PHYSTATUS BIT(17)
139#define LINKCTRL_FORCE_PIPE_EN BIT(16)
140#define LINKCTRL_FORCE_QACT BIT(8)
141#define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4)
142
143#define EXYNOS850_DRD_LINKPORT 0x08
144#define LINKPORT_HOST_NUM_U3 GENMASK(19, 16)
145#define LINKPORT_HOST_NUM_U2 GENMASK(15, 12)
146
147#define EXYNOS850_DRD_CLKRST 0x20
148/*
149 * On versions without SS ports (like E850), bit 3 is for the 2.0 phy (HS),
150 * while on versions with (like gs101), bits 2 and 3 are for the 3.0 phy (SS)
151 * and bits 12 & 13 for the 2.0 phy.
152 */
153#define CLKRST_PHY20_SW_POR BIT(13)
154#define CLKRST_PHY20_SW_POR_SEL BIT(12)
155#define CLKRST_LINK_PCLK_SEL BIT(7)
156#define CLKRST_PHY_SW_RST BIT(3)
157#define CLKRST_PHY_RESET_SEL BIT(2)
158#define CLKRST_PORT_RST BIT(1)
159#define CLKRST_LINK_SW_RST BIT(0)
160
161#define EXYNOS850_DRD_SSPPLLCTL 0x30
162#define SSPPLLCTL_FSEL GENMASK(2, 0)
163
164#define EXYNOS850_DRD_UTMI 0x50
165#define UTMI_FORCE_VBUSVALID BIT(5)
166#define UTMI_FORCE_BVALID BIT(4)
167#define UTMI_DP_PULLDOWN BIT(3)
168#define UTMI_DM_PULLDOWN BIT(2)
169#define UTMI_FORCE_SUSPEND BIT(1)
170#define UTMI_FORCE_SLEEP BIT(0)
171
172#define EXYNOS850_DRD_HSP 0x54
173#define HSP_FSV_OUT_EN BIT(24)
174#define HSP_VBUSVLDEXTSEL BIT(13)
175#define HSP_VBUSVLDEXT BIT(12)
176#define HSP_EN_UTMISUSPEND BIT(9)
177#define HSP_COMMONONN BIT(8)
178
179#define EXYNOS850_DRD_HSPPARACON 0x58
180#define HSPPARACON_TXVREF GENMASK(31, 28)
181#define HSPPARACON_TXRISE GENMASK(25, 24)
182#define HSPPARACON_TXRES GENMASK(22, 21)
183#define HSPPARACON_TXPREEMPPULSE BIT(20)
184#define HSPPARACON_TXPREEMPAMP GENMASK(19, 18)
185#define HSPPARACON_TXHSXV GENMASK(17, 16)
186#define HSPPARACON_TXFSLS GENMASK(15, 12)
187#define HSPPARACON_SQRX GENMASK(10, 8)
188#define HSPPARACON_OTG GENMASK(6, 4)
189#define HSPPARACON_COMPDIS GENMASK(2, 0)
190
191#define EXYNOS850_DRD_HSP_TEST 0x5c
192#define HSP_TEST_SIDDQ BIT(24)
193
194/* Exynos9 - GS101 */
195#define EXYNOS850_DRD_SECPMACTL 0x48
196#define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12)
197#define SECPMACTL_PMA_LCPLL_REF_CLK_SEL GENMASK(11, 10)
198#define SECPMACTL_PMA_REF_FREQ_SEL GENMASK(9, 8)
199#define SECPMACTL_PMA_LOW_PWR BIT(4)
200#define SECPMACTL_PMA_TRSV_SW_RST BIT(3)
201#define SECPMACTL_PMA_CMN_SW_RST BIT(2)
202#define SECPMACTL_PMA_INIT_SW_RST BIT(1)
203#define SECPMACTL_PMA_APB_SW_RST BIT(0)
204
205/* PMA registers */
206#define EXYNOS9_PMA_USBDP_CMN_REG0008 0x0020
207#define CMN_REG0008_OVRD_AUX_EN BIT(3)
208#define CMN_REG0008_AUX_EN BIT(2)
209
210#define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0
211#define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0)
212
213#define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700
214#define CMN_REG01C0_ANA_LCPLL_LOCK_DONE BIT(7)
215#define CMN_REG01C0_ANA_LCPLL_AFC_DONE BIT(6)
216
217/* these have similar register layout, for lanes 0 and 2 */
218#define EXYNOS9_PMA_USBDP_TRSV_REG03C3 0x0f0c
219#define EXYNOS9_PMA_USBDP_TRSV_REG07C3 0x1f0c
220#define TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE BIT(3)
221#define TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE BIT(2)
222#define TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE BIT(1)
223#define TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE BIT(0)
224
225/* TRSV_REG0413 and TRSV_REG0813 have similar register layout */
226#define EXYNOS9_PMA_USBDP_TRSV_REG0413 0x104c
227#define TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN BIT(7)
228#define TRSV_REG0413_OVRD_LN1_TX_RXD_EN BIT(5)
229
230#define EXYNOS9_PMA_USBDP_TRSV_REG0813 0x204c
231#define TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN BIT(7)
232#define TRSV_REG0813_OVRD_LN3_TX_RXD_EN BIT(5)
233
234/* PCS registers */
235#define EXYNOS9_PCS_NS_VEC_PS1_N1 0x010c
236#define EXYNOS9_PCS_NS_VEC_PS2_N0 0x0110
237#define EXYNOS9_PCS_NS_VEC_PS3_N0 0x0118
238#define NS_VEC_NS_REQ GENMASK(31, 24)
239#define NS_VEC_ENABLE_TIMER BIT(22)
240#define NS_VEC_SEL_TIMEOUT GENMASK(21, 20)
241#define NS_VEC_INV_MASK GENMASK(19, 16)
242#define NS_VEC_COND_MASK GENMASK(11, 8)
243#define NS_VEC_EXP_COND GENMASK(3, 0)
244
245#define EXYNOS9_PCS_OUT_VEC_2 0x014c
246#define EXYNOS9_PCS_OUT_VEC_3 0x0150
247#define PCS_OUT_VEC_B9_DYNAMIC BIT(19)
248#define PCS_OUT_VEC_B9_SEL_OUT BIT(18)
249#define PCS_OUT_VEC_B8_DYNAMIC BIT(17)
250#define PCS_OUT_VEC_B8_SEL_OUT BIT(16)
251#define PCS_OUT_VEC_B7_DYNAMIC BIT(15)
252#define PCS_OUT_VEC_B7_SEL_OUT BIT(14)
253#define PCS_OUT_VEC_B6_DYNAMIC BIT(13)
254#define PCS_OUT_VEC_B6_SEL_OUT BIT(12)
255#define PCS_OUT_VEC_B5_DYNAMIC BIT(11)
256#define PCS_OUT_VEC_B5_SEL_OUT BIT(10)
257#define PCS_OUT_VEC_B4_DYNAMIC BIT(9)
258#define PCS_OUT_VEC_B4_SEL_OUT BIT(8)
259#define PCS_OUT_VEC_B3_DYNAMIC BIT(7)
260#define PCS_OUT_VEC_B3_SEL_OUT BIT(6)
261#define PCS_OUT_VEC_B2_DYNAMIC BIT(5)
262#define PCS_OUT_VEC_B2_SEL_OUT BIT(4)
263#define PCS_OUT_VEC_B1_DYNAMIC BIT(3)
264#define PCS_OUT_VEC_B1_SEL_OUT BIT(2)
265#define PCS_OUT_VEC_B0_DYNAMIC BIT(1)
266#define PCS_OUT_VEC_B0_SEL_OUT BIT(0)
267
268#define EXYNOS9_PCS_TIMEOUT_0 0x0170
269
270#define EXYNOS9_PCS_TIMEOUT_3 0x017c
271
272#define EXYNOS9_PCS_EBUF_PARAM 0x0304
273#define EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE GENMASK(29, 24)
274
275#define EXYNOS9_PCS_BACK_END_MODE_VEC 0x030c
276#define BACK_END_MODE_VEC_FORCE_EBUF_EMPTY_MODE BIT(1)
277#define BACK_END_MODE_VEC_DISABLE_DATA_MASK BIT(0)
278
279#define EXYNOS9_PCS_RX_CONTROL 0x03f0
280#define RX_CONTROL_EN_BLOCK_ALIGNER_TYPE_B BIT(22)
281
282#define EXYNOS9_PCS_RX_CONTROL_DEBUG 0x03f4
283#define RX_CONTROL_DEBUG_EN_TS_CHECK BIT(5)
284#define RX_CONTROL_DEBUG_NUM_COM_FOUND GENMASK(3, 0)
285
286#define EXYNOS9_PCS_LOCAL_COEF 0x040c
287#define LOCAL_COEF_PMA_CENTER_COEF GENMASK(21, 16)
288#define LOCAL_COEF_LF GENMASK(13, 8)
289#define LOCAL_COEF_FS GENMASK(5, 0)
290
291#define EXYNOS9_PCS_HS_TX_COEF_MAP_0 0x0410
292#define HS_TX_COEF_MAP_0_SSTX_DEEMP GENMASK(17, 12)
293#define HS_TX_COEF_MAP_0_SSTX_LEVEL GENMASK(11, 6)
294#define HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT GENMASK(5, 0)
295
296
297#define KHZ 1000
298#define MHZ (KHZ * KHZ)
299
300#define PHY_TUNING_ENTRY_PHY(o, m, v) { \
301 .off = (o), \
302 .mask = (m), \
303 .val = (v), \
304 .region = PTR_PHY \
305 }
306
307#define PHY_TUNING_ENTRY_PCS(o, m, v) { \
308 .off = (o), \
309 .mask = (m), \
310 .val = (v), \
311 .region = PTR_PCS \
312 }
313
314#define PHY_TUNING_ENTRY_PMA(o, m, v) { \
315 .off = (o), \
316 .mask = (m), \
317 .val = (v), \
318 .region = PTR_PMA, \
319 }
320
321#define PHY_TUNING_ENTRY_LAST { .region = PTR_INVALID }
322
323#define for_each_phy_tune(tune) \
324 for (; (tune)->region != PTR_INVALID; ++(tune))
325
326struct exynos5_usbdrd_phy_tuning {
327 u32 off;
328 u32 mask;
329 u32 val;
330 char region;
331#define PTR_INVALID 0
332#define PTR_PHY 1
333#define PTR_PCS 2
334#define PTR_PMA 3
335};
336
337enum exynos5_usbdrd_phy_tuning_state {
338 PTS_UTMI_POSTINIT,
339 PTS_PIPE3_PREINIT,
340 PTS_PIPE3_INIT,
341 PTS_PIPE3_POSTINIT,
342 PTS_PIPE3_POSTLOCK,
343 PTS_MAX,
344};
345
346enum exynos5_usbdrd_phy_id {
347 EXYNOS5_DRDPHY_UTMI,
348 EXYNOS5_DRDPHY_PIPE3,
349 EXYNOS5_DRDPHYS_NUM,
350};
351
352struct phy_usb_instance;
353struct exynos5_usbdrd_phy;
354
355struct exynos5_usbdrd_phy_config {
356 u32 id;
357 void (*phy_isol)(struct phy_usb_instance *inst, bool isolate);
358 void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
359 unsigned int (*set_refclk)(struct phy_usb_instance *inst);
360};
361
362struct exynos5_usbdrd_phy_drvdata {
363 const struct exynos5_usbdrd_phy_config *phy_cfg;
364 const struct exynos5_usbdrd_phy_tuning **phy_tunes;
365 const struct phy_ops *phy_ops;
366 const char * const *clk_names;
367 int n_clks;
368 const char * const *core_clk_names;
369 int n_core_clks;
370 const char * const *regulator_names;
371 int n_regulators;
372 u32 pmu_offset_usbdrd0_phy;
373 u32 pmu_offset_usbdrd0_phy_ss;
374 u32 pmu_offset_usbdrd1_phy;
375};
376
377/**
378 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
379 * @dev: pointer to device instance of this platform device
380 * @reg_phy: usb phy controller register memory base
381 * @reg_pcs: usb phy physical coding sublayer register memory base
382 * @reg_pma: usb phy physical media attachment register memory base
383 * @clks: clocks for register access
384 * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
385 * @drv_data: pointer to SoC level driver data structure
386 * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
387 * instances each with its 'phy' and 'phy_cfg'.
388 * @extrefclk: frequency select settings when using 'separate
389 * reference clocks' for SS and HS operations
390 * @regulators: regulators for phy
391 */
392struct exynos5_usbdrd_phy {
393 struct device *dev;
394 void __iomem *reg_phy;
395 void __iomem *reg_pcs;
396 void __iomem *reg_pma;
397 struct clk_bulk_data *clks;
398 struct clk_bulk_data *core_clks;
399 const struct exynos5_usbdrd_phy_drvdata *drv_data;
400 struct phy_usb_instance {
401 struct phy *phy;
402 u32 index;
403 struct regmap *reg_pmu;
404 u32 pmu_offset;
405 const struct exynos5_usbdrd_phy_config *phy_cfg;
406 } phys[EXYNOS5_DRDPHYS_NUM];
407 u32 extrefclk;
408 struct regulator_bulk_data *regulators;
409};
410
411static inline
412struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst)
413{
414 return container_of((inst), struct exynos5_usbdrd_phy,
415 phys[(inst)->index]);
416}
417
418/*
419 * exynos5_rate_to_clk() converts the supplied clock rate to the value that
420 * can be written to the phy register.
421 */
422static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg)
423{
424 /* EXYNOS5_FSEL_MASK */
425
426 switch (rate) {
427 case 9600 * KHZ:
428 *reg = EXYNOS5_FSEL_9MHZ6;
429 break;
430 case 10 * MHZ:
431 *reg = EXYNOS5_FSEL_10MHZ;
432 break;
433 case 12 * MHZ:
434 *reg = EXYNOS5_FSEL_12MHZ;
435 break;
436 case 19200 * KHZ:
437 *reg = EXYNOS5_FSEL_19MHZ2;
438 break;
439 case 20 * MHZ:
440 *reg = EXYNOS5_FSEL_20MHZ;
441 break;
442 case 24 * MHZ:
443 *reg = EXYNOS5_FSEL_24MHZ;
444 break;
445 case 26 * MHZ:
446 *reg = EXYNOS5_FSEL_26MHZ;
447 break;
448 case 50 * MHZ:
449 *reg = EXYNOS5_FSEL_50MHZ;
450 break;
451 default:
452 return -EINVAL;
453 }
454
455 return 0;
456}
457
458static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
459 bool isolate)
460{
461 unsigned int val;
462
463 if (!inst->reg_pmu)
464 return;
465
466 val = isolate ? 0 : EXYNOS4_PHY_ENABLE;
467
468 regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
469 EXYNOS4_PHY_ENABLE, val);
470}
471
472/*
473 * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
474 * from clock core. Further sets multiplier values and spread spectrum
475 * clock settings for SuperSpeed operations.
476 */
477static unsigned int
478exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
479{
480 u32 reg;
481 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
482
483 /* restore any previous reference clock settings */
484 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
485
486 /* Use EXTREFCLK as ref clock */
487 reg &= ~PHYCLKRST_REFCLKSEL_MASK;
488 reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
489
490 /* FSEL settings corresponding to reference clock */
491 reg &= ~(PHYCLKRST_FSEL_PIPE_MASK |
492 PHYCLKRST_MPLL_MULTIPLIER_MASK |
493 PHYCLKRST_SSC_REFCLKSEL_MASK);
494 switch (phy_drd->extrefclk) {
495 case EXYNOS5_FSEL_50MHZ:
496 reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
497 PHYCLKRST_SSC_REFCLKSEL(0x00));
498 break;
499 case EXYNOS5_FSEL_24MHZ:
500 reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
501 PHYCLKRST_SSC_REFCLKSEL(0x88));
502 break;
503 case EXYNOS5_FSEL_20MHZ:
504 reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
505 PHYCLKRST_SSC_REFCLKSEL(0x00));
506 break;
507 case EXYNOS5_FSEL_19MHZ2:
508 reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
509 PHYCLKRST_SSC_REFCLKSEL(0x88));
510 break;
511 default:
512 dev_dbg(phy_drd->dev, "unsupported ref clk\n");
513 break;
514 }
515
516 return reg;
517}
518
519/*
520 * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
521 * from clock core. Further sets the FSEL values for HighSpeed operations.
522 */
523static unsigned int
524exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
525{
526 u32 reg;
527 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
528
529 /* restore any previous reference clock settings */
530 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
531
532 reg &= ~PHYCLKRST_REFCLKSEL_MASK;
533 reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
534
535 reg &= ~(PHYCLKRST_FSEL_UTMI_MASK |
536 PHYCLKRST_MPLL_MULTIPLIER_MASK |
537 PHYCLKRST_SSC_REFCLKSEL_MASK);
538 reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
539
540 return reg;
541}
542
543static void
544exynos5_usbdrd_apply_phy_tunes(struct exynos5_usbdrd_phy *phy_drd,
545 enum exynos5_usbdrd_phy_tuning_state state)
546{
547 const struct exynos5_usbdrd_phy_tuning *tune;
548
549 tune = phy_drd->drv_data->phy_tunes[state];
550 if (!tune)
551 return;
552
553 for_each_phy_tune(tune) {
554 void __iomem *reg_base;
555 u32 reg = 0;
556
557 switch (tune->region) {
558 case PTR_PHY:
559 reg_base = phy_drd->reg_phy;
560 break;
561 case PTR_PCS:
562 reg_base = phy_drd->reg_pcs;
563 break;
564 case PTR_PMA:
565 reg_base = phy_drd->reg_pma;
566 break;
567 default:
568 dev_warn_once(phy_drd->dev,
569 "unknown phy region %d\n", tune->region);
570 continue;
571 }
572
573 if (~tune->mask) {
574 reg = readl(reg_base + tune->off);
575 reg &= ~tune->mask;
576 }
577 reg |= tune->val;
578 writel(reg, reg_base + tune->off);
579 }
580}
581
582static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
583{
584 u32 reg;
585
586 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
587 /* Set Tx De-Emphasis level */
588 reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
589 reg |= PHYPARAM1_PCS_TXDEEMPH;
590 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
591
592 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
593 reg &= ~PHYTEST_POWERDOWN_SSP;
594 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
595}
596
597static void
598exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos5_usbdrd_phy *phy_drd)
599{
600 void __iomem *regs_base = phy_drd->reg_phy;
601 u32 reg;
602
603 /* link pipe_clock selection to pclk of PMA */
604 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
605 reg |= CLKRST_LINK_PCLK_SEL;
606 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
607
608 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL);
609 reg &= ~SECPMACTL_PMA_REF_FREQ_SEL;
610 reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1);
611 /* SFR reset */
612 reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST);
613 reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL |
614 SECPMACTL_PMA_LCPLL_REF_CLK_SEL);
615 /* PMA power off */
616 reg |= (SECPMACTL_PMA_TRSV_SW_RST | SECPMACTL_PMA_CMN_SW_RST |
617 SECPMACTL_PMA_INIT_SW_RST);
618 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
619
620 udelay(1);
621
622 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL);
623 reg &= ~SECPMACTL_PMA_LOW_PWR;
624 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
625
626 udelay(1);
627
628 /* release override */
629 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
630 reg &= ~LINKCTRL_FORCE_PIPE_EN;
631 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
632
633 udelay(1);
634
635 /* APB enable */
636 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL);
637 reg &= ~SECPMACTL_PMA_APB_SW_RST;
638 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
639}
640
641static void
642exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(struct exynos5_usbdrd_phy *phy_drd)
643{
644 void __iomem *regs_base = phy_drd->reg_pma;
645 u32 reg;
646
647 /* lane configuration: USB on all lanes */
648 reg = readl(regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8);
649 reg &= ~CMN_REG00B8_LANE_MUX_SEL_DP;
650 writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8);
651
652 /*
653 * FIXME: below code supports one connector orientation only. It needs
654 * updating once we can receive connector events.
655 */
656 /* override of TX receiver detector and comparator: lane 1 */
657 reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413);
658 reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN;
659 reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN;
660 writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413);
661
662 /* lane 3 */
663 reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813);
664 reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN;
665 reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_EN;
666 writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813);
667}
668
669static int
670exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock(struct exynos5_usbdrd_phy *phy_drd)
671{
672 static const unsigned int timeout_us = 40000;
673 static const unsigned int sleep_us = 40;
674 static const u32 locked = (CMN_REG01C0_ANA_LCPLL_LOCK_DONE |
675 CMN_REG01C0_ANA_LCPLL_AFC_DONE);
676 u32 reg;
677 int err;
678
679 err = readl_poll_timeout(
680 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_CMN_REG01C0,
681 reg, (reg & locked) == locked, sleep_us, timeout_us);
682 if (err)
683 dev_err(phy_drd->dev,
684 "timed out waiting for PLL lock: %#.8x\n", reg);
685
686 return err;
687}
688
689static void
690exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock(struct exynos5_usbdrd_phy *phy_drd)
691{
692 static const unsigned int timeout_us = 40000;
693 static const unsigned int sleep_us = 40;
694 static const u32 locked =
695 (TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE
696 | TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE
697 | TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE
698 | TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE);
699 u32 reg;
700 int err;
701
702 err = readl_poll_timeout(
703 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG03C3,
704 reg, (reg & locked) == locked, sleep_us, timeout_us);
705 if (!err)
706 return;
707
708 dev_err(phy_drd->dev,
709 "timed out waiting for CDR lock (l0): %#.8x, retrying\n", reg);
710
711 /* based on cable orientation, this might be on the other phy port */
712 err = readl_poll_timeout(
713 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_TRSV_REG07C3,
714 reg, (reg & locked) == locked, sleep_us, timeout_us);
715 if (err)
716 dev_err(phy_drd->dev,
717 "timed out waiting for CDR lock (l2): %#.8x\n", reg);
718}
719
720static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
721{
722 u32 reg;
723
724 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
725 /* Set Loss-of-Signal Detector sensitivity */
726 reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
727 reg |= PHYPARAM0_REF_LOSLEVEL;
728 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
729
730 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
731 /* Set Tx De-Emphasis level */
732 reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
733 reg |= PHYPARAM1_PCS_TXDEEMPH;
734 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
735
736 /* UTMI Power Control */
737 writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
738
739 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
740 reg &= ~PHYTEST_POWERDOWN_HSP;
741 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
742}
743
744static int exynos5_usbdrd_phy_init(struct phy *phy)
745{
746 int ret;
747 u32 reg;
748 struct phy_usb_instance *inst = phy_get_drvdata(phy);
749 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
750
751 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
752 if (ret)
753 return ret;
754
755 /* Reset USB 3.0 PHY */
756 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
757 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
758
759 /*
760 * Setting the Frame length Adj value[6:1] to default 0x20
761 * See xHCI 1.0 spec, 5.2.4
762 */
763 reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
764 LINKSYSTEM_FLADJ(0x20);
765 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
766
767 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
768 /* Select PHY CLK source */
769 reg &= ~PHYPARAM0_REF_USE_PAD;
770 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
771
772 /* This bit must be set for both HS and SS operations */
773 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
774 reg |= PHYUTMICLKSEL_UTMI_CLKSEL;
775 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
776
777 /* UTMI or PIPE3 specific init */
778 inst->phy_cfg->phy_init(phy_drd);
779
780 /* reference clock settings */
781 reg = inst->phy_cfg->set_refclk(inst);
782
783 /* Digital power supply in normal operating mode */
784 reg |= PHYCLKRST_RETENABLEN |
785 /* Enable ref clock for SS function */
786 PHYCLKRST_REF_SSP_EN |
787 /* Enable spread spectrum */
788 PHYCLKRST_SSC_EN |
789 /* Power down HS Bias and PLL blocks in suspend mode */
790 PHYCLKRST_COMMONONN |
791 /* Reset the port */
792 PHYCLKRST_PORTRESET;
793
794 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
795
796 fsleep(10);
797
798 reg &= ~PHYCLKRST_PORTRESET;
799 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
800
801 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
802
803 return 0;
804}
805
806static int exynos5_usbdrd_phy_exit(struct phy *phy)
807{
808 int ret;
809 u32 reg;
810 struct phy_usb_instance *inst = phy_get_drvdata(phy);
811 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
812
813 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
814 if (ret)
815 return ret;
816
817 reg = PHYUTMI_OTGDISABLE |
818 PHYUTMI_FORCESUSPEND |
819 PHYUTMI_FORCESLEEP;
820 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
821
822 /* Resetting the PHYCLKRST enable bits to reduce leakage current */
823 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
824 reg &= ~(PHYCLKRST_REF_SSP_EN |
825 PHYCLKRST_SSC_EN |
826 PHYCLKRST_COMMONONN);
827 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
828
829 /* Control PHYTEST to remove leakage current */
830 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
831 reg |= PHYTEST_POWERDOWN_SSP |
832 PHYTEST_POWERDOWN_HSP;
833 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
834
835 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
836
837 return 0;
838}
839
840static int exynos5_usbdrd_phy_power_on(struct phy *phy)
841{
842 int ret;
843 struct phy_usb_instance *inst = phy_get_drvdata(phy);
844 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
845
846 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
847
848 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks,
849 phy_drd->core_clks);
850 if (ret)
851 return ret;
852
853 /* Enable VBUS supply */
854 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators,
855 phy_drd->regulators);
856 if (ret) {
857 dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n");
858 goto fail_vbus;
859 }
860
861 /* Power-on PHY */
862 inst->phy_cfg->phy_isol(inst, false);
863
864 return 0;
865
866fail_vbus:
867 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks,
868 phy_drd->core_clks);
869
870 return ret;
871}
872
873static int exynos5_usbdrd_phy_power_off(struct phy *phy)
874{
875 struct phy_usb_instance *inst = phy_get_drvdata(phy);
876 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
877
878 dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
879
880 /* Power-off the PHY */
881 inst->phy_cfg->phy_isol(inst, true);
882
883 /* Disable VBUS supply */
884 regulator_bulk_disable(phy_drd->drv_data->n_regulators,
885 phy_drd->regulators);
886
887 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks,
888 phy_drd->core_clks);
889
890 return 0;
891}
892
893static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
894 u32 val, u32 cmd)
895{
896 unsigned int result;
897 int err;
898
899 writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
900
901 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
902 result, (result & PHYREG1_CR_ACK), 1, 100);
903 if (err == -ETIMEDOUT) {
904 dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val);
905 return err;
906 }
907
908 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
909
910 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
911 result, !(result & PHYREG1_CR_ACK), 1, 100);
912 if (err == -ETIMEDOUT) {
913 dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val);
914 return err;
915 }
916
917 return 0;
918}
919
920static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,
921 u32 addr, u32 data)
922{
923 int ret;
924
925 /* Write Address */
926 writel(PHYREG0_CR_DATA_IN(addr),
927 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
928 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),
929 PHYREG0_CR_CAP_ADDR);
930 if (ret)
931 return ret;
932
933 /* Write Data */
934 writel(PHYREG0_CR_DATA_IN(data),
935 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
936 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
937 PHYREG0_CR_CAP_DATA);
938 if (ret)
939 return ret;
940
941 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
942 PHYREG0_CR_WRITE);
943
944 return ret;
945}
946
947/*
948 * Calibrate few PHY parameters using CR_PORT register to meet
949 * SuperSpeed requirements on Exynos5420 and Exynos5800 systems,
950 * which have 28nm USB 3.0 DRD PHY.
951 */
952static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)
953{
954 unsigned int temp;
955 int ret = 0;
956
957 /*
958 * Change los_bias to (0x5) for 28nm PHY from a
959 * default value (0x0); los_level is set as default
960 * (0x9) as also reflected in los_level[30:26] bits
961 * of PHYPARAM0 register.
962 */
963 temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 |
964 LOSLEVEL_OVRD_IN_EN |
965 LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT;
966 ret = crport_ctrl_write(phy_drd,
967 EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN,
968 temp);
969 if (ret) {
970 dev_err(phy_drd->dev,
971 "Failed setting Loss-of-Signal level for SuperSpeed\n");
972 return ret;
973 }
974
975 /*
976 * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,
977 * to raise Tx signal level from its default value of (0x4)
978 */
979 temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420;
980 ret = crport_ctrl_write(phy_drd,
981 EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN,
982 temp);
983 if (ret) {
984 dev_err(phy_drd->dev,
985 "Failed setting Tx-Vboost-Level for SuperSpeed\n");
986 return ret;
987 }
988
989 /*
990 * Set proper time to wait for RxDetect measurement, for
991 * desired reference clock of PHY, by tuning the CR_PORT
992 * register LANE0.TX_DEBUG which is internal to PHY.
993 * This fixes issue with few USB 3.0 devices, which are
994 * not detected (not even generate interrupts on the bus
995 * on insertion) without this change.
996 * e.g. Samsung SUM-TSB16S 3.0 USB drive.
997 */
998 switch (phy_drd->extrefclk) {
999 case EXYNOS5_FSEL_50MHZ:
1000 temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M;
1001 break;
1002 case EXYNOS5_FSEL_20MHZ:
1003 case EXYNOS5_FSEL_19MHZ2:
1004 temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M;
1005 break;
1006 case EXYNOS5_FSEL_24MHZ:
1007 default:
1008 temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M;
1009 break;
1010 }
1011
1012 ret = crport_ctrl_write(phy_drd,
1013 EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG,
1014 temp);
1015 if (ret)
1016 dev_err(phy_drd->dev,
1017 "Fail to set RxDet measurement time for SuperSpeed\n");
1018
1019 return ret;
1020}
1021
1022static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
1023 const struct of_phandle_args *args)
1024{
1025 struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
1026
1027 if (WARN_ON(args->args[0] >= EXYNOS5_DRDPHYS_NUM))
1028 return ERR_PTR(-ENODEV);
1029
1030 return phy_drd->phys[args->args[0]].phy;
1031}
1032
1033static int exynos5_usbdrd_phy_calibrate(struct phy *phy)
1034{
1035 struct phy_usb_instance *inst = phy_get_drvdata(phy);
1036 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
1037
1038 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI)
1039 return exynos5420_usbdrd_phy_calibrate(phy_drd);
1040 return 0;
1041}
1042
1043static const struct phy_ops exynos5_usbdrd_phy_ops = {
1044 .init = exynos5_usbdrd_phy_init,
1045 .exit = exynos5_usbdrd_phy_exit,
1046 .power_on = exynos5_usbdrd_phy_power_on,
1047 .power_off = exynos5_usbdrd_phy_power_off,
1048 .calibrate = exynos5_usbdrd_phy_calibrate,
1049 .owner = THIS_MODULE,
1050};
1051
1052static void
1053exynos5_usbdrd_usb_v3p1_pipe_override(struct exynos5_usbdrd_phy *phy_drd)
1054{
1055 void __iomem *regs_base = phy_drd->reg_phy;
1056 u32 reg;
1057
1058 /* force pipe3 signal for link */
1059 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
1060 reg &= ~LINKCTRL_FORCE_PHYSTATUS;
1061 reg |= LINKCTRL_FORCE_PIPE_EN | LINKCTRL_FORCE_RXELECIDLE;
1062 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
1063
1064 /* PMA disable */
1065 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL);
1066 reg |= SECPMACTL_PMA_LOW_PWR;
1067 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
1068}
1069
1070static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
1071{
1072 void __iomem *regs_base = phy_drd->reg_phy;
1073 u32 reg;
1074 u32 ss_ports;
1075
1076 /*
1077 * Disable HWACG (hardware auto clock gating control). This will force
1078 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure
1079 * the PHY clock is not gated by the hardware.
1080 */
1081 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
1082 reg |= LINKCTRL_FORCE_QACT;
1083 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
1084
1085 reg = readl(regs_base + EXYNOS850_DRD_LINKPORT);
1086 ss_ports = FIELD_GET(LINKPORT_HOST_NUM_U3, reg);
1087
1088 /* Start PHY Reset (POR=high) */
1089 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
1090 if (ss_ports) {
1091 reg |= CLKRST_PHY20_SW_POR;
1092 reg |= CLKRST_PHY20_SW_POR_SEL;
1093 reg |= CLKRST_PHY_RESET_SEL;
1094 }
1095 reg |= CLKRST_PHY_SW_RST;
1096 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
1097
1098 /* Enable UTMI+ */
1099 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
1100 reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN |
1101 UTMI_DM_PULLDOWN);
1102 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
1103
1104 /* Set PHY clock and control HS PHY */
1105 reg = readl(regs_base + EXYNOS850_DRD_HSP);
1106 reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN;
1107 writel(reg, regs_base + EXYNOS850_DRD_HSP);
1108
1109 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */
1110 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
1111 reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf);
1112 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
1113
1114 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
1115 reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID;
1116 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
1117
1118 reg = readl(regs_base + EXYNOS850_DRD_HSP);
1119 reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL;
1120 writel(reg, regs_base + EXYNOS850_DRD_HSP);
1121
1122 reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL);
1123 reg &= ~SSPPLLCTL_FSEL;
1124 switch (phy_drd->extrefclk) {
1125 case EXYNOS5_FSEL_50MHZ:
1126 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7);
1127 break;
1128 case EXYNOS5_FSEL_26MHZ:
1129 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6);
1130 break;
1131 case EXYNOS5_FSEL_24MHZ:
1132 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2);
1133 break;
1134 case EXYNOS5_FSEL_20MHZ:
1135 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1);
1136 break;
1137 case EXYNOS5_FSEL_19MHZ2:
1138 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0);
1139 break;
1140 default:
1141 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",
1142 phy_drd->extrefclk);
1143 break;
1144 }
1145 writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL);
1146
1147 if (phy_drd->drv_data->phy_tunes)
1148 exynos5_usbdrd_apply_phy_tunes(phy_drd,
1149 PTS_UTMI_POSTINIT);
1150
1151 /* Power up PHY analog blocks */
1152 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
1153 reg &= ~HSP_TEST_SIDDQ;
1154 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
1155
1156 /* Finish PHY reset (POR=low) */
1157 fsleep(10); /* required before doing POR=low */
1158 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
1159 if (ss_ports) {
1160 reg |= CLKRST_PHY20_SW_POR_SEL;
1161 reg &= ~CLKRST_PHY20_SW_POR;
1162 }
1163 reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST);
1164 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
1165 fsleep(75); /* required after POR=low for guaranteed PHY clock */
1166
1167 /* Disable single ended signal out */
1168 reg = readl(regs_base + EXYNOS850_DRD_HSP);
1169 reg &= ~HSP_FSV_OUT_EN;
1170 writel(reg, regs_base + EXYNOS850_DRD_HSP);
1171
1172 if (ss_ports)
1173 exynos5_usbdrd_usb_v3p1_pipe_override(phy_drd);
1174}
1175
1176static int exynos850_usbdrd_phy_init(struct phy *phy)
1177{
1178 struct phy_usb_instance *inst = phy_get_drvdata(phy);
1179 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
1180 int ret;
1181
1182 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
1183 if (ret)
1184 return ret;
1185
1186 /* UTMI or PIPE3 specific init */
1187 inst->phy_cfg->phy_init(phy_drd);
1188
1189 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
1190
1191 return 0;
1192}
1193
1194static int exynos850_usbdrd_phy_exit(struct phy *phy)
1195{
1196 struct phy_usb_instance *inst = phy_get_drvdata(phy);
1197 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
1198 void __iomem *regs_base = phy_drd->reg_phy;
1199 u32 reg;
1200 int ret;
1201
1202 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks);
1203 if (ret)
1204 return ret;
1205
1206 /* Set PHY clock and control HS PHY */
1207 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
1208 reg &= ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN);
1209 reg |= UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP;
1210 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
1211
1212 /* Power down PHY analog blocks */
1213 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
1214 reg |= HSP_TEST_SIDDQ;
1215 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
1216
1217 /* Link reset */
1218 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
1219 reg |= CLKRST_LINK_SW_RST;
1220 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
1221 fsleep(10); /* required before doing POR=low */
1222 reg &= ~CLKRST_LINK_SW_RST;
1223 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
1224
1225 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
1226
1227 return 0;
1228}
1229
1230static const struct phy_ops exynos850_usbdrd_phy_ops = {
1231 .init = exynos850_usbdrd_phy_init,
1232 .exit = exynos850_usbdrd_phy_exit,
1233 .power_on = exynos5_usbdrd_phy_power_on,
1234 .power_off = exynos5_usbdrd_phy_power_off,
1235 .owner = THIS_MODULE,
1236};
1237
1238static void exynos5_usbdrd_gs101_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
1239{
1240 void __iomem *regs_pma = phy_drd->reg_pma;
1241 void __iomem *regs_phy = phy_drd->reg_phy;
1242 u32 reg;
1243
1244 exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(phy_drd);
1245
1246 /* force aux off */
1247 reg = readl(regs_pma + EXYNOS9_PMA_USBDP_CMN_REG0008);
1248 reg &= ~CMN_REG0008_AUX_EN;
1249 reg |= CMN_REG0008_OVRD_AUX_EN;
1250 writel(reg, regs_pma + EXYNOS9_PMA_USBDP_CMN_REG0008);
1251
1252 exynos5_usbdrd_apply_phy_tunes(phy_drd, PTS_PIPE3_PREINIT);
1253 exynos5_usbdrd_apply_phy_tunes(phy_drd, PTS_PIPE3_INIT);
1254 exynos5_usbdrd_apply_phy_tunes(phy_drd, PTS_PIPE3_POSTINIT);
1255
1256 exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(phy_drd);
1257
1258 /* reset release from port */
1259 reg = readl(regs_phy + EXYNOS850_DRD_SECPMACTL);
1260 reg &= ~(SECPMACTL_PMA_TRSV_SW_RST | SECPMACTL_PMA_CMN_SW_RST |
1261 SECPMACTL_PMA_INIT_SW_RST);
1262 writel(reg, regs_phy + EXYNOS850_DRD_SECPMACTL);
1263
1264 if (!exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock(phy_drd))
1265 exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock(phy_drd);
1266}
1267
1268static int exynos5_usbdrd_gs101_phy_init(struct phy *phy)
1269{
1270 struct phy_usb_instance *inst = phy_get_drvdata(phy);
1271 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
1272 int ret;
1273
1274 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
1275 /* Power-on PHY ... */
1276 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators,
1277 phy_drd->regulators);
1278 if (ret) {
1279 dev_err(phy_drd->dev,
1280 "Failed to enable PHY regulator(s)\n");
1281 return ret;
1282 }
1283 }
1284 /*
1285 * ... and ungate power via PMU. Without this here, we get an SError
1286 * trying to access PMA registers
1287 */
1288 exynos5_usbdrd_phy_isol(inst, false);
1289
1290 return exynos850_usbdrd_phy_init(phy);
1291}
1292
1293static int exynos5_usbdrd_gs101_phy_exit(struct phy *phy)
1294{
1295 struct phy_usb_instance *inst = phy_get_drvdata(phy);
1296 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
1297 int ret;
1298
1299 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) {
1300 ret = exynos850_usbdrd_phy_exit(phy);
1301 if (ret)
1302 return ret;
1303 }
1304
1305 exynos5_usbdrd_phy_isol(inst, true);
1306
1307 if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI)
1308 return 0;
1309
1310 return regulator_bulk_disable(phy_drd->drv_data->n_regulators,
1311 phy_drd->regulators);
1312}
1313
1314static const struct phy_ops gs101_usbdrd_phy_ops = {
1315 .init = exynos5_usbdrd_gs101_phy_init,
1316 .exit = exynos5_usbdrd_gs101_phy_exit,
1317 .owner = THIS_MODULE,
1318};
1319
1320static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
1321{
1322 int ret;
1323 struct clk *ref_clk;
1324 unsigned long ref_rate;
1325
1326 phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks,
1327 sizeof(*phy_drd->clks), GFP_KERNEL);
1328 if (!phy_drd->clks)
1329 return -ENOMEM;
1330
1331 for (int i = 0; i < phy_drd->drv_data->n_clks; ++i)
1332 phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i];
1333
1334 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks,
1335 phy_drd->clks);
1336 if (ret)
1337 return dev_err_probe(phy_drd->dev, ret,
1338 "failed to get phy clock(s)\n");
1339
1340 phy_drd->core_clks = devm_kcalloc(phy_drd->dev,
1341 phy_drd->drv_data->n_core_clks,
1342 sizeof(*phy_drd->core_clks),
1343 GFP_KERNEL);
1344 if (!phy_drd->core_clks)
1345 return -ENOMEM;
1346
1347 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i)
1348 phy_drd->core_clks[i].id = phy_drd->drv_data->core_clk_names[i];
1349
1350 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_core_clks,
1351 phy_drd->core_clks);
1352 if (ret)
1353 return dev_err_probe(phy_drd->dev, ret,
1354 "failed to get phy core clock(s)\n");
1355
1356 ref_clk = NULL;
1357 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) {
1358 if (!strcmp(phy_drd->core_clks[i].id, "ref")) {
1359 ref_clk = phy_drd->core_clks[i].clk;
1360 break;
1361 }
1362 }
1363 if (!ref_clk)
1364 return dev_err_probe(phy_drd->dev, -ENODEV,
1365 "failed to find phy reference clock\n");
1366
1367 ref_rate = clk_get_rate(ref_clk);
1368 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
1369 if (ret)
1370 return dev_err_probe(phy_drd->dev, ret,
1371 "clock rate (%ld) not supported\n",
1372 ref_rate);
1373
1374 return 0;
1375}
1376
1377static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
1378 {
1379 .id = EXYNOS5_DRDPHY_UTMI,
1380 .phy_isol = exynos5_usbdrd_phy_isol,
1381 .phy_init = exynos5_usbdrd_utmi_init,
1382 .set_refclk = exynos5_usbdrd_utmi_set_refclk,
1383 },
1384 {
1385 .id = EXYNOS5_DRDPHY_PIPE3,
1386 .phy_isol = exynos5_usbdrd_phy_isol,
1387 .phy_init = exynos5_usbdrd_pipe3_init,
1388 .set_refclk = exynos5_usbdrd_pipe3_set_refclk,
1389 },
1390};
1391
1392static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = {
1393 {
1394 .id = EXYNOS5_DRDPHY_UTMI,
1395 .phy_isol = exynos5_usbdrd_phy_isol,
1396 .phy_init = exynos850_usbdrd_utmi_init,
1397 },
1398};
1399
1400static const char * const exynos5_clk_names[] = {
1401 "phy",
1402};
1403
1404static const char * const exynos5_core_clk_names[] = {
1405 "ref",
1406};
1407
1408static const char * const exynos5433_core_clk_names[] = {
1409 "ref", "phy_pipe", "phy_utmi", "itp",
1410};
1411
1412static const char * const exynos5_regulator_names[] = {
1413 "vbus", "vbus-boost",
1414};
1415
1416static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
1417 .phy_cfg = phy_cfg_exynos5,
1418 .phy_ops = &exynos5_usbdrd_phy_ops,
1419 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
1420 .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
1421 .clk_names = exynos5_clk_names,
1422 .n_clks = ARRAY_SIZE(exynos5_clk_names),
1423 .core_clk_names = exynos5_core_clk_names,
1424 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
1425 .regulator_names = exynos5_regulator_names,
1426 .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
1427};
1428
1429static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
1430 .phy_cfg = phy_cfg_exynos5,
1431 .phy_ops = &exynos5_usbdrd_phy_ops,
1432 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
1433 .clk_names = exynos5_clk_names,
1434 .n_clks = ARRAY_SIZE(exynos5_clk_names),
1435 .core_clk_names = exynos5_core_clk_names,
1436 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
1437 .regulator_names = exynos5_regulator_names,
1438 .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
1439};
1440
1441static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = {
1442 .phy_cfg = phy_cfg_exynos5,
1443 .phy_ops = &exynos5_usbdrd_phy_ops,
1444 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
1445 .pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL,
1446 .clk_names = exynos5_clk_names,
1447 .n_clks = ARRAY_SIZE(exynos5_clk_names),
1448 .core_clk_names = exynos5433_core_clk_names,
1449 .n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
1450 .regulator_names = exynos5_regulator_names,
1451 .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
1452};
1453
1454static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
1455 .phy_cfg = phy_cfg_exynos5,
1456 .phy_ops = &exynos5_usbdrd_phy_ops,
1457 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
1458 .clk_names = exynos5_clk_names,
1459 .n_clks = ARRAY_SIZE(exynos5_clk_names),
1460 .core_clk_names = exynos5433_core_clk_names,
1461 .n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names),
1462 .regulator_names = exynos5_regulator_names,
1463 .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
1464};
1465
1466static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
1467 .phy_cfg = phy_cfg_exynos850,
1468 .phy_ops = &exynos850_usbdrd_phy_ops,
1469 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
1470 .clk_names = exynos5_clk_names,
1471 .n_clks = ARRAY_SIZE(exynos5_clk_names),
1472 .core_clk_names = exynos5_core_clk_names,
1473 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
1474 .regulator_names = exynos5_regulator_names,
1475 .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
1476};
1477
1478static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = {
1479 {
1480 .id = EXYNOS5_DRDPHY_UTMI,
1481 .phy_isol = exynos5_usbdrd_phy_isol,
1482 .phy_init = exynos850_usbdrd_utmi_init,
1483 },
1484 {
1485 .id = EXYNOS5_DRDPHY_PIPE3,
1486 .phy_isol = exynos5_usbdrd_phy_isol,
1487 .phy_init = exynos5_usbdrd_gs101_pipe3_init,
1488 },
1489};
1490
1491static const struct exynos5_usbdrd_phy_tuning gs101_tunes_utmi_postinit[] = {
1492 PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON,
1493 (HSPPARACON_TXVREF | HSPPARACON_TXRES |
1494 HSPPARACON_TXPREEMPAMP | HSPPARACON_SQRX |
1495 HSPPARACON_COMPDIS),
1496 (FIELD_PREP_CONST(HSPPARACON_TXVREF, 6) |
1497 FIELD_PREP_CONST(HSPPARACON_TXRES, 1) |
1498 FIELD_PREP_CONST(HSPPARACON_TXPREEMPAMP, 3) |
1499 FIELD_PREP_CONST(HSPPARACON_SQRX, 5) |
1500 FIELD_PREP_CONST(HSPPARACON_COMPDIS, 7))),
1501 PHY_TUNING_ENTRY_LAST
1502};
1503
1504static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_preinit[] = {
1505 /* preinit */
1506 /* CDR data mode exit GEN1 ON / GEN2 OFF */
1507 PHY_TUNING_ENTRY_PMA(0x0c8c, -1, 0xff),
1508 PHY_TUNING_ENTRY_PMA(0x1c8c, -1, 0xff),
1509 PHY_TUNING_ENTRY_PMA(0x0c9c, -1, 0x7d),
1510 PHY_TUNING_ENTRY_PMA(0x1c9c, -1, 0x7d),
1511 /* improve EDS distribution */
1512 PHY_TUNING_ENTRY_PMA(0x0e7c, -1, 0x06),
1513 PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00),
1514 PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36),
1515 PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06),
1516 PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x00),
1517 PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x36),
1518 /* improve LVCC */
1519 PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30),
1520 PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30),
1521 /* LFPS RX VIH shmoo hole */
1522 PHY_TUNING_ENTRY_PMA(0x0a08, -1, 0x0c),
1523 PHY_TUNING_ENTRY_PMA(0x1a08, -1, 0x0c),
1524 /* remove unrelated option for v4 phy */
1525 PHY_TUNING_ENTRY_PMA(0x0a0c, -1, 0x05),
1526 PHY_TUNING_ENTRY_PMA(0x1a0c, -1, 0x05),
1527 /* improve Gen2 LVCC */
1528 PHY_TUNING_ENTRY_PMA(0x00f8, -1, 0x1c),
1529 PHY_TUNING_ENTRY_PMA(0x00fc, -1, 0x54),
1530 /* Change Vth of RCV_DET because of TD 7.40 Polling Retry Test */
1531 PHY_TUNING_ENTRY_PMA(0x104c, -1, 0x07),
1532 PHY_TUNING_ENTRY_PMA(0x204c, -1, 0x07),
1533 /* reduce Ux Exit time, assuming 26MHz clock */
1534 /* Gen1 */
1535 PHY_TUNING_ENTRY_PMA(0x0ca8, -1, 0x00),
1536 PHY_TUNING_ENTRY_PMA(0x0cac, -1, 0x04),
1537 PHY_TUNING_ENTRY_PMA(0x1ca8, -1, 0x00),
1538 PHY_TUNING_ENTRY_PMA(0x1cac, -1, 0x04),
1539 /* Gen2 */
1540 PHY_TUNING_ENTRY_PMA(0x0cb8, -1, 0x00),
1541 PHY_TUNING_ENTRY_PMA(0x0cbc, -1, 0x04),
1542 PHY_TUNING_ENTRY_PMA(0x1cb8, -1, 0x00),
1543 PHY_TUNING_ENTRY_PMA(0x1cbc, -1, 0x04),
1544 /* RX impedance setting */
1545 PHY_TUNING_ENTRY_PMA(0x0bb0, 0x03, 0x01),
1546 PHY_TUNING_ENTRY_PMA(0x0bb4, 0xf0, 0xa0),
1547 PHY_TUNING_ENTRY_PMA(0x1bb0, 0x03, 0x01),
1548 PHY_TUNING_ENTRY_PMA(0x1bb4, 0xf0, 0xa0),
1549
1550 PHY_TUNING_ENTRY_LAST
1551};
1552
1553static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_init[] = {
1554 /* init */
1555 /* abnormal common pattern mask */
1556 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_BACK_END_MODE_VEC,
1557 BACK_END_MODE_VEC_DISABLE_DATA_MASK, 0),
1558 /* de-serializer enabled when U2 */
1559 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_2, PCS_OUT_VEC_B4_DYNAMIC,
1560 PCS_OUT_VEC_B4_SEL_OUT),
1561 /* TX Keeper Disable, Squelch on when U3 */
1562 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_3, PCS_OUT_VEC_B7_DYNAMIC,
1563 PCS_OUT_VEC_B7_SEL_OUT | PCS_OUT_VEC_B2_SEL_OUT),
1564 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS1_N1, -1,
1565 (FIELD_PREP_CONST(NS_VEC_NS_REQ, 5) |
1566 NS_VEC_ENABLE_TIMER |
1567 FIELD_PREP_CONST(NS_VEC_SEL_TIMEOUT, 3))),
1568 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS2_N0, -1,
1569 (FIELD_PREP_CONST(NS_VEC_NS_REQ, 1) |
1570 NS_VEC_ENABLE_TIMER |
1571 FIELD_PREP_CONST(NS_VEC_SEL_TIMEOUT, 3) |
1572 FIELD_PREP_CONST(NS_VEC_COND_MASK, 2) |
1573 FIELD_PREP_CONST(NS_VEC_EXP_COND, 2))),
1574 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS3_N0, -1,
1575 (FIELD_PREP_CONST(NS_VEC_NS_REQ, 1) |
1576 NS_VEC_ENABLE_TIMER |
1577 FIELD_PREP_CONST(NS_VEC_SEL_TIMEOUT, 3) |
1578 FIELD_PREP_CONST(NS_VEC_COND_MASK, 7) |
1579 FIELD_PREP_CONST(NS_VEC_EXP_COND, 7))),
1580 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_0, -1, 112),
1581 /* Block Aligner Type B */
1582 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL, 0,
1583 RX_CONTROL_EN_BLOCK_ALIGNER_TYPE_B),
1584 /* Block align at TS1/TS2 for Gen2 stability (Gen2 only) */
1585 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL_DEBUG,
1586 RX_CONTROL_DEBUG_NUM_COM_FOUND,
1587 (RX_CONTROL_DEBUG_EN_TS_CHECK |
1588 /*
1589 * increase pcs ts1 adding packet-cnt 1 --> 4
1590 * lnx_rx_valid_rstn_delay_rise_sp/ssp :
1591 * 19.6us(0x200) -> 15.3us(0x4)
1592 */
1593 FIELD_PREP_CONST(RX_CONTROL_DEBUG_NUM_COM_FOUND, 4))),
1594 /* Gen1 Tx DRIVER pre-shoot, de-emphasis, level ctrl */
1595 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_HS_TX_COEF_MAP_0,
1596 (HS_TX_COEF_MAP_0_SSTX_DEEMP | HS_TX_COEF_MAP_0_SSTX_LEVEL |
1597 HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT),
1598 (FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_DEEMP, 8) |
1599 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_LEVEL, 0xb) |
1600 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT, 0))),
1601 /* Gen2 Tx DRIVER level ctrl */
1602 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_LOCAL_COEF,
1603 LOCAL_COEF_PMA_CENTER_COEF,
1604 FIELD_PREP_CONST(LOCAL_COEF_PMA_CENTER_COEF, 0xb)),
1605 /* Gen2 U1 exit LFPS duration : 900ns ~ 1.2us */
1606 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_3, -1, 4096),
1607 /* set skp_remove_th 0x2 -> 0x7 for avoiding retry problem. */
1608 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_EBUF_PARAM,
1609 EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE,
1610 FIELD_PREP_CONST(EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE, 0x7)),
1611
1612 PHY_TUNING_ENTRY_LAST
1613};
1614
1615static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_postlock[] = {
1616 /* Squelch off when U3 */
1617 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_3, PCS_OUT_VEC_B2_SEL_OUT, 0),
1618
1619 PHY_TUNING_ENTRY_LAST
1620};
1621
1622static const struct exynos5_usbdrd_phy_tuning *gs101_tunes[PTS_MAX] = {
1623 [PTS_UTMI_POSTINIT] = gs101_tunes_utmi_postinit,
1624 [PTS_PIPE3_PREINIT] = gs101_tunes_pipe3_preinit,
1625 [PTS_PIPE3_INIT] = gs101_tunes_pipe3_init,
1626 [PTS_PIPE3_POSTLOCK] = gs101_tunes_pipe3_postlock,
1627};
1628
1629static const char * const gs101_clk_names[] = {
1630 "phy", "ctrl_aclk", "ctrl_pclk", "scl_pclk",
1631};
1632
1633static const char * const gs101_regulator_names[] = {
1634 "pll",
1635 "dvdd-usb20", "vddh-usb20", "vdd33-usb20",
1636 "vdda-usbdp", "vddh-usbdp",
1637};
1638
1639static const struct exynos5_usbdrd_phy_drvdata gs101_usbd31rd_phy = {
1640 .phy_cfg = phy_cfg_gs101,
1641 .phy_tunes = gs101_tunes,
1642 .phy_ops = &gs101_usbdrd_phy_ops,
1643 .pmu_offset_usbdrd0_phy = GS101_PHY_CTRL_USB20,
1644 .pmu_offset_usbdrd0_phy_ss = GS101_PHY_CTRL_USBDP,
1645 .clk_names = gs101_clk_names,
1646 .n_clks = ARRAY_SIZE(gs101_clk_names),
1647 .core_clk_names = exynos5_core_clk_names,
1648 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
1649 .regulator_names = gs101_regulator_names,
1650 .n_regulators = ARRAY_SIZE(gs101_regulator_names),
1651};
1652
1653static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
1654 {
1655 .compatible = "google,gs101-usb31drd-phy",
1656 .data = &gs101_usbd31rd_phy
1657 }, {
1658 .compatible = "samsung,exynos5250-usbdrd-phy",
1659 .data = &exynos5250_usbdrd_phy
1660 }, {
1661 .compatible = "samsung,exynos5420-usbdrd-phy",
1662 .data = &exynos5420_usbdrd_phy
1663 }, {
1664 .compatible = "samsung,exynos5433-usbdrd-phy",
1665 .data = &exynos5433_usbdrd_phy
1666 }, {
1667 .compatible = "samsung,exynos7-usbdrd-phy",
1668 .data = &exynos7_usbdrd_phy
1669 }, {
1670 .compatible = "samsung,exynos850-usbdrd-phy",
1671 .data = &exynos850_usbdrd_phy
1672 },
1673 { },
1674};
1675MODULE_DEVICE_TABLE(of, exynos5_usbdrd_phy_of_match);
1676
1677static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
1678{
1679 struct device *dev = &pdev->dev;
1680 struct device_node *node = dev->of_node;
1681 struct exynos5_usbdrd_phy *phy_drd;
1682 struct phy_provider *phy_provider;
1683 const struct exynos5_usbdrd_phy_drvdata *drv_data;
1684 struct regmap *reg_pmu;
1685 u32 pmu_offset;
1686 int i, ret;
1687 int channel;
1688
1689 phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
1690 if (!phy_drd)
1691 return -ENOMEM;
1692
1693 dev_set_drvdata(dev, phy_drd);
1694 phy_drd->dev = dev;
1695
1696 drv_data = of_device_get_match_data(dev);
1697 if (!drv_data)
1698 return -EINVAL;
1699 phy_drd->drv_data = drv_data;
1700
1701 if (of_property_present(dev->of_node, "reg-names")) {
1702 void __iomem *reg;
1703
1704 reg = devm_platform_ioremap_resource_byname(pdev, "phy");
1705 if (IS_ERR(reg))
1706 return PTR_ERR(reg);
1707 phy_drd->reg_phy = reg;
1708
1709 reg = devm_platform_ioremap_resource_byname(pdev, "pcs");
1710 if (IS_ERR(reg))
1711 return PTR_ERR(reg);
1712 phy_drd->reg_pcs = reg;
1713
1714 reg = devm_platform_ioremap_resource_byname(pdev, "pma");
1715 if (IS_ERR(reg))
1716 return PTR_ERR(reg);
1717 phy_drd->reg_pma = reg;
1718 } else {
1719 /* DTB with just a single region */
1720 phy_drd->reg_phy = devm_platform_ioremap_resource(pdev, 0);
1721 if (IS_ERR(phy_drd->reg_phy))
1722 return PTR_ERR(phy_drd->reg_phy);
1723 }
1724
1725 ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
1726 if (ret)
1727 return ret;
1728
1729 reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
1730 "samsung,pmu-syscon");
1731 if (IS_ERR(reg_pmu)) {
1732 dev_err(dev, "Failed to lookup PMU regmap\n");
1733 return PTR_ERR(reg_pmu);
1734 }
1735
1736 /*
1737 * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with
1738 * each having separate power control registers.
1739 * 'channel' facilitates to set such registers.
1740 */
1741 channel = of_alias_get_id(node, "usbdrdphy");
1742 if (channel < 0)
1743 dev_dbg(dev, "Not a multi-controller usbdrd phy\n");
1744
1745 /* Get regulators */
1746 phy_drd->regulators = devm_kcalloc(dev,
1747 drv_data->n_regulators,
1748 sizeof(*phy_drd->regulators),
1749 GFP_KERNEL);
1750 if (!phy_drd->regulators)
1751 return -ENOMEM;
1752 regulator_bulk_set_supply_names(phy_drd->regulators,
1753 drv_data->regulator_names,
1754 drv_data->n_regulators);
1755 ret = devm_regulator_bulk_get(dev, drv_data->n_regulators,
1756 phy_drd->regulators);
1757 if (ret)
1758 return dev_err_probe(dev, ret, "failed to get regulators\n");
1759
1760 dev_vdbg(dev, "Creating usbdrd_phy phy\n");
1761
1762 for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
1763 struct phy *phy = devm_phy_create(dev, NULL, drv_data->phy_ops);
1764
1765 if (IS_ERR(phy)) {
1766 dev_err(dev, "Failed to create usbdrd_phy phy\n");
1767 return PTR_ERR(phy);
1768 }
1769
1770 phy_drd->phys[i].phy = phy;
1771 phy_drd->phys[i].index = i;
1772 phy_drd->phys[i].reg_pmu = reg_pmu;
1773 switch (channel) {
1774 case 1:
1775 pmu_offset = drv_data->pmu_offset_usbdrd1_phy;
1776 break;
1777 case 0:
1778 default:
1779 pmu_offset = drv_data->pmu_offset_usbdrd0_phy;
1780 if (i == EXYNOS5_DRDPHY_PIPE3 && drv_data
1781 ->pmu_offset_usbdrd0_phy_ss)
1782 pmu_offset = drv_data->pmu_offset_usbdrd0_phy_ss;
1783 break;
1784 }
1785 phy_drd->phys[i].pmu_offset = pmu_offset;
1786 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
1787 phy_set_drvdata(phy, &phy_drd->phys[i]);
1788 }
1789
1790 phy_provider = devm_of_phy_provider_register(dev,
1791 exynos5_usbdrd_phy_xlate);
1792 if (IS_ERR(phy_provider)) {
1793 dev_err(phy_drd->dev, "Failed to register phy provider\n");
1794 return PTR_ERR(phy_provider);
1795 }
1796
1797 return 0;
1798}
1799
1800static struct platform_driver exynos5_usb3drd_phy = {
1801 .probe = exynos5_usbdrd_phy_probe,
1802 .driver = {
1803 .of_match_table = exynos5_usbdrd_phy_of_match,
1804 .name = "exynos5_usb3drd_phy",
1805 .suppress_bind_attrs = true,
1806 }
1807};
1808
1809module_platform_driver(exynos5_usb3drd_phy);
1810MODULE_DESCRIPTION("Samsung Exynos5 SoCs USB 3.0 DRD controller PHY driver");
1811MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
1812MODULE_LICENSE("GPL v2");
1813MODULE_ALIAS("platform:exynos5_usb3drd_phy");