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1/*
2 * PCI Express Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
27 *
28 */
29#ifndef _PCIEHP_H
30#define _PCIEHP_H
31
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/pci_hotplug.h>
35#include <linux/delay.h>
36#include <linux/sched.h> /* signal_pending() */
37#include <linux/pcieport_if.h>
38#include <linux/mutex.h>
39#include <linux/workqueue.h>
40
41#define MY_NAME "pciehp"
42
43extern int pciehp_poll_mode;
44extern int pciehp_poll_time;
45extern int pciehp_debug;
46extern int pciehp_force;
47extern struct workqueue_struct *pciehp_wq;
48extern struct workqueue_struct *pciehp_ordered_wq;
49
50#define dbg(format, arg...) \
51do { \
52 if (pciehp_debug) \
53 printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); \
54} while (0)
55#define err(format, arg...) \
56 printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
57#define info(format, arg...) \
58 printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
59#define warn(format, arg...) \
60 printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
61
62#define ctrl_dbg(ctrl, format, arg...) \
63 do { \
64 if (pciehp_debug) \
65 dev_printk(KERN_DEBUG, &ctrl->pcie->device, \
66 format, ## arg); \
67 } while (0)
68#define ctrl_err(ctrl, format, arg...) \
69 dev_err(&ctrl->pcie->device, format, ## arg)
70#define ctrl_info(ctrl, format, arg...) \
71 dev_info(&ctrl->pcie->device, format, ## arg)
72#define ctrl_warn(ctrl, format, arg...) \
73 dev_warn(&ctrl->pcie->device, format, ## arg)
74
75#define SLOT_NAME_SIZE 10
76struct slot {
77 u8 state;
78 struct controller *ctrl;
79 struct hotplug_slot *hotplug_slot;
80 struct delayed_work work; /* work for button event */
81 struct mutex lock;
82};
83
84struct event_info {
85 u32 event_type;
86 struct slot *p_slot;
87 struct work_struct work;
88};
89
90struct controller {
91 struct mutex ctrl_lock; /* controller lock */
92 struct pcie_device *pcie; /* PCI Express port service */
93 struct slot *slot;
94 wait_queue_head_t queue; /* sleep & wake process */
95 u32 slot_cap;
96 struct timer_list poll_timer;
97 unsigned int cmd_busy:1;
98 unsigned int no_cmd_complete:1;
99 unsigned int link_active_reporting:1;
100 unsigned int notification_enabled:1;
101 unsigned int power_fault_detected;
102};
103
104#define INT_BUTTON_IGNORE 0
105#define INT_PRESENCE_ON 1
106#define INT_PRESENCE_OFF 2
107#define INT_SWITCH_CLOSE 3
108#define INT_SWITCH_OPEN 4
109#define INT_POWER_FAULT 5
110#define INT_POWER_FAULT_CLEAR 6
111#define INT_BUTTON_PRESS 7
112#define INT_BUTTON_RELEASE 8
113#define INT_BUTTON_CANCEL 9
114
115#define STATIC_STATE 0
116#define BLINKINGON_STATE 1
117#define BLINKINGOFF_STATE 2
118#define POWERON_STATE 3
119#define POWEROFF_STATE 4
120
121#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
122#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
123#define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
124#define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
125#define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
126#define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS)
127#define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP)
128#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
129#define PSN(ctrl) ((ctrl)->slot_cap >> 19)
130
131extern int pciehp_sysfs_enable_slot(struct slot *slot);
132extern int pciehp_sysfs_disable_slot(struct slot *slot);
133extern u8 pciehp_handle_attention_button(struct slot *p_slot);
134extern u8 pciehp_handle_switch_change(struct slot *p_slot);
135extern u8 pciehp_handle_presence_change(struct slot *p_slot);
136extern u8 pciehp_handle_power_fault(struct slot *p_slot);
137extern int pciehp_configure_device(struct slot *p_slot);
138extern int pciehp_unconfigure_device(struct slot *p_slot);
139extern void pciehp_queue_pushbutton_work(struct work_struct *work);
140struct controller *pcie_init(struct pcie_device *dev);
141int pcie_init_notification(struct controller *ctrl);
142int pciehp_enable_slot(struct slot *p_slot);
143int pciehp_disable_slot(struct slot *p_slot);
144int pcie_enable_notification(struct controller *ctrl);
145int pciehp_power_on_slot(struct slot *slot);
146int pciehp_power_off_slot(struct slot *slot);
147int pciehp_get_power_status(struct slot *slot, u8 *status);
148int pciehp_get_attention_status(struct slot *slot, u8 *status);
149
150int pciehp_set_attention_status(struct slot *slot, u8 status);
151int pciehp_get_latch_status(struct slot *slot, u8 *status);
152int pciehp_get_adapter_status(struct slot *slot, u8 *status);
153int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *speed);
154int pciehp_get_max_link_width(struct slot *slot, enum pcie_link_width *val);
155int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *speed);
156int pciehp_get_cur_link_width(struct slot *slot, enum pcie_link_width *val);
157int pciehp_query_power_fault(struct slot *slot);
158void pciehp_green_led_on(struct slot *slot);
159void pciehp_green_led_off(struct slot *slot);
160void pciehp_green_led_blink(struct slot *slot);
161int pciehp_check_link_status(struct controller *ctrl);
162void pciehp_release_ctrl(struct controller *ctrl);
163
164static inline const char *slot_name(struct slot *slot)
165{
166 return hotplug_slot_name(slot->hotplug_slot);
167}
168
169#ifdef CONFIG_ACPI
170#include <acpi/acpi.h>
171#include <acpi/acpi_bus.h>
172#include <linux/pci-acpi.h>
173
174extern void __init pciehp_acpi_slot_detection_init(void);
175extern int pciehp_acpi_slot_detection_check(struct pci_dev *dev);
176
177static inline void pciehp_firmware_init(void)
178{
179 pciehp_acpi_slot_detection_init();
180}
181#else
182#define pciehp_firmware_init() do {} while (0)
183static inline int pciehp_acpi_slot_detection_check(struct pci_dev *dev)
184{
185 return 0;
186}
187#endif /* CONFIG_ACPI */
188#endif /* _PCIEHP_H */
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * PCI Express Hot Plug Controller Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
13 *
14 */
15#ifndef _PCIEHP_H
16#define _PCIEHP_H
17
18#include <linux/types.h>
19#include <linux/pci.h>
20#include <linux/pci_hotplug.h>
21#include <linux/delay.h>
22#include <linux/mutex.h>
23#include <linux/rwsem.h>
24#include <linux/workqueue.h>
25
26#include "../pcie/portdrv.h"
27
28extern bool pciehp_poll_mode;
29extern int pciehp_poll_time;
30
31/*
32 * Set CONFIG_DYNAMIC_DEBUG=y and boot with 'dyndbg="file pciehp* +p"' to
33 * enable debug messages.
34 */
35#define ctrl_dbg(ctrl, format, arg...) \
36 pci_dbg(ctrl->pcie->port, format, ## arg)
37#define ctrl_err(ctrl, format, arg...) \
38 pci_err(ctrl->pcie->port, format, ## arg)
39#define ctrl_info(ctrl, format, arg...) \
40 pci_info(ctrl->pcie->port, format, ## arg)
41#define ctrl_warn(ctrl, format, arg...) \
42 pci_warn(ctrl->pcie->port, format, ## arg)
43
44#define SLOT_NAME_SIZE 10
45
46/**
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
49 * @dsn: cached copy of Device Serial Number of Function 0 in the hotplug slot
50 * (PCIe r6.2 sec 7.9.3); used to determine whether a hotplugged device
51 * was replaced with a different one during system sleep
52 * @slot_cap: cached copy of the Slot Capabilities register
53 * @inband_presence_disabled: In-Band Presence Detect Disable supported by
54 * controller and disabled per spec recommendation (PCIe r5.0, appendix I
55 * implementation note)
56 * @slot_ctrl: cached copy of the Slot Control register
57 * @ctrl_lock: serializes writes to the Slot Control register
58 * @cmd_started: jiffies when the Slot Control register was last written;
59 * the next write is allowed 1 second later, absent a Command Completed
60 * interrupt (PCIe r4.0, sec 6.7.3.2)
61 * @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
62 * on reception of a Command Completed event
63 * @queue: wait queue to wake up on reception of a Command Completed event,
64 * used for synchronous writes to the Slot Control register
65 * @pending_events: used by the IRQ handler to save events retrieved from the
66 * Slot Status register for later consumption by the IRQ thread
67 * @notification_enabled: whether the IRQ was requested successfully
68 * @power_fault_detected: whether a power fault was detected by the hardware
69 * that has not yet been cleared by the user
70 * @poll_thread: thread to poll for slot events if no IRQ is available,
71 * enabled with pciehp_poll_mode module parameter
72 * @state: current state machine position
73 * @state_lock: protects reads and writes of @state;
74 * protects scheduling, execution and cancellation of @button_work
75 * @button_work: work item to turn the slot on or off after 5 seconds
76 * in response to an Attention Button press
77 * @hotplug_slot: structure registered with the PCI hotplug core
78 * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
79 * Link Status register and to the Presence Detect State bit in the Slot
80 * Status register during a slot reset which may cause them to flap
81 * @depth: Number of additional hotplug ports in the path to the root bus,
82 * used as lock subclass for @reset_lock
83 * @ist_running: flag to keep user request waiting while IRQ thread is running
84 * @request_result: result of last user request submitted to the IRQ thread
85 * @requester: wait queue to wake up on completion of user request,
86 * used for synchronous slot enable/disable request via sysfs
87 *
88 * PCIe hotplug has a 1:1 relationship between controller and slot, hence
89 * unlike other drivers, the two aren't represented by separate structures.
90 */
91struct controller {
92 struct pcie_device *pcie;
93 u64 dsn;
94
95 u32 slot_cap; /* capabilities and quirks */
96 unsigned int inband_presence_disabled:1;
97
98 u16 slot_ctrl; /* control register access */
99 struct mutex ctrl_lock;
100 unsigned long cmd_started;
101 unsigned int cmd_busy:1;
102 wait_queue_head_t queue;
103
104 atomic_t pending_events; /* event handling */
105 unsigned int notification_enabled:1;
106 unsigned int power_fault_detected;
107 struct task_struct *poll_thread;
108
109 u8 state; /* state machine */
110 struct mutex state_lock;
111 struct delayed_work button_work;
112
113 struct hotplug_slot hotplug_slot; /* hotplug core interface */
114 struct rw_semaphore reset_lock;
115 unsigned int depth;
116 unsigned int ist_running;
117 int request_result;
118 wait_queue_head_t requester;
119};
120
121/**
122 * DOC: Slot state
123 *
124 * @OFF_STATE: slot is powered off, no subordinate devices are enumerated
125 * @BLINKINGON_STATE: slot will be powered on after the 5 second delay,
126 * Power Indicator is blinking
127 * @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay,
128 * Power Indicator is blinking
129 * @POWERON_STATE: slot is currently powering on
130 * @POWEROFF_STATE: slot is currently powering off
131 * @ON_STATE: slot is powered on, subordinate devices have been enumerated
132 */
133#define OFF_STATE 0
134#define BLINKINGON_STATE 1
135#define BLINKINGOFF_STATE 2
136#define POWERON_STATE 3
137#define POWEROFF_STATE 4
138#define ON_STATE 5
139
140/**
141 * DOC: Flags to request an action from the IRQ thread
142 *
143 * These are stored together with events read from the Slot Status register,
144 * hence must be greater than its 16-bit width.
145 *
146 * %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or
147 * an Attention Button press after the 5 second delay
148 * %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the
149 * hotplug port was inaccessible when the interrupt occurred, requiring
150 * that the IRQ handler is rerun by the IRQ thread after it has made the
151 * hotplug port accessible by runtime resuming its parents to D0
152 */
153#define DISABLE_SLOT (1 << 16)
154#define RERUN_ISR (1 << 17)
155
156#define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
157#define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
158#define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
159#define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
160#define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
161#define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
162#define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
163
164void pciehp_request(struct controller *ctrl, int action);
165void pciehp_handle_button_press(struct controller *ctrl);
166void pciehp_handle_disable_request(struct controller *ctrl);
167void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
168int pciehp_configure_device(struct controller *ctrl);
169void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
170void pciehp_queue_pushbutton_work(struct work_struct *work);
171struct controller *pcie_init(struct pcie_device *dev);
172int pcie_init_notification(struct controller *ctrl);
173void pcie_shutdown_notification(struct controller *ctrl);
174void pcie_clear_hotplug_events(struct controller *ctrl);
175void pcie_enable_interrupt(struct controller *ctrl);
176void pcie_disable_interrupt(struct controller *ctrl);
177int pciehp_power_on_slot(struct controller *ctrl);
178void pciehp_power_off_slot(struct controller *ctrl);
179void pciehp_get_power_status(struct controller *ctrl, u8 *status);
180
181#define INDICATOR_NOOP -1 /* Leave indicator unchanged */
182void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn);
183
184void pciehp_get_latch_status(struct controller *ctrl, u8 *status);
185int pciehp_query_power_fault(struct controller *ctrl);
186int pciehp_card_present(struct controller *ctrl);
187int pciehp_card_present_or_link_active(struct controller *ctrl);
188int pciehp_check_link_status(struct controller *ctrl);
189int pciehp_check_link_active(struct controller *ctrl);
190void pciehp_release_ctrl(struct controller *ctrl);
191
192int pciehp_sysfs_enable_slot(struct hotplug_slot *hotplug_slot);
193int pciehp_sysfs_disable_slot(struct hotplug_slot *hotplug_slot);
194int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe);
195int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status);
196int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status);
197int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status);
198
199int pciehp_slot_reset(struct pcie_device *dev);
200
201static inline const char *slot_name(struct controller *ctrl)
202{
203 return hotplug_slot_name(&ctrl->hotplug_slot);
204}
205
206static inline struct controller *to_ctrl(struct hotplug_slot *hotplug_slot)
207{
208 return container_of(hotplug_slot, struct controller, hotplug_slot);
209}
210
211#endif /* _PCIEHP_H */